EPC23102 EPC-CO | Alldatasheet

Document overview

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Technical content

Features

  • Integrated high side and low side eGaN® FET with internal gate driver and level shifter
  • 5 V external bias supply
  • 3.3 V or 5 V CMOS input logic levels
  • Independent high side and low side control inputs
  • Logic lockout commands both FETs off when inputs are both high at same time
  • External resistors to tune SW switching times and over-voltage spikes above rail and below ground
  • Robust level shifter operating for hard and soft switching conditions
  • False trigger immunity from fast switching transients
  • Synchronous charging for high side bootstrap supply
  • Disable input engages low quiescent current mode from VDRV supply
  • Power on reset for low side VDD supply
  • Undervoltage lockout for high side VBOOT supply
  • Active gate pull-down for HS FET and LS FET with loss of VDRV supply
  • Thermally enhanced QFN package with exposed top for low thermal resistance from junction to top-side heatsink Device Information PART NUMBER Rated RDS(on) for HS and LS FETs at 25 °C QFN Package Size (mm) EPC23102 6.6 mΩ + 6.6 mΩ 3.5 x 5

eGaN® FET DATASHEET EPC23102 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 2 Figure 2: EPC23102 Quad Flat No-Lead (QFN) Package (Transparent Top View) EPC23102 Pinout Description Transparent Top View 543213 10 89 Pin Description

1 HSIN

2 LSIN

4 VDD

5 VDRV

6 RDRV

7 AGND

8 PGND

10 VIN

11 VPHASE

12 RBOOT

13 VBOOT

Pin Pin Name Pin Type Description 1 HSIN L High side PWM logic input, level referenced to AGND. Internal pull-down resistor is connected between HSIN and AGND. 2 LSIN L Low side PWM logic input, level referenced to AGND. Internal pull-down resistor is connected between LSIN and AGND.

3 EN L

VDD disable input, level referenced to AGND. Internal VDD will be disabled when EN is pulled up to VDRV or external 5 V source. Internal pull-down resistor is connected between EN and AGND, thereby VDD will follow VDRV with EN connected to AGND by default.

4 VDD S Internal power supply referenced to AGND, connect a bypass capacitor from

VDD to AGND.

5 VDRV S External 5 V nominal power supply referenced to AGND, connect a bypass

capacitor from VDRV to AGND.

6 RDRV G Insert resistor between RDRV to VDRV to control the turn-on slew rate of the

driven low side FET.

7 AGND S

Logic ground. Connect bypass capacitors between operating bias supplies, VDRV and VDD, to AGND. Internal IC connection between AGND and PGND. Use star ground external connection with PGND to system ground. 8 PGND P Input power supply ground return. Connected to source terminal of internal low side FET. Connect power loop capacitors from VIN to PGND.

9 SW P

Output switching node. Connected to output of half-bridge power stage. SW pin connects together the source terminal of high side FET and the drain terminal of the low side FET.

10 VIN P

Power bus input. Connected to drain terminal of internal high side FET. Connect power loop capacitors from VIN to PGND or power source terminals of low side FET. 11 VPHASE S Kelvin connection to SW, the output switching node. The floating bootstrap power supply, VBOOT , is also referenced to VPHASE.

12 RBOOT G Insert resistor between RBOOT to VBOOT to control the turn-on slew rate of the

internal high side FET. 13 VBOOT S Floating bootstrap power supply referenced to VPHASE (=SW). Connect an external bypass capacitor from VBOOT to VPHASE. Pin Type: P = Power, S = Bias Supplies, L = Logic Inputs/Outputs, G = Gate Drive Adjust

eGaN® FET DATASHEET EPC23102 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 3 Absolute Maximum Ratings SYMBOL PARAMETER MIN MAX UNITS VIN Input Voltage (VIN to PGND) 100 V SW(continuous) Output Switching Node (SW to PGND), Continuous 100 VDRV External Bias Supply (VDRV to AGND) 6 VDD Internal Low Side Supply Voltage (VDD to AGND) 6 VBOOT – VPHASE Internal High Side Supply Voltage (VBOOT to VPHASE), VPHASE = SW 6 HSIN, LSIN PWM Logic Inputs (HSIN to AGND and LSIN to AGND) 5.5 EN VDD Disable Input (EN to AGND) 5.5 TJ Junction Temperature 150 TSTG Storage Temperature -55 150 Recommended Operating Conditions SYMBOL PARAMETER MIN TYP MAX UNITS VIN Input Voltage (VIN to PGND) 10 80 V SW(Q3 Mode) Output Switch Node, 3rd Quadrant Mode -2.5 VIN + 2.5 SW(pulse2ns) Output Switch Node, Transient PW < 2 ns -10 VIN +10 VDRV External Bias Supply (VDRV to AGND) 4.75 5 5.5 VDD Internal Low Side Supply Voltage (VDD to AGND) 4.75 5 5.5 VBOOT – VPHASE Internal High Side Supply Voltage (VBOOT to VPHASE), VPHASE = SW 4.75 5 5.5 HSIN, LSIN PWM Logic Inputs 0 5 EN VDD Disable Input 0 5 PW_min Minimum Input On or Off Pulse Duration, 50% to 50% width 20 ns PW_max Maximum Input On or Off Pulse Duration, 50% to 50% width 200 µs TJ Operating Junction Temperature -40 125 °C Thermal Characteristics SYMBOL PARAMETER TYP UNITS RθJC_Top Thermal Resistance, Junction-to-Case (Top surface of exposed die substrate) 0.4 °C/W RθJB_Bottom Thermal Resistance, Junction-to-Board (At solder joints of VIN, SW and PGND pads) 3 RθJA_JEDEC Thermal Resistance, Junction-to-Ambient (using JEDEC 51-2 PCB) 43 RθJA_EVB Thermal Resistance, Junction-to-Ambient (using EPC90147 EVB) 25 ESD Ratings SYMBOL PARAMETER MIN MAX UNITS HBM Human-body model (JEDEC JS-001) +/-1000 VCDM Charged-device model (JEDEC JESD22-C101) +/-500 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur and device reliability may be affected. All voltage parameters are absolute voltages referenced to PGND (=AGND) unless indicated otherwise. Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to PGND (= AGND) unless indicated otherwise. Thermal Characteristics RθJA_JEDEC is measured using JESD51-2 standard setup with 1 cubic foot enclosure with no forced air cooling, heat dissipated only through natural convection. The test used JEDEC Standard 4-layers PCB with 2 oz top and bottom surface layers and 1 oz buried layers. RθJA_EVB is measured using EPC90147 EVB with no forced air cooling, this rating is more indicative of actual application environment. ESD Ratings

eGaN® FET DATASHEET EPC23102 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 4

Electrical Characteristics

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Low Side Power Supply IDRV_Q Off State Total Quiescent Current HSIN/LSIN/EN = 0 V, VDRV = VDD = 5 V 10 mAIDRV_100kHz Total Operating Current @100 kHz PWM = 100 kHz, 50% On-Time 18 IDRV_1MHz Total Operating Current @1 MHz PWM = 1 MHz, 50% On-Time 37 IVIN_disable VIN Quiescent Current at Disable Mode EN = VDRV = 5 V, VIN = 48 V 600 µAIDRV_disable VDRV Quiescent Current at Disable Mode EN = VDRV = 5 V, VIN = 48 V 50 Bootstrap Power Supply IBOOT_Q Off State Bootstrap Supply Current HSIN = 0 V, (VBOOT – VPHASE) = 5 V 6 mAIBOOT_100kHz Bootstrap Supply Current @100 kHz HS PWM = 100 kHz, 50% On-Time 8 IBOOT_1MHz Bootstrap Supply Current @1 MHz HS PWM = 1 MHz, 50% On-Time 20 VSYNC_BOOT Sync Boot Generated (VBOOT -VPHASE) ISYNC_BOOT = 20 mA 4.75 V Power On Reset and Undervoltage Lockout VDD_POR+ POR Trip Level VDD Rising LSIN = 5 V, VDD Ramps Up 4.0 V VDD_POR_HYST POR VDD Falling Hysteresis LSIN = 5 V, VDD Ramps Down 0.5 VBOOT_UVLO+ UVLO Trip Level (VBOOT - VPHASE) Rising HSIN = 5 V, VBOOT Ramps Up 4.0 VBOOT_UVLO_HYST UVLO (VBOOT - VPHASE) Falling Hysteresis HSIN = 5 V, VBOOT Ramps Down 0.5 Logic Input Pins VIH High-level Logic Threshold HSIN, LSIN Rising 2.4 VVIL Low-level Logic Threshold HSIN, LSIN Falling 0.8 VIHYST Logic Threshold Hysteresis VIH Rising – VIL Falling 0.3 RIN HSIN and LSIN Pull-Down Resistance HSIN, LSIN = 5 V 6.5 kΩ VDD Disable Input VTH_EN EN Input Threshold VDRV = 5 V 3.3 V REN EN Pull-Down Resistance EN = 5 V 150 kΩ High Side Internal Power FET RDS(on)_HS High Side FET RDS(on) IDS = +/-10 A, HSIN = 5 V, LSIN = 0 V 5.2 6.6 mΩ VHS_DS_Clamp High Side 3rd Quadrant Clamp IDS = - 10 A, HSIN & LSIN = 0 V -1.5 V ILEAK_VIN-SW Leakage Current (VIN to SW) HSIN = 0 V, VIN = 100 V, SW = 0 V 100 µA CWELL HV-Well Capacitance (SW to PGND) HSIN = 0 V, VIN = 48 V, SW = 48 V 61 pFCOSS_HSFET Output Capacitance (V IN to SW) HSIN = 0 V, VIN = 48 V, SW = 0 V 342 QOSS_HSFET Output Charge (VIN to SW) HSIN = 0 V, VIN = 48 V, SW = 0 V 28 nC EQOSS_HSFET Output Capacitance Stored Energy HSIN = 0 V, VIN = 48 V, SW = 0 V 0.5 µJ EON_HS_0 Turn-On Switching Energy (HS_FET) HS Turn-On, SW = 0 V to 48 V, RBOOT = 0 Ω, ILOAD = 10 A 2.5 EON_HS_1 HS Turn-On, SW = 0 V to 48 V, RBOOT = 2.2 Ω, ILOAD = 10 A 4.5 EOFF_HS Turn-Off Switching Energy (HS_FET) HS Turn-Off, SW = 48 V to 0 V, ILOAD = 10 A 0.15 Low Side Internal Power FET RDS(on)_HS Low Side FET RDS(on) IDS = +/-10 A, LSIN = 5 V, HSIN = 0 V 5.2 6.6 mΩ VHS_DS_Clamp Low Side 3rd Quadrant Clamp IDS = - 10 A, HSIN & LSIN = 0 V -1.5 V ILEAK_SW-PGND Leakage Current (SW to PGND) LSIN = 0 V, VIN = 100 V, SW = 100 V 100 µA COSS_LSFET Output Capacitance (SW to PGND) LSIN = 0 V, SW = 48 V, PGND = 0 V 343 pF QOSS_LSFET Output Charge (SW to PGND) LSIN = 0 V, SW = 48 V, PGND = 0 V 29 nC EQOSS_LSFET Output Capacitance Stored Energy LSIN = 0 V, SW = 48 V, PGND = 0 V 0.53 µJ EON_LS_0 Turn-On Switching Energy (LS_FET) LS Turn-On, SW = 48 V to 0 V, RBOOT = 0 Ω, ILOAD = 10 A 2.5 EON_LS_1 LS Turn-On, SW = 48 V to 0 V, RBOOT = 2.2 Ω, ILOAD = 10 A 4.5 EOFF_LS Turn-Off Switching Energy (LS_FET) LS Turn-Off, SW = 0 V to 48 V, ILOAD = 10 A 0.15 Nominal V IN = 48 V, V DRV = V DD = 5 V and (V BOOT – V PHASE) = 5 V. All typical ratings are specified at T A = 25˚C unless otherwise indicated. All voltage parameters are absolute voltages referenced to PGND (= AGND) unless indicated otherwise.

eGaN® FET DATASHEET EPC23102 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 5 100 nF 2.2 mH 47 mF 5 A 1 kΩ 5 W 50 Ω 37.4 Ω 150 Ω 150 Ω 37.4 Ω 150 Ω To oscilloscope 150 Ω High side input (5 V, 50 Ω) Low side input (5 V, 50 Ω)

5 V 48 V

1 µF RDRV 100 nF RDRV VDD HSIN LSIN VIN SW AGND EPC23102 EN VDRV VBOOT RBOOT PGND To oscilloscope To oscilloscope Dynamic Characteristics Parameter Definition Figure 3a: Test Circuit for Dynamic Characteristics Figure 3b: Logic Input to Output Switching Node Timing Diagram Electrical Characteristics (continued) Electrical Characteristics (continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Dynamic Characteristics (Logic Input to Output Switching Node) See Figure 3a and 3b for Timing Diagram and Test Circuit) t_delayHS_on High-Side On Propagation Delay SW = 0 V and HS FET Turn-On 20 ns t_delayLS_on Low-Side On Propagation Delay SW = 48 V and LS FET Turn-On 20 t_delayHS_off High-Side Off Propagation Delay SW = 48 V and HS FET Turn-Off 20 t_delayLS_off Low-Side Off Propagation Delay SW = 0 V and LS FET Turn-Off 20 t_matchon Delay Matching LSoff to HSon LS Turn-Off to HS Turn-On 0 t_matchoff Delay Matching HSoff to LSon HS Turn-Off to LS Turn-On 0 t_riseSW_HS0 SW Rise Time at High Side FET Turn-On (Buck Mode, Hard Switching) HS Turn-On Buck Mode, 0 V to 48 V, RBOOT = 0 Ω, ILoad = 5 A 1.5 t_riseSW_HS1 HS Turn-On Buck Mode, 0 V to 48 V, RBOOT = 2.2 Ω, ILoad = 5 A 3 t_fallSW_LS0 SW Fall Time at Low Side FET Turn-On (Boost Mode, Hard Switching) LS Turn-On Boost Mode, 48 V to 0 V, RDRV = 0 Ω, ILoad = 5 A 1.5 t_fallSW_LS1 LS Turn-On Boost Mode, 48 V to 0 V, RDRV= 2.2 Ω , ILoad = 5 A 3 HSIN LSIN 50% 50% -30 mV~0 V ~1.46 V SWa 30 mV t_delayHS_ont_delayLS_off t_delayLS_on t_delayHS_off 2.5 V 2.5 V

eGaN® FET DATASHEET EPC23102 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 8 Thermal derating curves in Figure 8 are derived from measurement data. At ambient temperature of 25°C using topside heatsink, the EPC23102 IC is specified with an output current handling capability greater than 35 A operating at 1 MHz switching frequency with airflow greater than 500 LFM. But without the benefit of topside heatsink, the same conditions at 1 MHz and 500 LFM, the current rating is reduced to

16 A at ambient temperature of 25°C showing the dramatic difference

of using the lower RθJC_top of the higher thermal conductive path. The internal supplies can be disabled to save quiescent power by turning off the series switch, QSA in Figure 9, with 5 V applied to the EN pin to engage chip shutdown mode. In this mode, minimum current is drawn from the external VDRV supply while VDD is open circuit. Whatever charges remain within the VDD bypass capacitor will be discharged by the chip internal circuits at nominal rate of 10 mA/CDD. In the chip shutdown circuit, series switch (QSA) between VDRV and VDD is turned off by internal disable circuit which itself derived its power from VIN such that the chip draws a maximum up to 600 µA at 48 V from V IN when shutdown mode is engaged. The minimum input voltage (VINmin) should be at least 10 V for the IC to be enabled. Below the minimum VIN the pass-transistor between VDRV and VDD will be off. Same condition when VDD disable pin, EN, is connected to 5 V. The series connected high voltage synchronous bootstrap FET, Q SB in Figure 9, between V DD and V BOOT for the high side floating bootstrap supply is activated only after the LS FET (Q2) is turned on to avoid overcharging during deadtime. The use of GaN FET in the charging path eliminates reverse recovery and reduces power dissipation. Another advantage is the lower dropout voltage of 100 to 200 mV from the synchronous FET versus typical Si bootstrap diode voltage of 0.6 V. With synchronous charging V BOOT is maintained closer to the V DD voltage, allowing the HS FET gate drive circuit to have similar gate drive current and delay performance as the LS FET gate drive circuit. Figure 8: Thermal Derating Curves for Output Current Rating of EPC23102 IC using EPC90147 Evaluation Board Figure 9: Simplified circuit diagram of VIN , VDRV , VDD , and VBOOT Power Supplies 25 35 45 55 Ambient Temperature (°C) Topside Heatsink No Heatsink No Heatsink Topside Heatsink Ambient Temperature (°C) ILOAD (A)ILOAD (A) 65 75 85 95 105 25 35 45 55 65 75 85 95 105 500 kHz

1 MHz

1.5 MHz

Air/f_low = 500 LFM Air/f_low = 1000 LFM Power Supplies – VIN , VDRV , VDD , and VBOOT The EPC23102 IC only requires an external 5 V V DRV power supply. Internal low side and high side power supplies, V DD and V BOOT, are generated from the external supply via two series connected switches. Figure 9 shows the simplified circuit diagram of the different power supplies inside the IC and their interaction with each other. VIN LSG VDRV QSA VDD QSB QOFF VDDON VBOOTON VBOOT AGND EN VDDON drive Sync boot drive

eGaN® FET DATASHEET EPC23102 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 11 A N D C T Type A N C D w1 w2 T Top View Bottom View Side View Bottom View Detail Loaded tape feed direction Top View Detail

eGaN® FET DATASHEET EPC23102 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 12 Notes: 1. Dimensioning and tolerancing conform to ASME Y14.5-2009 2. All dimensions are in millimeters 3. N is the total number of terminals 4. Dimension b applies to the metallized terminal. If the terminal has a radius on the other end of it, dimension b should not be measured in that radius area. 5. ND and NE refer to the number of terminals on each D and E side respectively. 6. Dimension b applies to the metallized terminal and is measured between 0.15 mm and 0.30 mm from the termi- nal tip. If the terminal has a radius on the other end of it, dimension b should not be measured in that radius area. 7. Coplanarity applies to the terminals and all the other bottom surface metallization. SYMBOL Dimension (mm) MIN Nominal MAX Note A 0.60 0.65 0.70 A1 0.00 0.02 0.05 A3 0.20 Ref b 0.20 0.25 0.30 6 b1 0.38 0.43 0.48 6 b2 0.49 0.54 0.59 D 3.50 BSC E 5.00 BSC e 0.50 BSC K 0.55 0.60 0.65 K1 0.12 0.17 0.22 K2 0.775 0.825 0.875 K3 0.15 0.20 0.25 SYMBOL Dimension (mm) MIN Nominal MAX Note L 0.30 0.40 0.50 L1 2.85 2.95 3.05 L2 3.25 3.35 3.45 aaa 0.05 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 N 13 3 ND 6 5 NE 4 5 Notes 1, 2 EPC23102CYYWWE123456 Site/date code Lot code 0.10 Max. Seating plane A Side View 2 Ceee 7 Nx C C// ccc 12345 11 1213 A A1 B A Top View Exposed die Side View 1 Caaa 2x Caaa 2x 4.470 Die size E 5.00 2.600 Die size D 5 4 3 2 bbb C L K K1 (2x) e L1L2 K3 (2x) (2x) b (10x) b1b2 (2x) Bottom View C A BM ddd M 108 9 Pads 1-7, 11, 12 and 13 are IC pins; Pad 9 is a SW pin ; Pad 8 is a PGND pin and 10 is a VIN pin

eGaN® FET DATASHEET EPC23102 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 13 1400 /uni20101400 850 1175 /uni20101650 /uni20101675 575 /uni2010425 /uni2010925 /uni20101175 /uni20101675 1650 /uni20102400 /uni20102425 /uni20101325 /uni2010825 /uni20102250 780 245 /uni00A0(8x) 680 795 /uni00A0(8x) 1030 /uni00A0 3210 /uni00A0(2x) /uni00A0 990 /uni00A0 1255/uni00A0 (2x)/uni00A0 3890 /uni00A0 1750 2500 1310 575 /uni2010425 /uni2010925 270 /uni00A0(8x) 490 /uni00A0(8x) 505 505 858 505 270 270 270 270 270 (12x) 230 (10x) 2941 /uni00A0(2x) 750 /uni00A0 (2x) /uni20101310 1550 /uni20101550 1425 /uni20101425 3309 384 530 /uni00A0(2x) 1750 850 1175 /uni20101175 /uni20101675 /uni20102300 /uni20102175 /uni20101325 /uni2010825 /uni20101825 2500 COPPER (units in μm) SOLDER MASK (units in μm)

eGaN® FET DATASHEET EPC23102 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 14 1375 /uni20101375 1550 /uni20101550 575 1470 /uni2010425 /uni2010925 /uni20101480 188 125 /uni00A0(8x) 150 275 /uni00A0(8x) 645 263 2830 /uni00A0(2x) 215 3140 480 /uni00A0(2x) 1750 822 1035 /uni20101175 /uni20101675 /uni20102300 /uni20102255 /uni20101325 /uni2010825 /uni20102083 2500 1310 1550 /uni20101550 575 1425 /uni2010425 /uni2010925 /uni20101425 250 250 /uni00A0(8x) 250 400 /uni00A0(8x) 800 450 2950 /uni00A0(2x) 430 2775 710 /uni00A0 (2x) 1750 540 /uni00A0 (2x) 250 (12x) 250 (10x) 400 250 /uni20101310 822 1040 /uni20101175 /uni20101675 /uni20102300 /uni20102175 /uni20101325 /uni2010825 /uni20101825 2500 PASTE (units in μm) PACKAGE (units in μm)

eGaN® FET DATASHEET EPC23102 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 15 Information subject to change without notice. Revisied July 2022 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx STATUS VERSION DATE REMARK ENGRT 1.0 7/20/2022 The following features and parameters do not meet the datasheet description and specifications: 1) The maximum operating VIN voltage should not exceed 60 V. 2) The maximum transient voltage at the output switch node, SW, should not exceed 70 V. Recommend to use at least 3.3 Ω for RBOOT and RDRV to modulate the over-voltage spike above VIN rail and below PGND to less than 10 V. Errata Sheet