EPC2021 EPC-CO | Alldatasheet

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Technical content

eGaN® FET DATASHEET EPC2021 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 1 EPC2021 eGaN® FETs are supplied only in passivated die form with solder bars. Die Size: 6.05 mm x 2.3 mm

Applications

  • High Frequency DC-DC Conversion
  • Motor Drive
  • Industrial Automation
  • Synchronous Rectification
  • Inrush Protection
  • Class-D Audio Benefits
  • Ultra High Efficiency
  • No Reverse Recovery
  • Ultra Low QG
  • Small Footprint EFFICIENT POWER CONVERSIONG D S HAL EPC2021 – 80 V (D-S) Enhancement Mode Power Transistor VDS , 80 V RDS(on) , 2.2 mΩ ID , 90 A Maximum Ratings PARAMETER VALUE UNIT VDS Drain-to-Source Voltage (Continuous) 80 V ID Continuous (TA = 25°C) 90 A Pulsed (25°C, TPULSE = 300 µs) 390 VGS Gate-to-Source Voltage 6 V Gate-to-Source Voltage -4 TJ Operating Temperature -40 to 150 TSTG Storage Temperature -40 to 150 Thermal Characteristics PARAMETER TYP UNIT RθJC Thermal Resistance, Junction-to-Case 0.4 °C/W RθJB Thermal Resistance, Junction-to-Board 1.1 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 42 Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. All measurements were done with substrate connected to source. # Defined by design. Not subject to production test. Static Characteristics (TJ = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 500 μA 80 V IDSS Drain-Source Leakage VGS = 0 V, VDS = 80 V 20 200 µA IGSS Gate-to-Source Forward Leakage VGS = 5 V, TJ = 25°C 0.02 4 mA Gate-to-Source Forward Leakage# VGS = 5 V, TJ = 125°C 0.1 9 mA Gate-to-Source Reverse Leakage VGS = -4 V 20 200 µA VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 13 mA 0.7 1.2 2.5 V RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 29 A 1.8 2.2 mΩ VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.5 V Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Note: Datasheet is applicable for devices with date code of 1918 and later. For older date code devices please contact EPC for data sheet

eGaN® FET DATASHEET EPC2021 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 5 DIE MARKINGS DIE OUTLINE Solder Bump View (685) Seating plane (785) 100 ± 20 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 A f d X30 B g e c X30 X28 Pad 1 is Gate; Pads 2 ,5, 6, 9, 10, 13, 14, 17, 18, 21, 22, 25, 26, 29 are Source; Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23, 24, 27, 28 are Drain; Pad 30 is Substrate.* *Substrate pin should be connected to Source DIM Micrometers MIN Nominal MAX A 6020 6050 6080 B 2270 2300 2330 c 2047 2050 2053 d 717 720 723 e 210 225 240 f 195 200 205 g 400 400 400 Side View YYYY ZZZZ TAPE AND REEL CONFIGURATION 8 mm pitch, 12 mm wide tape on 7” reel 7” inch reel Die orientation dot Gate solder bump is under this corner Die is placed into pocket solder bump side down (face side down) Loaded Tape Feed Direction a d e f g h c b DIM Dimension (mm) EPC2021 (Note 1) Target MIN MAX a 12.00 11.90 12.30 b 1.75 1.65 1.85 c (Note 2) 5.50 5.45 5.55 d 4.00 3.90 4.10 e 8.00 7.9 0 8.10 f (Note 2) 2.00 1.95 2.05 g 1.50 1.50 1.60 h 1.50 1.50 1.75 Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/ JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. 2021 2021 YYYY ZZZZ Die orientation dot Gate Pad bump is under this corner Part Number Laser Markings Part # Marking Line 1 Lot_Date Code Marking Line 2 Lot_Date Code Marking Line 3 EPC2021 2021 YYYY ZZZZ

eGaN® FET DATASHEET EPC2021 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 6 RECOMMENDED LAND PATTERN (units in µm) RECOMMENDED STENCIL DRAWING (units in µm) Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing. Intended for use with SAC305 Type 3 solder, reference 88.5% metals content. Additional assembly resources available at https://epc-co.com/epc/DesignSupport/ AssemblyBasics.aspx Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx 6050 400 X34 2300 1330 2050 720 200 X35 R60 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 6050 180 700 X30 2300 400 2030 X30 X28 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Land pattern is solder mask defined Solder mask opening is 180 µm It is recommended to have on-Cu trace PCB vias Pad 1 is Gate; 25, 26, 29 are Source; Pads 3, 4, 7, 8, 11, 12, 15, 16, 19, 20, 23, 24, 27, 28 are Drain; Pad 30 is Substrate.* *Substrate pin should be connected to Source Information subject to change without notice. Revised April, 2021