EPC2019 EPC-CO | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 6

Technical content

eGaN® FET DATASHEET EPC2019 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 1 EPC2019 – Enhancement Mode Power Transistor VDS, 200 V RDS(on) , 50 mW ID , 8.5 A EPC2019 eGaN® FETs are supplied only in passivated die form with solder bars

Applications

  • High Speed DC-DC conversion
  • Class-D Audio
  • High Frequency Hard-Switching and Soft-Switching Circuits Benefits
  • Ultra High Efficiency
  • Ultra Low RDS(on)
  • Ultra Low QG
  • Ultra Small Footprint EFFICIENT POWER CONVERSION G D S HAL Maximum Ratings PARAMETER VALUE UNIT VDS Drain-to-Source Voltage (Continuous) 200 V ID Continuous (TA = 25˚C, RθJA = 18°C/W) 8.5 A Pulsed (25°C, TPULSE = 300 µs) 42 VGS Gate-to-Source Voltage 6 V Gate-to-Source Voltage -4 TJ Operating Temperature -40 to 150 TSTG Storage Temperature -40 to 150 Thermal Characteristics PARAMETER TYP UNIT RθJC Thermal Resistance, Junction-to-Case 2.7 °C/W RθJB Thermal Resistance, Junction-to-Board 7.5 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 72 Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. Static Characteristics (TJ = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 125 μA 200 V IDSS Drain-Source Leakage VGS = 0 V, VDS = 160 V 20 100 µA IGSS Gate-to-Source Forward Leakage VGS = 5 V 0.8 2.5 mA Gate-to-Source Reverse Leakage VGS = -4 V 20 100 µA VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 1.5 mA 0.8 1.4 2.5 V RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 7 A 36 50 mΩ VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 V All measurements were done with substrate connected to source. Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.

eGaN® FET DATASHEET EPC2019 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 5 2019 YYYY ZZZZ Die orientation dot Gate Pad bump is under this corner Part Number Laser Markings Part # Marking Line 1 Lot_Date Code Marking line 2 Lot_Date Code Marking Line 3 EPC2019 2019 YYYY ZZZZ DIE MARKINGS TAPE AND REEL CONFIGURATION 4 mm pitch, 8 mm wide tape on 7” reel 7” reel a d e f g c b EPC2019 (note 1) 2019 YYYY ZZZZ Dimension (mm) target min max a 8.00 7.90 8.30 b 1.75 1.65 1.85 c (see note) 3.50 3.45 3.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10 f (see note) 2.00 1.95 2.05 g 1.5 1.5 1.6 Note 1: MSL 1 (moisture sensitivity level 1) classi/f_ied according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. Die orientation dot Gate solder bar is under this corner Die is placed into pocket solder bar side down (face side down) Loaded Tape Feed Direction Figure 12: Safe Operating Area 0.1 100 0.1 1 10 100 1000 I D – Drain Current (A) VDS - Drain-Source Voltage (V) Limited by RDS(on) TJ = Max Rated, TC = +25°C, Single Pulse Pulse Width 100 ms 10 ms 1 ms 100 µs 10 µs

eGaN® FET DATASHEET EPC2019 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 6 DIE OUTLINE Solder Bar View Side View 2 6 43 5 A e g g B c d X2 X4 f k h

815 Max

100 ± 20 Seating plane (685) DIM MIN Nominal MAX A 2736 2766 2796 B 920 950 980 c 697 700 703 d 247 250 253 e 168 183 198 f 245 250 255 g 600 600 600 h 450 450 450 i 235 250 265 MICROMETERS Pad no.1 is Gate; Pad no. 3, 5 are Drain; Pad no. 2, 4, 6 are Source; Pad no. 7 is Substrate.* *Substrate pin should be connected to Source Pad no. 1 is Gate Pad no. 3, 5 are Drain Pad no. 2, 4, 6 are Source Pad no. 7 is Substrate* *Substrate pin should be connected to Source 1 7 43 5 230 230 230 680 2766 950 600 600 450 The land pattern is solder mask defined. Copper is larger than the solder mask opening. Solder mask is 10 µm smaller per side than bump. RECOMMENDED LAND PATTERN (measurements in µm) Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx RECOMMENDED STENCIL DRAWING (units in µm) Recommended stencil should be 4 mil (100 μm) thick, must be laser cut , opening per drawing. The corner has a radius of R60. Intended for use with SAC305 Type 3 solder, reference 88.5% metals content Additional assembly resources available at https://epc-co.com/epc/DesignSupport/ AssemblyBasics.aspx 230 230 230 680 2766 950 600 600 450 1 7 43 5 Information subject to change without notice. Revised April, 2021