EPC2202 EPC-CO | Alldatasheet

Document overview

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Technical content

eGaN® FET DATASHEET EPC2202 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 1 EPC2202 eGaN® FETs are supplied only in passivated die form with solder bars. Die size: 2.1 mm x 1.6 mm

Applications

  • Lidar/Pulsed Power Applications
  • High Power Density DC -DC Converters
  • Class-D Audio
  • High Intensity Headlamps Benefits
  • Ultra High Efficiency
  • Ultra Low RDS(on)
  • Ultra Low QG
  • Ultra Small Footprint EFFICIENT POWER CONVERSION HAL EPC2202 - Automotive 80 V (D-S) Enhancement Mode Power Transistor VDS , 80 V RDS(on) , 17 mΩ ID , 18 A A E C- Q101 G D S Maximum Ratings PARAMETER VALUE UNIT VDS Drain-to-Source Voltage (Continuous) 80 V ID Continuous (TA = 25°C, RθJA = 12°C/W) 18 A Pulsed (25°C, TPULSE = 300 µs) 75 VGS Gate-to-Source Voltage 5.75 V Gate-to-Source Voltage -4 TJ Operating Temperature –40 to 150 TSTG Storage Temperature –40 to 150 Thermal Characteristics PARAMETER TYP UNIT RθJC Thermal Resistance, Junction-to-Case 2 °C/W RθJB Thermal Resistance, Junction-to-Board 4 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 69 Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. All measurements were done with substrate connected to source. Static Characteristics (TJ = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 300 μA 80 V IDSS Drain-Source Leakage VDS = 64 V, VGS = 0 V 20 250 µA IGSS Gate-to-Source Forward Leakage VGS = 5 V 0.01 3 mA Gate-to-Source Reverse Leakage VGS = -4 V 0.01 0.25 mA VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 3 mA 0.8 1.4 2.5 V RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 11 A 12 17 mΩ VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.8 V Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.

eGaN® FET DATASHEET EPC2202 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 5 2202 YYYY ZZZZ TAPE AND REEL CONFIGURATION 4mm pitch, 8mm wide tape on 7”reel 7” reel a d e f g c b EPC2202 (note 1) Dimension (mm) target min max a 8.00 7.90 8.30 b 1.75 1.65 1.85 c (see note) 3.50 3.45 3.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10 f (see note) 2.00 1.95 2.05 g 1.5 1.5 1.6 Note 1: MSL 1 (moisture sensitivity level 1) classi/f_ied according to IPC/JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. Die orientation dot Gate solder bar is under this corner Die is placed into pocket solder bar side down (face side down) Loaded Tape Feed Direction DIE MARKINGS 2202 YYYY ZZZZ Part Number Laser Markings Part # Marking Line 1 Lot_Date Code Marking line 2 Lot_Date Code Marking Line 3 EPC2202 2202 YYYY ZZZZ Die orientation dot Gate Pad bump is under this corner

eGaN® FET DATASHEET EPC2202 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2021 | | 6 Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx 1362 802 1632 560 180 180 2106 X2 3 4 5 61 RECOMMENDED LAND PATTERN (units in µm) Pad no. 1 is Gate; Pads no. 3, 5 are Drain; Pads no. 4, 6 are Source; Pad no. 2 is Substrate.* *Substrate pin should be connected to Source The land pattern is solder mask defined. DIE OUTLINE Solder Bar View Side View DIM MICROMETERS MIN Nominal MAX A 2076 2106 2136 B 1602 1632 1662 c 1379 1382 1385 d 577 580 583 e 235 250 265 f 195 200 205 g 400 400 400 B A d c e g 3 4 5 6 g f f

815 Max

(685) Recommended stencil should be 4mil (100 µm) thick, must be laser cut, opening per drawing. The corner has a radius of R60 Intended for use with SAC305 Type 3 solder, reference 88.5% metals content. Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx RECOMMENDED STENCIL DRAWING (measurements in µm) Pad no. 1 is Gate; Pads no. 3, 5 are Drain; Pads no. 4, 6 are Source; Pad no. 2 is Substrate. * *Substrate pin should be connected to Source 1362 802 1632 560 180 180 2106 X2 3 4 5 61 Information subject to change without notice. Revised April, 2021