EPC2055 EPC-CO | Alldatasheet

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eGaN® FET DATASHEET EPC2055 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1 EFFICIENT POWER CONVERSION HAL EPC2055 – Enhancement Mode Power Transistor VDS , 40 V RDS(on) , 3.6 mΩ ID , 29 A Maximum Ratings PARAMETER VALUE UNIT VDS Drain-to-Source Voltage (Continuous) 40 V Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150 °C) 48 ID Continuous (TA = 25°C) 29 A Pulsed (25°C, TPULSE = 300 µs) 161 VGS Gate-to-Source Voltage 6 V Gate-to-Source Voltage -4 TJ Operating Temperature -40 to 150 TSTG Storage Temperature -40 to 150 Thermal Characteristics PARAMETER TYP UNIT RθJC Thermal Resistance, Junction-to-Case 1 °C/W RθJB Thermal Resistance, Junction-to-Board 2.5 RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 64 Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details. # Defined by design. Not subject to production test. Static Characteristics (TJ = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.5 mA 40 V IDSS Drain-Source Leakage VGS = 0 V, VDS = 32 V 0.01 0.4 mA IGSS Gate-to-Source Forward Leakage VGS = 5 V 0.01 0.8 Gate-to-Source Forward Leakage# VGS = 5 V, TJ = 125°C 0.1 5 Gate-to-Source Reverse Leakage VGS = -4 V 0.01 0.4 VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 7 mA 0.7 1.1 2.5 V RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 15 A 3 3.6 mΩ VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.9 V Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. EPC2055 eGaN® FETs are supplied only in passivated die form with solder bars. Die Size: 2.5 mm x 1.5 mm

Applications

  • DC-DC Converters
  • Isolated DC-DC Converters
  • Sync rectification
  • High frequency (2 MHz) Ultra-thin Point of Load Converters with Input

12 V – 24 V

  • Lidar
  • USB-C Battery Chargers
  • LED Lighting
  • 12 V – 24 V Input Motor Drivers Benefits
  • Ultra High Efficiency
  • No Reverse Recovery
  • Ultra Low QG
  • Small Footprint G D S

eGaN® FET DATASHEET EPC2055 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 5 DIE MARKINGS DIE OUTLINE Solder Bump View Pad 1 is Gate; Pads 2 ,4, 6 are Source; Pads 3, 5 are Drain DIM Micrometers MIN Nominal MAX A 2470 2500 2530 B 1470 1500 1530 c 1175 d 1350 e 500 f 250 g 300 h 825 j 787.5 k 225Side View YYYY 2055 ZZZZ TAPE AND REEL CONFIGURATION 4 mm pitch, 8 mm wide tape on 7” reel 7” inch reel Die orientation dot Gate solder bar is under this corner Die is placed into pocket solder bump side down (face side down) Loaded Tape Feed Direction a d e f g h c b DIM Dimension (mm) EPC2204 (Note 1) Target MIN MAX a 8.00 7.9 0 8.30 b 1.75 1.65 1.85 c (Note 2) 3.50 3.45 3.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10 f (Note 2) 2.00 1.95 2.05 g 1.50 1.50 1.60 h 0.50 0.45 0.55 Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/ JEDEC industry standard. Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. Part Number Laser Markings Part # Marking Line 1 Lot_Date Code Marking Line 2 Lot_Date Code Marking Line 3 EPC2055 2055 YYYY ZZZZ 2055 YYYY ZZZZ Die orientation dot Gate Pad bump is under this corner 518 ± -25 Seating plane 638 120 ± 12 A d jk hg B e c f 3 4 5 6

eGaN® FET DATASHEET EPC2055 EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 6 RECOMMENDED LAND PATTERN (units in µm) RECOMMENDED STENCIL DRAWING (units in µm) Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing. The corner has a radius of R60. Intended for use with SAC305 Type 3 solder, reference 88.5% metals content. Split stencil design can be provided upon request, but EPC has tested this stencil design and not found any scooping issues. Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx Information subject to change without notice. Revised December, 2020 Land pattern is solder mask defined Solder mask opening is 180 µm It is recommended to have on-Cu trace PCB vias Pad 1 is Gate; Pads 2 ,4, 6 are Source; Pads 3, 5 are Drain DIM Nominal A 2500 B 1500 c1 1155 d1 1330 e 500 f1 230 g1 280 h1 805 j 787.5 k 225 DIM Nominal A 2500 B 1500 c1 1155 d1 1330 e 500 f1 230 g1 280 h1 805 j 787.5 k 225 A j k h1 g1 B e c1 3 4 5 6 A h1 g1 B e c1 R60 j k