EP80579

Intel Corporation

Intel짰 EP80579 Integrated Processor Product Line

Manufacturer: Intel Corporation

Document: 1916 Pages / 19Mb

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EP80579 INTEL | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 1916

Technical content

Datasheet sections

4 Order Number: 320066-003US
1.0 Introduction
1.1 Introduction
1.2 Document Organization
1.3 Referenced Documents and Related Websites
1.4 Acronyms
1.5 Glossary
2.0 Architectural Overview
2.1 Overview
2.1.1 Block Summary
2.1.2 External Interfaces
2.1.3 Frequencies and Gear Ratios
2.2 Signaling Architecture
2.3 DMA and Peer-to-Peer Data Transfers
3.0 Platform Memory and Device Configuration
3.1 Overview
3.1.1 Configuration Objectives
3.1.2 Terminology and Conventions
3.2 IA Platform Infrastructure
3.2.1 IA Platform View of Endianness
3.2.2 IA Platform View of Configuration
3.3 High-Level Views
3.3.1 Characteristics of External System Memory (DRAM)
3.3.2 Characteristics of Internal and External Memories
3.3.3 Characteristics of Device Configuration
3.4 Memory Map for IA-Attached Agents
3.5 Memory Map for AIOC-Attached Devices
3.6 Endianness
3.7 PCI Configuration
3.7.1 Overview
3.7.2 Device Tree
3.7.3 Materializing Device Structures
3.7.4 PCI Configuration Headers
4.0 Signaling
4.1 Overview
4.1.1 Terminology and Conventions
4.2 Existing Signaling Capabilities
4.2.1 IA-32 core/Platform
4.2.1.1 MSI and INTx Signaling
4.2.1.2 GPIO Signaling
4.2.2 Other Agents
4.3 Inter-Agent Signaling
4.3.1 Signaling that Travels Around the Signal Bridge
4.3.2 Signaling that is Bridged from a Side-Band Source Signal
4.3.2.1 Targeting the IA-32 core with a Bridged Signal
5.0 Error Handling
5.1 Overview
5.2 EP80579 View of Error Reporting

Datasheet sections

5.2.1 Hardware Capabilities
5.2.2 Software Usage Model
5.3 Error Reporting by the IMCH
5.3.1 Overview of the First and Next Error Architecture
5.3.2 Global Error Events
5.3.3 Unit-Level Errors from the Buffer Unit
5.3.4 Unit-Level Errors from the DRAM Interface
5.3.5 Unit-Level Errors from the FSB Interface
5.3.6 Unit-Level Errors from the NSI
5.3.7 Unit-Level Errors from the EDMA Engine
5.3.8 Unit-Level Errors from PCI Express* Ports A0 and A1
5.4 Error Reporting by the IICH
5.4.1 SMBus Interface
5.4.2 LPC Interface
5.4.5 SATA Interface
5.4.6 Serial I/O Interface
5.5 Error Reporting by the System Memory Controller
5.5.1 Handling Out-of-Bounds Addresses
5.5.2 IMCH - Memory Controller
5.6 Error Reporting by AIOC Devices
5.6.1 Gigabit Ethernet MAC
5.6.2 CAN Interface
5.6.3 SSP Interface
5.6.4 Local Expansion Bus
5.6.5 IEEE 1588, and GCU
6.0 Reset and Power Management
6.1 Reset and Powergood Distribution
6.1.1 Types of Reset
6.1.1.1 Powergood Implementation
6.1.1.2 Hard Reset Implementation
6.1.1.3 Software Controlled Reset
6.1.1.4 CPU Only Reset Implementation
6.1.1.5 S-state Wake Events
6.1.1.6 Targeted Reset Implementation
6.1.2 Platform Reset and Powergood
6.1.2.1 Platform Powergood
6.1.2.2 Platform Reset
6.1.2.3 Reset and Powergood Distribution
6.1.3 EP80579 Power Sequencing and Reset Sequence
6.2 BIOS Boot Flow (Initialization)
6.2.1 Memory Configuration
6.2.2 Memory Initialization
6.2.3 Boot from Network
6.3 Power Management
6.3.1 Power Management States
6.3.2 Power Management Support
6.3.2.1 Transitioning Between Power States
6.3.2.2 Power State Transition Timing Diagrams
6.3.3 Thermal Sensor
6.3.4 ACPI Implementation
7.0 Register Summary
7.1 Overview of Register Descriptions and Summaries

Datasheet sections

6 Order Number: 320066-003US
7.1.1 Register Description Tables
7.1.2 Register Field Access Attributes
7.1.3 Register Nomenclature and Values
7.2 IA-32 core Registers
7.3 IMCH and IICH Registers
7.3.1 IMCH Registers: Bus 0, Device 0, Function
7.3.2 IMCH Error Reporting Registers: Bus 0, Device 0, Function
7.3.3 EDMA Engine Registers: Bus 0, Device 1, Function
7.3.4 PCI Express* Port A Registers: Bus 0, Device 2, Function
7.3.5 PCI Express* Port A1 Registers: Bus 0, Device 3, Function
7.3.8 Root Complex: Bus 0, Device 31, Function
7.3.9 LPC Interface: Bus 0, Device 31, Function
7.3.10 SATA Controller: Bus 0, Device 31, Function
7.3.11 SMBus Controller: Bus 0, Device 31, Function
7.3.12 IA-32 Core Interface I/O-Mapped Register
7.3.13 IMCH PCI Configuration
7.3.14 APIC
7.3.16 APM Power Management
7.3.17 LPC DMA
7.3.19 High Precision Event Timers
7.3.20 Watchdog Timer and Serial I/O
7.3.21 Real Time Clock
7.4 AIOC Registers
7.4.1 PCI-to-PCI Bridge: Bus 0, Device 4, Function
7.4.2 Gigabit Ethernet MAC: Bus M, Devices 0, 1, and 2, Function
7.4.3 GCU: Bus M, Device 3, Function
7.4.4 CAN Interface: Bus M, Device 4 and 5, Function
7.4.5 SSP Interface: Bus M, Device 6, Function
7.4.6 IEEE 1588 Timestamp Unit: Bus M, Device 7, Function
7.4.7 Local Expansion Bus Interface: Bus M, Device 8, Function 0:
8.0 IA-32 Core
8.1 Overview
8.2 Theory of Operation
8.2.1 L2 Cache Size
8.2.2 Platform and JTAG Identifiers
8.2.3 FSB Physical Interface
8.2.4 IA-32 Core and FSB Frequency
9.0 CMI Introduction
9.1 System Architecture
9.2 PCI Express*
9.2.1 Supported PCI Express Configurations
9.2.1.1 Low power SKU with PCI Express ports removed
9.3 Supported Debug and Management Interfaces
9.4 Supported IMCH Integrated Features
9.4.1 EDMA Controller

Datasheet sections

9.4.2 Integrated Memory Init/Test Engine
9.4.3 Coherent Memory Write Buffer
9.4.4 RASUM Features
9.4.4.1 SEC-DED ECC
9.4.4.2 Integrated Memory Scrub Engine
9.5 IMCH Feature List
9.5.1 Memory Interface
9.5.2 PCI Express Interface in IMCH
9.5.3 EDMA Controller
9.5.4 Coherent Memory Write Buffer
9.5.5 Integrated Memory Scrub Engine
9.5.6 Hardware Memory Initialization Engine
9.5.7 System Management Functions
9.5.8 RASUM
9.6 IICH Feature List
9.6.1 Low-Pin count (LPC) Interface and Fi rmware Hub (FWH) Interface
9.6.2 Serial Peripheral Interface (SPI)
9.6.3 Integrated Serial ATA Host Controllers
9.6.4 USB
9.6.5 Interrupt Controller
9.6.6 Power Management Logic
9.6.7 DMA Controller
9.6.8 Timers Based on 82C54
9.6.9 High Precision Event Timers (HPET)
9.6.10 Real-Time Clock with 256-byte Battery-backed CMOS RAM
9.6.11 System TCO Reduction Circuits
9.6.12 SMBus
9.6.13 Watchdog Timer
9.6.14 Serial Port
9.6.15 GPIO
10.0 System Address Map
10.1 Overview
10.1.1 System Memory Spaces
10.1.2 VGA and MDA Memory Spaces
10.1.3 PAM Memory Spaces
10.1.4 TSEG SMM Memory Space
10.1.5 PCI Express Enhanced Configuration Aperture
10.1.6 IOAPIC Memory Space
10.1.7 FSB Interrupt Memory Space
10.1.8 High SMM Memory Space
10.1.9 PCI Device Memory (MMIO)
10.1.9.1 Device 2 Memory and Prefetchable Memory
10.1.9.2 Device 3 Memory and Prefetchable Memory
10.1.9.3 Device 4 Memory and Prefetchable Memory
10.2 IMCH Responses to EDMA Transactions
10.2.1 Fixed Address Spaces (EDMA)
10.2.2 Relocatable Address Spaces (EDMA)
10.3 I/O Address Space
10.3.1 Configuration Window
10.3.2 VGA and MDA Regions
10.4 Main Memory Addressing
10.5 System Management Mode (SMM) Space
10.5.1 SMM Addressing Ranges
10.5.1.1 SMM Space Restrictions

Datasheet sections

8 Order Number: 320066-003US
10.5.1.2 SMM Space Definition
10.6 Memory Reclaim Background
10.6.1 Memory Remapping Algorithm
10.7 IICH Register and Memory Mappings
10.7.1 I/O Map
10.7.1.1 Fixed I/O Address Ranges
10.7.1.2 Variable I/O Decode Ranges
10.7.2 Memory Map
10.7.3 Boot-Block Update Scheme
11.0 System Memory Controller
11.1 Overview
11.2 Memory Controller Feature List
11.3 Configurations
11.3.1 Rules for Populating DIMM Slots
11.3.2 DRAM Addressing
11.3.3 Memory Address Translation Tables
11.3.3.1 DDR2 Address Translation Tables
11.3.4 DRAM Timings
11.3.5 DQ/DQS Mapping
11.4 DDR2 Features
11.4.1 Interface Signalling Voltage
11.4.2 On-DIMM Die Termination (ODT)
11.4.2.1 ODT Control of Reads
11.4.2.2 ODT Control of Writes
11.4.3 On-Die Termination (ODTZ) on the EP80579
11.4.4 Refresh
11.4.5 Self-Refresh
11.4.6 RCOMP
11.4.7 DDR2 MR and EMR settings
11.4.8 Scrubbing Support
11.4.8.1 Demand Scrubbing
11.4.8.2 Background Scrubbing
11.5 Error Handling
12.0 Enhanced Direct Memory Access Controller (EDMA)
12.1 Overview
12.1.1 Features
12.1.2 Logical Block Diagram
12.2 Channel Programming Interface
12.3 Chaining Operation
12.3.1 Chain Descriptor Definition
12.3.2 DMA Chain Descriptor in Memory
12.3.3 Chain Descriptor Usage
12.3.4 Scatter/Gather Transfer
12.3.5 Appending to a Descriptor Chain
12.3.6 Splicing a Descriptor Chain into a Linked List
12.4 Transfer Types
12.4.1 Local Memory to Local Memory
12.4.2 Local Memory to I/O Subsystem Memory
12.4.3 I/O Memory to Local Memory
12.4.4 I/O Memory to I/O Memory
12.5 Addressing
12.5.1 Address Coherence

Datasheet sections

12.5.2 Addressing Modes
12.5.2.1 Standard Byte Movement Mode
12.5.2.2 Decrement/Byte Reversal Mode
12.5.2.3 Constant Address Modes
12.5.2.4 Buffer and Memory Initialization Modes
12.5.3 PCI Express Traffic Class
12.6 Channel Data Queuing
12.7 Error Conditions
12.7.1 Controller Interface Error
12.7.2 Memory Interface Error
12.7.3 I/O Interface Error
12.8 Channel Arbitration
12.8.1 Normal Arbitration Scheme
12.8.2 Prioritized Arbitration Scheme
12.9 Configuration
12.9.1 Power Up/Default Status
12.9.2 Channel-Specific Register Definitions
12.9.2.1 Channel Control Register – CCR
12.9.2.2 Channel Status Register – CSR
12.9.2.3 Current Descriptor Address Register – CDAR
12.9.2.4 Current Descriptor Upper Address Register – CDUAR
12.9.2.5 Source Address Register – SAR
12.9.2.6 Source Upper Address Register – SUAR
12.9.2.7 Destination Address Register – DAR
12.9.2.8 Destination Upper Address Register – DUAR
12.9.2.9 Next Descriptor Address Register – NDAR
12.9.2.10 Next Descriptor Upper Address Register – NDUAR
12.9.2.11 Transfer Count Register – TCR
12.9.2.12 Descriptor Control Register – DCR
12.10 Interrupts
12.10.1 Interrupt Routing Mechanisms
12.10.2 Message Signaled Interrupt (MSI)
12.10.2.1 MSI Control Register – MSICR
12.10.2.2 MSI Address Register – MSIAR
12.10.2.3 MSI Data Register – MSIDR
12.10.3 Interrupt Ordering
12.10.3.1 Interrupt Ordering for Memory Destination
12.10.3.2 Interrupt Ordering for Outbound Destination
12.11 Initiating an EDMA Transfer
12.11.1 Setup and Initiation
12.11.2 Suspend Function
12.11.3 Stop Function
12.11.4 EDMA Process Flow
13.0 Platform Configuration
13.1 RASUM Features - SMBus Access
13.2 Platform Configuration Structure Conceptual Overview
13.2.1 IMCH PCI Devices
13.2.2 IICH PCI Devices
13.3 Routing Configuration Accesses
13.3.1 Standard PCI Bus Configuration Mechanism
13.3.2 PCI Bus #0 Configuration Mechanism
13.3.3 Primary PCI and Downstream Configuration Mechanism
13.3.4 IMCH PCI Express Bus Configuration Mechanism
13.3.5 IMCH Configuration Cycle Flow Chart
13.4 IMCH Register Introduction
13.5 IMCH Sticky Registers

Datasheet sections

10 Order Number: 320066-003US
13.6 IMCH I/O Mapped Registers
13.6.0.1 Offset 0CF8h: CONFIG_ADDRESS - Configuration Address Register
13.6.0.2 Offset 0CFCh: CONFIG_DATA - Configuration Data Register
13.7 IMCH Memory Mapped Registers
13.8 PCI Express Enhanced Configuration Mechanisms
13.8.1 PCI Express Configuration Transaction Header
13.8.2 Enhanced Configuration Hardware Implications
13.8.3 Enhanced Configuration Memory Address Map
13.8.4 Enhanced Configuration FSB Address Format
14.0 RAS Features and Exception Handling
14.1 RAS Features
14.1.1 Data Protection
14.1.1.1 DRAM ECC
14.1.1.2 PCI Express Interface
14.1.1.3 Data Error Propagation Between Interfaces/Units
14.1.2 DRAM Data Integrity
14.1.2.1 Periodic Memory Scrubbing
14.1.2.2 DRAM Hardware Initialization
14.1.2.3 Uncorrectable Retries
14.1.2.4 DRAM Refresh
14.1.2.5 DDR I/O Hardware Assisted Calibration
14.1.3 PCI Express Data Integrity
14.1.3.1 PCI Express Training
14.1.3.2 PCI Express Retry
14.1.3.3 PCI Express Recovery
14.1.3.4 PCI Express Retrain
14.1.4 Test/Support Major Buses
14.1.4.1 IICH XOR
14.1.4.2 SMB (IMCH)
14.1.4.3 SMB (IICH)
14.1.4.4 I2C
14.2 Exception Handling
14.2.1 FERR/NERR Global Register Scheme
14.2.1.1 FERR/NERR Unit Registers
14.2.1.2 Clearing FERR/NERR Registers
14.2.1.3 FERR/NERR Unit Specific
14.2.1.4 SERR/SMI/SCI Enabling Registers
14.2.1.5 MCERR Enabling Registers
14.2.1.6 Error Escalation Register
14.2.1.7 Error Masking
14.2.1.8 PCI Express Errors and Errors on Behalf of PCI Express
14.2.1.9 Configurable Error Containment at the Legacy Interface
14.3 Error Conditions Signaled
15.0 Platform Management (IMCH)
15.1 Integrated SMBus Interface
15.2 SMBus Target Architecture
15.2.1 High Level Operation
15.2.1.1 SMBus Register Summary
15.2.1.2 Internal Register Access Mechanism
15.2.1.3 SMBus Register Definitions
15.2.1.4 Unsupported Access Addresses
15.2.1.5 SMBus Transaction Pictograms
15.2.2 Suggested SMBus Usage Models
15.2.2.1 Remote Error Handling
15.2.2.2 Remote Platform Monitoring
15.3 Platform Power Management Support

Datasheet sections

15.3.1 Supported System Power States
15.3.1.1 Supported CPU Power States
15.3.1.2 Supported Device Power States
15.3.1.3 Supported Bus Power States
15.3.2 DDR2 Interface Power Management
15.3.3 PCI Express Interface Power Management
15.3.3.1 PCI Express Link Power State Definitions
15.3.3.2 Software Controlled PCI Express Link States
15.3.3.3 Hardware Controlled PCI Express Link States
15.3.3.4 System Clocking Solution Dependencies
15.3.3.5 Device and Link PM Initialization
15.3.4 Device and Slot Power Limits
15.3.5 PME Support
15.3.5.1 PME Wake Signaling
15.3.5.2 PME Messaging
15.3.6 BIOS Support for PCI Express PM Messaging
15.3.6.1 PCI Express PME_TURN_OFF Semantic
16.0 IMCH Registers
16.1 IMCH Registers: Bus 0, Device 0, Function
16.1.1 Register Details
16.1.1.1 Offset 00h: VID – Vendor Identification Register
16.1.1.2 Offset 02h: DID – Device Identification Register
16.1.1.3 Offset 04h: PCICMD: PCI Command Register
16.1.1.4 Offset 06h: PCISTS: PCI Status Register
16.1.1.5 Offset 08h: RID - Revision Identification Register
16.1.1.6 Offset 0Ah: SUBC - Sub-Class Code Register
16.1.1.7 Offset 0Bh: BCC – Base Class Code Register
16.1.1.8 Offset 0Eh: HDR - Header Type Register
16.1.1.9 Offset 14h: SMRBASE - System Memory RCOMP Base
16.1.1.10 Offset 2Ch: SVID - Subsystem Vendor Identification Register
16.1.1.11 Offset 2Eh: SID - Subsystem Identification Register
16.1.1.12 Offset 4Ch: NSIBAR - Root Complex Block Address Register
16.1.1.13 Offset 50h: CFG0 - IMCH Configuration 0 Register
16.1.1.14 Offset 51h: IMCH_CFG1 – IMCH Configuration 1 Register
16.1.1.15 Offset 53h: CFGNS1 - Configuration 1 Register
16.1.1.16 Offset 58h: FDHC - Fixed DRAM Hole Control Register
16.1.1.17 Offset 59h: PAM0 - Programmable Attribute Map 0 Register
16.1.1.18 Offset 5Ah: PAM1 - Programmable Attribute Map 1 Register
16.1.1.19 Offset 5Bh: PAM2 - Programmable Attribute Map 2 Register
16.1.1.20 Offset 5Ch: PAM3 - Programmable Attribute Map 3 Register
16.1.1.21 Offset 5Dh: PAM4 - Programmable Attribute Map 4 Register
16.1.1.22 Offset 5Eh: PAM5 - Programmable Attribute Map 5 Register
16.1.1.23 Offset 5Fh: PAM6 - Programmable Attribute Map 6 Register
16.1.1.24 Offset 9Ch: DEVPRES - Device Present Register
16.1.1.26 Offset 9Eh: SMRAM - System Management RAM Control Register
16.1.1.27 Offset 9Fh: EXSMRAMC - Expansion System Management RAM Control
16.1.1.28 Offset B8h: IMCH_MENCBASE - IA/ASU Shared Non-Coherent (AIOC-Direct)
16.1.1.29 Offset BCh: IMCH_MENCLIMIT - IA/ASU Shared Non-Coherent (AIOC-Direct)
16.1.1.30 Offset C4h: TOLM - Top of Low Memory Register
16.1.1.31 Offset C6h: REMAPBASE - Remap Base Address Register
16.1.1.32 Offset C8h: REMAPLIMIT – Remap Limit Address Register
16.1.1.33 Offset CAh: REMAPOFFSET - Remap Offset Register

Datasheet sections

12 Order Number: 320066-003US
16.1.1.34 Offset CCh: TOM - Top Of Memory Register
16.1.1.35 Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced Configuration
16.1.1.36 Offset D8h: CACHECTL0 - Write Cache Control 0 Register
16.1.1.37 Offset DEh: SKPD - Scratchpad Data Register
16.1.1.38 Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register
16.1.1.39 Offset 60h: DRB[0-3] – DRAM Row [3:0] Boundary Register
16.1.1.40 Offset 70h: DRA[0-1] – DRAM Row [0:1] Attribute Register
16.1.1.41 Offset 78h: DRT0 - DRAM Timing Register
16.1.1.42 Offset 64h: DRT1 – DRAM Timing Register
16.1.1.43 Offset 7Ch: DRC – DRAM Controller Mode Register
16.1.1.44 Offset 84h: ECCDIAG – ECC Detection/Correction
16.1.1.45 Offset 88h: SDRC – DDR SDRAM Secondary Control Register
16.1.1.46 Offset 8Ch: CKDIS – CK/CK# Clock Disable Register
16.1.1.47 Offset 8Dh: CKEDIS - CKE Clock Disable Register
16.1.1.48 Offset 90h: SPARECTL - SPARE Control Register
16.1.1.49 Offset B0h: DDR2ODTC - DDR2 ODT Control Register
16.2 DRAM Controller Error Reporting Registers: Bus 0, Device 0, Function
16.2.1 Register Details
16.2.1.1 Offset 00h: VID - Vendor Identification Register
16.2.1.2 Offset 02h: DID - Device Identification Register
16.2.1.3 Offset 04h: PCICMD - PCI Command Register
16.2.1.4 Offset 06h: PCISTS - PCI Status Register
16.2.1.5 Offset 08h: RID - Revision Identification Register
16.2.1.6 Offset 0Ah: SUBC - Sub-Class Code Register
16.2.1.7 Offset 0Bh: BCC - Base Class Code Register
16.2.1.8 Offset 0Dh: MLT - Master Latency Timer Register
16.2.1.9 Offset 0Eh: HDR - Header Type Register
16.2.1.10 Offset 2Ch: SVID - Subsystem Vendor Identification Register
16.2.1.11 Offset 2Eh: SID - Subsystem Identification Register
16.2.1.12 Offset 40h: GLOBAL_FERR - Global First Error Register
16.2.1.13 Offset 44h: GLOBAL_NERR - Global Next Error Register
16.2.1.14 Offset 48h: NSI_FERR - NSI First Error Register
16.2.1.15 Offset 4Ch: NSI_NERR - NSI Next Error Register
16.2.1.16 Offset 50h: NSI_SCICMD - NSI SCI Command Register
16.2.1.17 Offset 54h: NSI_SMICMD - NSI SMI Command Register
16.2.1.18 Offset 58h: NSI_SERRCMD - NSI SERR Command Register
16.2.1.19 Offset 5Ch: NSI_MCERRCMD - NSI MCERR Command Register
16.2.1.20 Offset 60h: FSB_FERR - FSB First Error Register
16.2.1.21 Offset 62h: FSB_NERR - FSB Next Error Register
16.2.1.22 Offset 64h: FSB_EMASK - FSB Error Mask Register
16.2.1.23 Offset 68h: FSB_SCICMD - FSB SCI Command Register
16.2.1.24 Offset 6Ah: FSB_SMICMD - FSB SMI Command Register
16.2.1.25 Offset 6Ch: FSB_SERRCMD - FSB SERR Command Register
16.2.1.26 Offset 6Eh: FSB_MCERRCMD - FSB MCERR Command Register
16.2.1.27 Offset 70h: BUF_FERR - Memory Buffer First Error Register
16.2.1.28 Offset 72h: BUF_NERR - Memory Buffer Next Error Register
16.2.1.29 Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register
16.2.1.30 Offset 78h: BUF_SCICMD - Memory Buffer SCI Command Register
16.2.1.31 Offset 7Ah: BUF_SMICMD - Memory Buffer SMI Command Register
16.2.1.32 Offset 7Ch: BUF_SERRCMD - Memory Buffer SERR
16.2.1.33 Offset 7Eh: BUF_MCERRCMD - Memory Buffer MCERR
16.2.1.34 Offset E4h: NSIERRINJCTL - NSI Error Injection Control Register
16.2.1.35 Offset E8h: BERRINJCTL - Buffer Error Injection Control Register
16.2.1.36 Offset 80h: DRAM_FERR - DRAM First Error Register
16.2.1.37 Offset 82h: DRAM_NERR - DRAM Next Error Register
16.2.1.38 Offset 84h: DRAM_EMASK - DRAM Error Mask Register

Datasheet sections

16.2.1.39 Offset 88h: DRAM_SCICMD - DRAM SCI Command Register
16.2.1.40 Offset 8Ah: DRAM_SMICMD - DRAM SMI Command Register
16.2.1.41 Offset 8Ch: DRAM_SERRCMD - DRAM SERR Command Register
16.2.1.42 Offset 8Eh: DRAM_MCERRCMD - DRAM MCERR Command Register
16.2.1.43 Offset 98h: THRESH_SEC0 - Rank 0 SEC Error
16.2.1.44 Offset 9Ah: THRESH_SEC1 - Rank 1 SEC Error
16.2.1.45 Offset A0h: DRAM_SECF_ADD - DRAM First Single Bit Error Correct Address
16.2.1.46 Offset A4h: DRAM_DED_ADD - DRAM Double Bit Error
16.2.1.47 Offset A8h: DRAM_SCRB_ADD - DRAM Scrub Error
16.2.1.48 Offset B0h: DRAM_SEC_R0 - DRAM Rank 0 SEC Error
16.2.1.49 Offset B2h: DRAM_DED_R0 - DRAM Rank 0 DED Error
16.2.1.50 Offset B4h: DRAM_SEC_R1 - DRAM Rank 1 SEC Error
16.2.1.51 Offset B6h: DRAM_DED_R1 - DRAM Rank 1 DED Error
16.2.1.52 Offset C2h: THRESH_DED - DED Error Threshold Register
16.2.1.53 Offset C4h: DRAM_SECF_SYNDROME - DRAM First Single Error Correct
16.2.1.54 Offset C6h: DRAM_SECN_SYNDROME - DRAM Next Single Error Correct
16.2.1.55 Offset C8h: DRAM_SECN_ADD - DRAM Next Single Bit Error Correct Address
16.2.1.56 Offset DCh: RANKTHREX - Rank Error Threshold Exceeded Register
16.2.1.57 Offset ECh: DERRINJCTL - DRAM Error Injection Control Register
16.3 EDMA Registers: Bus 0, Device 1, Function
16.3.1 Register Details
16.3.1.1 Offset 00h: VID - Vendor Identification Register
16.3.1.2 Offset 02h: DID - Device Identification Register
16.3.1.3 Offset 04h: PCICMD - PCI Command Register
16.3.1.4 Offset 06h: PCISTS - PCI Status Register
16.3.1.5 Offset 08h: RID - Revision Identification Register
16.3.1.6 Offset 0Ah: SUBC - Sub-Class Code Register
16.3.1.7 Offset 0Bh: BCC - Base Class Code Register
16.3.1.8 Offset 0Eh: HDR - Header Type Register
16.3.1.9 Offset 10h: EDMALBAR - EDMA Low Base Address Register
16.3.1.10 Offset 2Ch: SVID - Subsystem Vendor Identification Register
16.3.1.11 Offset 2Eh: SID - Subsystem Identification Register
16.3.1.12 Offset 34h: CAPPTR - Capabilities Pointer Register
16.3.1.13 Offset 3Ch: INTRLINE - Interrupt Line Register
16.3.1.14 Offset 3Dh: INTRPIN - Interrupt Pin Register
16.3.1.15 Offset 40h: EDMACTL - EDMA Control Register
16.3.1.16 Offset 80h: EDMA_FERR - EDMA First Error Register
16.3.1.17 Offset 84h: EDMA_NERR - EDMA Next Error Register
16.3.1.18 Offset 88h: EDMA_EMASK - EDMA Error Mask Register
16.3.1.19 Offset A0h: EDMA_SCICMD - EDMA SCI Command Register
16.3.1.20 Offset A4h: EDMA_SMICMD - EDMA SMI Command Register
16.3.1.21 Offset A8h: EDMA_SERRCMD - EDMA SERR Command Register
16.3.1.22 Offset ACh: EDMA_MCERRCMD - EDMA MCERR Command Register
16.3.1.23 Offset B0h: MSICR - MSI Control Register
16.3.1.24 Offset B4h: MSIAR - MSI Address Register
16.3.1.25 Offset B8h: MSIDR - MSI Data Register
16.4 PCI Express* Port A Standard and Enhanced Registers: Bus 0,

Datasheet sections

14 Order Number: 320066-003US
16.4.1 Register Details
16.4.1.1 Offset 00h: VID - Vendor Identification Register
16.4.1.2 Offset 02h: DID - Device Identification Register
16.4.1.3 Offset 02h: DID - Device Identification Register
16.4.1.4 Offset 04h: PCICMD - PCI Command Register
16.4.1.5 Offset 06h: PCISTS - PCI Status Register
16.4.1.6 Offset 08h: RID - Revision Identification Register
16.4.1.7 Offset 0Ah: SUBC - Sub-Class Code Register
16.4.1.8 Offset 0Bh: BCC - Base Class Code Register
16.4.1.9 Offset 0Ch: CLS - Cache Line Size Register
16.4.1.10 Offset 0Eh: HDR - Header Type Register
16.4.1.11 Offset 18h: PBUSN - Primary Bus Number Register
16.4.1.12 Offset 19h: SBUSN - Secondary Bus Number Register
16.4.1.13 Offset 1Ah: SUBUSN - Subordinate Bus Number Register
16.4.1.14 Offset 1Ch: IOBASE - I/O Base Address Register
16.4.1.15 Offset 1Dh: IOLIMIT - I/O Limit Address Register
16.4.1.16 Offset 1Eh: SECSTS - Secondary Status Register
16.4.1.17 Offset 20h: MBASE - Memory Base Address Register
16.4.1.18 Offset 22h: MLIMIT - Memory Limit Address Register
16.4.1.19 Offset 24h: PMBASE - Prefetchable Memory Base Address Register
16.4.1.20 Offset 26h: PMLIMIT - Prefetchable Memory Limit Address Register
16.4.1.21 Offset 28h: PMBASU - Prefetchable Memory Base
16.4.1.22 Offset 2Ch: PMLMTU - Prefetchable Memory Limit Upper
16.4.1.23 Offset 34h: CAPPTR - Capabilities Pointer Register
16.4.1.24 Offset 3Ch: INTRLINE - Interrupt Line Register
16.4.1.25 Offset 3Dh: INTRPIN - Interrupt Pin Register
16.4.1.26 Offset 3Eh: BCTRL - Bridge Control Register
16.4.1.27 Offset 44h: VSCMD0 - Vendor Specific Command Byte 0 Register
16.4.1.28 Offset 45h: VSCMD1 - Vendor Specific Command Byte 1 Register
16.4.1.29 Offset 46h: VSSTS0 - Vendor Specific Status Byte 0 Register
16.4.1.30 Offset 47h: VSSTS1 - Vendor Specific Status Byte 1 Register
16.4.1.31 Offset 48h: VSCMD2 - Vendor Specific Command Byte 2 Register
16.4.1.32 Offset 50h: PMCAPID - Power Management Capabilities
16.4.1.33 Offset 51h: PMNPTR - Power Management Next Capabilities Pointer Register
16.4.1.34 Offset 52h: PMCAPA - Power Management Capabilities
16.4.1.35 Offset 54h: PMCSR - Power Management Status and Control
16.4.1.36 Offset 56h: PMCSRBSE - Power Ma nagement Status and Control Bridge
16.4.1.37 Offset 58h: MSICAPID - MSI Capabilities Structure Register
16.4.1.38 Offset 59h: MSINPTR - MSI Next Capabilities Pointer Register
16.4.1.39 Offset 5Ah: MSICAPA - MSI Capabilities Register
16.4.1.40 Offset 5Ch: MSIAR - MSI Address for PCI Express* Register
16.4.1.41 Offset 60h: MSIDR - MSI Data Register
16.4.1.42 Offset 64h: PEACAPID - PCI Express* Features Capabilities ID
16.4.1.43 Offset 65h: PEANPTR - PCI Express* Next Capabilities Pointer
16.4.1.44 Offset 66h: PEACAPA - PCI Express* Features Capabilities Register
16.4.1.45 Offset 68h: PEADEVCAP - PCI Express* Device Capabilities
16.4.1.46 Offset 6Ch: PEADEVCTL - PCI Express* Device Control Register
16.4.1.47 Offset 6Eh: PEADEVSTS - PCI Express* Device Status Register
16.4.1.48 Offset 70h: PEALNKCAP - PCI Express* Link Capabilities Register
16.4.1.49 Offset 70h: PEA1LNKCAP - PCI Express* Link Capabilities Register

Datasheet sections

16.4.1.50 Offset 74h: PEALNKCTL - PCI Express* Link Control Register
16.4.1.51 Offset 76h: PEALNKSTS - PCI Express* Link Status Register
16.4.1.52 Offset 78h: PEASLTCAP - PCI Express* Slot Capabilities Register
16.4.1.53 Offset 78h: PEA1SLTCAP - PCI Express* Slot Capabilities Register
16.4.1.54 Offset 7Ch: PEASLTCTL - PCI Express* Slot Control Register
16.4.1.55 Offset 7Eh: PEASLTSTS - PCI Express* Slot Status Register
16.4.1.56 Offset 80h: PEARPCTL - PCI Express* Root Port Control Register
16.4.1.57 Offset 84h: PEARPSTS - PCI Express* Root Port Status Register
16.4.1.58 Offset 100h: ENHCAPST - Enhanced Capability Structure Register
16.4.1.59 Offset 104h: UNCERRSTS - Uncorrect able Error Status Register
16.4.1.60 Offset 108h: UNCERRMSK - Uncorrectable Error Mask Register
16.4.1.61 Offset 10Ch: UNCERRSEV - Uncorrectable Error Severity Register
16.4.1.62 Offset 110h: CORERRSTS - Correctable Error Status Register
16.4.1.63 Offset 114h: CORERRMSK - Correctable Error Mask Register
16.4.1.64 Offset 118h: AERCACR - Advanced Error Capabilities and
16.4.1.65 Offset 11Ch: HDRLOG0 - Header Log DW 0 (1st 32 bits) Register
16.4.1.66 Offset 120h: HDRLOG1 - Header Log DW 1 (2nd 32 bits) Register
16.4.1.67 Offset 124h: HDRLOG2 - Header Log DW 2 (3rd 32 bits) Register
16.4.1.68 Offset 128h: HDRLOG3 - Header Log DW 3 (4th 32 bits) Register
16.4.1.69 Offset 12Ch: RPERRCMD - Root (Port) Error Command Register
16.4.1.70 Offset 130h: RPERRMSTS - Root (Port) Error Message Status
16.4.1.71 Offset 134h: ERRSID - Error Source ID Register
16.4.1.72 Offset 140h: PEAUNITERR - PCI Express* Unit Error Register
16.4.1.73 Offset 144h: PEAMASKERR - PCI Express* Unit Mask Error
16.4.1.74 Offset 148h: PEAERRDOCMD - PCI Express* Error Do
16.4.1.75 Offset 14Ch: UNCEDMASK - Uncorrectable Error Detect Mask
16.4.1.76 Offset 150h: COREDMASK - Correctable Error Detect Mask
16.4.1.77 Offset 158h: PEAUNITEDMASK - PCI Express* Unit Error Detect Mask Register
16.4.1.78 Offset 160h: PEAFERR - PCI Express* First Error Register
16.4.1.79 Offset 164h: PEANERR - PCI Express* Next Error Register
16.4.1.80 Offset 168h: PEAERRINJCTL - Error Injection Control Register
16.5 Memory Mapped I/O Registers for DRAM Controller
16.5.1 Detailed Register Description
16.5.1.1 Offset 00h: NOTESPAD - Note (Sticky) Pad for BIOS Support
16.5.1.2 Offset 02h: NOTEPAD - Note Pad for BIOS Support Register
16.5.1.3 Offset 40h: DCALCSR – DDR Calibration Control and Status
16.5.1.4 Offset 44h: DCALADDR - DDR Calibration Address Register
16.5.1.5 Offset 48h: DCALDATA[0-71] - DRAM Calibration Data Registers
16.5.1.6 Offset 94h: RCVENAC - Receiver Enable Algorithm Control
16.5.1.7 Offset 98h: DSRETC - DRAM Self-Refresh (SR) Extended Timing and Control
16.5.1.8 Offset 9Ch: DQSFAIL1 - DQSFAIL1 Configuration Register
16.5.1.9 Offset A0h: DQSFAIL0 - DQSFAIL0 Configuration Register
16.5.1.10 DRRTC: Receive Enable Reference Output Timing Control Registers
16.5.1.11 Offset A4h: DRRTC00 - Receive Enable Reference Output Timing Control
16.5.1.12 Offset A8h: DRRTC01 - Receive Enable Reference Output Timing Control
16.5.1.13 Offset C4h: DRRTC02 - Receive Enable Reference Output Timing Control

Datasheet sections

16 Order Number: 320066-003US
16.5.1.14 DQS Calibration Registers
16.5.1.15 Offset B4h: DQSOFCS00 - DQS Calibration Register
16.5.1.16 Offset B8h: DQSOFCS01 - DQS Calibration Register
16.5.1.17 Offset C6h: DQSOFCS02 - DQS Calibration Register
16.5.1.18 Offset BCh: DQSOFCS10 - DQS Calibration Register
16.5.1.19 Offset C0h: DQSOFCS11 - DQS Calibration Register
16.5.1.20 Offset C7h: DQSOFCS12 - DQS Calibration Register
16.5.1.21 WPTRTC DDR I/O Write Pointer Timing
16.5.1.22 Offset CCh: WPTRTC0 - Write Pointer Timing Control 0 Register
16.5.1.23 Offset D0h: WPTRTC1 - Write Pointer Timing Control 1 Register
16.5.1.24 DDQSCVDP and DDQSCADP
16.5.1.25 Offset D4h: DDQSCVDP0 - DQS DELAY CALIBRATION VICTIM PATTERN
16.5.1.26 Offset D8h: DDQSCVDP1 - DQS DELAY CALIBRATION VICTIM PATTERN
16.5.1.27 Offset DCh: DDQSCADP0 - DQS DELAY CALIBRATION AGGRESSOR PATTERN
0 Register
16.5.1.28 Offset E0h: DDQSCADP1 - DQS DELAY CALIBRATION AGGRESSOR PATTERN
1 Register
16.5.1.29 Offset F0h: DIOMON - DDR I/O Monitor Register
16.5.1.30 Offset F8h: DRAMISCTL - Miscellan eous DRAM DDR Cluster Control Register
16.5.1.31 Offset C8h: DRAMDLLC - DDR I/O DLL Control Register
16.5.1.32 Offset E8h: FIVESREG - Fixed 5s Pattern Register
16.5.1.33 Offset ECh: AAAAREG - Fixed As Pattern Register
16.5.1.34 Memory BIST Registers
16.5.1.35 Offset 140h: MBCSR - MemBIST Control Register
16.5.1.36 Offset 144h: MBADDR - Memory Test Address Register
16.5.1.37 Offset 148h: MBDATA[0:9] - Memory Test Data Register
16.5.1.38 Offset 19Ch: MB_START_ADDR - Memory Test Start Address
16.5.1.39 Offset 1A0h: MB_END_ADDR - Memory Test End Address Register
16.5.1.40 Offset 1A4h: MBLFSRSED - Memory Test Circular Shift and LFSR Seed
16.5.1.42 Offset 1B0h: MB_ERR_DATA00 - Memory Test Error Data
16.5.1.43 Offset 1B4h: MB_ERR_DATA01 - Memory Test Error Data
16.5.1.44 Offset 1B8h: MB_ERR_DATA02 - Memory Test Error Data
16.5.1.45 Offset 1BCh: MB_ERR_DATA03 - Memory Test Error Data
16.5.1.46 Offset 1C0h: MB_ERR_DATA04 - Memory Test Error Data
16.5.1.47 Offset 1C4h: MB_ERR_DATA10 - Memory Test Error Data
16.5.1.48 Offset 1C8h: MB_ERR_DATA11 - Memory Test Error Data
16.5.1.49 Offset 1CCh: MB_ERR_DATA12 - Memory Test Error Data
16.5.1.50 Offset 1D0h: MB_ERR_DATA13 - Memory Test Error Data
16.5.1.51 Offset 1D4h: MB_ERR_DATA14 - Memory Test Error Data
16.5.1.52 Offset 1D8h: MB_ERR_DATA20 - Memory Test Error Data
16.5.1.53 Offset 1DCh: MB_ERR_DATA21 - Memory Test Error Data
16.5.1.54 Offset 1E0h: MB_ERR_DATA22 - Memory Test Error Data
16.5.1.55 Offset 1E4h: MB_ERR_DATA23 - Memory Test Error Data
16.5.1.56 Offset 1E8h: MB_ERR_DATA24 - Memory Test Error Data
16.5.1.57 Offset 1ECh: MB_ERR_DATA30 - Memory Test Error Data
16.5.1.58 Offset 1F0h: MB_ERR_DATA31 - Memory Test Error Data
16.5.1.59 Offset 1F4h: MB_ERR_DATA32 - Memory Test Error Data
16.5.1.60 Offset 1F8h: MB_ERR_DATA33 - Memory Test Error Data
16.5.1.61 Offset 1FCh: MB_ERR_DATA34 - Memory Test Error Data
16.5.1.62 Offset 260h: DDRIOMC0 - DDR IO Mode Control Register
16.5.1.63 Offset 264h: DDRIOMC1 - DDR IO Mode Control Register
16.5.1.64 Offset 268h: DDRIOMC2 - DDR IO Mode Control Register
16.5.1.65 Offset 284h: WL_CNTL[4:0] - Write Levelization[4:0] Control

Datasheet sections

16.5.1.66 Offset 298h: WDLL_MISC - DLL Miscellaneous Control
16.6 Memory Mapped I/O for EDMA Registers
16.6.1 Register Details
16.6.1.1 Offset 00h: CCR0 - Channel 0 Channel Control Register
16.6.1.2 Offset 04h: CSR0 - Channel 0 Channel Status Register
16.6.1.3 Offset 08h: CDAR0 - Channel 0 Current Descriptor Address
16.6.1.4 Offset 0Ch: CDUAR0 - Channel 0 Current Descriptor Upper Address Register
16.6.1.5 Offset 10h: SAR0 - Channel 0 Source Address Register
16.6.1.6 Offset 14h: SUAR0 - Channel 0 Source Upper Address Register
16.6.1.7 Offset 18h: DAR0 - Channel 0 Destination Address Register
16.6.1.8 Offset 1Ch: DUAR0 - Channel 0 Destination Upper Address
16.6.1.9 Offset 20h: NDAR0 - Channel 0 Next Descriptor Address Register
16.6.1.10 Offset 24h: NDUAR0 - Channel 0 Next Descriptor Upper
16.6.1.11 Offset 28h: TCR0 - Channel 0 Transfer Count Register
16.6.1.12 Offset 2Ch: DCR0 - Channel 0 Descriptor Control Register
16.6.1.13 Offset 40h: CCR1 - Channel 1 Channel Control Register
16.6.1.14 Offset 44h: CSR1 - Channel 1 Channel Status Register
16.6.1.15 Offset 48h: CDAR1 - Channel 1 Current Descriptor Address
16.6.1.16 Offset 4Ch: CDUAR1 - Channel 1 Current Descriptor Upper Address Register
16.6.1.17 Offset 50h: SAR1 - Channel 1 Source Address Register
16.6.1.18 Offset 54h: SUAR1 - Channel 1 Source Upper Address Register
16.6.1.19 Offset 58h: DAR1 - Channel 1 Destination Address Register
16.6.1.20 Offset 5Ch: DUAR1 - Channel 1 Destination Upper Address
16.6.1.21 Offset 60h: NDAR1 - Channel 1 Next Descriptor Address Register
16.6.1.22 Offset 64h: NDUAR1 - Channel 1 Next Descriptor Upper
16.6.1.23 Offset 68h: TCR1 - Channel 1 Transfer Count Register
16.6.1.24 Offset 6Ch: DCR1 - Channel 1 Descriptor Control Register
16.6.1.25 Offset 80h: CCR2 - Channel 2 Channel Control Register
16.6.1.26 Offset 84h: CSR2 - Channel 2 Channel Status Register
16.6.1.27 Offset 88h: CDAR2 - Channel 2 Current Descriptor Address
16.6.1.28 Offset 8Ch: CDUAR2 - Channel 2 Current Descriptor Upper Address Register
16.6.1.29 Offset 90h: SAR2 - Channel 2 Source Address Register
16.6.1.30 Offset 94h: SUAR2 - Channel 2 Source Upper Address Register
16.6.1.31 Offset 98h: DAR2 - Channel 2 Destination Address Register
16.6.1.32 Offset 9Ch: DUAR2 - Channel 2 Destination Upper Address
16.6.1.33 Offset A0h: NDAR2 - Channel 2 Next Descriptor Address Register
16.6.1.34 Offset A4h: NDUAR2 - Channel 2 Next Descriptor Upper
16.6.1.35 Offset A8h: TCR2 - Channel 2 Transfer Count Register
16.6.1.36 Offset ACh: DCR2 - Channel 2 Descriptor Control Register
16.6.1.37 Offset C0h: CCR3 - Channel 3 Channel Control Register
16.6.1.38 Offset C4h: CSR3 - Channel 3 Channel Status Register
16.6.1.39 Offset C8h: CDAR3 - Channel 3 Current Descriptor Address
16.6.1.40 Offset CCh: CDUAR3 - Channel 3 Current Descriptor Upper Address Register
16.6.1.41 Offset D0h: SAR3 - Channel 3 Source Address Register
16.6.1.42 Offset D4h: SUAR3 - Channel 3 Source Upper Address Register

Datasheet sections

18 Order Number: 320066-003US
16.6.1.43 Offset D8h: DAR3 - Channel 3 Destination Address Register
16.6.1.44 Offset DCh: DUAR3 - Channel 3 Destination Upper Address
16.6.1.45 Offset E0h: NDAR3 - Channel 3 Next Descriptor Address Register
16.6.1.46 Offset E4h: NDUAR3 - Channel 3 Next Descriptor Upper
16.6.1.47 Offset E8h: TCR3 - Channel 3 Transfer Count Register
16.6.1.48 Offset ECh: DCR3 - Channel 3 Descriptor Control Register
16.6.1.49 Offset 100h: DCGC - EDMA Controller Global Command
16.6.1.50 Offset 104h: DCGS - EDMA Controller Global Status
16.7 Memory Mapped I/O for NSI Registers
16.7.1 Register Details
16.7.1.1 Offset 00h: NSIVCECH - NSI Virtual Channel Enhanced Capability Header
16.7.1.2 Offset 04h: NSIPVCCAP1 - NSI Port VC Capability Register
16.7.1.3 Offset 08h: NSIPVCCAP2 - Port VC Capability Register
16.7.1.4 Offset 0Ch: NSIPVCCTL - NSI Port VC Control Register
16.7.1.5 Offset 10h: NSIVC0RCAP - NSI VC0 Resource Capability Register
16.7.1.6 Offset 14h: NSIVC0RCTL - NSI VC0 Resource Control Register
16.7.1.7 Offset 1Ah: NSIVC0RSTS - NSI VC0 Resource Status Register
16.7.1.8 Offset 80h: NSIRCILCECH - NSI Root Complex Internal Link Control Enhanced
16.7.1.9 Offset 84h: NSILCAP - NSI Link Capabilities Register
17.0 Bridging and Configuration
17.1 Root Complex Memory-Mapped Configuration Register Details
17.1.1 VC Configuration Registers
17.1.1.1 Offset 0000h: VCH - Virtual Channel Capability Header Register
17.1.1.2 Offset 0004h: VCAP1 - Virtual Channel Capability 1 Register
17.1.1.3 Offset 0008h: VCAP2 - Virtual Channel Capability 2 Register
17.1.1.4 Offset 000Ch: PVC - Port Virtual Channel Control Register
17.1.1.5 Offset 000Eh: PVS - Port Virtual Channel Status Register
17.1.1.6 Offset 0010h: V0CAP - Virtual Channel 0 Resource Capability
17.1.1.7 Offset 0014h: V0CTL - Virtual Channel 0 Resource Control Register
17.1.1.8 Offset 001Ah: V0STS - Virtual Channel 0 Resource Status Register
17.1.2 Root Complex Topology Capability Structure Registers
17.1.2.2 Offset 0104h: ES - Element Self Description Register
17.1.2.3 Offset 0110h: ULD - Upstream Link Description Register
17.1.2.4 Offset 0118h: ULBA - Upstream Link Base Address Register
17.1.3 Internal Link Configuration Registers
17.1.3.1 Offset 01A0h: ILCL - Internal Link Capabilities List Register
17.1.3.2 Offset 01A4h: LCAP - Link Capabilities Register
17.1.3.3 Offset 01A8h: LCTL - Link Control Register
17.1.3.4 Offset 01AAh: LSTS - Link Status Register
17.1.4 TCO Configuration
17.1.4.1 Offset 3000h: TCTL - TCO Control Register
17.1.5 Interrupt Configuration Registers
17.1.5.1 Offset 3100h: D31IP - Device 31 Interrupt Pin Register
17.1.5.2 Offset 3108h: D29IP - Device 29 Interrupt Pin Register
17.1.5.3 Offset 3140h: D31IR - Device 31 Interrupt Route Register
17.1.5.4 Offset 3144h: D29IR - Device 29 Interrupt Route Register
17.1.5.5 Offset 31FFh: OIC - Other Interrupt Control Register
17.1.6 General Configuration Registers

Datasheet sections

17.1.6.1 Offset 3400h: RC - RTC Configuration Register
17.1.6.2 Offset 3404h: HPTC - High Performance Precision Timer Configuration
17.1.6.3 Offset 3410h: GCS: General Control and Status Register
17.1.6.4 Offset 3414h: BUC - Backed Up Control Register
17.1.6.5 Offset 3418h: FD - Function Disable Register
17.1.6.6 Offset 341Ch: PRC - Power Reduction Control Register Clock
18.0 System Management
18.1 Overview
18.2 TCO I/O-Mapped Configuration Register Details
18.2.1 TCO PCI Configuration Registers
18.2.2 Bus 0, Device 31, Function 0: TCO Configuration Register (I/O-Mapped via ABASE
18.2.2.1 Offset 00h: TRLD - TCO Timer Reload and Current Value Register
18.2.2.2 Offset 02h: TDI - TCO Data In Register
18.2.2.3 Offset 03h: TDO - TCO Data Out Register
18.2.2.4 Offset 04h: TSTS1 - TCO 1 Status Register
18.2.2.5 Offset 06h: TSTS2 - TCO 2 STS Register
18.2.2.6 Offset 08h: TCTL1 - TCO 1 Control Register
18.2.2.7 Offset 0Ah: TCTL2 - TCO 2 Control Register
18.2.2.8 Offset 0Ch: TMSG[1-2] - TCO MESSAGE Register
18.2.2.9 Offset 0Eh: TWDS - TCO Watchdog Status Register
18.2.2.10 Offset 10h: LE - Legacy Elimination Register
18.2.2.11 Offset 12h: TTMR - TCO Timer Initial Value Register
18.3 TCO Signal Usage
18.3.1 INTRUDER# Signal
18.3.2 Pin Straps
18.3.3 SMLINK Signals
18.4 TCO Theory of Operation
18.4.1 Overview
18.4.2 Detecting a DOA CPU or System
18.4.3 Handling an Operating System Lockup
18.4.4 Handling a CPU or Other Hardware Lockup
18.4.5 Handling an Intruder
18.4.6 Handling a Potentially Failing Power Supply
18.4.7 Handling an ECC Error or Other Memory Error
18.4.8 SMM to Operating System and Operating System to SMM Calls
18.4.9 Detecting an Improper FWH Programming
18.4.10 IRQ1 and IRQ12 for Legacy Elimination
18.5 Event Reporting via SMLink/SMBus
18.5.1 Overview
18.5.1.1 TCO Compatible Mode
18.5.2 Message Format
18.5.3 Connecting an External LAN Controller
19.0 LPC Interface: Bus 0, Device 31, Function
19.1 Overview
19.2 LPC Interface Configuration Register Details
19.2.1 PCI Configuration Registers
19.2.1.1 Offset 00h: ID: Vendor Identification Register
19.2.1.2 Offset 04h: CMD: Device Command Register
19.2.1.3 Offset 06h: STS: Status Register
19.2.1.4 Offset 08h: RID - Revision ID Register
19.2.1.5 Offset 09h: CC: Class Code Register
19.2.1.6 Offset 0Dh: MLT: Master Latency Timer Register
19.2.1.7 Offset 0Eh: HTYPE: Header Type Register

Datasheet sections

20 Order Number: 320066-003US
19.2.1.8 Offset 2Ch: SID: Subsystem Identifiers Register
19.2.2 ACPI/GPIO Configuration Registers
19.2.2.1 Offset 40h: ABASE: ACPI Base Address Register
19.2.2.2 Offset 44h: ACT: ACPI Control Register
19.2.2.3 Offset 48h: GBA: GPIO Base Address Register
19.2.2.4 Offset 4Ch: GC: GPIO Control Register
19.2.3 Interrupt Configuration Registers
19.2.3.1 Offset 60h: PARC: PIRQA Routing Control Register
19.2.3.2 Offset 61h: PBRC: PIRQB Routing Control Register
19.2.3.3 Offset 62h: PCRC: PIRQC Routing Control Register
19.2.3.4 Offset 63h: PDRC: PIRQD Routing Control Register
19.2.3.5 Offset 64h: SCNT: Serial IRQ Control Register
19.2.3.6 Offset 68h: PERC: PIRQE Routing Control Register
19.2.3.7 Offset 69h: PFRC: PIRQF Routing Control Register
19.2.3.8 Offset 6Ah: PGRC: PIRQG Routing Control Register
19.2.3.9 Offset 6Bh: PHRC: PIRQH Routing Control Register
19.2.4 LPC I/O Configuration Registers
19.2.4.1 Offset 80h: iOD: i/O Decode Ranges Register
19.2.4.2 Offset 82h: IOE: I/O Enables Register
19.2.4.3 Offset 84h: LG1: LPC Generic Decode Range 1 Register
19.2.4.4 Offset 88h: LG2: LPC Generic Decode Range 2 Register
19.2.5 Power Management Configuration Registers
19.2.6 FWH Configuration Registers
19.2.6.1 Offset D0h: FS1: FWH ID Select 1 Register
19.2.6.2 Offset D4h: FS2: FWH ID Select 2 Register
19.2.6.3 Offset D8h: FDE: FWH Decode Enable Register
19.2.6.4 Offset DCh: BC: BIOS Control Register
19.2.7 Root Complex Register Block Configuration Register
19.2.7.1 Offset F0h: RCBA: Root Complex Base Address Register
19.2.8 Manufacturing Information Register
19.2.8.1 Offset F8h: MANID: Manufacturer ID Register
19.3 Interface
19.3.1 Overview
19.3.2 Cycle Types
19.3.3 Aborting a Cycle
19.3.4 Memory Cycle Notes
19.3.5 I/O Cycle Notes
19.3.6 DMA Cycle Notes
19.3.7 Bus Master Cycle Notes
19.3.8 FWH Cycle Notes
19.3.9 LPC PD# Protocol
19.3.10 Cycle Posting Policies
19.3.11 Configuration
19.3.11.1 LPC Interface Decoders
19.3.11.2 Bus Master Device Mapping and START Fields
19.3.11.3 Firmware Memory IDSEL fields
19.3.12 SERR# Generation
20.0 LPC DMA
20.1 Overview
20.2 LPC DMA I/O-Mapped Register Details
20.2.1 Register Descriptions
20.2.1.1 Offset 00h: DMA_BCA[0-3] - DMA Base and Current Address Registers for
20.2.1.2 Offset C4h: DMA_BCA[5-7] - DMA Base and Current Address Registers for

Datasheet sections

20.2.1.3 Offset 01h: DMA_BCC[0-3] - DMA Base and Current Count Registers for
20.2.1.4 Offset C6h: DMA_BCC[5-7] - DMA Base and Current Count Registers for
20.2.1.5 Offset 08h: DMA_COMMAND - DMA Command Register
20.2.1.6 Offset 87h: DMA_MPL[0-3] - DMA Memory Low Page Registers for Channels
20.2.1.7 Offset 8Bh: DMA_MPL[5-7] - DMA Memory Low Page Registers for Channels
20.2.1.8 Offset 08h: DMA_STATUS - DMA Status Register
20.2.1.9 Offset 0Ah: DMA_WSM - DMA Write Single Mask Register
20.2.1.10 Offset 0Bh: DMA_CHM - DMA Channel Mode Register
20.2.1.11 Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register
20.2.1.12 Offset 0Dh: DMA_MC - DMA Master Clear Register
20.2.1.13 Offset 0Eh: DMA_CM - DMA Clear Mask Register
20.2.1.14 Offset 0Fh: DMA_WAM - DMA Write All Mask Register
20.3 DMA Channel Arbitration
20.4 Special Cases in Address/Count
20.4.1 Address Overrun/Underrun
20.4.3 Autoinitialize
20.4.4 Software Commands
20.5 Theory of Operation for LPC DMA
20.5.1 Asserting DMA Requests
20.5.2 Abandoning DMA Requests
20.5.3 General Flow of DMA Transfers
20.5.4 Terminal Count
20.5.5 Verify Mode
20.5.6 DMA Request Deassertion
20.5.7 SYNC Field/LDRQ# Rules
21.0 Serial Peripheral Interface
21.1 Overview
21.1.1 Features
21.2 External Interface
21.3 SPI Protocol
21.3.1 SPI Pin-Level Protocol
21.3.1.1 Addressing
21.3.1.2 Data Transaction
21.3.1.3 Bus Errors
21.3.1.4 Instructions
21.3.1.5 SPI Timings
21.4 Host Side Interface
21.4.1 SPI Host Interface Registers
21.4.2 Register Overview
21.4.2.1 Offset 3020h: SPIS – SPI Status
21.4.2.2 Offset 3022h: SPIC – SPI Control
21.4.2.3 Offset 3024h: SPIA – SPI Address
21.4.2.4 Offset 3028h: SPID0 – SPI Data
21.4.2.5 SPID[0-6] – SPI Data N
21.4.2.6 Offset 3070h: BBAR – BIOS Base Address
21.4.2.7 Offset 3074h: PREOP – Prefix Opcode Configuration
21.4.2.8 Offset 3076h: OPTYPE – Opcode Type Configuration
21.4.2.9 Offset 3078h: OPMENU – Opcode Menu Configuration
21.4.2.10 Offset 3080h: PBR0 – Protected BIOS Range [0-2]
21.4.3 Running SPI Cycles from the Host
21.4.3.1 Memory Reads
21.4.3.2 Generic Programmed Commands

Datasheet sections

22 Order Number: 320066-003US
21.4.3.3 Flash Protection
21.4.3.4 Decoding Memory Ranges for SPI
21.5 BIOS Programming Considerations
21.5.1 SPI Initialization
22.0 General Purpose I/O: Bus 0, Device 31, Function
22.1 Overview
22.1.1 GPIO Summary Table
22.2 General Purpose I/O-Mapped Configuration Register Details
22.2.1 Register Descriptions
22.2.1.1 Offset 00h: GPIO_USE_SEL1 -GPIO Use Select 1 {31:0}
22.2.1.2 Offset 04h: GP_IO_SEL1 - GPIO Input/Output Select 1 {31:0}
22.2.1.3 Offset 0Ch: GP_LVL1 - GPIO Level 1 for Input or Output {31:0}
22.2.1.4 Offset 18h: GPO_BLINK - GPIO Blink Enable Register
22.2.1.5 Offset 2Ch: GPI_INV - GPIO Signal Invert Register
22.2.1.6 Offset 30h: GPIO_USE_SEL2 - GPIO Use Select 2 {63:32}
22.2.1.7 Offset 34h: GP_IO_SEL2 - GPIO Input/Output Select 2 {63:32} Register813
22.2.1.8 Offset 38h: GP_LVL2 - GPIO Level for Input or
22.3 Additional GPIO Theory of Operation
22.3.1 SMI# and SCI Routing
22.3.2 Triggering
23.0 SATA: Bus 0, Device 31, Function
23.1 SATA PCI Configuration Registers
23.1.1 PCI Header
23.1.1.1 Offset 00h: ID - Identifiers Register
23.1.1.2 Offset 04h: CMD - Command Register
23.1.1.3 Offset 06h: STS - Device Status Register
23.1.1.4 Offset 08h: RID - Revision ID Register
23.1.1.5 PI - Programming Interface Register
23.1.1.6 Offset 0Ah: CC - Class Code Register
23.1.1.7 Offset 0Dh: MLT – Master Latency Timer Register
23.1.1.8 Offset 10h: PCMDBA – Primary Command Block Base Address
23.1.1.9 Offset 14h: PCTLBA – Primary Control Block Base Address Register
23.1.1.10 Offset 18h: SCMDBA – Secondary Command Block Base
23.1.1.11 Offset 1Ch: SCTLBA – Secondary Control Block Base Address
23.1.1.12 Offset 20h: LBAR – Legacy Bus Master Base Address Register
23.1.1.13 Offset 24h: ABAR – AHCI Base Address Register
23.1.1.14 Offset 2Ch: SS - Sub System Identifiers Register
23.1.1.15 Offset 34h: CAP – Capabilities Pointer Register
23.1.1.16 Offset 3Ch: INTR - Interrupt Information Register
23.1.2 Additional SFF-8038i Configuration Registers
23.1.2.1 Offset 40h: PTIM – Primary Timing Register
23.1.2.2 STIM – Secondary Timing Register
23.1.2.3 Offset 44h: D1TIM – Device 1 IDE Timing Register
23.1.2.4 Offset 48h: SYNCC – Synchronous DMA Control Register
23.1.2.5 Offset 4Ah: SYNCTIM – Synchronous DMA Timing Register
23.1.2.6 Offset 54h: IIOC – IDE I/O Configuration Register
23.1.3 PCI Power Management Capabilities
23.1.3.1 Offset 70h: Offset 70h: PID – PCI Power Management Capability ID Register

Datasheet sections

23.1.3.2 Offset 72h: PC – PCI Power Management Capabilities Register
23.1.3.3 Offset 74h: PMCS – PCI Power Management Control And
23.1.4 Message Signaled Interrupt Capability
23.1.4.1 Offset 80h: MID – Message Signaled Interrupt Identifiers Register
23.1.4.2 Offset 82h: MC – Message Signaled Interrupt Message
23.1.4.3 Offset 84h: MA – Message Signaled Interrupt Message
23.1.4.4 Offset 88h: MD – Message Signaled Interrupt Message
23.1.5 Additional Configuration Registers
23.1.5.1 Offset 90h: MAP – Port Mapping Register
23.1.5.2 Offset 92h: PCS – Port Control and Status Register
23.1.6 Serial ATA Capability Registers
23.1.6.1 Offset A8h: SATACR0 – Serial ATA Capability Register
23.1.6.2 Offset ACh: SATACR1 – Serial ATA Capability Register
23.1.7 Additional Configuration Registers
23.1.7.1 Offset C0h: ATC – APM Trapping Control Register
23.1.7.2 Offset C4h: ATS – ATM Trapping Status Register
23.1.7.3 Offset D0h: SP – Scratch Pad Register
23.1.7.4 Offset E0h: BFCS – BIST FIS Control/Status Register
23.1.7.5 Offset E4h: BFTD1 – BIST FIS Transmit Data 1 Register
23.1.7.6 Offset E8h: BFTD2 – BIST FIS Transmit Data 2 Register
23.1.7.7 Offset F8h: MANID – Manufacturing ID Register
23.2 SATA I/O Mapped Registers
23.2.1 Primary Devices
23.2.1.1 Offset 00h: PCMD – Primary Command Register
23.2.1.2 Offset 02h: PSTS – Primary Status Register
23.2.1.3 Offset 04h: PDTP – Primary Descriptor Table Pointer Register
23.2.2 Secondary Devices
23.2.2.1 Offset 08h: SCMD – Secondary Command Register
23.2.2.2 Offset 0Ah: SSTS – Secondary Status Register
23.2.2.3 Offset 0Ch: SDTP – Secondary Descriptor Table Pointer Register
23.2.3 AHCI Index and Data Registers
23.2.3.1 Offset 10h: INDEX – AHCI Index Register
23.2.3.2 Offset 14h: DATA – AHCI Data Register
23.3 SATA Memory Mapped Registers
23.3.1 Generic Host Controller
23.3.1.1 Offset 00h: HCAP – HBA Capabilities Register
23.3.1.2 Offset 04h: GHC – Global HBA Control Register
23.3.1.3 Offset 08h: IS – Interrupt Status Register
23.3.1.4 Offset 0Ch: PI – Ports Implemented Register
23.3.1.5 Offset 10h: VS – AHCI Version Register
23.3.2 Vendor Specific Registers
23.3.2.1 Offset A0h: SGPO - SPGIO Control Register
23.3.3 Port DMA Registers
23.3.3.2 Offset 104h: PxCLBU[0-1] – Port [0-1] Command List Base Address Upper 32-
23.3.3.3 Offset 108h: PxFB[0-1] – Port [0-1] FIS Base Address Register
23.3.3.4 Offset 10Ch: PxFBU[0-1] – Port [0-1] FIS Base Address Upper 32-bits
23.3.3.5 Offset 110h: PxIS[0-1] – Port [0-1] Interrupt Status Register
23.3.3.6 Offset 114h: PxIE[0-1] – Port [0-1] Interrupt Enable Register
23.3.3.7 Offset 118h: PxCMD[0-1] – Port [0-1] Command Register
23.3.4 Port Interface Registers (One Set Per Port)

Datasheet sections

24 Order Number: 320066-003US
23.3.4.1 Offset 120h: PxTFD[0-1] – Port [0-1] Task File Data Register
23.3.4.2 Offset 124h: PxSIG[0-1] – Port [0-1] Signature Register
23.3.4.3 Offset 128h: PxSSTS[0-1] – Port [0-1] Serial ATA Status Register
23.3.4.4 Offset 12Ch: PxSCTL[0-1] – Port [0-1] Serial ATA Control Register
23.3.4.5 Offset 130h: PxSERR[0-1] – Port [0-1] Serial ATA Error Register
23.3.4.6 Offset 134h: PxSACT[0-1] – Port [0-1] Serial ATA Active Register
23.3.4.7 Offset 138h: PxCI[0-1] – Port [0-1] Command Issue Register
23.3.4.8 Offset 13Ch: PxSNTF[0-1] – Port [0-1] SNotification Register
23.4 Overview
23.5 Legacy Operation
23.5.1 Transfer Examples
23.5.1.1 Register FIS Only
23.5.1.2 Non-Queued DMA Data Transfers
23.5.1.3 SW Assisted Queued DMA Transfer
23.5.2 Error Handling
23.5.2.1 Errors on DMI
23.5.2.2 Errors on SATA Interface
23.5.3 Hot Plug Operation
23.5.5 Power Management Operation
23.5.5.1 Introduction
23.5.5.2 Power State Mappings
23.5.5.3 Power State Transitions
23.5.5.4 SMI Trapping (APM)
23.5.6 Interrupt Architecture
23.5.7 Staggered Spin-up
23.5.8 HW/SW Operation for Detecting an SATA Device Presence
23.5.8.1 Introduction
23.5.8.2 Hardware Flow
23.5.8.3 Software Flow
23.5.9 SMI Generation
23.5.10 LED
23.6 AHCI Operation
23.6.1 System Memory Structures
23.6.2 Error Reporting and Recovery
23.6.2.1 Error Types
23.6.2.2 Error Recovery
23.6.3 Hot Plug Operation
23.6.4 Power Management Operation
23.6.4.1 Introduction
23.6.4.2 Power State Mappings
23.6.4.3 Power State Transitions
23.6.4.4 PME
23.7 Additional Information
23.7.1 Mode Switching
23.7.1.1 AHCI Mode
23.7.1.2 IDE Mode
24.0 SMBus Controller Functional Description: Bus 0, Device 31, Function
24.1 Overview
24.1.1 Host Controller
24.1.2 Slave Interface
24.2 SMBus Controller PCI Configuration Register Details
24.2.1 SMBus Controller PCI Configuration Register Descriptions
24.2.1.1 Offset 00h: VID: Vendor ID Register
24.2.1.2 Offset 02h: DID: Device ID Register
24.2.1.3 Offset 04h: CMD: Command Register

Datasheet sections

24.2.1.4 Offset 06h: DS – Device Status Register
24.2.1.5 Offset 08h: RID: Revision ID Register
24.2.1.6 Offset 09h: PI: Programming Interface Register
24.2.1.7 Offset 0Ah: SCC: Sub Class Code Register
24.2.1.8 Offset 0Bh: BCC: Base Class Code Register
24.2.1.9 Offset 20h: SM_BASE: SMB Base Address Register
24.2.1.10 Offset 2Ch: SVID: SVID Register
24.2.1.11 Offset 2Eh: SID: Subsystem Identification Register
24.2.1.12 Offset 3Ch: INTLN: Interrupt Line Register
24.2.1.13 Offset 3Dh: NTPN: Interrupt Pin Register
24.2.1.14 Offset 40h: HCFG: Host Configuration Register
24.2.1.15 Offset F8h: MANID: Manufacturer ID Register
24.3 SMBus Controller I/O-Mapped Configuration Register Details
24.3.1 SMBus Controller I/O-Mapped Configuration Register Descriptions
24.3.1.1 Offset 00h: HSTS: Host Status Register
24.3.1.2 Offset 02h: HCTL: Host Control Register
24.3.1.3 Offset 03h: HCMD: Host Command Register
24.3.1.4 Offset 04h: TSA: Transmit Slave Address Register
24.3.1.5 Offset 05h: HD0: Data 0 Register
24.3.1.6 Offset 06h: HD1: Data 1 Register
24.3.1.7 Offset 07h: HBD: Host Block Data Register
24.3.1.8 Offset 08h: PEC: Packet Error Check Data Register
24.3.1.9 Offset 0Ch: AUXS: Auxiliary Status Register
24.3.1.10 Offset 0Dh: AUXC: Auxiliary Control Register
24.3.1.11 Offset 0Eh: SMLC: SMLINK_PIN_CTL Register
24.3.1.12 Offset 0Fh: SMBC: SMBUS_PIN_CTL Register
24.4 Host Controller
24.4.1 Overview
24.4.2 Command Protocols
24.4.2.1 Quick Command
24.4.2.2 Send Byte/Receive Byte
24.4.2.3 Write Byte/Word
24.4.2.4 Read Byte/Word
24.4.2.5 Process Call
24.4.2.6 Block Read/Write
24.4.2.7 I2C Read
24.4.2.8 Block Write-Block Read Process Call
24.4.3 I2C Behavior
24.4.4 Heartbeat for Use with External LAN
24.5 Bus Arbitration
24.6 Bus Timings
24.6.1 Clock Stretching
24.6.2 Bus Time Out (CMI as SMB Master)
24.7 Interrupts/SMI#
24.8 CRC Generation and Checking
24.8.1 Slave Interface I/O Space
24.8.2 Register Details
24.8.2.1 Offset 09h: RSA: Receive Slave Address Register
24.8.2.2 Offset 0Ah: SD: Slave Data Register
24.8.2.3 Offset 10h: SSTS: Slave Status Register
24.8.2.4 Offset 11h: SCMD: Slave Command Register
24.8.2.5 Offset 14h: NDA: Notify Device Address Register
24.8.2.6 Offset 16h: NDLB: Notify Data Low Byte Register
24.8.2.7 Offset 17h: NDHB: Notify Data High Byte Register
24.9 Slave Interface Behavioral Description
24.9.1 Format of Slave Write Cycle
24.9.2 Format of Read Command
24.9.3 Format of the Host Notify Command

Datasheet sections

26 Order Number: 320066-003US
25.1.1 Register Details
25.1.1.1 ID - Identifiers Register
25.1.1.2 PCICMD - Command Register
25.1.1.3 PCISTS - Device Status Register
25.1.1.4 RID - Revision ID Register
25.1.1.5 SUBC - Sub Class Code Register
25.1.1.6 BCC - Base Class Code Register
25.1.1.7 MLT - Master Latency Timer Register
25.1.1.8 HDR - Header Type Register
25.1.1.9 USBIOBAR - Base Address Register
25.1.1.10 USBx_SVID - USB Subsystem Vendor ID Register
25.1.1.11 USBx_SID - USB Subsystem ID Register
25.1.1.12 INTL - Interrupt Line Register
25.1.1.13 INTP - Interrupt Pin Register
25.1.1.14 SBRN - Serial Bus Release Number Register
25.1.1.15 USBLKMCR - USB Legacy Keyboard/Mouse Control Register
25.1.1.16 USBREN - USB Resume Enable Register
25.1.1.17 USBCWP - USB Core Well Policy Register
25.1.1.18 MANID - Manufacturer ID Register
25.2.1 Register Details
25.2.1.1 USBCMD: USB Command Register
25.2.1.2 USBSTS: USB Status Register
25.2.1.3 USBINTR: USB Interrupt Enable Register
25.2.1.4 FRNUM: Frame Number Register
25.2.1.5 FRBASEADD: Frame List Base Address Register
25.2.1.6 SOFMOD: Start of Frame Modify Register
25.2.1.7 PSCR - Port Status and Control Register
25.3 Data Transfers to/from Main Memory
25.4 Data Structures in Main Memory
25.5 Data Transfers To/From Main Memory
25.5.1 Executing the Schedule
25.5.2 Processing Transfer Descriptors
25.5.3 Command Register, Status Register, and TD Status Bit Interaction
25.5.4 Transfer Queuing
25.6 USB Buffer Management
25.7 Data Encoding and Bit Stuffing
25.8 Bus Protocol
25.8.1 Bit Ordering
25.8.2 SYNC Field
25.8.3 Packet Field Formats
25.8.3.1 Packet Identifier Field
25.8.4 Address Fields
25.8.4.1 Address Field
25.8.4.2 Endpoint Field
25.8.5 Frame Number Field
25.8.6 Data Field
25.8.7 Cyclic Redundancy Check (CRC)
25.9 Packet Formats
25.10 USB Interrupts
25.10.1 Overview
25.10.2 Transaction-Based Interrupts
25.10.2.1 CRC Error/Time-out
25.10.2.2 Interrupt on Completion
25.10.2.3 Short Packet Detect

Datasheet sections

25.10.2.4 Serial Bus Babble
25.10.2.5 Stalled
25.10.2.6 Data Buffer Error
25.10.2.7 Bit Stuff Error
25.10.3 Non-Transaction Based Interrupts
25.10.3.1 Resume Received
25.10.3.2 Process Error
25.10.3.3 Host System Error
25.10.3.4 Implementation Notes
25.11 USB Power Management
25.12 USB Legacy Keyboard Operation
26.1 Overview
26.2.1 Register Details
26.2.1.1 Offset 00h: VID - Vendor ID Register
26.2.1.2 Offset 02h: DID - Device Identification Register
26.2.1.3 Offset 04h: CMD - Command Register
26.2.1.4 Offset 06h: DSR - Device Status Register
26.2.1.5 Offset 08h: RID - Revision ID Register
26.2.1.6 Offset 09h: PI - Programming Interface Register
26.2.1.7 Offset 0Ah: SCC - Sub Class Code Register
26.2.1.8 Offset 0Bh: BCC - Base Class Code Register
26.2.1.9 Offset 0Dh: MLT - Master Latency Timer Register
26.2.1.10 Offset 10h: MBAR - Memory Base Address Register
26.2.1.13 Offset 34h: CAP_PTR - Capabilities Pointer Register
26.2.1.14 Offset 3Ch: ILINE - Interrupt Line Register
26.2.1.15 Offset 3Dh: IPIN - Interrupt Pin Register
26.2.1.16 Offset 50h: PM_CID - PCI Power Management Capability ID
26.2.1.17 Offset 51h: PM_NEXT - Next Item Pointer #1 Register
26.2.1.18 Offset 52h: PM_CAP - Power Management Capabilities Register
26.2.1.19 Offset 54h: PM_CS - Power Management Control/Status Register
26.2.1.20 Offset 58h: DP_CID - Debug Port Capability ID Register
26.2.1.21 Offset 59h: DP_NEXT - Next Item Pointer #2 Register
26.2.1.22 Offset 5Ah: DP_BASE - Debug Port Base Offset Register
26.2.1.23 Offset 60h: SBRN - Serial Bus Release Number Register
26.2.1.24 Offset 61h: FLA - Frame Length Adjustment Register
26.2.1.25 Offset 62h: PWC - Port Wake Capability Register
26.2.1.26 Offset 64h: CUO - Classic USB Override Register
26.2.1.30 Offset 80h: AC - Access Control Register
26.2.1.31 Offset F8h: MANID - Manufacturer ID Register
26.3.1 Host Controller Capability Register Details
26.3.1.1 Offset 00h: CAPLENGTH - Capability Length Register
26.3.1.2 Offset 02h: HCIVERSION - Host Controller Interface Version Number Register

Datasheet sections

28 Order Number: 320066-003US
26.3.2 Host Controller Operational Register Details
26.3.2.4 Offset 2Ch: FRINDEX - Frame Index Register
26.3.2.5 Offset 30h: CTRLDSSEGMENT - Control Data Structure
26.3.2.6 Offset 34h: PERIODICLISTBASE - Periodic Frame List Base Address Register
26.3.2.8 Offset 60h: CONFIGFLAG - Configure Flag Register
26.3.2.9 Offset 64h: PORTSC - Port N Status and Control Register
26.4 EHC Initialization
26.4.1 Power On
26.4.2 Driver Initialization
26.4.3 EHC Resets
26.5 Data Structures in Main Memory
26.6.1 Periodic List Execution
26.6.1.1 Read Policies for Periodic DMA
26.6.1.2 Write Policies for Periodic DMA
26.6.2 Asynchronous List Execution
26.6.2.1 Read Policies for Asynchronous DMA
26.6.2.2 Write Policies for Asynchronous DMA
26.7 Data Encoding and Bit Stuffing
26.8 Packet Formats
26.9.2 Host Interface Parity Errors
26.10.1 Pause Feature
26.10.2 Suspend Feature
26.10.3 ACPI Device States
26.10.4 ACPI System States
26.11 Interaction with Classic Host Controllers
26.11.1 Port-Routing Logic
26.11.2 Device Connects
26.11.3 Device Disconnects
26.11.4 Effect of Resets on Port-Routing Logic
26.13.2 Debug Port Register Details
26.13.2.1 Offset A0h: CNTL_STS - Control/Status Register
26.13.2.2 Offset A4h: USBPID - USB PIDs Register
26.13.2.3 Offset A8h: DATABUF - Data Buffer Bytes 7:0
26.13.2.4 Offset B0h: CONFIG - Configuration Register
26.13.3.1 Behavioral Rules
26.13.3.2 OUT Transactions
26.13.3.3 IN Transactions
26.13.3.4 Debug Software
27.0 Power Management
27.1 Features
27.2 IMCH-IICH Messages

Datasheet sections

27.3 Power Management Register Details
27.3.1 Power Management PCI Configuration Registers
27.3.1.1 Offset A0h: GEN_PMCON_1 - General PM Configuration
27.3.1.2 Offset A2h: GEN_PMCON_2 - General PM Configuration
27.3.1.3 Offset A4h: GEN_PMCON_3 - General PM Configuration
27.3.1.4 Offset B8h: GPI_ROUT - GPI Routing Control Register
27.3.2 APM Power Management I/O-Mapped Registers
27.3.3 General Power Management I/O-Mapped Registers
27.3.3.1 Offset 00h: PM1_STS – Power Management 1 Status Register
27.3.3.2 Offset 02h: PM1_EN - Power Management 1 Enables Register
27.3.3.3 Offset 04h: PM1_CNT - Power Management 1 Control Register
27.3.3.4 Offset 08h: PM1_TMR - Power Management 1 Timer Register
27.3.3.5 Offset 10h: PROC_CNT - Processor Control Register
27.3.3.6 Offset 14h: LV2 - Level 2 Register
27.3.3.7 Offset 28h: GPE0_STS - General Purpose Event 0 Status Register
27.3.3.8 Offset 2Ch: PMBASE_GPE0_EN - General Purpose
27.3.3.9 Offset 30h: SMI_EN - SMI Control and Enable Register
27.3.3.10 Offset 34h: SMI_STS - SMI Status Register
27.3.3.11 Offset 38h: ALT_GPI_SMI_EN - Alternate GPI SMI Enable
27.3.3.12 Offset 3Ah: ALT_GPI_SMI_STS - Alternate GPI SMI Status
27.3.3.13 Offset 44h: DEVTRAP_STS - DEVTRAP_STS Register
27.4 SMI#/SCI Generation
27.4.0.1 PCI Express* SCI
27.5 Dynamic Processor Clock Control
27.5.1 Overview
27.5.2 Transition Rules Among S0/Cx and Sx States
27.5.3 S0/C0, S0/C2, Entry/Exit Timings and Sequences
27.5.3.1 C0 →C2→C0 Timings and Diagram
27.5.3.2 C0 →C2 Entry Sequence
27.5.3.3 C2 →C0 Break Sequence
27.6 Sleep States
27.6.1 Sleep State Overview
27.6.2 Initiating Sleep States
27.6.3 Exiting Sleep States
27.6.4 Sx-G3-Sx, Handling Power Failures
27.7 Processor Thermal Management
27.7.1 PROCHOT# Signal for SMI# or SCI
27.7.2 Processor Passive Cooling
27.7.3 On-Demand Passive Cooling
27.7.4 Active Cooling
27.8 Event Input Signals, Messages and Their Usage
27.8.1 PWRBTN# – Power Button
27.8.1.1 Power Button Override Function
27.8.1.2 Sleep Button
27.8.2 RI# – Ring Indicate Signal
27.8.3 PME# – PCI Power Management Event
27.8.4 SYS_RESET# Button

Datasheet sections

30 Order Number: 320066-003US
27.8.5 Processor Thermal Trip
27.8.6 SATA SCI
27.8.7 PCI Express* PME Event Message
27.9 Alternate (ALT) Access Mode
27.9.1 Write Only Registers with Read Paths in Alternate Access Mode
27.9.2 PIC Reserved Bits
27.9.3 Read-Only Registers with Write Paths in ALT Access Mode
27.10 System Power Supplies, Planes, and Signals
27.10.1 Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5#
27.10.2 SLP_S4# and Suspend-To-RAM Sequencing
27.10.3 PWROK Signal
27.10.4 CPUPWRGD Signal
27.10.5 Controlling Leakage and Power Consumption During Low-Power States
27.10.6 VRMPWROK
27.11 Legacy Power Management Theory of Operation
27.11.1 Overview
27.11.2 APM Power Management
28.0 IA-32 Core Interface
28.1 IA-32 Core Interface I/O-Mapped Register Details
28.1.1 Register Descriptions
28.1.1.1 Offset 61h: NMI_SC - NMI Status and Control Register
28.1.1.2 Offset 70h: NMI_EN - NMI Enable (and Real Time Clock Index)
28.1.1.3 Offset 92h: PORT92 - Fast A20 and Init Register
28.1.1.4 Offset F0h: COPROC_ERR - Coprocessor Error Register
28.1.1.5 Offset CF9h: RST_CNT - Reset Control Register
28.2 IA-32 Core Interface Signals
28.2.1 A20M# (Mask A20)
28.2.2 INIT# (Initialization)
28.2.3 INTR# (Interrupt Signals)
28.2.4 STPCLK# and CPUSLP# (Stop Clock Request and Processor Sleep Signals)
28.2.5 Enhanced Intel SpeedStep Technology (EIST) Signals
28.2.6 DPSLP# (Deeper Sleep)
29.0 Real Time Clock
29.1 Overview
29.2 RTC I/O Registers
29.3 Real Time Clock Indexed Register Details
29.3.1 Real Time Clock Register Details
29.3.1.1 Offset 0Ah: RTC_REGA - Register A (General Configuration)
29.3.1.2 Offset 0Bh: RTC_REGB - Register B (General Configuration)
29.3.1.3 Offset 0Ch: RTC_REGC - Register C (Flag Register)
29.3.1.4 Offset 0Dh: RTC_REGD - Register D (Flag Register)
29.4 Update Cycles
29.5 Interrupts
29.6 Lockable RAM Ranges
29.7 Century Rollover
29.8 Month and Year Alarms
30.0 Interrupts
30.1 Overview
30.2.1 Overview
30.2.2 I/O Registers
30.2.2.1 ICW1[0-1] - Initialization Command Word 1 Register
30.2.2.2 ICW2[0-1] - Initialization Command Word 2 Register

Datasheet sections

30.2.2.3 MICW3 - Master Initialization Command Word 3 Register
30.2.2.4 SICW3 - Slave Initialization Command Word 3 Register
30.2.2.5 ICW4[0-1] - Initialization Command Word 4 Register
30.2.2.6 OCW1[0-1] - Operational Control Word 1 (Interrupt Mask)
30.2.2.7 OCW2[0-1] - Operational Control Word 2 Register
30.2.2.8 OCW3[0-1] - Operational Control Word 3 Register
30.2.2.9 ELCR1 - Master Edge/Level Control Register
30.2.2.10 ELCR2 - Slave Edge/Level Control Register
30.2.3 Interrupt Handling
30.2.3.1 Generating Interrupts
30.2.3.2 Acknowledging Interrupts
30.2.3.3 Hardware/Software Interrupt Sequence
30.2.4 Initialization Command Words (ICW)
30.2.4.1 ICW1
30.2.4.2 ICW2
30.2.4.3 ICW3
30.2.4.4 ICW4
30.2.5 Operation Command Words (OCW)
30.2.6 Modes of Operation
30.2.6.1 Fully Nested Mode
30.2.6.2 Special Fully Nested Mode
30.2.6.3 Automatic Rotation Mode (Equal Priority Devices)
30.2.6.4 Specific Rotation Mode (Specific Priority)
30.2.6.5 Poll Mode
30.2.6.6 Edge and Level Triggered Mode
30.2.7 End of Interrupt (EOI) operations
30.2.7.1 Normal EOI
30.2.7.2 Automatic EOI Mode
30.2.8 Masking Interrupts
30.2.8.1 Masking on an Individual Interrupt Request
30.2.8.2 Special Mask Mode
30.2.9 Steering of PCI Interrupts
30.3 Advanced Interrupt Controller: APIC
30.3.1 Interrupt Handling
30.3.2 PCI/PCI Express* Message-Based Interrupts
30.3.2.1 Front Side Bus Interrupt Delivery
30.3.2.2 Edge-Triggered Operation
30.3.2.3 Level-Triggered Operation
30.3.2.4 Registers Associated with Front-Side Bus Interrupt Delivery
30.3.2.5 EOI
30.3.2.6 Interrupt Message Format
30.3.3 APIC Memory-Mapped Register Details
30.3.3.1 APIC_IDX - Index Register
30.3.3.2 APIC_DAT – Data Register
30.3.3.3 APIC_EOI - EOI Register
30.3.4 Index Registers
30.3.4.1 APIC_ID – Identification Register
30.3.4.2 APIC_VS - Version Register
30.3.4.3 APIC_RTE[0-39] - Redirection Table Entry
30.4 PCI Interrupts via /PCI Express*
30.5 Serial Interrupt
30.5.1 Overview
30.5.2 Start Frame
30.5.3 Data Frames
30.5.4 Stop Frame
30.5.5 Serial Interrupts Not Supported via SERIRQ

Datasheet sections

32 Order Number: 320066-003US
30.5.6 Special Notes on IRQ14 and IRQ15
30.5.7 Data Frame Format
31.1 Overview
31.2.1 Timer Registers
31.2.1.1 Offset 43h: TCW - Timer Control Word Register
31.2.1.2 Offset 40h: TSB[0-2] - Interval Timer Status Byte Format
31.2.1.3 Offset 40h: TCAP[0-2] - Interval Timer Counter Access Ports
31.3 Counters
31.3.1 Counter 0, System Timer
31.3.2 Counter 1, Refresh Request Signal
31.3.3 Counter 2, Speaker Tone
31.3.4 Counter Operating Modes
31.4 Timer Programming
31.5 Reading from the Interval Timer
31.5.1 Simple Read
31.5.2 Counter Latch Command
31.5.3 Read Back Command
32.0 High Precision Event Timers
32.1 Overview
32.2 Register Details
32.2.1 Register Descriptions
32.2.1.1 Offset 000h: GCAP_ID - General Capabilities and ID Register
32.2.1.2 Offset 010h: GEN_CONF - General Configuration Register
32.2.1.3 Offset 020h: GINTR_STA - General Interrupt Status Register
32.2.1.4 Offset 0F0h: MAIN_CNT - Main Counter Value Register
32.2.1.5 Offset 100h: HPTCC[0-2] - Timer n Configuration and
32.2.1.6 Offset 108h: HPTCV[0-2] - Timer n Comparator Value Register
32.3 Theory Of Operation
32.3.1 Timer Accuracy Rules
32.3.2 Interrupt Mapping
32.3.3.1 Non-Periodic Mode
32.3.3.2 Periodic Mode
32.3.4 Enabling the Timers
32.3.5 Interrupt Levels
32.3.6 Handling Interrupts
32.3.7 Unloading Device Driver Issues
33.0 Serial I/O Unit and Watchdog Timer
33.1 Overview
33.2 Features
33.3 Functional Description
33.3.1 Host Processor Interface (LPC)
33.4 LPC Interface
33.4.1 LPC Cycles
33.4.1.1 I/O Read and Write Cycles
33.4.2 Policy
33.4.3 LPC Transfers
33.4.3.1 I/O Transfers
33.5 Logical Devices 4 and 5: Serial Ports (UART1 and UART2)

Datasheet sections

33.5.1 UART Feature List
33.5.2 UART Operational Description
33.5.2.1 Programmable Baud Rate Generator
33.5.3 UART Register Details
33.5.3.1 Offset 00h: RBR - Receive Buffer Register
33.5.3.2 Offset 00h: THR - Transmit Holding Register
33.5.3.3 Offset 01h: IER - Interrupt Enable Register
33.5.3.4 Offset 02h: IIR - Interrupt Identification Register
33.5.3.5 Offset 02h: FCR - FIFO Control Register
33.5.3.6 Offset 03h: LCR - Line Control Register
33.5.3.7 Offset 04h: MCR - Modem Control Register
33.5.3.8 Offset 05h: LSR - Line Status Register
33.5.3.9 Offset 06h: MSR - Modem Status Register
33.5.3.10 Offset 07h: SCR - Scratchpad Register
33.5.3.11 Offset 00h: DLL - Programmable Baud Rate Generator Divisor Latch Register
33.5.3.12 Offset 01h: DLH - Programmable Baud Rate Generator Divisor Latch Register
33.5.4 FIFO Operation
33.5.4.1 FIFO Interrupt Mode Operation
33.5.4.2 FIFO Polled Mode Operation
33.6 Logical Device 6: Watchdog Timer
33.6.1 Overview
33.6.2 Watchdog Timer Register Details
33.6.2.1 Offset 00h: PV1R0 - Preload Value 1 Register
33.6.2.2 Offset 01h: PV1R1 - Preload Value 1 Register
33.6.2.3 Offset 02h: PV1R2 - Preload Value 1 Register
33.6.2.4 Offset 04h: PV2R0 - Preload Value 2 Register
33.6.2.5 Offset 05h: PV2R1 - Preload Value 2 Register
33.6.2.6 Offset 06h: PV2R2 - Preload Value 2 Register
33.6.2.7 Offset 08h: GISR - General Interrupt Status Register
33.6.2.8 Offset 0Ch: RR0 - Reload Register
33.6.2.9 Offset 0Dh: RR1 - Reload Register
33.6.2.10 Offset 10h: WDTCR - WDT Configuration Register
33.6.2.11 Offset 18h: WDTLR - WDT Lock Register
33.6.3 Theory Of Operation
33.6.3.1 RTC Well and WDT_TOUT# Functionality
33.6.3.2 Register Unlocking Sequence
33.6.3.3 Reload Sequence
33.6.3.4 Low Power State
33.7 Serial IRQ
33.7.1 Timing Diagrams For SIW_SERIRQ Cycle
33.7.1.1 SIW_SERIRQ Cycle Control
33.7.1.2 SIW_SERIRQ Data Frame
33.7.1.3 Stop Cycle Control
33.7.1.4 Latency
33.7.1.5 EOI/ISR Read Latency
33.7.1.6 Reset and Initialization
33.8 Configuration
33.8.1 Configuration Port Address
33.8.2 Primary Configuration Address Decoder
33.8.2.1 Entering the Configuration State
33.8.2.2 Exiting the Configuration State
33.8.2.3 Configuration Sequence
33.8.2.4 Configuration Mode
33.8.3 SIW Configuration Register Summary
33.8.3.1 Global Control/Configuration Registers [00h - 2Fh]
33.8.3.2 Logical Device Configuration Registers [30h — FFh]

Datasheet sections

34 Order Number: 320066-003US
34.0 PCI-to-PCI Bridge
34.1 Summary
34.2 PCI-to-PCI Bridge Detailed Register Descriptions
34.2.1 PCI-to-PCI Bridge Header
34.2.2 PCI-to-PCI Bridge Configuration Space
34.2.2.1 Offset 0h: VID – Vendor Identification Register
34.2.2.2 Offset 2h: DID – Device Identification Register
34.2.2.3 Offset 4h: PCICMD – Device Command Register
34.2.2.4 Offset 6h: PCISTS – Device Status Register
34.2.2.5 Offset 8h: RID – Revision ID Register
34.2.2.6 Offset 9h: CC – Class Code Register
34.2.2.7 Offset Ch: CLS – Cacheline Size Register
34.2.2.8 Offset Dh: LT – Latency Timer Register
34.2.2.9 Offset Eh: HDR – Header Type Register
34.2.2.10 Offset 10h: CSRBAR0 – Control and Status Registers Base Address Register
34.2.2.11 Offset 14h: CSRBAR1 – Control and Status Registers Base Address Register
34.2.2.12 Offset 18h: PBNUM – Primary Bus Number Register
34.2.2.13 Offset 19h: SECBNM – Secondary Bus Number Register
34.2.2.14 Offset 1Ah: SUBBNM – Subordinate Bus Number Register
34.2.2.15 Offset 1Bh: SECLT – Secondary Latency Timer Register
34.2.2.16 Offset 1Ch: IOB – I/O Base Register
34.2.2.17 Offset 1Dh: IOL – I/O Limit Register
34.2.2.18 Offset 1Eh: SECSTA – Secondary Status Register
34.2.2.19 Offset 20h: MEMB – Memory Base Register
34.2.2.20 Offset 22h: MEML – Memory Limit Register
34.2.2.21 Offset 24h: PMBASE – Prefetchable Memory Base Register
34.2.2.22 Offset 26h: PMLIMIT – Prefetchable Memory Limit Register
34.2.2.23 Offset 28h: PMBASU – Prefetchable Memory Base Upper Register
34.2.2.24 Offset 2Ch: PMLMTU – Prefetchable Memory Limit Upper Register
34.2.2.25 Offset 30h: IOBU – I/O Base Upper Register
34.2.2.26 Offset 32h: IOLU – I/O Limit Upper Register
34.2.2.27 Offset 34h: CP – Capabilities Pointer Register
34.2.2.28 Offset 3Ch: IRQL – Interrupt Line Register
34.2.2.29 Offset 3Dh: IRQP – Interrupt Pin Register
34.2.2.30 Offset 3Eh: BCTL – Bridge Control Register
34.2.2.31 Offset DCh: PCID – Power Management Capability ID Register
34.2.2.32 Offset DDh: PCP – Power Management Next Capability Pointer
34.2.2.33 Offset DEh: PMCAP – Power Management Capability Register
34.2.2.34 Offset E0h: PMCS – Power Management Control and Status
34.2.2.35 Offset E2h: PMCSE – Power Management Control and Status Extension
35.0 PCI-to-PCI Bridge: AIOC Configuration
35.1 Overview
35.2 Feature List
35.3 PCI Configuration Registers
35.3.1 Description of PCI Configuration Header Space
35.4 Interrupt Handling for AIOC Devices
35.5 Power Management of AIOC Devices
35.6 Gigabit Ethernet MAC Configuration Spaces: Bus M, Device 0-2, Function
35.6.1 Register Details
35.6.1.1 Offset 00h: VID – Vendor Identification Register
35.6.1.2 Offset 02h: DID – Device Identification Register

Datasheet sections

35.6.1.3 Offset 02h: DID – Device Identification Register
35.6.1.4 Offset 02h: DID – Device Identification Register
35.6.1.5 Offset 04h: PCICMD – Device Command Register
35.6.1.6 Offset 06h: PCISTS – Device Status Register
35.6.1.7 Offset 08h: RID – Revision ID Register
35.6.1.8 Offset 09h: CC – Class Code Register
35.6.1.9 Offset 0Eh: HDR – Header Type Register
35.6.1.10 Offset 10h: CSRBAR – Control and Status Registers Base
35.6.1.11 Offset 14h: IOBAR – CSR I/O Mapped BAR Register
35.6.1.12 Offset 2Ch: SVID – Subsystem Vendor ID Register
35.6.1.13 Offset 2Eh: SID – Subsystem ID Register
35.6.1.14 Offset 34h: CP – Capabilities Pointer Register
35.6.1.15 Offset 3Ch: IRQL – Interrupt Line Register
35.6.1.16 Offset 3Dh: IRQP – Interrupt Pin Register
35.6.1.17 Offset DCh: PCID – Power Management Capability ID Register
35.6.1.18 Offset DDh: PCP – Power Management Next Capability Pointer
35.6.1.19 Offset DEh: PMCAP – Power Management Capability Register
35.6.1.20 Offset E0h: PMCS – Power Management Control and Status
35.6.1.21 Offset E4h: SCID – Signal Target Capability ID Register
35.6.1.22 Offset E5h: SCP – Signal Target Next Capability Pointer Register
35.6.1.23 Offset E6h: SBC – Signal Target Byte Count Register
35.6.1.24 Offset E7h: STYP – Signal Target Capability Type Register
35.6.1.25 Offset E8h: SMIA – Signal Target IA Mask Register
35.6.1.26 Offset E9h: Reserved Register
35.6.1.27 Offset EAh: Reserved Register
35.6.1.28 Offset ECh: SINT – Signal Target Raw Interrupt Register
35.6.1.29 Offset F0h: MCID – Message Signalled Interrupt Capability ID
35.6.1.30 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
35.6.1.31 Offset F2h: MCTL – Message Signalled Interrupt Control Register
35.6.1.32 Offset F4h: MADR – Message Signalled Interrupt Address
35.6.1.33 Offset F8h: MDATA – Message Signalled Interrupt Data Register
35.7 Gigabit Ethernet MAC I/O Spaces: Bus M, Device 0-2, Function
35.7.1 Register Details
35.7.1.1 Offset 0000h: IOADDR - IOADDR Register
35.7.1.2 Offset 0004h: IODATA - IODATA Register
35.8 GCU Configuration Space: Bus M, Device 3, Function
35.8.1 Register Details
35.8.1.1 Offset 00h: VID – Vendor Identification Register
35.8.1.2 Offset 02h: DID – Device Identification Register
35.8.1.3 Offset 04h: PCICMD – Device Command Register
35.8.1.4 Offset 06h: PCISTS – Device Status Register
35.8.1.5 Offset 08h: RID – Revision ID Register
35.8.1.6 Offset 09h: CC – Class Code Register
35.8.1.7 Offset 0Eh: HDR – Header Type Register
35.8.1.8 Offset 10h: CSRBAR – Control and Status Registers Base
35.8.1.9 Offset 2Ch: SVID – Subsystem Vendor ID Register
35.8.1.10 Offset 2Eh: SID – Subsystem ID Register
35.8.1.11 Offset 34h: CP – Capabilities Pointer Register
35.8.1.12 Offset DCh: PCID – Power Management Capability ID Register
35.8.1.13 Offset DDh: PCP – Power Management Next Capability Pointer
35.8.1.14 Offset DEh: PMCAP – Power Management Capability Register

Datasheet sections

36 Order Number: 320066-003US
35.8.1.15 Offset E0h: PMCS – Power Management Control and Status
35.9 CAN Controller Configuration Spaces: Bus M, Device 4-5, Function
35.9.1 Register Details
35.9.1.1 Offset 00h: VID – Vendor Identification Register
35.9.1.2 Offset 02h: DID – Device Identification Register
35.9.1.3 Offset 02h: DID – Device Identification Register
35.9.1.4 Offset 04h: PCICMD – Device Command Register
35.9.1.5 Offset 06h: PCISTS – Device Status Register
35.9.1.6 Offset 08h: RID – Revision ID Register
35.9.1.7 Offset 09h: CC – Class Code Register
35.9.1.8 Offset 0Eh: HDR – Header Type Register
35.9.1.9 Offset 10h: CSRBAR – Control and Status Registers Base
35.9.1.10 Offset 2Ch: SVID – Subsystem Vendor ID Register
35.9.1.11 Offset 2Eh: SID – Subsystem ID Register
35.9.1.12 Offset 34h: CP – Capabilities Pointer Register
35.9.1.13 Offset 3Ch: IRQL – Interrupt Line Register
35.9.1.14 Offset 3Dh: IRQP – Interrupt Pin Register
35.9.1.15 Offset 40h: CANCTL – CAN Control Register
35.9.1.16 Offset DCh: PCID – Power Management Capability ID Register
35.9.1.17 Offset DDh: PCP – Power Management Next Capability Pointer
35.9.1.18 Offset DEh: PMCAP – Power Management Capability Register
35.9.1.19 Offset E0h: PMCS – Power Management Control and Status
35.9.1.20 Offset E4h: SCID – Signal Target Capability ID Register
35.9.1.21 Offset E5h: SCP – Signal Target Next Capability Pointer Register
35.9.1.22 Offset E6h: SBC – Signal Target Byte Count Register
35.9.1.23 Offset E7h: STYP – Signal Target Capability Type Register
35.9.1.24 Offset E8h: SMIA – Signal Target IA Mask Register
35.9.1.25 Offset E9h: Reserved Register
35.9.1.26 Offset EAh: Reserved Register
35.9.1.27 Offset ECh: SINT – Signal Target Raw Interrupt Register
35.9.1.28 Offset F0h: MCID – Message Signalled Interrupt Capability ID
35.9.1.29 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
35.9.1.30 Offset F2h: MCTL – Message Signalled Interrupt Control Register
35.9.1.31 Offset F4h: MADR – Message Signalled Interrupt Address
35.9.1.32 Offset F8h: MDATA – Message Signalled Interrupt Data Register
35.10 SSP Controller Configuration Space: Bus M, Device 6, Function
35.10.1 Register Details
35.10.1.1 Offset 00h: VID – Vendor Identification Register
35.10.1.2 Offset 02h: DID – Device Identification Register
35.10.1.3 Offset 04h: PCICMD – Device Command Register
35.10.1.4 Offset 06h: PCISTS – Device Status Register
35.10.1.5 Offset 08h: RID – Revision ID Register
35.10.1.6 Offset 09h: CC – Class Code Register
35.10.1.7 Offset 0Eh: HDR – Header Type Register
35.10.1.8 Offset 10h: CSRBAR – Control and Status Registers Base
35.10.1.9 Offset 2Ch: SVID – Subsystem Vendor ID Register
35.10.1.10 Offset 2Eh: SID – Subsystem ID Register
35.10.1.11 Offset 34h: CP – Capabilities Pointer Register
35.10.1.12 Offset 3Ch: IRQL – Interrupt Line Register
35.10.1.13 Offset 3Dh: IRQP – Interrupt Pin Register
35.10.1.14 Offset DCh: PCID – Power Management Capability ID Register

Datasheet sections

35.10.1.15 Offset DDh: PCP – Power Management Next Capability Pointer
35.10.1.16 Offset DEh: PMCAP - Power Management Capability
35.10.1.17 Offset E0h: PMCS – Power Management Control and Status
35.10.1.18 Offset E4h: SCID – Signal Target Capability ID Register
35.10.1.19 Offset E5h: SCP – Signal Target Next Capability Pointer Register
35.10.1.20 Offset E6h: SBC – Signal Target Byte Count Register
35.10.1.21 Offset E7h: STYP – Signal Target Capability Type Register
35.10.1.22 Offset E8h: SMIA – Signal Target IA Mask Register
35.10.1.23 Offset E9h: Reserved Register
35.10.1.24 Offset EAh: Reserved Register
35.10.1.25 Offset ECh: SINT – Signal Target Raw Interrupt Register
35.10.1.26 Offset F0h: MCID – Message Signalled Interrupt Capability ID
35.10.1.27 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
35.10.1.28 Offset F2h: MCTL – Message Signalled Interrupt Control
35.10.1.29 Offset F4h: MADR – Message Signalled Interrupt Address
35.10.1.30 Offset F8h: MDATA – Message Signalled Interrupt Data Register
35.11 IEEE 1588 Hardware Assist Unit Configuration Space: Bus M, Device 7, Function 0
35.11.1 Register Details
35.11.1.1 Offset 00h: VID – Vendor Identification Register
35.11.1.2 Offset 02h: DID – Device Identification Register
35.11.1.3 Offset 04h: PCICMD – Device Command Register
35.11.1.4 Offset 06h: PCISTS – Device Status Register
35.11.1.5 Offset 08h: RID – Revision ID Register
35.11.1.6 Offset 09h: CC – Class Code Register
35.11.1.7 Offset 0Eh: HDR – Header Type Register
35.11.1.8 Offset 10h: CSRBAR – Control and Status Registers Base
35.11.1.9 Offset 2Ch: SVID – Subsystem Vendor ID Register
35.11.1.10 Offset 2Eh: SID – Subsystem ID Register
35.11.1.11 Offset 34h: CP – Capabilities Pointer Register
35.11.1.12 Offset 3Ch: IRQL – Interrupt Line Register
35.11.1.13 Offset 3Dh: IRQP – Interrupt Pin Register
35.11.1.14 Offset DCh: PCID – Power Management Capability ID Register
35.11.1.15 Offset DDh: PCP – Power Management Next Capability Pointer
35.11.1.16 Offset DEh: PMCAP – Power Management Capability Register
35.11.1.17 Offset E0h: PMCS – Power Management Control and Status
35.11.1.18 Offset E4h: SCID – Signal Target Capability ID Register
35.11.1.19 Offset E5h: SCP – Signal Target Next Capability Pointer Register
35.11.1.20 Offset E6h: SBC – Signal Target Byte Count Register
35.11.1.21 Offset E7h: STYP – Signal Target Capability Type Register
35.11.1.22 Offset E8h: SMIA – Signal Target IA Mask Register
35.11.1.23 Offset E9h: Reserved Register
35.11.1.24 Offset EAh: Reserved Register
35.11.1.25 Offset ECh: SINT – Signal Target Raw Interrupt Register
35.11.1.26 Offset F0h: MCID – Message Signalled Interrupt Capability ID
35.11.1.27 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
35.11.1.28 Offset F2h: MCTL – Message Signalled Interrupt Control
35.11.1.29 Offset F4h: MADR – Message Signalled Interrupt Address

Datasheet sections

38 Order Number: 320066-003US
35.11.1.30 Offset F8h: MDATA – Message Signalled Interrupt Data Register
35.12 Expansion Bus Configuration Space: Bus M, Device 8, Function
35.12.1 Register Details
35.12.1.1 Offset 00h: VID – Vendor Identification Register
35.12.1.2 Offset 02h: DID – Device Identification Register
35.12.1.3 Offset 04h: PCICMD – Device Command Register
35.12.1.4 Offset 06h: PCISTS – Device Status Register
35.12.1.5 Offset 08h: RID – Revision ID Register
35.12.1.6 Offset 09h: CC – Class Code Register
35.12.1.7 Offset 0Eh: HDR – Header Type Register
35.12.1.8 Offset 10h: CSRBAR – Control and Status Registers Base
35.12.1.9 Offset 14h: MMBAR – Expansion Bus Base Address Register
35.12.1.10 Offset 2Ch: SVID – Subsystem Vendor ID Register
35.12.1.11 Offset 2Eh: SID – Subsystem ID Register
35.12.1.12 Offset 34h: CP – Capabilities Pointer Register
35.12.1.13 Offset 3Ch: IRQL – Interrupt Line Register
35.12.1.14 Offset 3Dh: IRQP – Interrupt Pin Register
35.12.1.15 Offset 40h: LEBCTL – LEB Control Register
35.12.1.16 Offset DCh: PCID – Power Management Capability ID Register
35.12.1.17 Offset DDh: PCP – Power Management Next Capability Pointer
35.12.1.18 Offset DEh: PMCAP – Power Management Capability Register
35.12.1.19 Offset E0h: PMCS – Power Management Control and Status
35.12.1.20 Offset E4h: SCID – Signal Target Capability ID Register
35.12.1.21 Offset E5h: SCP – Signal Target Next Capability Pointer Register
35.12.1.22 Offset E6h: SBC – Signal Target Byte Count Register
35.12.1.23 Offset E7h: STYP – Signal Target Capability Type Register
35.12.1.24 Offset E8h: SMIA – Signal Target IA Mask Register
35.12.1.25 Offset E9h: Reserved Register
35.12.1.26 Offset EAh: Reserved Register
35.12.1.27 Offset ECh: SINT – Signal Target Raw Interrupt Register
35.12.1.28 Offset F0h: MCID – Message Signalled Interrupt Capability ID
35.12.1.29 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
35.12.1.30 Offset F2h: MCTL – Message Signalled Interrupt Control
35.12.1.31 Offset F4h: MADR – Message Signalled Interrupt Address
35.12.1.32 Offset F8h: MDATA – Message Signalled Interrupt Data Register
36.0 AIOC Interfaces
36.1 Overview
36.2 Gigabit Ethernet (GbE)
36.2.1 Integrated DMA Features
36.2.2 MAC Features
36.2.3 Host Off-Loading Features
36.2.4 Interfaces
36.2.5 Power Management
36.2.6 Serial EEPROM Interface
36.3 Local Expansion Bus Interface (LEB)
36.4 Serial Synchronous Port (SSP)
36.5 Controller Area Network (CAN)
36.6 IEEE 1588 Time Synchronization Hardware Assist
37.0 Gigabit Ethernet Controller
37.1 Overview

Datasheet sections

37.1.1 Terminology and Conventions
37.1.1.1 Register and Bit References
37.1.1.2 Byte and Bit Designations
37.1.1.3 Numbering
37.1.1.4 Memory Alignment Terminology
37.1.1.5 Alignment and Byte Ordering
37.1.1.6 Packet Buffer
37.1.2 Wake On LAN
37.2 Feature List
37.3 Functional Block Diagram
37.4 Usage Model
37.4.1 Protocol Translation
37.4.2 Power Management
37.4.3 Software Initialization and Diagnostics
37.4.3.1 Power Up State
37.4.3.2 Memory Initialization
37.4.3.3 General Configuration
37.4.3.4 Link Setup Mechanisms and Control/Status Bit Summary
37.4.3.5 Receive Initialization
37.4.3.6 Transmit Initialization
37.4.3.7 Initialization of Statistics
37.4.3.8 GbE Line Rate Configuration Change
37.4.3.9 Network Boot
37.4.3.10 Diagnostics
37.5 Functional Description
37.5.1 Ethernet Addressing
37.5.2 Interrupt Control & Tuning
37.5.2.1 Interrupt Cause Set/Read Registers
37.5.2.2 Interrupt Mask Set (Read)/Clear Registers
37.5.2.3 Interrupt Throttling Register
37.5.3 Hardware Acceleration Capability
37.5.3.1 Checksum Off-Loading
37.5.3.2 TCP Segmentation
37.5.4 Buffer and Descriptor Structure
37.5.5 Packet Reception
37.5.5.1 Packet Address Filtering
37.5.5.2 Receive Data Storage
37.5.5.3 Receive Descriptor Format
37.5.5.4 Receive Descriptor Fetching
37.5.5.5 Receive Descriptor Write-Back
37.5.5.6 Receive Descriptor Queue Structure
37.5.5.7 Receive Interrupts
37.5.5.8 Receive Packet Checksum Off loading
37.5.6 Packet Transmission
37.5.6.1 Transmit Data Storage
37.5.6.2 Transmit Descriptor Formats
37.5.6.3 Legacy Transmit Descriptor Format
37.5.6.4 TCP/IP Context Transmit Descriptor Format
37.5.6.5 TCP/IP Data Descriptor Format
37.5.6.6 Transmit Descriptor Structure
37.5.6.7 Transmit Descriptor Fetching
37.5.6.8 Transmit Descriptor Write-back
37.5.6.9 Transmit Interrupts
37.5.6.10 Transmit Checksum Off loading
37.5.7 TCP Segmentation
37.5.7.1 Assumptions
37.5.7.2 Transmission Process
37.5.7.3 TCP Segmentation Performance

Datasheet sections

40 Order Number: 320066-003US
37.5.7.4 Packet Format
37.5.7.5 TCP Segmentation Indication
37.5.7.6 TCP Segmentation Data Descriptors
37.5.7.7 IP and TCP/UDP Headers
37.5.7.8 Transmit Checksum Off loading with TCP Segmentation
37.5.7.9 IP/TCP/UDP Header Updating
37.5.7.10 Data Flow
37.5.8 Ethernet Interfaces
37.5.8.1 MAC/PHY GMII/MII Interface
37.5.8.2 Duplex Operation
37.5.8.3 Physical Layer Auto-Negotiation & Link Setup Features
37.5.8.5 Flow Control
37.5.10 Wake on LAN
37.5.10.1 Advanced Power Management Wakeup
37.5.10.2 ACPI Power Management Wakeup
37.5.10.3 Wake-up Packets: Pre-defined Filters
37.5.10.4 Wake-up Packets: Flexible Filters
37.5.11 Serial EEPROM
37.5.11.1 EEPROM Device
37.5.11.2 Software Accesses
37.5.11.3 Signature Field
37.5.11.4 EEPROM Map
37.5.11.5 Hardware Accessed Words
37.5.11.6 Software Accessed Words
37.5.12 Error Handling
37.5.12.1 CSR (Target) Accesses
37.5.12.2 DMA Host (Master) Accesses
37.5.12.3 Internal Memories
37.5.13 Reset Operation
37.5.13.1 Soft Reset
37.5.13.2 MAC Disable
37.5.14 Endianness
37.6 GbE Controller Register Summary
37.6.1 Registers Overview
37.6.1.1 Memory-Mapped Access to Intern al Registers and Memories
37.6.1.2 I/O-Mapped Access to Internal Registers and Memories
37.6.1.3 Register Conventions
37.6.2 General Registers: Detailed Descriptions
37.6.2.1 CTRL – Device Control Register
37.6.2.2 STATUS – Device Status Register
37.6.2.3 CTRL_EXT – Extended Device Control Register
37.6.2.4 CTRL_AUX – Auxiliary Device Control/Status Register
37.6.2.5 EEPROM_CTRL – EEPROM Control Register
37.6.2.6 EEPROM_RR – EEPROM Read Register
37.6.2.7 FCAL – Flow Control Address Low Register
37.6.2.8 FCAH – Flow Control Address High Register
37.6.2.9 FCT – Flow Control Type Register
37.6.2.10 VET – VLAN EtherType Register
37.6.2.11 FCTTV – Flow Control Transmit Timer Value Register
37.6.2.12 PBA – Packet Buffer Allocation Register
37.6.3 Interrupt Registers: Detailed Descriptions
37.6.3.1 ICR0 – Interrupt 0 Cause Read Register
37.6.3.2 ITR0 – Interrupt 0 Throttling Register
37.6.3.3 ICS0 – Interrupt 0 Cause Set Register

Datasheet sections

37.6.3.4 IMS0 – Interrupt 0 Mask Set/Read Register
37.6.3.5 IMC0 – Interrupt 0 Mask Clear Register
37.6.3.6 ICR1 – Interrupt 1 Cause Read Register
37.6.3.7 ICS1 – Interrupt 1 Cause Set Register
37.6.3.8 IMS1 – Interrupt 1 Mask Set/Read Register
37.6.3.9 IMC1 – Interrupt 1 Mask Clear Register
37.6.3.10 ICR2 – Error Interrupt Cause Read Register
37.6.3.11 ICS2 – Error Interrupt Cause Set Register
37.6.3.12 IMS2 – Error Interrupt Mask Set/Read Register
37.6.3.13 IMC2 – Error Interrupt Mask Clear Register
37.6.4 Receive Registers: Detailed Descriptions
37.6.4.1 RCTL – Receive Control Register
37.6.4.2 FCRTL: Flow Control Receive Threshold Low Register
37.6.4.3 FCRTH – Flow Control Receive Threshold High Register
37.6.4.4 RDBAL – Receive Descriptor Base Address Low Register
37.6.4.5 RDBAH – Receive Descriptor Base Address High Register
37.6.4.6 RDLEN – Receive Descriptor Length Register
37.6.4.7 RDH – Receive Descriptor Head Register
37.6.4.8 RDT – Receive Descriptor Tail Register
37.6.4.9 RDTR – RX Interrupt Delay Timer (Packet Timer) Register
37.6.4.10 RXDCTL – Receive Descriptor Control Register
37.6.4.11 RADV – Receive Interrupt Absolute Delay Timer Register
37.6.4.12 RSRPD – Receive Small Packet Detect Interrupt Register
37.6.4.13 RXCSUM – Receive Checksum Control Register
37.6.4.14 MTA[0-127] – 128 Multicast Table Array Registers
37.6.4.15 RAL[0-15] – Receive Address Low Register
37.6.4.16 RAH[0-15] – Receive Address High Register
37.6.4.17 VFTA[0-127] – 128 VLAN Filter Table Array Registers
37.6.5 Transmit Registers: Detailed Descriptions
37.6.5.1 TCTL – Transmit Control Register
37.6.5.2 TIPG – Transmit IPG Register
37.6.5.3 AIT – Adaptive IFS Throttle Register
37.6.5.4 TDBAL – Transmit Descriptor Base Address Low Register
37.6.5.5 TDBAH – Transmit Descriptor Base Address High Register
37.6.5.6 TDLEN – Transmit Descriptor Length Register
37.6.5.7 TDH – Transmit Descriptor Head Register
37.6.5.8 TDT – Transmit Descriptor Tail Register
37.6.5.9 TIDV – Transmit Interrupt Delay Value Register
37.6.5.10 TXDCTL – Transmit Descriptor Control Register
37.6.5.11 TADV – Transmit Absolute Interrupt Delay Value Register
37.6.5.12 TSPMT – TCP Segmentation Pad and Minimum Threshold Register
37.6.6 Statistical Registers: Detailed Descriptions
37.6.6.1 CRCERRS – CRC Error Count Register
37.6.6.2 ALGNERRC – Alignment Error Count Register
37.6.6.3 RXERRC – Receive Error Count Register
37.6.6.4 MPC – Missed Packet Count Register
37.6.6.5 SCC – Single Collision Count Register
37.6.6.6 ECOL – Excessive Collisions Count Register
37.6.6.7 MCC – Multiple Collision Count Register
37.6.6.8 LATECOL – Late Collisions Count Register
37.6.6.9 COLC – Collision Count Register
37.6.6.10 DC – Defer Count Register
37.6.6.11 TNCRS – Transmit with No CRS Count Register
37.6.6.12 CEXTERR – Carrier Extension Error Count Register
37.6.6.13 RLEC – Receive Length Error Count Register
37.6.6.14 XONRXC – XON Received Count Register
37.6.6.15 XONTXC – XON Transmitted Count Register
37.6.6.16 XOFFRXC – XOFF Received Count Register
37.6.6.17 XOFFTXC – XOFF Transmitted Count Register

Datasheet sections

42 Order Number: 320066-003US
37.6.6.18 FCRUC – FC Received Unsupported Count Register
37.6.6.19 PRC64 – Good Packets Received Count (64 Bytes) Register
37.6.6.20 PRC127 – Good Packets Received Count (65-127 Bytes) Register
37.6.6.21 PRC255 – Good Packets Received Count (128-255 Bytes)
37.6.6.22 PRC511 – Good Packets Received Count (256-511 Bytes)
37.6.6.23 PRC1023 – Good Packets Received Count (512-1023 Bytes)
37.6.6.24 PRC1522 – Good Packets Received Count (1024 to Max Bytes)
37.6.6.25 GPRC – Good Packets Received Count (Total) Register
37.6.6.26 BPRC – Broadcast Packets Received Count Register
37.6.6.27 MPRC – Multicast Packets Received Count Register
37.6.6.28 GPTC – Good Packets Transmitted Count Register
37.6.6.29 GORCL – Good Octets Received Count Low Register
37.6.6.30 GORCH – Good Octets Received Count High Register
37.6.6.31 GOTCL – Good Octets Transmitted Count Low Register
37.6.6.32 GOTCH – Good Octets Transmitted Count High Register
37.6.6.33 RNBC – Receive No Buffers Count Register
37.6.6.34 RUC – Receive Undersize Count Register
37.6.6.35 RFC – Receive Fragment Count Register
37.6.6.36 ROC – Receive Oversize Count Register
37.6.6.37 RJC – Receive Jabber Count Register
37.6.6.38 TORL – Total Octets Received Low Register
37.6.6.39 TORH – Total Octets Received High Register
37.6.6.40 TOTL – Total Octets Transmitted Low Register
37.6.6.41 TOTH – Total Octets Transmitted High Register
37.6.6.42 TPR – Total Packets Received Register
37.6.6.43 TPT – Total Packets Transmitted Register
37.6.6.44 PTC64 – Packets Transmitted Count (64 Bytes) Register
37.6.6.45 PTC127 – Packets Transmitted Count (65-127 Bytes) Register
37.6.6.46 PTC255 – Packets Transmitted Count (128-255 Bytes) Register
37.6.6.47 PTC511 – Packets Transmitted Count (256-511 Bytes) Register
37.6.6.48 PTC1023 – Packets Transmitted Count (512-1023 Bytes) Register
37.6.6.49 PTC1522: Packets Transmitted Count (1024-1522 Bytes) Register
37.6.6.50 MPTC – Multicast Packets Transmitted Count Register
37.6.6.51 BPTC – Broadcast Packets Transmitted Count Register
37.6.6.52 TSCTC – TCP Segmentation Context Transmitted Count Register
37.6.6.53 TSCTFC – TCP Segmentation Context Transmit Fail Count
37.6.7 Management Register Descriptions
37.6.7.1 WUC – Wake Up Control Register (0x05800; RW)
37.6.7.2 WUFC – Wake Up Filter Control Register (0x05808; RW)
37.6.7.3 WUS – Wake Up Status Register (0x05810; RW)
37.6.7.4 IPAV – IP Address Valid Register (0x05838; RW)
37.6.7.5 IP4AT[0-3] - (0x5840 - 0x5858; RW) – IPv4 Address Table
37.6.7.6 IPV6_ADDR0BYTES_1_4 – IPv6 Address Table Register (0x5880),
37.6.7.7 IPV6_ADDR0BYTES_5_8 – IPv6 Address Table Register,
37.6.7.8 IPV6_ADDR0BYTES_9_12 – IPv6 Address Table Register,
37.6.7.9 IPV6_ADDR0BYTES_13_16 – IPv6 Address Table Register,
37.6.7.10 FFLT[0-3] – Flexible Filter Length Table Registers
37.6.7.11 FFMT[0-127] – Flexible Filter Mask Table Registers

Datasheet sections

37.6.7.12 FFVT[0-127] – Flexible Filter Value Table Registers
37.6.8 Error Register Descriptions
37.6.8.1 INTBUS_ERR_STAT – Internal Bus Error Status Register
37.6.8.2 MEM_TST – Memory Error Test Register
37.6.8.3 MEM_STS – Memory Error Status Register
37.7 Power Management
37.7.1 Assumptions
37.7.2 D3cold support
37.7.3 Power States
37.7.3.2 D0u State
37.7.3.3 D0a
37.7.4 Timing of Power-State Transitions
37.7.4.1 Power up (off to Dr to D0u to D0a)
37.7.4.2 Transition from D0a to D3 and Back without Reset
37.7.4.3 Transition from D0a to D3 and Back with Reset
37.7.4.4 Reset without Transition to D3
37.7.4.5 Timing Requirements
37.7.4.6 Timing Guarantees
37.7.5 Power Management Extended Capabilities Registers
38.0 Global Configuration Unit
38.1 Overview
38.2 Feature List
38.3 Usage Model
38.3.1 RCOMP
38.3.1.1 GbE
38.3.1.2 LEB
38.4 Register Summary
38.4.1 Detailed Register Descriptions
38.4.1.1 Offset 0x00000010h: MDIO_STATUS - MDIO Status Register
38.4.1.2 Offset 0x00000014h: MDIO_COMMAND - MDIO Command
38.4.1.3 Offset 0x00000018h: MDIO_DRIVE - MDIO Drive Register
38.4.1.4 Offset 0x00000020h: MDC_DRIVE - MDC Drive Register
38.4.1.5 Offset 0x00000024h: GCU_GBE_RC_CTRL - GCU GbE RCOMP
38.4.1.6 Offset 0x00000044h: GCU_GBE_RC_STAT - GCU GbE RCOMP
38.4.1.7 Offset 0x00000050h: GCU_LEB_RC_STAT - GCU Local
38.4.1.8 Offset 0x00000054h: GCU_LEB_RC_CTRL - GCU Local
38.4.1.9 Offset 0x00000060h: SSP_DRIVE - SSP Drive Register
38.4.1.10 Offset 0x00000064h: TDM_DRIVE_3 - TDM Drive Register for
38.4.1.11 Offset 0x00000068h: TDM_DRIVE_12 - TDM Drive Register
38.4.1.12 Offset 0x00000028h: CAN_DRIVE - CAN Drive Register
39.0 Controller Area Network - CAN
39.1 Overview
39.2 Feature List
39.3 Functional Block Diagram
39.4 Usage Model
39.4.1 CAN Basics
39.4.2 Addressing and Bus Arbitration

Datasheet sections

44 Order Number: 320066-003US
39.4.3 Frame Types
39.4.3.1 Data Frame
39.4.3.2 Remote Frame
39.4.3.3 Error Frames
39.4.3.4 Overload Frames
39.4.4 CAN Bit Timing
39.4.4.1 Introduction
39.4.4.2 Setting Proper Bit Rate, tseg1 and tseg2
39.5 Theory of Operation
39.5.1 Modes of Operation
39.5.2 Error Handling
39.5.3 Send/Receive Procedure
39.5.3.1 Send Procedure
39.5.3.2 Receive Procedures
39.5.3.3 Rx Message Processing
39.5.3.4 Acceptance Filter
39.5.3.5 RTR Auto-Reply
39.5.3.6 RxBuffer Linking
39.5.4 TxMessage Registers
39.6 Register Summary
39.6.1 Detailed Register Descriptions
39.6.1.1 Offset 00000000h: Int_status - Interrupt Status Register
39.6.1.2 Offset 00000004h: Int_Ebl - Interrupt Enable Register
39.6.1.3 Offset 00000008h: Buffer Status - Buffer Status Indicators
39.6.1.4 Offset 0000000Ch: ErrorStatus - Error Status Indicators
39.6.1.5 Offset 00000010h: Command - Operating Modes
39.6.1.6 Offset 00000014h: Config - CAN Configuration Register
39.6.1.7 Offset 00000020h: TxMessageControl[0-7] - Transmit Message Control and
39.6.1.8 Offset 00000024h: TxMessageID[0-7] - Transmit Message ID
39.6.1.9 Offset 00000028h: TxMessageDataHigh[0-7] - Transmit Message Data High
39.6.1.11 Offset 000000A0h: RxMessageControl[0-15] - Receive Message Command
39.6.1.12 Offset 000000A4h: RxMessageID[0-15] - Receive Message ID
39.6.1.13 Offset 000000A8h: RxMessageDataHigh[0-15] - Receive Message Data High
39.6.1.15 Offset 000000B0h: RxMessageAMR[0-15] - Receive Message AMR
39.6.1.16 Offset 000000B4h: RxMessageACR[0-15] - Receive Message ACR
39.6.1.17 Offset 000000B8h: RxMessageAMR_Data[0-15] - Receive Message AMR Data
39.6.1.18 Offset 000000BCh: RxMessageACR_Data[0-15] - Receive Message ACR Data
40.0 SSP Serial Port
40.1 Overview
40.2 Feature List
40.3 Theory of Operation
40.3.1 Endianness
40.3.2 Error Handling
40.4 Register Summary
40.4.1 SSP Control Register
40.4.1.1 Offset 00h: SSCR0 - SSP Control Register 0 Details
40.4.1.2 Data Size Select (DSS)

Datasheet sections

40.4.1.3 Frame Format (FRF)
40.4.1.4 External Clock Select (ECS)
40.4.1.5 Synchronous Serial Port Enable (SSE)
40.4.1.6 Serial Clock Rate (SCR)
40.4.2 SSP Control Register
40.4.2.1 Offset 04h: SSCR1 - SSP Control Register 1 Details
40.4.2.2 Receive FIFO Interrupt Enable (RIE)
40.4.2.3 Transmit FIFO Interrupt Enable (TIE)
40.4.2.4 Loop Back Mode (LBM)
40.4.2.5 Serial Clock Polarity (SPO)
40.4.2.6 Serial Clock Phase (SPH)
40.4.2.7 National Microwire* Data Size (MWDS)
40.4.2.8 Transmit FIFO Interrupt Threshold (TFT)
40.4.2.9 Receive FIFO Interrupt Threshold (RFT)
40.4.2.10 Enable FIFO Write/Read Function (EFWR)
40.4.2.11 Select FIFO for Enable FIFO Write/Read (STRF)
40.4.3 SSP Status Register
40.4.3.1 Offset 08h: SSSR - SSP Status Register Details
40.4.3.2 Transmit FIFO Not Full Flag (TNF) (Read-Only,
40.4.3.3 Receive FIFO Not Empty Flag (RNE)
40.4.3.4 SSP Busy Flag (BSY) (Read-Only, Non-Interruptible)
40.4.3.5 Transmit FIFO Service Request Flag (TFS) (Read-Only,
40.4.3.6 Receive FIFO Service Request Flag (RFS) (Read-Only,
40.4.3.7 Receiver Overrun Status (ROR) (Read/Write,
40.4.3.8 Transmit FIFO Level
40.4.3.9 Receive FIFO Level
40.4.4 SSP Interrupt Test Register
40.4.4.1 Offset 0Ch: SSITR - SSP Interrupt Test Register Details
40.4.5 SSP Data Register
40.4.5.1 Offset 10h: SSDR - SSP Data Register Details
41.0 IEEE 1588 Time Synchronization Hardware Assist
41.1 Overview
41.2 Feature List
41.2.1 Signal Descriptions
41.3 Functional Block Diagram
41.4 Usage Model
41.4.1 Channel Mapping
41.5 Functional Description
41.5.1 IEEE 1588 Overview
41.5.1.1 Initialization
41.5.1.2 Time Synchronization
41.5.1.3 PTP Message Formats
41.5.2 Time Stamping Operation
41.5.2.1 Sync Messages
41.5.2.2 Follow-up Messages
41.5.2.3 Delay_Req Message
41.5.2.4 Delay_Response Messages
41.5.2.5 Error Handling
41.5.3 IEEE1588 over Ethernet
41.5.3.1 Timestamping Mechanism
41.5.3.2 PTP Message Detection in Ethernet Frames
41.5.3.3 Modes of Operation

Datasheet sections

46 Order Number: 320066-003US
41.5.4 IEEE1588 over CAN
41.5.5 Auxiliary Snapshots
41.5.6 Target Time Expiration
41.5.7 System Time
41.5.8 Interrupts
41.5.9 Reset
41.6 Register Summary
41.6.1 Detailed Register Descriptions
41.6.1.1 Offset 0000h: TS_Control - Time Sync Control Register
41.6.1.2 Offset 0004h: TS_Event - Time Sync Event Register
41.6.1.3 Offset 0008h: TS_Addend - Addend Register
41.6.1.4 Offset 000Ch: TS_Accum - Accumulator Register
41.6.1.5 Offset 0010h: TS_Test - Time Sync Test Register
41.6.1.6 Offset 0014h: TS_PPS - PPS Compare Register
41.6.1.7 Offset 0018h: TS_TSysTimeLo - Raw System Time Low Register
41.6.1.8 Offset 001Ch: TS_RSysTimeHI - Raw System Time High Register
41.6.1.9 Offset 0020h: TS_SysTimeLo - System Time Low Register
41.6.1.10 Offset 0024h: TS_SysTimeHi - System Time High Register
41.6.1.11 Offset 0028h: TS_TrgtLo - Target Time Low Register
41.6.1.12 Offset 002Ch: TS_TrgtHi - Target Time High Register
41.6.1.13 Offset 0030h: TS_ASMLo - Auxiliary Slave Mode Snapshot
41.6.1.14 Offset 0034h: TS_ASMHi - Auxiliary Slave Mode Snapshot
41.6.1.15 Offset 0038h: TS_AMMSLo - Auxiliary Master Mode Snapshot
41.6.1.17 Offset 0040h: TS_Ch_Control[0-7] - Time Synchronization Channel Control
41.6.1.18 Offset 0044h: TS_CH_EVENT[0-7] - Time Synchronization Channel Event
41.6.1.19 Offset 0048h: TS_TxSnapLo[0-7] - Transmit Snapshot Low Register (Per
41.6.1.20 Offset 004Ch: TS_TxSnapHi[0-7] - Transmit Snapshot High Register (Per
41.6.1.21 Offset 0050h: TS_RxSnapLo[0-7] - Receive Snapshot Low Register (Per
41.6.1.22 Offset 0054h: TS_RxSnapHi[0-7] - Receive Snapshot High Register (Per
41.6.1.23 Offset 0058h: TS_SrcUUIDLo[0-7] - Source UUID0 Low Register (Per
41.6.1.24 Offset 005Ch: TS_SrcUUIDHI[0-7] - SequenceID/SourceUUID High Register
41.6.1.25 Offset 0140h: TS_CANx_Status[0-1] - Time Synchronization Channel Event
41.6.1.26 Offset 0144h: TS_CANSnapLo[0-1] - Transmit Snapshot Low Register (Per
41.6.1.27 Offset 0148h: TS_CANSnapHi[0-1] - Transmit Snapshot High Register (Per
41.6.1.28 Offset 01F0h: TS_Aux_TrgtLo - Auxiliary Target Time Low
41.6.1.29 Offset 01F4h: TS_Aux_TrgtHi -Auxiliary Target Time High
41.6.1.30 Offset 0200h: L2_EtherType - L2 EtherType Register
41.6.1.31 Offset 0204h: UD_EtherType - User Defined EtherType Register
41.6.1.32 Offset 0208h: UD_Header_Offset - User Defined Header Offset
41.6.1.33 Offset 020Ch: UD_Header - User Defined Header Register

Datasheet sections

42.0 Local Expansion Bus Controller
42.1 Overview
42.2 Feature List
42.3 Block Diagram
42.4 Theory of Operation
42.4.1 Outbound Transfers
42.4.1.1 Chip Select Address Allocation
42.4.1.2 Address and Data Byte Steering
42.4.1.3 Expansion Bus Interface Configuration
42.4.1.4 Using I/O Wait
42.4.1.5 Parity
42.4.1.6 Special Design Knowledge for Using HPI mode
42.4.1.7 Expansion Bus Outbound Timing Diagrams
42.5 Register Summary
42.5.1 Timing and Control Registers
42.5.1.1 EXP_TIMING_CS0 - Expansion Bus Timing Register
42.5.1.2 EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers
42.5.2 Configuration and Status Registers
42.5.2.1 EXP_CNFG0 - Configuration Register
42.5.2.2 EXP_PARITY_STATUS - Expansion Bus Parity Status Register
42.6 Performance Estimation
43.0 Global Design for Test Features
43.1 JTAG
43.1.1 JTAG Functions Overview
43.1.2 EP80579 TAP Controllers
43.1.2.1 IA-32 Core
43.1.2.2 MCH TAP Extension
43.1.3 EP80579 JTAG ID Codes
43.1.4 Special Requirements and Limitations
43.1.5 JTAG Instructions Summary: MCH
43.2 I/O Testing
43.2.1 JTAG Boundary Scan
43.2.1.1 Pins Excluded from Boundary Scan Chain
44.0 IA-32 Core
44.1 JTAG
44.1.1 Usage
44.1.1.1 Description
45.0 IMCH Design for Test
45.1 IMCH Design for Test Features
45.1.1 Features
45.2 JTAG
45.2.1 IMCH JTAG Instructions
45.2.1.1 JTAG Chain Details
45.3 High Speed I/O Testing
46.0 ICH Design for Test
46.1 JTAG
46.2 I/O Test Mode
46.2.1 Test Mode Entry Methods
46.2.1.1 Non-Functional Test Mode Entry
46.2.2 Test Mode Registers
46.2.2.1 TEST0 - Test Control Register

Datasheet sections

48 Order Number: 320066-003US
46.2.3 XOR Chains
47.0 SKUs, Power Savings and Pre-Boot Firmware
47.1 Overview
47.2 SKUs, Strap Options and Pre-Boot Firmware Programmable Configuration Modes
47.2.1 SKU Features
47.2.2 DDR2 Frequencies Supported by the EP80579
47.2.3 Strap Options (Platform-based Configuration)
47.2.4 Pre-Boot Firmware Programmable SKU Options
48.0 Package Specifications
48.1 Package Introduction
48.2 Functional Signal Definitions
48.3 JTAG Boundary Scan Chain (BSC) and XOR Chain
48.4 Signal Pin Descriptions
48.4.1 IA-32 Core
48.4.1.1 Thermal Diode
48.4.1.2 Global Clock CRU
48.4.1.3 Sideband Miscellaneous Signals
48.4.2 Integrated Memory Controller Hub (IMCH)
48.4.2.1 IMCH Reset
48.4.2.2 DDR2 SDRAM
48.4.2.3 PCI Express*
48.4.3 Integrated I/O Controller Hub (IICH)
48.4.3.1 Real Time Clock
48.4.3.2 General Purpose I/O (GPIO) and Interrupts
48.4.3.3 Serial Peripheral Interface (SPI)
48.4.3.4 Low Pin Count (LPC) Interface
48.4.3.5 SMBus
48.4.3.6 UART Interface
48.4.3.7 Serial ATA (SATA) Interface
48.4.3.8 Universal Serial Bus (USB) Interface
48.4.3.9 Power Management Interface
48.4.3.10 IICH Miscellaneous Signals
48.4.4 Acceleration and I/O Complex (AIOC)
48.4.4.1 Controller Area Network (CAN) Bus
48.4.4.2 Gigabit Ethernet (GbE) Interface
48.4.4.3 Time Division Multiplexing (TDM) Interface
48.4.4.4 Local Expansion Bus (LEB) Interface
48.4.4.5 Synchronous Serial Port (SSP) Interface
48.4.4.6 IEEE 1588-2008 Hardware Assist Interface
48.4.5 Miscellaneous
48.4.5.1 JTAG
48.4.5.2 Miscellaneous Signals
48.4.5.3 Reserved
48.4.5.4 No Connect
48.4.6 Power
48.5 Flip-Chip Ball Grid Array (FCBGA) Package Dimensions
48.6 Ball Map Information
49.0 Electrical Specifications
49.1 Absolute Maximum Ratings
49.1.1 Input and I/O Pin Undershoot and Overshoot Specifications
49.2 Power Characteristics
49.2.1 Power Supply Requirements

Datasheet sections

49.3 Clocks
49.3.1 External Clock Requirements
49.4 Power and Reset Sequencing
49.5 AC/DC Characteristics
49.5.1 Power Management
49.5.1.1 Power Management Signal List
49.5.1.2 Power Management AC Characteristics
49.5.2 DDR2
49.5.2.1 DDR2 Signal List
49.5.2.2 DDR2 DC Characteristics
49.5.2.3 DDR2 AC Characteristics
49.5.3 PCI Express*
49.5.3.1 PCI Express* Signal List
49.5.3.2 PCI Express* Differential Transmitter and Receiver Specifications
49.5.3.3 PCI Express* Clock Specifications
49.5.4 Serial ATA (SATA)
49.5.4.1 SATA Signal List
49.5.4.2 SATA DC Characteristics
49.5.4.3 SATA DC Output Characteristics
49.5.4.4 SATA LED
49.5.4.5 SATA AC Characteristics
49.5.5 Universal Serial Bus (USB)
49.5.5.1 USB Signal List
49.5.5.2 USB DC Characteristics
49.5.5.3 USB AC Characteristics
49.5.5.4 USB AC Specifications
49.5.6 System Management Bus (SMBus)
49.5.6.1 SMBus Signal List
49.5.6.2 SMBus DC Characteristics
49.5.6.3 SMBus AC Characteristics
49.5.7 UART
49.5.7.1 UART Signal List
49.5.7.2 UART DC Characteristics
49.5.7.3 UART AC Characteristics
49.5.7.4 UART Receiver AC Specifications
49.5.8 Serial Peripheral Interface (SPI)
49.5.8.1 SPI Signal List
49.5.8.2 SPI DC Characteristics
49.5.8.3 SPI AC Characteristics
49.5.9 Low Pin Count (LPC)
49.5.9.1 LPC Signal List
49.5.9.2 LPC DC Characteristics
49.5.9.3 LPC AC Characteristics
49.5.10 General Purpose I/O (GPIO)
49.5.10.1 GPIO Signal List
49.5.10.2 GPIO DC Characteristics
49.5.10.3 GPIO AC Specifications
49.5.11 IICH Interrupt Signal
49.5.11.1 IICH Interrupt Signal List
49.5.11.2 IICH Interrupt Signal DC Characteristics
49.5.11.3 IICH Interrupt Signal AC Input, Output Characteristics
49.5.11.4 IICH Interrupt Signal Timing Specification
49.5.11.5 IICH Clock AC Specifications
49.5.12 Real Time Clock (RTC)
49.5.12.1 RTC Signal List
49.5.12.2 RTC DC Characteristics
49.5.12.3 RTC AC Characteristics

Datasheet sections

50 Order Number: 320066-003US
49.5.13 Gigabit Ethernet (GbE: RMII, RGMII, MDIO, EEPROM)
49.5.13.1 Gigabit Ethernet Signal List
49.5.13.2 Gigabit Ethernet DC Characteristics
49.5.13.3 Gigabit Ethernet AC Characteristics
49.5.13.4 GbE Reset Conditions
49.5.13.5 RComp
49.5.13.6 Voltage Domains
49.5.14 Time Division Multiplex (TDM)
49.5.14.1 TDM Signal List
49.5.14.2 TDM DC Characteristics
49.5.14.3 TDM DC Clock Specification
49.5.14.4 TDM AC Characteristics
49.5.15 Local Expansion Bus (LEB)
49.5.15.1 LEB Signal List
49.5.15.2 LEB DC Characteristics
49.5.15.3 LEB AC Characteristics
49.5.16 Controller Area Network (CAN)
49.5.16.1 CAN Signal List
49.5.16.2 CAN DC Characteristics
49.5.17 Synchronous Serial Port (SSP)
49.5.17.1 SSP Signal List
49.5.17.2 SSP DC Characteristics
49.5.17.3 SSP AC Characteristics
49.5.18 IEEE 1588-2008 Hardware Assist Interface
49.5.18.1 IEEE 1588-2008 Hardware Assist Signal List
49.5.18.2 IEEE 1588-2008 Hardware Assist DC Characteristics
49.5.18.3 IEEE 1588-2008 Hardware Assist AC Characteristics
49.5.19 IICH Miscellaneous Signals (PME#, PCIRST#, SPKR)
49.5.19.1 IICH Miscellaneous Signal List
49.5.19.2 IICH Miscellaneous Signals DC Characteristics
49.5.19.3 IICH Miscellaneous Signals AC Characteristics
49.5.20 Clock Resource Unit (CRU)
49.5.20.1 CRU Signal List
49.5.20.2 CRU DC Characteristics
49.5.20.3 CRU AC Specifications
49.5.21 Sideband Miscellaneous Signals
49.5.21.1 Sideband Miscellaneous Signals Signal List
49.5.21.2 Sideband Miscellaneous Signals DC Characteristics
49.5.21.3 Sideband Miscellaneous Signals AC Characteristics
49.5.22 IMCH Reset
49.5.22.1 IMCH Reset Signal List
49.5.22.2 IMCH Reset Signals DC Characteristics
49.5.22.3 IMCH Reset Signals AC Characteristics
49.5.23 JTAG
49.5.23.1 JTAG Signal List
49.5.23.2 JTAG DC Characteristics
49.5.23.3 JTAG AC Characteristics
50.0 Thermal Specifications and Design Considerations
50.1 Thermal Characteristics
50.1.1 Specifications
50.1.2 Thermal Design Power (TDP) Dissipation
50.2 Thermal Sensor
50.2.1 Catastrophic Thermal Protection
50.2.1.1 THRMTRIP# Control Sequence
50.2.2 Thermal Sensor Features
50.2.2.1 PROCHOT# Control Sequence

Datasheet sections

50.2.2.2 Processor Passive Cooling
50.2.2.3 On-Demand Passive Cooling

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Legal Lines and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Intel, Intel logo, Intel StrataFlash and Pentium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2009, Intel Corporation. All Rights Reserved.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 3 Product Features System on a Chip (SoC) — Integrated Intel ® Architecture (IA) processor and chipset (MCH/ICH) technology — Extensive integration of standard Intel architecture communications interfaces provide cost, power and board area savings (Gigabit Ethernet (GbE), Time Division Multiplexing (TDM) ‡ processing, Security Services Unit (SSU),‡ and Acceleration Services Units (ASU)‡) SKU Support1 — Embedded: Intel architecture compatibility and high-speed interfaces (GbEs, PCI Express*) — Application Services: Security — Packet security compatibility and IP Telephony packet security, TDM, and High-Level Data Link Control (HDLC) Intel Architecture Processor — Low-power and high-performance architecture based on Intel Architecture (IA-32) processor — Three operating frequency SKUs: - 600 MHz, 1066 MHz, or 1200 MHz — 256 KB L2 data coherent cache (2 way) Integrated Memory Control Hub (IMCH) and Integrated I/O Control Hub (IICH) Compatible — Enhanced DMA (EDMA) controller — Two SATA Gen1 or Gen2 interfaces — Two USB 1.1 or USB 2.0 ports — Two integrated, 16550-compatible UARTs — LPC 1.1 interface — Serial Peripheral Interface (SPI) — Two SMBus 2.0 compliant interfaces —G P I O s — Watchdog Timer — One 32/64-bit and two 32-bit high-precision event timers Acceleration Services Unit (ASU)‡ — High performance accelerator on-chip engines for packet processing — Support capabilities for commonly used protocol implementations such as TCP/IP, UDP, IPSec, SSL, NAT, and SRTP Security Services Unit (SSU)‡ — High-performance on-chip Crypto Accelerator — Support capabilities for commonly used cryptographic protocol implementations † Intel recommends using the SPI for Pre-boot firmware due to the reduced availability of LPC FWH. ‡ Feature must be enabled with EP80579 software. Refer to the EP80579 software documentation for more information. 1. For complete information about product features and SKUs, please refer to Chapter 47.0, “SKUs, Power Savings and Pre-Boot Firmware”. Single-Channel Double-Data-Rate (DDR) SDRAM Memory — Supports DDR2 at 400/533/667/800 MT/s — Supports 32 or 64-bit interfaces — Error correction code (ECC); single-bit correct/ double-bit detect (SEC/DED) coverage — Addressable from Intel architecture processor and PCI Express Three Gigabit Ethernet MACs — Three 10/100/1000 ports with RGMII/RMII interfaces — MDIO interface for external PHY configuration — Serial EEPROM interface supports network boot and wake-on LAN Industry Standard PCI Express Interface — Supports 1x8, 2x4, or 2x1 configurations as a root complex Integrated Serial ATA (SATA) Host Controllers — Independent DMA operation on two ports — Data transfer rates up to 3.0 Gb/s —A l t e r n a t e D e v i c e I D Integrated High-speed Serial Interface (TDM)‡ — Supports up to 12 external T1/E1 and codecs — Supports up to 128 HDLC channels Local Expansion Bus (LEB) — Supports up to eight chip selects — 25-bit address and 16-bit data — Supports HPI-8 and HPI-16 Dual Controller Area Network (CAN) — Supports two CAN 2.0b interfaces Single Synchronous Serial Port (SSP) Compatible IEEE 1588-2008 Hardware Assistance — Supports two GbE and two CAN interfaces — Time master/target support 1088-Ball FCBGA package — Dimensions of 37.5 mm x 37.5 mm — 1.092-mm solder ball pitch — Lead-free only — RoHS 5/6 compliant Typical Applications — Embedded, Security and/or IP Telephony

applications

Revision History

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Changed the following signal names:

E X _ R E Q _ G N T # t o R e s e r v e d 1 9
E X _ S L A V E _ C S # t o R e s e r v e d 2 0
E X _ G N T _ R E Q # t o N C 5 7
E X _ W A I T # t o N C 5 8
EX_WDTXFER to NC59 Corrected signal name:
SIU_CST1 to SIU_CST1#
SIU_CST2 to SIU_CST2# Updated:
Section Product Features
Table 1-4, “Glossary Table”
Table 2-1, “EP80579 External Interface Summary”
Table 5-32, “Summary of Local Expansion Bus Error Conditions”
Table 6-5, “Powergood Reset Timings”
Section 6.3.2.1, “Transitioning Between Power States”
Section 11.4.6, “RCOMP”
Section 16.5.1.64, “Offset 268h: DDRIOMC2 - DDR IO Mode Control Register 2”
Section 23.1.1.5, “PI - Programming Interface Register”
Section 37.5.11.6.3, “Checksum Word Calculation”
Section 42.5, “Register Summary”
Table 42-7, “EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers”
Table 42-9, “EXP_PARITY_STATUS - Expansion Bus Parity Status Register”
Table 42-10, “LEB Performance Calculation - Estimated AIOC Latencies”
Table 48-24, “Expansion Bus Signals”
Table 48-22, “Gigabit Ethernet Interface Signals” with signal name changes
Figure 49-28, “LPC Valid Delay from Rising Clock Edge Diagram” and Figure 49-32, “IICH Clock (CLK14) Timing Diagram” with signal name corrections
Table 49-10, “Power Management DC Input Characteristics” PWRBTN# pin
Table 49-11, “Power Management DC Output Characteristics” PWRBTN# pin
Table 49-36, “SMBus DC Input Characteristics” Intruder# pin
Table 49-37, “SMBus DC Output Characteristics” Intruder# pin
Table 49-106, “IMCH Reset Signals DC Input Characteristics” CLK100 (Continued Next Page)

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Industrial temperatures to Chapter 49.0, “Electrical Specifications” and Chapter 50.0, “Thermal Specifications and Design Considerations” The following changes were made due to defeaturing LEB Mastering:
Section 2.2, “Signaling Architecture”
Table 2-1, “EP80579 External Interface Summary” - LEB Description
Table 2-4, “Summary of Communication” - removed “LEB Master”
Table 3-7, “Address Space Sizes of AIOC-attached Devices” - removed LEB row
N o t e E i n Table 3-11, “PCI Configuration Header Support for Type 0 Headers in AIOC Devices”
Section 4.2.2, “Other Agents” - fourth bullet removed “master”
Table 5-32, “Summary of Local Expansion Bus Error Conditions” - Notes description
R e m o v e d r o w s i n Table 7-67, “Bus M, Device 8, Function 0: Summary of Local Expansion Bus Registers Mapped Through CSRBAR PCI Memory BAR"” containing LEB content
Removed LEB content from Section 36.3, “Local Expansion Bus Interface (LEB)”
Removed content from Section 42.0, “Local Expansion Bus Controller”
“EXP_MST_CONTROL - Expansion Bus Control Register”
“EXP_LOCK0 - Expansion Bus Lock Register”
“Offset D0500010h: CMD_TRNS1_W[0-3] - Command Translation Window Register “
Removed LEB content from Section 42.1, “Overview” and Section 42.2, “Feature List”
Removed LEB content from Figure 42-1, “Expansion Bus Controller”
Removed LEB content and also “Inbound Transfers” , “Arbitration”, “Expansion Bus Inbound Timing Diagrams” and “External Expansion Bus Timing Diagram” content from Section 42.4, “Theory of Operation”
Removed Table 42-16 and Section 42.5.2.6 Removed: Removed two rows with D30/D31 content from Table 1-4, Section 6.1.2.3.1, “IICH”, Table 28-9, and from PCIRST# description in Table 48-28. Date Revision Description

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Added:

Chapter 28.0, “IA-32 Core Interface” Updated:
Figure 6-1, “Powergood and Reset Interface”
Table 49-12, “Power Sequencing Signal Timings”
Table 16-26, “Offset 9Ch: DEVPRES - Device Present Register”
Table 16-40, “Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register”
Section 22.1, “Overview”
T e x t i n Section 35.12.1.9, “Offset 14h: MMBAR – Expansion Bus Base Address Register”
T e x t i n Section 42.5.1.2, “EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers”
Figure 42-2, “Chip Select Address Allocation When There Are no 32-MByte Devices Programmed”
Figure 42-4, “Chip Select Address Allocation when a 32 Mbyte device is programmed”
Figure 48-3, “FCBGA Package — Bottom View”
Table 48-24, “Expansion Bus Signals”
Table 48-29, “Reserved Pin List”
Table 48-30, “No Connect Pin List”
Table 49-7, “Maximum Supply Current Embedded SKU”
Table 49-11, “Power Management DC Output Characteristics”
Table 49-36, “SMBus DC Input Characteristics”
Table 49-38, “SMBus DC Clock Specification”
Table 49-48, “SPI DC Output Characteristics”
Table 49-67, “DC Output Characteristics: RMII Mode of Operation”
Table 49-82, “EEPROM Timing Values”
Table 49-84, “TDM DC Output Characteristics”
Table 49-89, “LEB DC Output Characteristics”
Table 49-93, “CAN DC Output Characteristics”
Table 49-95, “SSP DC Output Characteristics”
Table 49-99, “IEEE 1588-2008 Hardware Assist DC Output Characteristics”
Table 49-101, “IICH Miscellaneous Signals DC Output Characteristics”
Table 49-108, “JTAG DC Output Specifications (BPM4_PRDY_OUT)” July 2008 001 Initial release of this document. Date Revision Description

Order Number: 320066-003US Introduction and Overview, Volume 1 of 6

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1.0 Introduction

1.1 Introduction

The Intel® EP80579 Integrated Processor product line is made of up of the Intel® EP80579 Integrated Processor and the Intel® EP80579 Integrated Processor with Intel® QuickAssist Technology. The Intel® EP80579 Integrated Processor product line is an integrated System On a Chip (SoC). The Intel® EP80579 Integrated Processor with Intel® QuickAssist Technology architecture combines Intel Architecture (IA)-based communications processors, a memory hub controller (IMCH), an I/O architecture (IICH), and high speed I/O interfaces (PCI Express*, Gigabit Ethernet). The Intel EP80579 Integrated Processor with Intel® QuickAssist Technology also features high- performance packet processing and security capabilities. The Intel® EP80579 Integrated Processor product line architecture is designed to provide best-in-class processing performance, stringent power usage, and reasonable cost targets while maintaining IA implementation and providing the required I/O throughput. The intended audience for this document is architects, hardware/software design engineers or designer who may need specific technical information for the development and programming of the EP80579 integrated processor SoC. This document is also intended for an audience that has a thorough understanding of IA-32 microprocessor, memory controller and I/O architectures as well as a basic understanding of system software architectures (operating system and pre-boot firmware).

1.2 Document Organization

Note: The Intel® EP80579 Integrated Processor product line is referred to as the "EP80579". In cases where the features are specific to a given processor we will use Intel® EP80579 Integrated Processor or Intel® EP80579 Integrated Processor with Intel® QuickAssist Technology. This document first provides an overview of the Intel® EP80579 Integrated Processor product line architecture. The overview chapter provides a block diagram and defines the ’s external and internal interfaces. This is followed by a functional description of the following blocks:

IA Complex (including the IA-32 core, IMCH and IICH).
Acceleration and I/O Complex (including ASU, SSU, and high-speed I/O interfaces such as Gigabit Ethernet and TDM).
Test and Debug information, including JTAG.
Technical Specifications (SKUs, Packaging, Electrical and Thermal).

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1.3 Referenced Document s and Related Websites

Visit the Intel® EP80579 Integrated Processor product line Website for other information: http://www.intel.com/go/SoC Table 1-1. Referenced Documents Document Title Location Advanced Configuration and Power Interface (ACPI) Specification http://www.acpi.info/ Enhanced Host Controller Specification (EHCI and UHCI) http://www.intel.com/technology/USB/spec.htm/ IEEE 1149.1: IEEE Standard Test Access Port and Boundary-Scan Architecture http://ieeexplore.ieee.org IEEE 1588:Precision Clock Synchronization Protocol for Networked Measurement and Control Systems http://ieeexplore.ieee.org Intel Architecture Software Developer’s Manual, Volumes 1–3 http://developer.intel.com/design/pentium4/ manuals/index_new.htm#sdm_vol1 Intel Corporation, Advanced Host Controller Interface Specification for Serial ATA http://www.intel.com/technology/serialata/ ahci.htm Intel Corporation, Enhanced Host Controller Interface Specification for Universal Serial Bus http://www.intel.com/technology/usb/ ehcispec.htm Intel Corporation, Low Pin Count (LPC) Interface Specification http://www.intel.com/design/chipsets/industry/ lpc.htm Intel Corporation, Multiprocessor Specification http://www.intel.com/design/archives/processors/ pro/docs/242016.htm Intel Corporation, Universal Host Controller Interface (UHCI) Specification http://www.intel.com/technology/usb/ ehcispec.htm Intel Corporation, Universal Serial Bus (USB) Specification http://www.intel.com/technology/usb/spec.htm Intel Corporation, USB2 Debug Device Functional Specification http://www.intel.com/technology/usb/download/ DebugDeviceSpec_R090.pdf Intel® 82093AA I/O Advanced Programmable Interrupt Controller (I/O APIC) http://www.intel.com/design/chipsets/specupdt/ 290710.htm?iid=search& Intel® EP80579 Integrated Processor product line Platform Design Guide http://www.intel.com/go/SoC Intel® EP80579 Integrated Processor product line Specification Update http://www.intel.com/go/SoC Intel® EP80579 Integrated Processor product line Thermal/Mechanical Design Guide http://www.intel.com/go/SoC JEDEC Specification http://www.jedec.org/default.cfm Low Pin Count Specification (LPC) http://www.intel.com/design/chipsets/industry/ lpc.htm Serial ATA Specification http://www.serialata.org/specifications.asp SMBus Specification http://www.smbus.org/specs/ Universal Host Controller Specification (EHCI and UHCI) http://www.intel.com/technology/USB/spec.htm/ Universal Serial Bus Specification http://www.usb.org/developers/docs/ http://www.intel.com/technology/USB/spec.htm/

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1.4 Acronyms

This section describes acronyms that are used throughout this document. Table 1-2. Related Websites Specification or Technology Website AC’97 Rev 2.2 Specification http://developer.intel.com/ial/scalableplatforms/ audio/index.htm #97spec/ ACPI and related specifications http://www.acpi.info/spec.htm AT Attachment-6 with Packet Interface (ATA/ATAPI-6) http://T13.org (T13 1410D) BIOS Boot Specifications http://www.phoenix.com/en/customer+services/ white+papers-specs/ Communication and Network Riser Rev 1.2 Specification http://developer.intel.com/technology/cnr/ download.htm Front Panel I/O Connectivity Design Guide http://www.formfactors.org/DeveloperResources.asp PCI and PCI Express* related specifications http://www.pcisig.com/specifications PIRQ Routing Table Information http://www.microsoft.com/whdc/archive/pciirq.mspx Power Management Specifications http://www.microsoft.com/whdc/resources/respec/ specs/pmref/default.mspx Table 1-3. Acronym Table Term Description ACPI Advanced Configuration and Power Interface Specification, an industry specification of the common interfaces enabling robust operating system (OS)-directed motherboard device configuration and power management of both devices and entire systems. AHCI Advanced Host Controller Interface, an industry specification of the interface between memory and SATA devices. AIO IMCH A-unit I/O Mux Leg AIOC Acceleration and I/O Complex AMC Audio/Modem Codec ARP Address resolution protocol ASF Alert Specification Format. This is the next generation of “Alert on LAN*” implementation. ASU Acceleration Services Unit BAR PCI Base Address Register used to define the base and limit of an I/O or memory region assigned to a PCI device. BER Bit Error Rate BGA Ball Grid Array CM Coherent Memory CMC Common Mode Choke CMI C ore (IA-32 core) interface, Memory controller hub, I/O controller hub CNR Communications and Networking Riser CRC See Cyclic Redundancy Check in Table 1-4. CSMA/CD Carrier Sense Multiple Access/Carrier Detect DDP Direct Data Placement Protocol DDR DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) is a system memory technology.

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DED Double-bit Error Detect DMA See Direct Memory Access in Table 1-4. DW Double Word. A legacy reference to 32 bits of data on a naturally aligned four-byte boundary (i.e. the least significant two bits of the byte address are b00). This is a legacy term used by PCI and must not be used other than in that context. ECC Error Checking and Correction EDMA Enhanced DMA EMI Electro Magnetic Interference EOP/EOF End Of Packet / End Of Frame ESD Electrostatic Discharge EXP A generic designation for the I/O interconnect technology also known as PCI Express*. FRU Field Replaceable Unit FS Full-speed. Refers to USB. FSB Front Side Bus (a common external interface for IA processors) FWH Firmware Hub. A non-volatile memory device used to store the system BIOS/pre-boot firmware. GbE Gigabit Ethernet controller GMII Gigabit MII HBA Host Bus Adapter - necessary when connecting a peripheral to a computer that doesn’t have native support for that peripheral’s interface. HCD Host Controller Device - USB interface for programmers HECBASE PCI Express* Enhanced Configuration Base Register HPET High Precision Event Time (HPET) - The IA-PC HPET Architecture defines a set of timers that can be used by the operating system. The timers are defined such that the OS may be able to assign specific timers to be used directly by specific applications. Each timer can be configured to generate a separate interrupt. HSI High Speed Interface. Refers to USB. I/O 1. Input/Output. 2. When used as a qualifier to a transaction type, specifies that transaction targets Intel Architecture™ specific I/O space (e.g., I/O read). IA Intel Architecture instruction set commonly known as “x86” IA-CPU IA-CPU, IA Complex and IA Processor are the same terminology ICH I/O Controller Hub, ICH and IICH are interchangeable for entire document IICH Integrated I/O Controller Hub, ICH and IICH are interchangeable for entire document IMCH Integrated Memory Controller Hub, MCH and IMCH are interchangeable for the entire document INTx Legacy PCI interrupt architecture that encodes interrupts on one of four side-band signals (INTA, INTB, INTC, and INTD). IP Internet Protocol ISA See Industry Standard Architecture in Table 1-4 LEB Local Expansion Bus, or LE Bus LML Latency Measurement Logic LPC Low Pin Count LS Low-speed. Refers to USB. LSb Least Significant Bit Table 1-3. Acronym Table Term Description

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 97 Intel® EP80579 Integrated Processor LSB Least Significant Byte MCH Memory Controller Hub, MCH and IMCH are interchangeable for the entire document MII Media Independent Interface (16 pins per port) MMIO Memory Mapped I/O MMR Memory Mapped Register MSb Most Significant Bit MSB Most Significant Byte MSI Message-signaled interrupt that encodes inte rrupts as an in-band 32-bit write transaction. MTBF Mean Time Between Failures NCM Non Coherent Memory NIC Network interface controller NOS Network Operating System NSI North South Interface. The designation for the proprietary, internal high-speed serial interconnect between the IMCH and the IICH. OS Operating System. OSPM Operating System directed Power Management P2P See Peer-to-Peer in Table 1-4 PB Packet Buffer PBM Packet Buffer Memory PCI Peripheral Component Interconnect Local Bus. A 32- or 64-bit bus with multiplexed address and data lines that is primarily intended for use as an interconnect mechanism within a system between processor/memory and peripheral components or add-in cards. PCM Pulse Code Modulation PEC Packet Error Checking. This is an SMBUS 2.0 feature. PHY Physical Layer Device POC Power-on-configuration RASUM Reliability, Availability, Serviceability, Usability, and Manageability, which are all important characteristics of servers. RCBA Root Complex Base Address register at D31:F0:RegF0h. It specifies the physical address of the CMI Configuration Space. Also used in RCBA + offset xxxxh or RCBA + xxxxh (where xxxxh is the offset) to indicate register location in the CMI Configuration Space. RCRB Root Complex Register Block, as defined in the PCI Express* Specification v1.0a. In the IICH context, it refers to a part of the CMI Configuration Space (see RCBA, above). RDMA Remote Direct Memory Access RFL Receive FIFO Level RGMII Reduced GMII RMII Reduced MII (7 pins per port) RMW Read-Modify-Write operation RTC Real-Time Clock RTCRESET# Signal that resets the RTC well (but does not clear the RTC RAM memory contents). RX Receive SATA Serial Advanced Technology Attachment SATA* Serial ATA, an industry specification of the interface for storage controllers and devices. Table 1-3. Acronym Table Term Description

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1.5 Glossary

This section presents a glossary for this document. SEC Single-bit Error Correct SEC/DED Single Error Correct/Double Error Detect - A specific data protection algorithm that distributes data and ECC across 144 bits. Enables correction of single bit errors. Allows detection of double bit errors. SOP/SOF Start Of Packet / Start Of Frame SMM System Management Mode SPD Serial Presence Detect SSU Security Services Unit STR Suspend To Ram TAP Test Access Port used for testability and debug of the component. TX Transmit TCO Total Cost of Ownership TCP Transmission Control Protocol TDM Time Division Multiplexed TDR Time Domain Reflectometry TFL Transit FIFO Level TID See Transaction Identifier in Table 1-4 USB Universal Serial Bus VCMI IA-32 core, IA-32 C ore interface, Memory controller hub, I/O controller hub VLAN Virtual Local Area Network WDT Watch Dog Timer Table 1-3. Acronym Table Term Description Table 1-4. Glossary Table (Sheet 1 of 5) Term Definition µBGA Micro Ball Grid Array AIOC Direct (AD) AIOC Direct (AD) memory regions are not coherent with IA caches when accessed from AIOC agents. Accesses to these memory regions enter the memory system through the Memory Controller avoiding the IMCH. Memory regions that are not coherent with IA caches need not be accessible to the IA CPU. Agent A logical device connected to a bus or shared interconnect that can either initiate accesses or be the target of accesses. ALT Access Mode Mode to allow the reading of write-only registers, usually used when saving/restoring register content for power management sleep state implementations. Anti-Etch Any plane-split, void or cutout in a V CC or GND plane is referred to as an anti-etch. Asserted Signal is set to a level that represents logical true. Asynchronous 1. An event that causes a change in state with no relationship to a clock signal. 2. When applied to transactions or a stream of transactions, a classification for those that do not require service within a fixed time interval.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 99 Intel® EP80579 Integrated Processor Atomic operation A series of two or more transactions to a device by the same initiator which are guaranteed to complete without intervening accesses by a different master. Most commonly required for a read-modify-write (RMW) operation. Block Locking Ability to lock the FWH’s blocks to write-protect, read-protect, or open state. Buffer 1. A random access memory structure. 2. The term I/O buffer is also used to describe a low- level input receiver and output driver combination. Cx States Processor power states (Cx states) are processor power consumption and thermal management states within the global working state, G0.

C0: Processor power state - While the processor is in this state, it executes instructions.
C1: Processor power state - This power state has the lowest latency. The hardware latency in this state must be low enough that the operating software does not consider the latency aspect of the state when deciding whether to use it.
C2: Processor power state - This state offers improved power savings over the C1 state. The worst-case hardware latency for this state is provided via the ACPI system firmware and operating software can use this information to determine when the C1 state should be used instead of the C2 state.
C3: Processor power state - This state is not supported. The C3 state offers improved power savings over the C1 and C2 states. The worst-case hardware latency for this state is provided via the ACPI system firmware and the operating software can use this information to determine when the C2 state should be used instead of C3 state. While in the C3 state, the processor’s caches maintain state but ignore any snoops. Cache Line The unit of memory that is copied to and individually tracked in a cache. Specifically, 64 bytes of data or instructions aligned on a 64-byte physical address boundary. Cfg Used as a qualifier for transactions that target PCI configuration address space. Character The raw data Byte in an encoded system (i.e., the 8b value in a 8b/10b encoding scheme). This is the meaningful quantum of information to be transmitted or that is received across an encoded transmission path. CMI IA-32 C ore interface, Memory controller hub, I/O controller hub Coherent (C) Transactions that ensure that the processor’s view of memory through the cache is consistent with that obtained through the I/O subsystem. In EP80579 integrated processor, Coherent (C) memory regions are coherent with IA caches when accessed from AIOC agents. Accesses to these memory regions enter the memory system through the IMCH. Memory regions that are coherent with IA caches must be accessible to the IA CPU. Command The distinct phases, cycles, or packets that make up a transaction. Requests and Completions are referred to generically as Commands. Completion A packet, phase, or cycle used to terminate a Transaction on a interface, or within a component. A Completion will always refer to a preceding Request and may or may not include data and/or other information. Core Power Well Main system power, turns off in S3 – S5 Cyclic Redundancy Check A number derived from, and stored or transmitted with, a block of data in order to detect corruption. By recalculating the CRC and comparing it to the value originally transmitted, the receiver can detect some types of transmission errors. Deasserted Signal is set to a level that represents logical false. Deferred Transaction A processor bus Split Transaction. The requesting agent receives a Deferred Response which allows other transactions to occur on the bus. Later, the response agent completes the original request with a separate Deferred Reply transaction. Delayed Transaction A transaction where the target retries an initial request, but unknown to the initiator, forwards or services the request on behalf of the initiator and stores the completion or the result of the request. The original initiator subsequently reissues the request and receives the stored completion. Direct Memory Access Method of accessing memory on a system without interrupting the processors on that system. Downstream Describes commands or data flowing away from the processor-memory complex and toward I/ O. The terms Upstream and Downstream are never used to describe transactions as a whole. (e.g. Downstream data may be the result of an Outbound Write, or an Inbound Read. The Completion to an Inbound Read travels Downstream.) Table 1-4. Glossary Table (Sheet 2 of 5) Term Definition

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Full Duplex A connection or channel that allows data or messages to be transmitted in opposite directions simultaneously. Gb/s Gigabits per second (10 9 bits per second) GB/s Gigabytes per second (10 9 bytes per second) Global visibility An operation is said to be globally visible when all side-effects of the operation are visible to every observer in the system. For example, a write to some resource (e.g., memory location, control register, etc.) R achieves global visibility when a read of R by all other agents is guaranteed to return the new value. Gx States Global system states (Gx states) apply to the entire system and are visible to the user.

G3: Mechanical off - A computer state that is entered and left by a mechanical switch. It is implied by the entry of this off state through a mechanical means that no electrical current is running through the circuitry and that it can be worked on without damaging the hardware or endangering service personnel.
G2/S5: Soft Off - A computer state where the computer consumes a minimal amount of power.
G1: Sleeping - A computer state where the computer consumes a small amount of power, user mode threads are not being executed, and the system “appears” to be off (from an end user’s perspective, the display is off, and so on).
G0: Working - A computer state where the system dispatches user mode (application) threads and they execute. In this state, peripheral devices are having their power state changed dynamically. Half Duplex A connection or channel that allows data or messages to be transmitted in either direction, but not simultaneously. Implicit Writeback A snoop-initiated data transfer from the bus agent with the modified Cache Line to the memory controller due to an access to that line. Inbound A transaction where the request destination is the processor-memory complex and is sourced from I/O. The terms Inbound and Outbound refer to transactions as a whole and never to Requests or Completions in isolation. (e.g., an Inbound Read generates Downstream data, whereas an Inbound Write has Upstream data. Even more confusing, the Completion to an Inbound Read travels Downstream.) Industry Standard Architecture A 16-bit bus architecture associated with the IBM AT motherboard designed to connect motherboard circuitry to expansion card devices that is now considered Legacy. Initiator The source of requests. [IBA] An agent sending a request packet on 3GIO is referred to as the Initiator for that Transaction. The Initiator may receive a completion for the Request. [3GIO] ISA Regime A special legacy mode to support ISA-based devices which have been integrated into the chipset. It opens a dedicated channel from the peripheral device to the processor bus. While in this mode, the legacy device is granted exclusive accesses to memory and the ability to use Tenured Transactions. Isochronous A classification of transactions or a stream of transactions that require service within a fixed time interval. Lane A set of differential signal pairs, one pair for transmission and one pair for reception. A by-N Link is composed of N Lanes. Layer A level of abstraction commonly used in interface specifications as a tool to group elements related to a basic function of the interface within a layer and to identify key interactions between layers. Legacy Functional requirements handed down from previous chipsets, or PC compatibility requirements from the past. Link The collection of two Ports and their interconnecting Lanes. A Link is a dual simplex communications path between two components. LPC Bus Low Pin Count connection used to connect to the super I/O device. Master A device or logical entity that is capable of initiating transactions. A Master is any potential Initiator. Mbyte/s Megabytes per second (10 6 bytes per second) Mem Used as a qualifier for transactions that target memory space. (For example, a Mem read to I/ O.) Table 1-4. Glossary Table (Sheet 3 of 5) Term Definition

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 101 Intel® EP80579 Integrated Processor Metastability A characteristic of flip flops that describes the state where the output becomes non- deterministic. Most commonly caused by a setup or hold time violation. Multi Media Timer (MMT) See High Precision Event Timer (HPET) in Table 1-3. Non-Coherent Transactions that may cause the processor’s view of memory through the cache to be different than that obtained through the I/O subsystem. North Usually refers to bridges. The bridge or device that is closer to the processor-memory complex. Ordering Refers to the order in which signals and/or memory accesses to different locations must reach global visibility to ensure some behavior. Note that this excludes the “ordering” necessary to prevent data hazards which are accesses to the same location. Outbound A transaction where the request destination is I/O and is sourced from the processor-memory complex. The terms Inbound and Outbound refer to transactions as a whole and never to Requests or Completions in isolation. (For example, an Outbound Read generates Upstream data, whereas an Outbound Write has Downstream data. Even more confusing, the Completion to an Outbound Read travels Upstream.) OWord 128 bits of data on a naturally aligned sixteen-byte boundary (e.g., the least significant four bits of the byte address are b”0000”). This is the native size of the IMCH datapath. Packet The indivisible unit of data transfer and routing, consisting of a header, data, and CRC. PCI Reset PCIRST#. This is the secondary PCI Bus reset signal. It is a logical OR of the primary interface PLTRST# signal and the state of the Secondary Bus Reset bit. Peer-to-Peer Transactions that occur between two devices independent of memory or the processor. Platform Reset IICH asserts PLTRST# to reset devices that reside on the primary PCI bus. The IICH asserts PLTRST# during power-up and when a hard reset sequence is initiated through the CF9h register. PLTRST# is driven inactive a minimum of 1 ms after both PWROK and VRMPWRGD are driven high. PLTRST# is driven for a minimum of 1 ms when initiated through the CF9h register. Plesiochronous From Greek, meaning almost synchronous. Describes signals that have the same nominal digital rate, but are synchronized on different clocks. Any variation in rate is constrained within specified limits, which allows a device to process the data signal without buffer underflow or overflow by making periodic compensating adjustments that repeat or delete dummy data bits. However, there is no limit to the phase difference that can accumulate between the signals over time. Port 1. Logically, an interface between a component and a PCI Express* Link. 2. Physically, a group of Transmitters and Receivers located on the same chip that define a Link. Posted A Transaction that is considered complete by the initiating agent or source before it actually completes at the Target of the Request or destination. All agents or devices handling the Request on behalf of the original Initiator must then treat the Transaction as being system visible from the initiating interface all the way to the final destination. Commonly refers to memory writes. Push Model Method of messaging or data transfer that predominately uses writes instead of reads. Queue A first-in first-out (FIFO) structure. Receiver 1. The Agent that receives a Packet across an interface regardless of whether it is the ultimate destination of the packet. 2. More narrowly, the circuitry required to convert incoming signals from the physical medium to more perceptible forms. Request A packet, phase, or cycle used to initiate a Transaction on a interface, or within a component. Reserved The contents or undefined states or information that are not defined at this time. Using any reserved area is not permitted. Reserved register bits must be set to 0. However, when stated, there may be specific instances where a reserved register is either non-zero, or there may be a requirement to make it non-zero. Resume Power Well Trickle from power supply, only turns off when power is disconnected from wall. Resume Reset Signal that resets the parts of the IICH in the resume power well, generated when the trickle supply turns on. RTC Power Well Powered by a coin cell battery and only turns off when the battery is drained. Powers the RTC and some resume events. Table 1-4. Glossary Table (Sheet 4 of 5) Term Definition

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§ § Sx States Sleeping states (Sx states) are types of sleeping states within the global sleeping state, G1.

S5: Soft Off state. The main memory power pl ane is shut down in addition to the clock synthesizer and core well power planes for the processor and CMI. The CMI resume well is still powered.
S4: Sleeping state - This state is only used to transition to or from the S5 state. The S4 state is not a supported power management state in CMI.
S3: Suspend to RAM (STR) state - The clock synthesizer and core well power planes for the processor and CMI are shut down, but the main memory power plane and the CMI resume well remain active. All clocks from synthesizers are shut down during the S3 state.
S0: Awake state - Power Management state when all power planes are active. Simplex A connection or channel that allows data or messages to be transmitted in one direction only. SMBus System Management Bus. A two-wire interface through which various system components may communicate. Snooping A means of ensuring cache coherency by monitoring all memory accesses on a common multi- drop bus to determine if an access is to information resident within a cache. South Usually refers to bridges. The bridge or device that is further from the processor-memory complex. South Port The PCI Express* downstream root port(s) on the IICH. Split Lock Sequence A sequence of transactions that occurs when the target of a lock operation is split across a processor bus data alignment or Cache Line boundary, resulting in two read transactions and two write transactions to accomplish a read-modify-write operation. Split Transaction A transaction that consists of distinct Request and Completion phases or packets that allow use of bus, or interconnect, by other transactions while the Target is servicing the Request. Symbol An expanded and encoded representation of a data Byte in an encoded system (e.g., the 10b value in a 8b/10b encoding scheme). This is the value that is transmitted over the physical medium. Symbol Time The amount of time required to transmit a symbol. Target A device that responds to bus Transactions. The agent receiving a request packet is referred to as the Target for that Transaction. Tenured Transaction A transaction that holds the bus or interconnect until complete, effectively blocking all other transactions while the Target is servicing the Request. Transaction An overloaded term that represents an operation between two or more agents that can be comprised of multiple phases, cycles, or packets. Transaction Identifier A multi-bit field used to uniquely identify a transaction. Commonly used to relate a Completion with its originating Request in a Split Transaction system. Transmitter 1. The Agent that sends a Packet across an interface regardless of whether it was the original generator of the packet. 2. More narrowly, the circuitry required to drive signals onto the physical medium. Upstream Describes commands or data flowing toward the processor-memory complex and away from I/ O. The terms Upstream and Downstream are never used to describe transactions as a whole. (For example, Upstream data may be the result of an Inbound Write, or an Outbound Read. The Completion to an Outbound Read travels Upstream.) VCMI IA-32 core, IA-32 C ore interface, Memory controller hub, I/O controller hub Table 1-4. Glossary Table (Sheet 5 of 5) Term Definition

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2.0 Architectural Overview

2.1 Overview

This chapter provides an overview of the Intel® EP80579 Integrated Processor product line architecture. Section 2.1.1, “Block Summary” gives a high-level summary for each of the major blocks and their internal interfaces. Section 2.1.2, “External Interfaces” reviews the EP80579’s external chip interfaces. The block diagrams in Figure 2-1 and Figure 2-1 show the major EP80579 blocks.

2.1.1 Block Summary

The EP80579 IA-32 core runs at 600, 1066, and 1200 MHz with an internal 400 or 533 MHz front-side bus (FSB) interface. The IA-32 core features a 256 Kilobyte 2- way level 2 cache (L2).
The EP80579 IMCH provides the main path to memory for the IA-32 core and all peripherals that perform coherent I/O (e.g. PCI Express*, the IICH to coherent memory). The IMCH includes the four channel DMA engine as well as a PCI Express* root complex with 1x8, 2x4, or 2x1 interfaces. The memory controller operates at 200-266-333-400 MHz, depending on external DDR and SKU configuration. Depending on SKU, the EP80579 supports a single channel, 64-bit with ECC, memory controller for external DDR-2 memory (400, 533, 667, and 800 MHz). The EP80579 also supports a 32-bit with ECC mode for cost-sensitive applications.
The EP80579 IICH provides a set of PC platform-compatible I/O devices that include two SATA1.0/2.0, one USB1.1/2.0 host controller supporting two USB ports, and two serial 16550 compatible UART interfaces. The IICH complex interfaces to the MCH through the “NSI” internal bus interface.
The EP80579 Acceleration and I/O Complex (AIOC) supports three Gigabit Ethernet media access controllers, MDIO, Local Expansion Bus (LEB), two Controller Area Network (CAN) interfaces, IEEE1588 (2-GbE and 2-CAN ports), and SSP. In addition some SKU have three high-speed serial TDM interfaces that provide up to 12 T1/E1. ASU and SSU provide the high performance packet processing and accelerate common security capability.

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Figure 2-1. Intel ® EP80579 Integrated Processor Block Diagram Acceleration and I/O Complex IMCH PCI Express Interface (x1) (Gen1, 1x8, 2x4 or 2x1 root complex) IA Complex IA-32 core L2 Cache (256 KB) IICH SATA 2.0 (x2) USB 2.0 (x2) UART (x2) GPIO (x36) SMBus (x2) APIC, DMA, Timers, Watch Dog Timer, RTC, HPET (x3) Memory Controller HubFSB EDMA Memory Controller 64b with ECC) Local Expansion Bus (16b @

80 MHz)

MDIO (x1) CAN (x2) SSP (x1) IEEE-1588 GigE MAC GigE MAC GigE MAC Transparent PCI-to-PCI Bridge SPI LPC1.1

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 105 Intel® EP80579 Integrated Processor Figure 2-2. Intel ® EP80579 Integrated Processor with Intel® QuickAssist Technology Block Diagram Acceleration and I/O Complex ‡ Enabling software required. IMCH PCI Express Interface (x1) (Gen1, 1x8, 2x4 or 2x1 root complex) IA Complex IA-32 core L2 Cache (256 KB) IICH APIC, DMA, Timers, Watch Dog Timer, RTC, HPET (x3) Memory Controller HubFSB EDMA Memory Controller 64b with ECC) TDM Interface‡ (12 E1/T1) Local Expansion Bus (16b @ MDIO (x1) CAN (x2) SSP (x1) IEEE-1588 Acceleration Services Unit‡ Security Services Unit‡ (3DES, AES, (A)RC4, MD5, SHA-x, PKE, TRNG) 256 KB ASU SRAM GigE MAC GigE MAC GigE MAC Transparent PCI-to-PCI Bridge UART (x2) GPIO (x36) SMBus (x2) SATA 2.0 (x2) USB 2.0 (x2) SPI LPC1.1

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2.1.2 External Interfaces

Table 2-1 summarizes the key features of the external interfaces. Table 2-1. EP80579 External Interface Summary Name Qty. Description External DDR Memory 1 Single channel memory controller with an ECC enabled 64-bit interface that, depending on SKU, supports external DDR-2 memory (400, 533, 667 and 800 MHz). Minimum memory size is 128 MB (in 32 bit mode). Maximum memory size is 4GB. The EP80579 integrated processor also supports a 32-bit mode (with ECC) for cost-sensitive applications. PCI Express* (root) 1 Supports 1x8, 2x4, or 2x1 configurations as a root complex. Gigabit Ethernet 3 10/100/1000 Gigabit Ethernet MACs with RGMII/RMII interface. Two of the three ports support IEEE 1588 hardware assist. TDM 3

8.192 MHz high-speed synchronous serial TDM interfaces that support up to 12

T1/E1 links (SKU dependent) with Intel software driver provided for HDLC support. Local Expansion Bus 1 25/16-bit 80MHz local expansion bus with 8 programmable chip selects. USB 2.0 1 Universal Serial Bus 2.0 host controller interface, supports two USB ports (shared with USB1.1 ports) USB 1.1 1 Universal Serial Bus 1.1 host controller interface, supports two USB ports (shared with USB2.0 ports) LPC 1 Low Pin Count Bus (LPC) interface to attached PC compatible boot flash memory up to 64MB. SPI 1 Serial Peripheral Interface (SPI). GPIO 36 Programmable General Purpose I/O (GPIO) pins. Note, Intel recomends using this interface to boot from. Of the 36pins, many have alternate functions defined. SMBus/I2C 2 I2C compatible SMBus2.0 connections. UART 2 16550 compatible asynchronous serial ports that support data rate of at least 115Kbits/sec. SATA 2 SATA1.0 or 2.0 used to attached external hard drives. SSP 1 Synchronous Serial Port CAN 2 Controller Area Network interfaces. MDIO 1 MDIO interface to support the ethernet interfaces. IEEE-1588 1 IEEE-1588 Hardware Assist

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2.1.3 Frequencies and Gear Ratios

This section discusses frequencies and gear ratios. The IA core used in the EP80579 is an IA-32 core, and can run at frequencies between 600 and 1200 MHz (actually supported CPU frequencies vary by SKU, see Chapter 47.0, “SKUs, Power Savings and Pre-Boot Firmware”). Based on divider ratios in its PLL design, the IA-32 core imposes a 6:1 minimum core/bus frequency ratio. This limits maximum FSB frequency to 400 or 533 MHz front-side bus (FSB) interface. The IA-32 core/FSB frequency combinations supported are listed in Table 2-2. Table 2-3 summarizes the memory controller clock ratios.

2.2 Signaling Architecture

As defined in Table 2-4, the EP80579 supports communication between the IA, AIOC devices (ASU, SSU, internal I/O devices) and externally attached bus master (PCI Express* through different memory types using a variety of operations. Table 2-2. IA-32 core / FSB Frequency Ratios (depends on SKU and configuration) IA-32 core [MHz] FSB [MHz] Ratio 600 400 6:1 1066 533 8:1 1200 533 9:1 Table 2-3. Memory Controller Frequencies DDR Clock [MHz] DDR Technology

200 DDR2-400

266 DDR2-533

333 DDR2-667

400 DDR2-800

Table 2-4. Summary of Communication Operation Agent Targeted Memory Typea a. “X” cells are supported with normal or MMIO accesses and “-” cells are not supported. External DRAM (Coherent) External DRAM (AIOC Direct) Read, Write IA X X b ASU X X PCI-E DMA, EDMA X X b GbE X X Atomic IA X - ASU X X PCI-E DMA, EDMA - - GbE - -

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The EP80579 allows signaling to occur between IA, AIOC complex, and externally- attached agents in the appropriate native signaling format. The EP80579 supports basic producer/consumer behavior between agents. Because the AIOC complex devices are exposed to the IA platform as PCI devices, they follow PCI ordering semantics when interacting with IA. This enables two fundamental producer/consumer models in coherent memory: the polled and interrupt methods. For the Polled method: 1. Producer writes data to location “X” in Coherent Memory. 2. Producer sets flag to location “Y” in Coherent Memory 3. Consumer waits for flag to be set in Coherent Memory 4. Consumer read data from location “X” in Coherent Memory To ensure this behavior, agents generating traffic into the IMCH must ensure that the writes originating from an agent are globally observable in the same order. In the above case X and Y must be globally observable in the same order. For the Interrupt method: 1. Producer writes data to location “X” in Coherent Memory. 2. Producer generates an interrupt to Consumer (asynchronous signal) 3. Consumer reads interrupt status from Producer’s address space. Consumer waits for read to complete before issuing the next transaction. 4. Consumer reads data from location “X” in Coherent Memory To ensure this behavior, an MMIO read issued to the PCI device (item 3 above) after a write that originated from this PCI device (item 1 above) must not complete out of order. The read completion must push ahead (flush) the write. Also the MMIO read (item 3 above) should be to a location that is in the device. In the EP80579, it should not be to the PCI configuration registers but the device registers pointed to by the PCI BAR 1. This ensures that IA device driver software for the EP80579 is not required to include explicit memory fence operations to enable producer-consumer synchronization for interrupt handling. Examples: 1. : GigE placing received data in coherent DRAM and interrupting IA, IA issuing a GigE CSR read, whose read completion must serialize the received DRAM data stream. 2. : TDM placing received data in coherent DRAM, then interrupting the IA, then IA gets a pointer to the data. An IA pointer dereference from the IA must see the TDM DRAM data. 3. : ASU placing data in coherent DRAM, then interrupting the IA, then IA gets a pointer to the data. An IA pointer dereference from the IA must see the ASU DRAM data. b. Agents in the IA-32 core may access AIOC-Direct memory (non-coherent) via uncacheable 1, 2 or 4-byte IA loads/store, IA MMX 8-byte MOVQ instructions or 64-byte DMA transfers. While such IA-32 core accesses to AIOC-Direct memory are not ordered with respect to other ASU memory traffic, the AIOC-Direct memory supports limited one-way communication in which IA agent (or the Internal PCI agent) is the sole writer and the internal PCI agent (or the IA agent) views such memory locations as read-only. Hardware will ensure that self-aligned 1,2, 4, 8 and 64-byte updates will be atomically visible to all readers. 1. The reason for this requirement is that the MCH config bus us ed to access the PCI configuration registers does not serialize the EP80579 internal PCI bus. GigE IA⇔ TDM IA⇔ ASU IA⇔

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 109 Intel® EP80579 Integrated Processor For communication using memory that is not coherent with the IA processor caches, or for direct communication between AIOC agents (e.g. between ASU, TDM, and GigE devices), the EP80579 may require software to insert explicit fencing operations to ensure correct producer/consumer behavior. Details are discussed in Chapter 4.0, “Signaling”.

2.3 DMA and Peer-to-Peer Data Transfers

The EP80579 provides multiple DMA and DMA-like features that are summarized here:

IMCH EDMA Engine: The four channel IMCH “Enhanced DMA” (EDMA) engine which supports DWORD aligned DMA. The EDMA engine supports memory-to- memory and memory-to-PCIe transfers. Read DMA granularity ranges from 1 byte to 4 Kilobytes. Write DMA granularity ranges from 1 to 256 bytes. The EDMA engine supports different source/target byte alignments that are important for packet processing, and is only programmable via IA PCI configuration space with completions signaled via IA interrupts. The EDMA engine can support burst data movement between “AIOC-direct memory” and IA coherent memory.
IICH DMA: Supports IICH agents to/from memory, this is only used by USB and SATA.
LPC DMA: Supports LPC agents. See Chapter 20.0, “LPC DMA”.
No Peer-to-Peer Reads: The IMCH does not support peer-to-peer reads. Table 2-5 lists the supported DMA and peer-to-peer data transfer options. § § Table 2-5. DMA and Peer-to-Peer Data Transfer Options Usage Model# Operation Source Destination Initiator Owner (Software)

1 PCI DMA read DRAM PCI Ex device PCI Ex Device IA device driver

2 PCI DMA write PCI Ex Device DRAM PCI Ex Device IA device driver

3A I O C r e a d DRAM or AIOC device AIOC device (GE) Device IA, ASU 4A I O C w r i t e A I O C d e v i c e DRAM or AIOC device (GE) Device IA, ASU

5 AIOC 3rd party read DRAM AIOC device (SSU) ASU ASU

6 AIOC 3rd party write AIOC device (SSU) DRAM ASU ASU

7 Peer-to-Peer PCI

8 Peer-to-Peer PCI

Ex Device PCI Ex Device only AIOC Master or PCI Ex Device AIOC Master Device Driver

9 Mem-to-Mem DRAM DRAM EDMA Engine IA

10 Mem-to-Memory

Mapped IO DRAM PCI Ex or AIOC device EDMA Engine IA

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3.0 Platform Memory and Device Configuration

3.1 Overview

This chapter presents the views of the major address spaces and device configuration structures as seen by various internal and external agents. Three related aspects are covered:

The memory maps seen by various internal and external agents.
The endianness seen by various agents and mechanisms the EP80579 uses to allow communication between agents with different endianness expectations.
The PCI configuration infrastructure, which the EP80579 exposes through its memory maps.

3.1.1 Configuration Objectives

The EP80579 device and configuration model operates in a system-on-a-chip environment and blends the architectures of many disparate components into a unified whole. The major goals for the device configuration and access architecture include:

Provide a configuration and access model that is aligned with existing IA platform algorithms.
Support a unified address space model. The IA-32 core is the primary agent responsible for device configuration. This is true across all supported SKUs. To provide device configuration and operation capabilities that are aligned with the IA platform, the EP80579 uses the existing PCI infrastructure to expose on-die software- visible sub-blocks as devices on the PCI fabric. Figure 3-1 presents a logical overview of this organization.

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The on-die IMCH and IICH devices materialize on PCI bus 0 while the AIOC devices materialize on PCI bus “M” that is behind a transparent PCI-to-PCI bridge on PCI bus 0 (the bus that the internal IMCH and IICH devices use). For simplicity, the figure does not show external devices.

3.1.2 Terminology and Conventions

Throughout this chapter, we will use the generic term “device” to refer to either a PCI device or a function of a PCI device. The text will be explicit when the distinction between device and function is important. Addresses are always in hexadecimal and broken into 16-bit segments, for example, 0_FEED_BEEF. When the distinction is important and not obvious, addresses are subscripted with “V”, “P”, or “S” for virtual, physical, or system address spaces, respectively. The EP80579 addresses its DRAM in units of 8-byte quadwords. Before assigning byte addresses to the byte lanes in DRAM, we will refer to the locations as byte lane A through H as Table 3-1 illustrates. The byte located in address 0, lane A is referred to as 0A, the byte in address 0 lane B is 0B, etc. Figure 3-1. Device-Centric Logical View of EP80579 Devices IA CPU AIOC Devices ASU SSU GbE IMCH / IICH Devices DRAM EDMA USB Transparent PCI-to-PCI Bridge PCI Bus 0 PCI Host Bridge PCI Bus M Table 3-1. Main Memory DRAM Organization Address Byte Lane H Byte Lane G Byte Lane F Byte Lane E Byte Lane D Byte Lane C Byte Lane B Byte Lane A

00 H 0 G 0 F 0 E 0 D 0 C 0 B 0 A

88 H 8 G 8 F 8 E 8 D 8 C 8 B 8 A

16 16H 16G 16F 16E 16D 16C 16B 16A

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3.2 IA Platform Infrastructure

The IMCH and IICH blocks (which, along with the IA-32 core, are collectively referred to as the VCMI) in the EP80579 provide an IA platform infrastructure with respect to endianness, address spaces and memory maps, configuration, etc. This section focuses on the IA views and expectations around the endianness, address spaces and memory maps, and configuration for a basic IA platform. The EP80579 operates within this framework. These discussions highlight how and where the EP80579 differs from the framework. For additional detailed information on the IA infrastructure in the EP80579 specifically, see Section 9.0, “CMI Introduction”, which discusses the IMCH implementation.

3.2.1 IA Platform View of Endianness

All memory in an EP80579 platform is little-endian to match requirements and expectations of an IA platform. The byte lanes (see Table 3-1 on page 112) are connected from the memory interface to the IMCH such that little-endian IA-32 core sees “byte 0” of a quad-word in memory in byte lane A and “byte 7” of a quad-word in memory in byte lane H. Consider the following C code: char c, *cp; // 1 byte short s, *sp; // 2 bytes long l, *lp; // 4 bytes long long ll, *llp; // 8 bytes cp = sp = lp = llp = (void *) 0x8; // QW address 1 c = *cp; s = *sp; l = *lp; ll = *llp; Executing this code on the IA-32 core in an EP80579 yields the following results: c == 8A s == 8B8A l == 8D8C8B8A ll == 8H8G8F8E8D8C8B8A Where the right-hand values in these results use the notation that Table 3-1 on page 112 in Section 3.1.2 describes to identify the byte lanes and address.

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3.2.2 IA Platform View of Configuration

Because the IMCH and IICH blocks in the EP80579 come from an IA heritage, the EP80579 exposes much of the functionality in these blocks through a PCI infrastructure. The EP80579 extends this PCI infrastructure to expose the functionality in the AIOC, as Section 3.7, “PCI Configuration” on page 119 describes. Before describing how the AIOC integrates with the IA-based IMCH and IICH blocks, it is helpful to consider how the PCI exposes IMCH and IICH functionality. Logically, the software-visible sub-blocks of the IMCH and IICH materialize as PCI devices and functions 1 on PCI bus 0 of the system through three independent address spaces:

Configuration Space: Each function of each device has at least 256B of configuration space that is mapped to a fixed location by the platform (PCI Express* devices can provide for larger configuration spaces). This space provides system software with basic information on the device and allows for device- independent configuration.
Memory-Mapped I/O (MMIO) and I/O Spaces: Each function of each device can request up to six MMIO and I/O regions of device-specified sizes to be mapped into physical address space through base address registers in the configuration header. System software selects the base address of each region. These spaces support device-specific operation such as access to device-specific control registers. Of the thirty-two possible device slots on bus 0, five slots are reserved for software- visible blocks in the EP80579 IMCH and IICH and remainder are unused. In general, the IMCH claims configuration accesses (i.e., those accesses that target configuration space) to device numbers 0, 1, 2, and 3 of bus 0 and routes configuration accesses to the remaining devices to the IICH over an internal NSI interface using Type

0 PCI configuration transactions

2 (see Section 13.2, “Platform Configuration Structure Conceptual Overview” and Section 13.3, “Routing Configuration Accesses”. In the EP80579 design, transactions to bus 0 devices that are sent through NSI to the IICH and unclaimed by the IICH will master abort. Figure 3-2 presents a logical view of the EP80579 infrastructure for the software-visible blocks in the IICH and IMCH. 1. Except where the distinction is important, this document uses the term “device” to refer to both devices and functions in the PCI sense of these words. 2. Configuration transactions take the Type 1 form while in transit through the PCI fabric to their destination bus; upon reaching their destination bus, they become Type 0 transactions.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 115 Intel® EP80579 Integrated Processor Table 3-2 summarizes the address space requirements (both in memory and I/O space) of the IMCH and IICH. Figure 3-2. Logical Overview of the CMI PCI Infrastructure IICH IMCHIA Dev: 0 Dev: 1 Dev: 2,3 Dev: 29 Dev: 31 PCI Bus 0 NSI NSI USB SATA, SPI, LPC, SMBus EDMA PCI-Ex IMCH, DDR Table 3-2. Basic CMI Platform Address Space Requirements for IMCH and IICH Devices Unit PCI Block Mem, I/O Size Register Dev. Fn. IMCH

0 Northbridge Mem 4KB

SMRBASE (see Section 16.1.1.9, “Offset 14h: SMRBASE - System Memory RCOMP Base Address Register”)

1 DRAM, Error Handling N/A N/A

EDMALBAR (see Section 16.3.1.9, “Offset 10h: EDMALBAR - EDMA Low Base Address Register”

20 PCI-Express (HSI A0)

×8 or ×4 N/A N/A

30 PCI-Express (HSI A1)

×4 N/A N/A IICH 29 0 USB 1.1 I/O 32B USBIOBAR (see Section 25.1.1.9, “USBIOBAR - Base Address Register”) 7 USB 2.0 Mem 1KB MBAR (see Section 26.2.1.10, “Offset 10h: MBAR - Memory Base Address Register”)

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The IMCH and IICH devices in the EP80579 on PCI bus 0 allocate 18KB of memory space above and beyond the PCI L allocations in Figure 3-2 and 72B of I/O space through PCI BARs (this memory could be allocated in the “open” regions in Figure 3-2). This table does not include any memory regions that external devices (i.e., those attached to a IMCH PCI Express* port) or AIOC devices might allocate. In addition to the IMCH and IICH devices, the EP80579 includes an IA-32 core that provides MSRs and other configuration structures.

3.3 High-Level Views

This section presents an overview of some of the general characteristics of the agents that the various EP80579 memory maps expose.

3.3.1 Characteristics of External System Memory (DRAM)

The address spaces in the EP80579 expose up to 4GB of physical system memory, in the form of DRAM, to be accessed by both on- and off-die agents.

0 LPC/SPI N/A N/A

PCMDBA (see Section 23.1.1.8, “Offset 10h: PCMDBA – Primary Command Block Base Address Register”) I/O 4B PCTLBA (see Section 23.1.1.9, “Offset 14h: PCTLBA – Primary Control Block Base Address Register”) I/O 8B SCMDBA (see Section 23.1.1.10, “Offset 18h: SCMDBA – Secondary Command Block Base Address Register”) I/O 4B SCTLBA I/O 16B LBAR (see Section 23.1.1.12, “Offset 20h: LBAR – Legacy Bus Master Base Address Register”) Mem 1KB ABAR (see Section 23.1.1.13, “Offset 24h: ABAR – AHCI Base Address Register”) 3S M B U SN / A N / A Table 3-2. Basic CMI Platform Address Space Requirements for IMCH and IICH Devices Table 3-3. Memory Regions Region Managed By Accesses to System Memory by AIOC Agents Coherent with IA Caches? Contents IA O/S IA O/S Y IA O/S and application code and data structures IA/ASU Shared (Coherent) EP80579 Drivera a. The EP80579 Driver includes the EP80579-specific software stacks that run on the IA, ASU, etc. Y IA and AIOC shared data structures IA/ASU Shared (AIOC-Direct) EP80579 Drivera N AIOC data structures; IA-32 core may access a portion via the EP80579 driver

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 117 Intel® EP80579 Integrated Processor Of the regions in Table 3-3, the “IA/ASU Shared (Coherent)” and “IA/ASU Shared (AIOC-Direct)” regions are not managed by the IA O/S. The EP80579 software expects that the BIOS carves this memory out of the memory map early in the boot process and sets it aside for use by the Intel® EP80579 Integrated Processor with Intel® QuickAssist Technology software stack. As a result, the IA O/S does not allocate, manage, page, etc. these regions of memory. The regions in Table 3-3 fall into one of two categories with respect to IA cache coherency: one that is coherent with IA caches for AIOC accesses and one that is not. It is important to note that the coherent/non-coherent category of a region affects only how the AIOC hardware handles a DRAM accesses. The category, in and of itself, does not have any implications on how IA must always access the region. The EP80579 expects that, in general, all agents in the system can access all memory, consistent with their addressing capabilities, in the three regions that Table 3-3 lists. Exceptions to this general rule may arise due to the size of the address space that an agent supports or due to agent-specific aliasing of DRAM addresses onto other structures. The following sections on the memory maps outline any agent-specific exceptions. Finally, memory accesses that originate from the AIOC (or a device attached to the AIOC) must honor the coherency requirements in Table 3-3 based on the region they target. For consistency, software is expected to configure the EP80579 such that memory that the IA-32 core cannot access is not part of regions that are expected to be coherent with IA caches.

3.3.2 Characteristics of Internal and External Memories

Table 3-4 defines the supported operations by memory type. The table uses the following notation to indicate the behavior of the EP80579:

“–” means the operation is not supported by the EP80579.
“S” implies that the operation happens as a single atomic 1 update to memory. In other words, either the update is observable in its entirety or not at all.
“M” implies that the operation may happen as multiple updates to memory. In other words, other agents can observe different parts of the affected memory location change values in any order but the end state of the memory location will be the desired value. This “flickering lights” effect makes such memory accesses useless for multi-agent synchronization unless a semaphore or flag variable is used to guard access to the shared location This table only applies to aligned-to-size operations; that is, a 4-byte operation is aligned to a 4-byte boundary, an 8-byte operation is aligned to an 8-byte boundary, etc.) 1. In the sense that it cannot be divided into multiple smaller writes. 2. Note that in guarding the location, visibility of the new flag must imply that the “flickering” has stopped.

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3.3.3 Characteristics of Device Configuration

To be able to leverage existing IA BIOS, O/S, and power management software, the EP80579’s configuration mechanisms follow existing IA platform approaches. Of the four major components of the EP80579:

The IA-32 core can use normal IA platform configuration algorithms.
The IMCH and IICH can use normal IA platform configuration algorithms.
To interoperate with normal IA platform configuration algorithms, the AIOC must be configured by the IA processor. With the EP80579, the boot and configuration process is: 4. The IA boots from a FLASH device on the IICH SPI (LPC) interface. System software discovers and configures the devices on PCI bus 0 in the IMCH/IICH. 5. System software discovers and configures the devices behind the Transparent PCI- to-PCI bridge into the AIOC. This may amount to allocating memory regions specified by the BARs 6. System software configures other buses on the system. Once this process completes, the EP80579 is ready for operation. It may be necessary for software to re-order the devices on bus 0 in the IMCH/IICH/ AIOC to ensure that the AIOC can obtain the resources it needs. Since enumeration involves either a depth-first or a breadth-first traversal of the device tree from device zero (depending on the implementation of the platform PCI enumeration and discovery code), the system may not be able to honor a request for a large memory region from an AIOC device if this device is enumerated late in the process due to a large device number. This issue is not unique to the EP80579 and is handled in whatever fashion standard IA platform software handles such resource issues. Table 3-5. Supported Operations by Memory Type Operation IA-32 core AIOC Agents Type Size Bytes Coherent (IA WB Cacheable) AIOC-Directa a. AIOC-Direct is a feature of the Intel® EP80579 Integrated Processor with Intel® QuickAssist Technology SKU. Coherent AIOC-Direct a Read, Write 1S S – – 2S S – – 4S S S M 8S S S S 1 6 SMMM 32 – – M M

64 S – M M

128 – – M M Atom Read- Modify-Write (Semaphore) 1S M – – 2S M – – 4S M S S 8S M – – 1. A 32-bit BAR can request a single memory size that is a power of 2 from 16B to 2GB according to the PCI specification.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 119 Intel® EP80579 Integrated Processor

3.4 Memory Map for IA-Attached Agents

There are two constraints in the EP80579 CMI and Memory Controller designs:

The IA-32 core only supports 32-bit physical addresses.
The Memory Controller supports at most 4GB of physical memory. This discussion focuses on the perspective of an IA-attached agent; Section 3.5, “Memory Map for AIOC-Attached Devices” on page 119 provides similar discussion for AIOC-attached agents.

3.5 Memory Map for AIOC-Attached Devices

AIOC-attached agents support several independent target IDs that provide independent address spaces. Table 3-7 summarizes, the addressing capabilities of AIOC agents range from 25 to 32-bits.

3.6 Endianness

The EP80579 operates in an IA platform environment that is little-endian.

3.7 PCI Configuration

This section presents an overview of the implementation that integrates the AIOC and memory controller with the IA PCI infrastructure for configuration.

PCI mechanisms (configuration spac e, memory-mapped I/O spaces, and I/O spaces) expose state for configuration.
The IA-32 core performs all system configuration and initialization. Table 3-6. Device Exposure from an IA-attached Memory Map Perspective Device to Access Materializes In Region Notes PCIe GigE MACs IMCH/IICH AIOC devices PCI L
PCI BAR(s) set by IA O/S or BIOS specify address mapping(s).
IA-32 core configures through I/O or PCI enhanced config spaces.
Reads, config space access between I/O agents not supported.
Region is at least 128MB per definition of TOLM, see Section 16.1.1.30, “Offset C4h: TOLM - Top of Low Memory Register”. DRAM DRAM AD
Contains IA/ASU Shared (AIOC-Direct) region from Table 3-3.
MENCBASE and MENCLIMIT registers define address range.
IA caches not coherent with AIOC accesses to this region.
Must include all DRAM that is inaccessible to the IA-32 core. DRAM C
Contains I/A O/S, IA/ASU Shared (Coherent) regions from Table 3-3.
IA caches coherent with AIOC accesses to this region.
Cannot include any DRAM that is inaccessible to the IA-32 core. Table 3-7. Address Space Sizes of AIOC-attached Devices Address Space Size [b] Devices

32 Gigabit Ethernet MACs

32 ASU, SSU, TDM, SSP, CAN, 1588

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The IA-32 core configures the AIOC, IMCH and IICH using standard IA platform algorithms (i.e., PCI-based discovery, enumeration, and configuration) with modifications for the specific mix of functionality that the EP80579 CPU, IMCH, and IICH instantiations provide.
IA software configures external PCIe devices in the EP80579 using normal PCI discovery and configuration algorithms. The device and bus numbers for external devices are assigned by the BIOS and/or O/S during boot-time enumeration as normal.
An EP80579-specific user driver handles interaction with external non-PCI agents attached to the EP80579 through its AIOC-side I/O interfaces. That is, the EP80579 user driver, not BIOS, will “discover” and operate any devices attached to the local expansion bus, for example. Note that since these devices do not implement PCI semantics, it is expected that they will not allocate MMIO regions beyond those already allocated for the PCI view of the appropriate AIOC device.
The O/S always allocates an aperture in the memory map for any PCI device that defines one or more BARs, even if the device is unknown to the O/S at discovery. The PCI abstraction that the AIOC provides for its devices is primarily a software abstraction for the purposes of configuration; the AIOC itself does not contain PCI devices.

3.7.1 Overview

The EP80579 integrates the AIOC and memory controller into the PCI fabric as Figure 3-3 describes. This figure presents a logical view of the system. Figure 3-3. Attaching the AIOC to the CMI PCI Fabric (Logical Perspective) AIOC ComplexIICHIMCHIA FSB NSI Devices PCI Bus 0 PCI Bus 0 Devices ASU/SSU DRAM (AD) Memory Controller (in IMCH) Bridge LEB, CAN, SSP, 1588 GigE DRAM (C) PCI Bus M

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 121 Intel® EP80579 Integrated Processor In this figure, PCI bus 0 originates in the IMCH and reaches internal IMCH PCI devices through internal paths. Bus 0 is bridged into the IICH via an NSI interconnect and into the AIOC. The memory controller materializes internally to the IMCH as device 0 of PCI bus 0. The internal transparent bridge materializes the devices for the AIOC through a bridged hierarchy as Figure 3-4 illustrates. In this hierarchy, a Transparent PCI-to-PCI bridge appear on PCI bus 0 with the remaining AIOC devices materializing behind the bridge on PCI bus M

3.7.2 Device Tree

This section describes how the devices on the EP80579 die map onto the PCI device tree. In general, the EP80579 exposes the structures and sub-blocks that Section 3.7.1 describes through PCI devices that materialize behind a transparent bridge on bus 0. Figure 3-4 presents an overview of the device tree for on-die EP80579 software-visible sub-blocks (see also Figure 13-1, “Bus 0 Device Map” on page 348). As mentioned earlier, AIOC devices materialize on bus “M” behind a bridge on PCI bus 0 where the IA BIOS or O/S assign the secondary bus number “M” at discovery. Devices can request space in the system memory and I/O address maps through BARs in the configuration header. In general, the EP80579 materializes most device control and status registers in memory-mapped regions allocated by a BAR. The only exception 1. The IA BIOS and/or O/S assigns the specific bus number during PCI discovery and enumeration. Figure 3-4. Overview of PCI infrastructure for On-die Devices AIOC IICH IMCH Dev: 0 Dev: 1 Dev: 2, 3 Dev: 29 Dev: 31 Dev: 7 Dev: 8 Dev: 0,1,2 Dev: 3 Dev: 4, 5 Dev: 6 PCI Bus M 1588 LEB GbE MAC 0/1/ 2 MDIO CAN 0/1 SSP USB SATA, SPI, LPC, SMBus EDMA PCI-E PCI Bus 0 NSI NSI IMCH DDR (M) Transparent PCI-to-PCI Bridge PCI Bus 0 Dev: 12 ASU Dev: 9 Dev: 10 Reserved TDM Reserved Dev: 11

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lies in the standard PCI configuration, status, and capability registers that PCI requires which materialize only in PCI configuration space. The AIOC devices that lie behind the bridge allocate by either the BIOS or OS to their regions of address and I/O space within a contiguous region of address space that the bridge claims. It is assumed that system software configures the aperture for the bridge to be large enough to cover all of the address space that the devices behind the bridge request. The remainder of this section summarizes the device tree that the EP80579 implements. This summary includes a mapping between PCI devices and the EP80579 blocks along with the value of the device ID, class code, and a summary of the resources (i.e., registers, memory, etc.) that each device requests. Table 3-9 summarizes the PCI devices that the IMCH and IICH materialize. Table 3-9. IMCH and IICH PCI Device Summary Device Name EP80579 Units PCI SKU ID Number Resourcesa a. “MBAR” is a memory space BAR, “IOBAR” is an I/O space BAR, “PM” is a power management capability, and “MSI” is an MSI capability. B/D/Fb b. PCI bus number, device number, and function number. BSPc c. PCI base class code, subclass code, and programming interface PCI configuration register values. Device ID Memory Controller Hub IMCH 0 / 0 / 0 060000h 5020h 1,2,3,4,5,6, 7,8 MBAR (4KB and 4KB) Error Reporting IMCH 0 / 0 / 1 FF0000h 5021h 1,2,3,4,5,6, 7,8 EDMA EDMA 0 / 1 / 0 088000h 5023h 1,2,3,4,5,6, 7,8 MSI, MBAR (4KB) PCI-Ex Port 0 PEA0 0 / 2 / 0 060400h 5024h 1,2,3,4,5,6, 7,8 PM, MSI PCI-Ex Port 1 PEA1 0 / 3 / 0 060400h 5025h 1,2,3,4,5,6, 7,8 PM, MSI PCI-to-PCI Bridge IMCH 0 / 4 / 0 060400h 5037h 1,2,3,4,5,6, 7,8 USB 1.1 Controller USB1.1 0 / 29 / 0 0C0300h 5033h 1,2,3,4,5,6, 7,8 IOBAR (32B) USB 2.0 Controller USB2.0 0 / 29 / 7 0C0320h 5035h 1,2,3,4,5,6, 7,8 PM, MBAR (1KB) LPC/SPI LPC/SPI 0 / 31 / 0 060100h 5031h 1,2,3,4,5,6, 7,8 IOBAR (128B, 64B) SATA SATA 0 / 31 / 2 01018Ah, 010601h, 010401h, 010401hd d. SATA SC and PI values depends on the SATA mode and map value settings. 5028h, 5029h, 502Ah, 502Bhe e. SATA DID value depends on the SATA mode settings. 1,2,3,4,5,6, 7,8 PM, MSI, IOBAR (8B, 8B, 4B, 4B, 16B), MBAR (1KB) SMBus SMBUS 0 / 31 / 3 0C0500h 5032h 1,2,3,4,5,6, 7,8 IOBAR (32B)

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 123 Intel® EP80579 Integrated Processor A summary of the registers, memory-mapped, and I/O-mapped resources that Table 3-9 and Table 3-10 identify can be found in Section 7.0, “Register Summary”. Detailed descriptions of these resources can be found in the chapters that cover the relevant block. Table 3-10. AIOC PCI Device Summary Device Name EP80579 Units PCI SKU ID Number Resourcesa a. “MBAR” is a memory space BAR, “IOBAR” is an I/O space BAR, “PM” is a power management capability, “MSI” is an MSI capability, and “ST” is an EP80579 signal target capability. B/D/Fb b. PCI bus number, device number, and function number. BSPc c. PCI base class code, subclass code, and programming interface PCI configuration register values. Device ID GigE MAC 0 GbE 0 M / 0 / 0 020000h 5040h 2,4,6,8 PM, MSI, ST, MBAR (128KB), IOBAR (32B) 5041h 1,3,7,5 5042h Reserved d d. These device IDs are reserved for future SKUs. 5043h Reserved d GigE MAC 1 GbE 1 M / 1 / 0 020000h 5044h 2,4,6,8 PM, MSI, ST, MBAR (128KB), IOBAR (32B) 5045h 1,3,7,5 5046h Reserved d 5047h Reserved d GigE MAC 2 GbE 2 M / 2 / 0 020000h 5048h 2,4,6,8 PM, MSI, ST, MBAR (128KB), IOBAR (32B) 5049h 1,3,7,5 504Ah Reserved d 504Bh Reserved d MDIO MDIO M / 3 / 0 FF0000h 503Eh 1,2,3,4,5,6,7 ,8 PM, MBAR (4KB) CAN Interface 0 CAN 0 M / 4 / 0 0C0900h 5039h 1,2,3,4,5,6,7 ,8 PM, MSI, ST, MBAR (4KB) CAN Interface 1 CAN 1 M / 5 / 0 0C0900h 503Ah 1,2,3,4,5,6,7 ,8 PM, MSI, ST, MBAR (4KB) SSP SSP M / 6 / 0 078000h 503Bh 1,2,3,4,5,6,7 ,8 PM, MSI, ST, MBAR (4KB) IEEE 1588 1588 M / 7 / 0 111000h 503Ch 1,2,3,4,5,6,7 ,8 PM, MSI, ST, MBAR (4KB) Local Expansion Bus LE Bus M / 8 / 0 068000h 503Dh 1,2,3,4,5,6,7 PM, MSI, ST, MBAR (4KB and 0-256MBe) e. The size of the region that the 0-256MB MBAR requests is a multiple of 32MB between 0MB and 256MB (inclusive) based on reset-time platform configuration. ASU ASU M / 9 / 0 0B4000h 502Ch 2,4,6,8 PM, MSI, ST, MBAR (8KB, 16KB, 16KB, and 4KB) 502Dh 1,3,7,5 502Eh Reserved d 502Fh Reserved d Reserved Reserved M / 10 / 0 088000h 503Fh 1,2,3,4,5,6,7 ,8 Reserved TDM TDM M / 11 / 0 0B4000h 504Ch 1,3,5,7 PM, MSI, ST, MBAR (4KB and 4KB) Reserved Reserved M / 12 / 0 110100h 5030h 1,2,3,4,5,6,7 ,8 Reserved

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3.7.3 Materializing Device Structures

The EP80579 exposes AIOC resources through standard PCI abstractions: configuration spaces, memory-mapped I/O spaces, and I/O spaces. Access to MMIO and I/O spaces are accessed through memory and I/O read/write instructions, respectively. The addressing of these spaces for a given device depends on the specific mapping that the PCI configuration header establishes through BARs. PCI defines two mechanisms for accessing the 256B of each device/function configuration registers located in PCI configuration space.

PCI Mechanism: The header is accessed using 1-, 2-, or 4-byte IN and OUT instructions that access the PCI configuration address and data I/O ports at addresses 0CF8h - 0CFBh and 0CFCh - 0CFFh, respectively, in the IA I/O space. This mechanism allows access only to the 256B PCI-compatible configuration space
PCI Express* Enhanced Mechanism: The header is accessed using 1-, 2-, or 4-byte memory accesses to the 256MB region starting at HECBASE (0_E000_0000P by default. This mechanism allows access to an expanded 4KB configuration space that PCI Express* defines (the first 256B are, by definition, the PCI-compatible configuration space). These mechanisms differ in the address space they use to access the header. The PCI mechanism travels through IA I/O space while the PCI Express* Enhanced mechanism travels through IA memory space. The address format that the mechanisms use is identical to the standard IA platform format that encodes the PCI bus, device, and function numbers along with a register offset or number (see Section 13.6.0.1, “Offset 0CF8h: CONFIG_ADDRESS - Configuration Address Register” and Section 13.8.4, “Enhanced Configuration FSB Address Format” for details). For either access method, the hardware in the AIOC that implements the configuration headers must be able to process accesses of the appropriate sizes.

3.7.4 PCI Configuration Headers

The PCI specification requires each PCI device to provide a 256B configuration space. The first 64B of this space contains a standard PCI configuration header and the remaining 192B contains any device-specific registers, capabilities records, etc. needed by the function. There are two flavors of configuration headers:

All non-bridge devices provide a PCI type 0 configuration headers. This form of header is used to represent devices on the PCI fabric.
All bridge devices provide a PCI type 1 configuration header. This form of header is used to represent bridge devices in the PCI fabric. Because the AIOC devices are not PCI devices, they do not fully support all PCI configuration header fields 1. The following tables describe the support in greater detail. Table 3-11 summarizes the fields in a PCI type 0 header (i.e., header for non-bridge devices) and identifies which fields the EP80579 implements for AIOC devices. The EP80579 hardware implements the appropriate PCI semantics for all supported registers and fields in this table. 1. Configuration headers for IMCH and IICH devices follow PCI expectations as these devices are PCI compliant.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 125 Intel® EP80579 Integrated Processor Table 3-11. PCI Configuration Header Support for Type 0 Headers in AIOC Devices (Sheet 1 of 2) Offset Register and Field Bit(s) Supt. a Acc.b Notes 00h - 01h Vendor ID 15:0 Y RO Required by PCI. 02h - 03h Device ID 15:0 Y RO Required by PCI. 04h - 05h Command Register Interrupt Disable 10 Y RW Supported in devices that can use INTx c. N RO Not supported in devices that do not use INTx d. Fast Back-to-Back Enable 9 N RO Not supported. SERR# Enable 8 N RO Not supported. INTx/MSI signal AIOC errors. Parity Error Response 6 N RO Not supported. INTx/MSI signal AIOC errors. VGA Palette Snoop 5 N RO Not supported. Mem. Write & Inval. Enable 4 N RO Not supported. Special Cycles 3 N RO Not supported. Bus Master Enable 2 NR W ASU, GbE, TDM, LEB devices: Not supportede, bit is implemented as RW but has no effect YR O All devices except ASU, GbE, TDM, LEB: these devices cannot be bus masters. Memory Space Enable 1 YR W All devices except 1588; these devices each materialize in memory space. NR O For IEEE1588; IEEE1588 does not materialize in memory space. I/O Space Enable 0 Y RW For GbE; GbE materializes in I/O space. NR O All devices except GbE; these devices do not materialize in I/O space. 06h - 07h Status Register Detected Parity Error 15 N RO Not supported; INTx/MSI signal errors. Signalled System Error 14 N RO Not supported. INTx/MSI signal AIOC errors. Received Master- Abort 13 N RO Not supported e. Received Target- Abort 12 N RO Not supported e. Signalled Target- Abort 11 N RO Not supported; AIOC devices do not target- abort. DEVSEL Timing 10:9 N RO Not supported. Master Data Parity Error 8 N RO Not supported. INTx/MSI signal AIOC errors. Fast Back-to-Back Capable 7 N RO Not supported. 66MHz Capable 5 N RO Not supported. Capabilities List 4 Y RO Setup based on capabilities exposure by device. Interrupt Status 3 Y RO Supported in devices that can use INTx c. N RO Not supported in devices that do not use INTx d. 08h Revision ID 7:0 Y RO Required by PCI. 09h - 0Bh Class Code 23:0 Y RO Required by PCI.

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Table 3-12 summarizes the fields in a PCI type 1 header (i.e., header for bridge devices) and identifies which fields the EP80579 implements. The EP80579 hardware implements the appropriate PCI semantics for all supported registers and fields in this table. 0Ch Cache Line Size 7:0 N RO Not supported. 0Dh Latency Timer 7:0 N RO Not supported. 0Eh Header Type 7:0 Y RO Required by PCI. 0Fh BIST 7:0 N RO Not supported. 10h - 27h Base Address (x6) 6 x 31:0 YR W Devices that materialize in I/O or memory spaces will populate these slots as necessary based on address space needs. 28h - 2Bh CIS Pointer 31:0 N RO Not supported. 2Ch - 2Dh Subsystem VID 15:0 Y RO Required by PCI. 2Eh - 2Fh Subsystem ID 15:0 Y RO Required by PCI. 34h Capability Pointer 7:0 Y RO Setup based on capabilities exposure by device. 3Ch Interrupt Line 7:0 Y RW Supported in devices that can use INTx c. N RO Not supported in devices that do not use INTx d. 3Dh Interrupt Pin 7:0 Y RO Supported in devices that can use INTx c. N RO Not supported in devices that do not use INTx d. 3Eh Min_Gnt 7:0 N RO Not supported. 3Fh Max_Lat 7:0 N RO Not supported. a. Supported fields provide appropriate PCI semantics. Unsupported fields always return zero on reads unless otherwise noted. b. RO and RW access types indicate that the register or field supports read-only access and read/write access, respectively. c. AIOC devices that may signal via INTx include GbE, CAN, SSP, and IEEE1588. d. AIOC devices that cannot signal via INTx include LEB. e. This behavior is a deviation from the PCI specification for only the GbE and a device that can be a bus master. Table 3-11. PCI Configuration Header Support for Type 0 Headers in AIOC Devices (Sheet 2 of 2) Offset Register and Field Bit(s) Supt. a Acc.b Notes

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 127 Intel® EP80579 Integrated Processor Table 3-12. PCI Configuration Header Support for Type 1 Headers in AIOC Devices (Sheet 1 of 3) Offset Register and Field Bit(s) Supt. a Acc.b Notes 00h - 01h Vendor ID 15:0 Y RO Required by PCI. 02h - 03h Device ID 15:0 Y RO Required by PCI. 04h - 05h Command Register Interrupt Disable 10 N RW Bridge-generated interrupts not supported. Fast Back-to-Back Enable 9 N RO Not supported. SERR# Enable 8 N RW Bridge delivers events that would be master aborts (primarily address decode) as SERR#. Parity Error Response 6 N RW Not supported. INTx/MSI signal AIOC errors. VGA Palette Snoop 5 N RO Not supported. Mem. Write & Inval. Enable 4 N RO Not supported. Special Cycles 3 N RO Not supported. Bus Master Enable 2 N RW Not supported c. Memory Space Enable 1N R W Bridge itself does not expose any non-standard registers via memory space. I/O Space Enable 0 N RW Bridge itself does not expose any non-standard registers via I/O space. 06h - 07h Status Register Detected Parity Error 15 N RO Not supported. INTx/MSI signal AIOC errors. Signalled System Error 14 N RO Not supported. INTx/MSI signal AIOC errors. Received Master- Abort 13 N RO Not supported c. Received Target- Abort 12 N RO Not supported c. Signalled Target- Abort 11 N RO Not supported; AIOC devices do not target- abort. DEVSEL Timing 10:9 N RO Not supported. Master Data Parity Error 8 N RO Not supported. INTx/MSI signal AIOC errors. Fast Back-to-Back Capable 7 N RO Not supported. 66MHz Capable 5 N RO Not supported. Capabilities List 4 Y RO Setup based on capabilities exposure by bridge. Interrupt Status 3 N RO Bridge-generated interrupts not supported. 08h Revision ID 7:0 Y RO Required by PCI. 09 - 0Bh Class Code 23:0 Y RO Required by PCI. 0Ch Cache Line Size 7:0 N RO Not supported. 0Dh Latency Timer 7:0 N RO Not supported. 0Eh Header Type 7:0 Y RO Required by PCI. 0Fh BIST 7:0 N RO Not supported. 10h - 17h Base Address (x2) 2 x 31:0 NR O Not supported. Bridge does not expose non- standard registers via BAR. 18h Primary Bus Number 7:0 Y RW Required by PCI.

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Number 7:0 Y RW Required by PCI. 1Ah Subordinate Bus Number 7:0 Y RW Required by PCI. 1Bh Secondary Latency Timer 7:0 Y RO Not Supported. 1Ch I/O Base 7:0 Y RW Supported, AIOC devices materialize in I/O space. 1Dh I/O Limit 7:0 Y RW Supported, AIOC devices materialize in I/O space. 1Eh - 1Fh Secondary Status Register Detected Parity Error 15 N RO Not supported. INTx/MSI signal AIOC errors. Received System Error 14 N RO Not supported. INTx/MSI signal AIOC errors Received Master- Abort 13 N RO Not supported c. Received Target- Abort 12 N RO Not supported c. Signalled Target- Abort 11 N RO Secondary-side devices cannot target-abort. DEVSEL Timing 10:9 N RO Not supported. Master Data Parity Error 8 N RO Not supported. INTx/MSI signal AIOC errors. Fast Back-to-Back Capable 7 N RO Not supported. 66MHz Capable 5 N RO Not supported. 20h - 21h Memory Base 15:0 Y RW Supported, AIOC devices materialize in memory space. 22h - 23h Memory Limit 15:0 Y RW Supported, AIOC devices materialize in memory space. 24h - 25h Prefetch Memory Base 15:0 N RW d Prefetchable memory devices not supported. 26h - 27h Prefetch Memory Limit 15:0 N RW d Prefetchable memory devices not supported. 28h - 2Bh Prefetch Base (upper 32b) 31:0 N RW d Prefetchable memory devices not supported. 2Ch - 2Fh Prefetch Limit (upper 32b) 31: 0 N RW d Prefetchable memory devices not supported. 30h - 31h I/O Base (upper 16b) 15:0 N RO I/O spaces larger than 64KB not supported. 32h - 33h I/O Limit (upper 16b) 15:0 N RO I/O spaces larger than 64KB not supported. 34h Capability Pointer 7:0 Y RO Setup based on capabilities exposure by bridge. 38h - 3Bh Expansion ROM Base 31:0 N RO Not supported. 3Ch Interrupt Line 7:0 N RO Bridge-generated interrupts not supported. 3Dh Interrupt Pin 7:0 N RO Bridge-generated interrupts not supported. Table 3-12. PCI Configuration Header Support for Type 1 Headers in AIOC Devices (Sheet 2 of 3) Offset Register and Field Bit(s) Supt. a Acc.b Notes

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 129 Intel® EP80579 Integrated Processor For additional details on the headers for AIOC devices, see Section 35.3.1, “Description of PCI Configuration Header Space”. The specific portion of the 256B PCI configuration space that is active in a device depends on the needs of the specific device. In general, a device requires far less than 256B of storage to implement a typical configuration space. Regions of the 256B configuration space that are not required are reserved and need only support default behavior compliant with the PCI specification: All PCI devices must treat Configuration Space write operations to reserved registers as no-ops; that is, the access must be completed normally on the bus and the data discarded. Read accesses to reserved or unimplemented registers must be completed normally and a data value of 0 returned. § § 3Eh - 3Fh Bridge Control Register Discard Timer SERR# Enable 11 N RO Not supported. Discard Timer Status 10 N RO Not supported. Secondary Discard Timeout 9 N RO Not supported. Primary Discard Timeout 8 N RO Not supported. Fast Back-to-Back Enable 7 N RO Not supported. Secondary Bus Reset 6 N RW Not supported. Master Abort Mode 5 Y RO Bridge delivers events that would be master aborts (primarily address decode) as SERR#. VGA Enable 3 N RW Not supported. ISA Enable 2 N RW Not supported. SERR# Enable 1 N RW Not supported. Parity Error Response 0 N RW Not supported. a. Supported fields provide appropriate PCI semantics. Unsupported fields always return zero on reads unless otherwise noted and need not provide PCI semantics. b. RO and RW access types indicate that the register or field supports read-only access and read/write access, respectively. c. This is a known deviation from the PCI specification since the bridge can be a bus master. d. This is a deviation from the PCI specification since this register should be RO on bridges that do not support prefetchable regions. The registers are RW for compatibility with the base IP. Software is expected to set these fields to indicate an empty region since no secondary-side devices (i.e., bus M) request prefethcable memory. Table 3-12. PCI Configuration Header Support for Type 1 Headers in AIOC Devices (Sheet 3 of 3) Offset Register and Field Bit(s) Supt. a Acc.b Notes

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4.0 Signaling

4.1 Overview

This chapter presents an overview of the inter-agent signaling mechanisms supported along with the implications on transaction ordering necessary to support producer/ consumer software algorithms. This chapter concentrates primarily signaling for functional, not error, purposes while Section 5.0, “Error Handling” provides additional discussion on error signaling. The EP80579 signaling model operates in a system-on-a-chip environment and must blend the signaling architectures of many disparate components into a unified whole.

Allow signaling between IA agents (i.e., the IA-32 core, IMCH, IICH, and external PCI-Express-attached devices) and AIOC agents.
Support producer/consumer relationships between agents in the IA or AIOC.
Provide compatibility with existing IA signaling mechanisms for internal IMCH/IICH agents and external devices.
Provide compatibility with IA platform signaling semantics and abstractions. There are two tightly related parts to the signaling model:
T h e signaling mechanism determines how takes a signal from a source agent, performs any necessary translation, and delivers it to a target agent in a form the target can understand.
T h e ordering mechanism determines how orders a given signal from a source agent with respect to the data stream that the source agent produces to meet ordering requirements. Figure 4-1. Logical Overview of Signaling Architecture AIOC IA Complex (CPU, IMCH, IICH) Signal Bridging PCI ExPCI Device(s) Internal PCI Agents EP80579

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The IA complex attaches to the AIOC through a transparent PCI-to-PCI Bridge. Within the AIOC, the “Signal Bridge” block in Figure 4-1 represents the hardware in the AIOC, that converts signaling between the AIOC and IA domains and presents the appropriate abstractions to agents on either side of the bridge.

4.1.1 Terminology and Conventions

Throughout this section, we use the following terminology:

Global visibility: An operation is said to be globally visible when all side-effects of the operation are visible to every observer in the system. For example, a write to some resource (e.g., memory location, control register, etc.) R achieves global visibility when a read of R by all other agents is guaranteed to return the new value.
Ordering: Ordering refers to the order in which signals and/or memory accesses to different locations must reach global visibility to ensure some behavior. Note that this excludes the “ordering” necessary to prevent data hazards which are accesses to the same location.
Signal: A message sent between agents to indicate some condition of interest. A signal may be an interrupt, a memory write, etc. This section uses the term when the specific transport medium is not important.

4.2 Existing Signaling Capabilities

There are several agents in the EP80579 that can be both the source and the target of a “signal”: the IA-32 core and accelerators in the AIOC. In addition, there are several other agents in the EP80579 that can be the source of a signal: devices in the IMCH or IICH, the error reporting hardware, the Gigabit Ethernet MAC, the SSP interface, the CAN interfaces, the IEEE 1588 interface, externally-attached PCI-Express devices, and externally-attached local expansion bus devices (via GPIO or INTx interrupts). This section summarizes the existing signaling capabilities of each of these agents. When discussing signaling, this section classifies all signals into one of two general categories:

Ordered signals must maintain a particular relationship with the data stream. For example, a MAC signals a CPU with an ordered signal after the MAC finishes writing inbound packet data to memory.
Unordered signals need not maintain a particular relationship with the data stream. For example, memory interface hardware signals a CPU with an unordered signal when the interface encounters an uncorrectable memory error. Signals of either type may participate in producer/consumer operations between agents; however, the operation can use only ordered signals if the producer/consumer operation involves the data stream 1. Finally, note that this classification refers specifically to the data stream; signals may also be ordered with respect to other events (e.g., data being available in a local device buffer). 1. For producer/consumer operation to work correctly, software and hardware must be able to establish ordering relationships between various events in the operation. Such a relationship cannot be established between the data stream and a signal that is unordered with respect to the data stream.

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4.2.1 IA-32 core/Platform

The IA-32 core supports two inbound signaling mechanisms that the EP80579 can use to accept signals from other agents: a legacy interrupt (INTx) and a message-signaled interrupt (MSI). The INTx mechanism encodes an interrupt on one of four out-of-band interrupt signals that drive interrupt controllers in the IA platform. The MSI mechanism encodes an interrupt as an in-band 32-bit write to a memory-mapped location. When the platform observes a write to an MSI location, it generates an interrupt to the CPU. The operating system or system software specifies, in large part, the data value that travels with an MSI; the device has limited ability to change or modify this value in the PCI MSI model. The IA platform also supports signaling for errors through events that the platform eventually maps onto interrupts, such as SERR or SMI. Section 5.0, “Error Handling” discusses these mechanisms in further detail. These mechanisms are not used in functional inter-agent signaling.

4.2.1.1 MSI and INTx Signaling

The EP80579 supports both MSI and INTx mechanisms to interoperate with IA platform system software since not all operating systems or devices support MSIs. The PCI configuration header of each device indicates the capabilities of the device (i.e., if it can generate an MSI, which pin it uses in INTx mode, etc.) and also allows system software to specify the signaling mechanism the device should use when the device is capable of both MSI and INTx signaling. Further, when signaling the IA platform, software must tolerate “warts” of the IA signaling model such as spurious interrupts, etc. For outbound signaling from the IA-32 core to other agents, the EP80579 relies on memory writes to MMIO locations to transport signals or IA can issue an MMIO read to a device CSR.

4.2.1.2 GPIO Signaling

The EP80579 provides the ability to configure a subset of its GPIO pins as interrupts. GPIO pins 16-21, 23-25, 27, 28, 30, 31, 33, 34, and 40 can function in either an interrupt mode or as a GPIO. Each of these GPIO pins can be connected to a single input on the APIC when software configures the GPIO as an interrupt. These pins are then available to external devices, such as a device attached to the Local Expansion Bus, for use as signals. The EP80579 handles signals arriving through a GPIO interrupt are handled like all other interrupts connected to the APIC. For additional information, see the GPIO material in Section 22.0, “General Purpose I/O: Bus 0, Device 31, Function 0”.

4.2.2 Other Agents

The remaining agents that are relevant to the EP80579 signaling model can only signal in the outbound direction; that is, they only generate signals from the agent into EP80579. These agents operate as follows:

IMCH, IICH, and externally-attached PCI devices generate IA platform INTx or MSI signals based on PCI device and platform configuration. PCI mechanisms such as SERR can also support error reporting (see Section 5.0, “Error Handling”).
Gigabit Ethernet MAC generates a side-band interrupt signal.
CAN, SSP, and IEEE 1588 Interfaces generate side-band interrupt signals.
Externally-attached Local Expansion Bus devices generate side-band interrupt signals. These signals are not carried on the Local Expansion bus itself but rather are presented to the IA-32 core through GPIO pins that the system configures to generate signals.

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4.3 Inter-Agent Signaling

Signals may originate from a number of sources within the system but may only target one of the on-die agents in the EP80579: the IA-32 core or AIOC accelerator. This section considers inter-agent signaling mechanisms available in the EP80579. This material looks at signaling in isolation. Because the EP80579 integrates devices from several different fabrics, signaling between different agents may require bridge functionality to convert signals between the various existing capabilities that Section 4.2, “Existing Signaling Capabilities” on page 132 describes. Figure 4-2 presents a logical view of the flow of signals through the EP80579. In this model, a signal originates from a source agent as an in- or side-band signal. Depending on the specific situation, the signal may either reach the destination directly or through a signal bridge. The signal bridge in EP80579 does not provide any mechanism to ensure that a destination agent responds to a given inbound signal. As a result, software must be able to keep up with the signaling rates if catching and processing every signal is a requirement. If software is unable to keep up with the signaling rate, one or more signals can be dropped. Table 4-1 summarizes the cross product of the combinations of producer and consumer agents that EP80579 supports for signaling between agents. This table identifies the types of signaling allowed as well as any bridging that the EP80579 hardware must provide to support signaling between the indicated agents. Table 4-1. Supported Inter-Agent Signaling Figure 4-2. Logical View of Signaling Flow Signal Bridge Destination Agent In- or side-band signal from Source Agent Signal for Destination Agent in Destination Format Source Agent Signal Bridging On-Die Signal Consumer IA-32 core Signal Producer IA-32 core Not Supporteda a. Support not required since there is only one such agent in an EP80579. IMCH, IICH Devices PCI MSI / INTx via PCI GigE MAC Side band: PCI MSI / INTx SSP Side band: PCI MSI / INTx CAN Side band: PCI MSI / INTx

1588 Side band: PCI MSI / INTx

b. This includes signaling for errors in the memory controller, local expansion bus, etc. Side band: PCI MSI / INTx External PCI Express* Device PCI MSI / INTx via PCI External Local Expansion Bus Device MSI / INTx via GPIO

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 135 Intel® EP80579 Integrated Processor In this table, “:” and “via” indicates bridged and direct paths for the signaling (see Figure 4-2), respectively. All EP80579 hardware that inter-operates with IA platform structures for signaling, such as the signal bridge, operate in IA physical address space. This allows it to access IA platform devices, such as the LAPIC that are accessed via MMIO reads and writes in the PCI L memory region. The next two sections cover the various signaling scenarios that are represented in the cells of Table 4-1: signaling that travels around the bridge and that is bridged from a side band signal.

4.3.1 Signaling that Travels Around the Signal Bridge

For signaling that does not need to travel through the signal bridge, the EP80579 does not require any specific signaling support. In these cases, the signaling occurs over an existing path. For example, an interrupt from a IICH USB controller would travel over the existing IICH INTx or MSI path based on device configuration.

4.3.2 Signaling that is Bridged from a Side-Band Source Signal

The majority of signaling scenarios in Table 4-1 that require bridging are conversions between side band signals and a signal that targets the IA-32 core. The EP80579 uses a centralized agent, the signal bridge to perform this conversion. One or more side- band signals arrive at the signal bridge from each AIOC device that is capable of signaling. The bridge is responsible for generating the appropriate outbound signal to either an ASU device or the IA-32 core. Figure 4-3 presents an overview of the signal bridge hardware for a subset of the EP80579 AIOC devices. Figure 4-3. Signal Bridging Logically, the signal bridge consists of the MSI and Signal Target capability records from the PCI configuration headers for the AIOC devices. The MSI capability record for a device includes a message address register (mar in Figure 4-3) and Message data register (mdr in Figure 4-3) that indicate the address and data for the MSI as per the PCI definition of this capability. The Signal Target capability record for a device includes a mask that determines how the bridge steers the signal, data which identifies additional signaling data, and a status that indicates which side-band signal(s) has been asserted 1. The Signal Target capability is a vendor-specific capability record whose format the EP80579 defines. In the example show in Figure 4-3, side band signals arrive from Gigabit Ethernet MAC and other AIOC agents. These agents correspond to AIOC PCI devices. Here, the GbE agent generates a signal that the signal bridge delivers as an MSI to IA based on the 1. The status is not shown in Figure 4-3. MSI [C], f(Z) IA INT<n> Signal Bridge

11 INTb

mar ?, mdr ? mar C, mdr Z ASU mar A, mdr X MSI mask M11, data ? mask M9, data S mask M0, data ? mask M10, data ? Signal Target AIOC AIOC AIOC GbE 0 n n n n

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configuration in the MSI and Signal Target capability records in the PCI configuration header. These records allow the signal bridge to determine how to handle an inbound signal from a device. All side band signals from a given source are collected at the signal bridge. For example, a source may provide interrupt lines and error condition lines that cause the EP80579 to send a signal when any one is asserted. Sets of side band signals are then associated with each AIOC PCI device that can signal. When a given side band signal asserts, the signal bridge looks up the MSI and Signal Target capability records in the PCI configuration header that corresponds to the device. These resources tell the signal bridge how and where to deliver the outbound signal:

If the masks in the Signal Target capability record indicate the signal should be delivered to the IA-32 core, the signal bridge sends an MSI or INTx signal to the IA- 32 core. — If the PCI configuration header selects MSI messaging, the signal bridge generates an MSI transaction from the device that generates the signal to the IA-32 core in accordance with the MSI capability record. — If the PCI configuration header selects INTx messaging, the signal bridge generates an INTx transaction to the IA-32 core. The status register in the Signal Target Capability provides the state of the side-band signals associated with a given AIOC PCI device to help software disambiguate the source of the signal.

4.3.2.1 Targeting the IA-32 core with a Bridged Signal

To remain compatible with existing IA software stacks, EP80579 hardware supports the PCI MSI and legacy INTx signaling mechanisms into the CMI in response to signals targeting the IA-32 core.

MSI enable field selects the signaling mechanism an MSI-capable device uses: —I N T x l e g a c y m o d e . —M S I m o d e .
MSI capability record specifies how IA system software wants MSI-capable devices to signal the IA-32 core through a message address and message data register.
Interrupt pin and line registers specify the interrupt pin and line that the hardware uses for legacy INTx mode.
Interrupt disable bit in the command register specifies whether or not the device generates any signals. Based on the PCI abstraction, these are per-device fields that are logically associated with a given device and that all devices that can signal the IA-32 core must implement. Software is free to mix signal delivery mechanisms at the device level. For example, it may configure the EP80579 such that the Gigabit Ethernet MACs signal through MSIs while the remaining AIOC devices signal through INTx. When device X signals the IA-32 core, it consults the PCI configuration header for device X to determine how to deliver the signal to IA (i.e., via MSI or INTx). For signaling via MSI, the header identifies the address and data value in the MSI transaction. Hardware builds the 32-bit data value for the MSI transaction from the contents of the PCI MSI Message Data Register, mdr, according to the PCI semantics. Specifically, the data value sent in the MSI to IA is:
Bits 31:16 are zero.
Bits 15:0 are mdr, the value of the PCI MSI Data Register in the PCI configuration header of the source device

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 137 Intel® EP80579 Integrated Processor The address is given directly by the PCI MSI Message Address Register, mar. Finally, the source of the MSI transaction is set to the bus/device/function number of the device that generates the signal. For signaling via INTx, the header identifies the interrupt line and pin that the EP80579 should use. In this case, hardware generates the appropriate transactions for INTx upstream into the CMI. Since the INTx mechanism cannot transport any information beyond the fact that a signal occurred, the EP80579 needs to expose enough device state to the software stack, via device-specific control register(s), to allow software to be able to determine both the source and cause of the interrupt. Such state would be in addition to the generic interrupt state that each PCI device provides through its PCI configuration header as per the PCI specification To integrate with the existing IMCH/IICH, the signal bridge in the EP80579 will generate four INTx signals that it tracks based on the interrupt state of the blocks from the AIOC that can generate signals. These four INTx signals are provided to interrupt hardware in the IA platform hardware where they are ORed with similar signals from other agents and converted into the appropriate signaling to the IA-32 core. This hardware will also provide a signal back to the IMCH that indicates when the local INTx state can be deasserted. In addition to generating any transaction(s) necessary to send the signal to the IA, the AIOC must preserve the semantics of PCI interrupts and signals with respect to the state in the PCI configuration headers for the AIOC devices.

Signaling to the IA-32 core by a device should operate in accordance with the MSI mode and configuration in the MSI capability record.
Signaling to the IA-32 core by a device must be disabled when the interrupt disable bit in the PCI command register is set
The interrupt status bit in the PCI status register should reflect the status of an INTx signal. This preserves the PCI abstraction for AIOC devices. § § 1. This assumes that the device requests exactly on e message in the PCI MSI capability record [PCI_3].

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5.0 Error Handling

5.1 Overview

This section presents an overview of the error handling mechanisms that the EP80579 provides. The intent of this discussion is to provide a broad background to error handling on the chip. Register definitions and other error handling details can be found in the discussions of the relevant units throughout this document.

5.2 EP80579 View of Error Reporting

This section describes the guiding principles on which the error logging and reporting registers are based for the EP80579. For the purposes of this discussion, an “error” is an exceptional condition that is beyond the control of the EP80579 hardware or software and might result in data corruption or data loss. This definition does not cover “functional” errors that are not beyond the control of the EP80579. For example, this section discusses double-bit ECC errors as they involves data corruption that occurs through no overt action of the EP80579; it does not cover an underflow error on a ring since this is a functional condition that can be managed in software to avoid data loss.

5.2.1 Hardware Capabilities

With respect to their error handling capabilities, the blocks on the EP80579 can be divided into three groups: the IA blocks (including the IA-32 core, IMCH exclusive of the memory interface, IICH), the memory controller interface, and the AIOC blocks. Generally speaking,

The IA blocks (see Section 5.3, “Error Reporting by the IMCH” on page 141 and Section 5.4, “Error Reporting by the IICH” on page 149) use the FERR/NERR and PCI error reporting infrastructures.
The memory controller block (see Section 5.5, “Error Reporting by the System Memory Controller” on page 153) uses the FERR/NERR error reporting infrastructure.
The AIOC blocks (see Section 5.6, “Error Reporting by AIOC Devices” on page 155) use their existing error reporting infrastructures that are “bridged” into the IA-32 core to report errors to IA through PCI signals (i.e., INTx or MSI depending on device configuration). These blocks do not support other PCI error reporting capabilities such as SERR or the IMCH FERR/NERR architecture. This organization allows an EP80579 system to use standard IA platform reporting abstractions and algorithms throughout the IA portion of the chip (including the memory controller). AIOC devices then use PCI INTx or MSI signaling to present their error handling within the IA infrastructure. Utilizing signaling in this fashion implies that the responsibility for error handling in AIOC devices resides with Intel provided AIOC device drivers in the EP80579 software stack.

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The EP80579 hardware, where appropriate, supports two general capabilities for error handling. The first is support for data “poisoning” to propagate errors through the chip. The second is support for mechanisms to allow software to inspect the cause of the error. To allow software to inspect the error, each unit in the EP80579 that is capable of detecting errors typically provides hardware support to:

Log sufficient information for software to determine what the error was along with relevant details on the error.
Disable error detection and reporting.
Report if more than one error occurred. At a minimum, the unit will note that a second error occurred. Optionally, a unit may gather additional information on subsequent errors such as the type(s) of errors or other relevant details. A given unit need not support all of these capabilities.To illustrate these capabilities, consider the EP80579 DRAM interface. DRAM on the EP80579 is protected by ECC, so, on a read with a double-bit error, the memory controller reports an error. The memory controller can poison the data return value to inform future consumers of the data that the data is bad. For software, registers in the memory controller provide the ability to mask this error along with logging registers that captures the address that was being read when the error was encountered. On an unmasked double-bit error, the logging register captures the address and the memory controller signals the IA-32 core through the FERR/NERR infrastructure. The error address register is locked at this point, so subsequent errors will not overwrite it until software handles the error and unlocks the registers by writing a register to clear the error condition. The memory controller provides a “next error” register that can capture information on other unmasked errors that occur before software clears the double-bit error condition. In general, the CMI will attempt to route requests based on their understanding of the address space layout of the platform (that is, the amount of installed physical DRAM, attached PCI Express* devices, etc.). There are several tables throughout the EAS that define how various parts of the chip handle this routing task:
Section 10.1, “Overview” and Section 10.2, “IMCH Responses to EDMA Transactions” describes how the IMCH responses to transactions from the EDMA engine.
The memory controller does not perform bounds checking on addresses, error handling behavior is determined by the upstream agents that pass the request to the memory controller as Section 5.5.1, “Handling Out-of-Bounds Addresses” on page 154 describes. The IA portion uses the standard IA mechanisms to handle cases where this routing encounters errors (e.g., accessing an unpopulated region of memory). These cases cause aborts and are escalated through the normal error handling paths. On errors in requests arriving from the memory target, the IMCH will drop writes (i.e., not forward them into the IMCH) and poison data returns for reads through the appropriate push/ pull data error signals. These error conditions are reported through IMCH error reporting registers.

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5.2.2 Software Usage Model

The software responsibilities for error handling are split between BIOS and system/ application software. The manner in which the software uses the capabilities that the hardware provides depends on the specific software stack under consideration. In general, BIOS does not establish a usage model for error handling. Its primary responsibility is to configure the error handling registers throughout the EP80579 in a manner consistent with the needs of system and application software. The EP80579 reference BIOS provides this level of support. However, in general, a BIOS implementation may also log information on error events reported via SMI 1. In this case, BIOS populates data structures in SMBIOS2 that an operating system can later retrieve. Generally speaking, the software is more interested in seeing an error rather than the specific location where it is sent. The usage model from the system or application perspective depends on the manner in which the hardware reports the event to the system along with the specific error event. There are two general types of reporting that one can consider: through a kernel-trapped signal and through a non-kernel- trapped signal. A particular error event need be reported through at least one of these mechanisms. When the hardware reports an error event through a signal that the OS kernel handles on its own (e.g., MCERR, SERR, etc.), the operating system takes whatever corrective action it implements for the signal: bug check, panic, halt, reboot, event logging, clean up and continue, etc. In this case, the OS kernel establishes the usage model. This approach is only applicable to the IA and memory controller blocks since the AIOC devices can only report error events through INTx or MSI signals that the OS kernel passes off to the appropriate driver software rather than handle in the kernel. When the hardware reports an error event error through a signal that the software outside of the OS kernel handles on its own (e.g., INTx, MSI, etc.), it is the responsibility of driver or other non-kernel software to take corrective action. All AIOC agents fall into this category since their hardware uses only INTx or MSI for error reporting. In this case, it is the responsibility of the driver software to establish the error handling usage model. Typically, the action the driver takes in response to an error event will match those taken by the OS kernel: panic, clean up and continue, etc.

5.3 Error Reporting by the IMCH

See Section 14.2, “Exception Handling” and Section 14.3, “Error Conditions Signaled” for further discussion on IMCH error handling.

5.3.1 Overview of the First and Next Error Architecture

The IMCH provides a “first” and “next” error architecture wherein errors accumulate locally in unit-level first/next error registers that the IMCH aggregates into global first/ next error registers. Once a unit records an error event in its “first” error register, it will record all subsequent errors in its “next” error register until software clears the error condition in the first error register. The error events are then classified into “fatal” and “non-fatal” groups for reporting through the global first and next error registers. The architecture allows software to mask individual error events at the unit level. In addition, through per-unit registers, software can configure the hardware to report the error event through IA SMI, SCI, SERR, or MCERR signals. 1. This approach only works for error events that the EP80579 can report through SMI. Specifically, this approach would not work for error events from AIOC agents which cannot report through SMI in the EP80579. 2. System Management BIOS (SMBIOS) is a specification to lay out data structures and access methods in a BIOS which provides for storage and retrieval of information about the PC in question

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The actions taken by the hardware in response to an error event depends on the manner in which software has configured the IMCH to report the error. For unmasked events that the IMCH signals through SMI, SCI, or SERR, the IMCH presents the error to the IA-32 core indirectly through the IICH. In these cases, the IMCH sends an error message to the IICH (via NSI) that IICH interrupt logic handles by signaling the IA-32 core through an interrupt. For unmasked events that the IMCH signals through MCERR, the IMCH directly presents the error to the IA-32 core (via FSB). In this case, the IMCH directly signals the IA-32 core through the MCERR protocol on the FSB. After receiving the message, software will query the global IMCH error registers (see Section 5.3.2, “Global Error Events”) to determine which IMCH unit is responsible for the error. With that information, software can query the unit that generated the event to determine the specific cause.

5.3.2 Global Error Events

Table 5-1 summarizes the error events that the IMCH captures in its GLOBAL_FERR and GLOBAL_NERR error registers (see Section 16.2.1.12, “Offset 40h: GLOBAL_FERR - Global First Error Register” and Section 16.2.1.13, “Offset 44h: GLOBAL_NERR - Global Next Error Register”). Each of these events rolls up one or more unmasked error events from an individual IMCH unit. To determine the specific error event that causes a signal, software consults the unit-specific error registers that Table 5-1 indicates. The global registers provide summary information only; masking takes place at the unit level. Table 5-1. Summary of IMCH Global Error Conditions Event Fatality a a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR. Unit-Specific Registers Notes DRAM Controller Fatal Error Fatal DRAM_FERR, DRAM_NERR Fatal error in DRAM interface. FSB Fatal Error Fatal FSB_FERR, FSB_NERR Fatal error on internal CPU/IMCH FSB interface. NSI Fatal Error Fatal NSI_FERR, NSI_NERR Fatal error on internal IMCH/IICH NSI interface. DMA Fatal Error Fatal EDMA_FERR, EDMA_NERR Fatal error from DMA controller. PCI Express* Port A1, A0 Fatal Error Fatal PEAFERR, PEANERRb b. Each port has its own independent PEAFERR and PEANERR registers in the PCI configuration space for the port controller device. Fatal error from PCI Express* Port A1 (PEA1) or A0 (PEA0). Buffer Unit Non-Fatal Error Non-Fatal BUF_FERR, BUF_NERR Non-fatal error in posted memory write buffer. DRAM Controller Non-Fatal Error Non-Fatal DRAM_FERR, DRAM_NERR Non-fatal error in DRAM interface. FSB Non-Fatal Error Non-Fatal FSB_FERR, FSB_NERR Non-fatal error on internal CPU/IMCH FSB interface. NSI Non-Fatal Error Non-Fatal NSI_FERR, NSI_NERR Non-fatal error on internal IMCH/IICH NSI interface. DMA Non-Fatal Error Non-Fatal EDMA_FERR, EDMA_NERR Non-fatal error from DMA controller. PCI Express* Port A1, A0 Non-Fatal Error Non-Fatal PEAFERR, PEANERRb Non-fatal error from PCI Express* Port A1 (PEA1) or A0 (PEA0).

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 143 Intel® EP80579 Integrated Processor Section 5.3.8 discuss the specific per-unit events that the IMCH hardware captures and rolls up into the global conditions that Table 5-1 lists.

5.3.3 Unit-Level Errors from the Buffer Unit

The IMCH buffer unit captures error events from the memory system coherent Posted Memory Write Buffer (PMWB) in the BUF_FERR and BUF_NERR registers. The buffer unit reports an error event to the IA-32 core through SCI, SMI, SERR, or MCERR signals based on the settings in the BUF_SCICMD, BUF_SMICMD, BUF_SERRCMD, and BUF_MCERRCMD registers. Software can independently configure the specific signal that each buffer unit error event uses. Table 5-2 summarizes the error conditions that the PMWB can generate. Table 5-3 summarizes the capabilities of the IMCH buffer unit error handling for each of the features that the unit is expected to provide.

5.3.4 Unit-Level Errors from the DRAM Interface

These errors include the error events reported by the memory controller, see Section 5.5, “Error Reporting by the System Memory Controller” on page 153 for additional details. Table 5-2. Summary of IMCH Buffer Unit Error Conditions Event Type Fatality a a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR. Reports viab b. Based on BUF_SCICMD, BUF_SMICMD, BUF_SERRCMD, and BUF_MCERRCMD register values. Notes DRAM to PMWB Parity Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Parity error detected on read from DRAM agent by PMWB. System Bus or I/O to PMWB Parity Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Parity error detected on write to PMWB from system bus or I/O agent. PMWB to System Bus Parity Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Parity error detected on data to the system bus. PMWB to DRAM Parity Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Parity error detected when PMWB is flushed to DRAM. Table 5-3. Summary of IMCH Buffer Unit Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting The BUF_EMASK (see Section 16.2.1.29, “Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register”), BUF_SCICMD, BUF_SMICMD, BUF_SERRCMD, and BUF_MCERRCMD registers enable and mask error reporting. The PCICMD register (see Section 16.2.1.3, “Offset 04h: PCICMD - PCI Command Register”) also enables and masks SERR signals. Logging Details IMCH does not capture error logging information beyond the event flags in the BUF_FERR, BUF_NERR and PCISTS (see Section 16.2.1.4, “Offset 06h: PCISTS - PCI Status Register”) registers. Reporting Multiple Errors The BUF_NERR register captures “next” errors. This register indicates up to one additional error (beyond the first error) of each type. Data Poisoning IMCH passes along error information to poison data.

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5.3.5 Unit-Level Errors from the FSB Interface

The FSB interface captures error events from the FSB interface that connects the IA-32 core to the IMCH in the FSB_FERR and FSB_NERR registers. The FSB interface reports an error event to the IA-32 core through SCI, SMI, SERR, or MCERR signals based on the settings in the FSB_SCICMD, FSB_SMICMD, FSB_SERRCMD, and FSB_MCERRCMD registers. Software can independently configure the specific signal that each buffer unit error event uses. Table 5-4 summarizes the error conditions that the FSB can generate. Table 5-5 summarizes the capabilities of the FSB error handling for each of the features that the unit is expected to provide. Although the IMCH supports all of the errors Table 5-4 lists with the features in Table 5-5, the EP80579 implementation does not take full advantage of these capabilities since its FSB implementation does not support all of the features necessary. Table 5-4. Summary of IMCH FSB Error Conditions Event Type Fatality a a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR. Reports viab b. Based on FSB_SCICMD, FSB_SMICMD, FSB_SERRCMD, and FSB_MCERRCMD register values. Notes Outgoing I/O Data Parity Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Parity error on outgoing data from I/O subsystem. Outgoing Memory Data Parity Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Parity error on outgoing data from memory subsystem. FSB BINIT# Detected Uncorrectable Fatal N/A c c. Although the IMCH supports these errors, the EP80579 will not ever generate them since its on-die FSB implementation does not support BINIT# or parity. Electrical high-to-low transition of BINIT#. FSB MCERR# Detected Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Electrical high-to-low transition of MCERR# when CMI is not driving. Non-DRAM Lock Error Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Lock detected to memory space that does not map to DRAM. FSB Addr. Above TOM/TOLM Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Address detected above TOM/TOLM. FSB Data Parity Uncorrectable Non-Fatal N/A c Parity error on FSB detected. FSB Addr. Strobe Glitch Detected Uncorrectable Fatal N/A c Glitch detected on FSB address strobe. FSB Data Strobe Glitch Detected Uncorrectable Fatal N/A c Glitch detected on FSB data strobe. FSB Request/Addr Parity Uncorrectable Fatal N/A c Party error on FSB address or request signals. Table 5-5. Summary of IMCH FSB Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting The FSB_EMASK FSB_SCICMD, FSB_SMICMD, FSB_SERRCMD, and FSB_MCERRCMD registers enable and mask error reporting. The PCICMD register also enables and masks SERR signals. Logging Details FSB does not capture error logging information beyond the event flags in the FSB_FERR, FSB_NERR and PCISTS Reporting Multiple Errors The FSB_NERR register captures “next” errors. This register indicates up to one additional error (beyond the first error) of each type. Data Poisoning FSB passes along e rror information to poison data.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 145 Intel® EP80579 Integrated Processor For additional discussion on the IMCH responses to transactions from the FSB interface, see Section 10.1, “Overview”.

5.3.6 Unit-Level Errors from the NSI

The IMCH hardware captures error events from the NSI interface that connects the IMCH to the IICH in the NSI_FERR and NSI_NERR registers. The NSI interface reports an error event to the IA-32 core through IA SCI, SMI, SERR, or MCERR signals based on the settings in the NSI_SCICMD, NSI_SMICMD, NSI_SERRCMD, and NSI_MCERRCMD registers. Software can independently configure the specific signal that each buffer unit error event uses. Table 5-6 summarizes the error conditions that the NSI can generate. Table 5-6. Summary of IMCH NSI Error Conditions Event Type Fatality a Reports viab Notes Unsupported Request Uncorrectable Fatal, Non- Fatal SCI, MCERR, SMI, or SERR Unsupported request detected. Malformed TLP Uncorrectable Fatal, Non- Fatal SCI, MCERR, SMI, or SERR Malformed TLP detected. Receiver Overflow Uncorrectable Fatal SCI, MCERR, SMI, or SERR Overflow detected in posted, non- posted, or completion upstream queue. Unexpected Completion Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Completion received that does not correspond to an outstanding request. Completer Abort Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Completer abort detected. Completion Timeout Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Request not completed within timeout window. Poisoned TLP Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Portion of TLP data payload was corrupt. Data Link Protocol Error Uncorrectable Fatal SCI, MCERR, SMI, or SERR Error detected in data link protocol. Replay Timer Timeout Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Replay timer expired. REPLAY_NUM Rollover Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Retry buffer replay counter rolled over. Bad DLLP CRC Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Calculated DLLP CRC did not equal received value. Bad TLP CRC Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Calculated TLP CRC did not equal received value. Receiver Error Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Packet framing error. Received Fatal Error Message Uncorrectable Fatal SCI, MCERR, SMI, or SERR Fatal error message received over NSI link. Received Non- Fatal Error Message Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Non-fatal error message received over NSI link.

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Table 5-7 summarizes the capabilities of the NSI error handling for each of the features that the unit is expected to provide. For additional discussion on the IMCH responses to transactions from the NSI interface, see Section 10.1, “Overview”.

5.3.7 Unit-Level Errors from the EDMA Engine

The IMCH EDMA unit captures error events from the EDMA engine in the EDMA_FERR and EDMA_NERR registers (The EDMA unit reports an error event to the IA-32 core through IA SCI, SMI, SERR, or MCERR signals based on the settings in the EDMA_SCICMD, EDMA_SMICMD, EDMA_SERRCMD, and EDMA_MCERRCMD registers. Software can independently configure the specific signal that each EDMA unit error event uses. Table 5-8 summarizes the error conditions that the EDMA can generate. Received Correctable Error Message Correctable Non-Fatal SCI, MCERR, SMI, or SERR Correctable error message received over NSI link. Parity Error on Data from Core Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Parity error detected on data received from core. Link Down Uncorrectable Fatal SCI, MCERR, SMI, or SERR Link transitioned from DL_UP to DL_DOWN. a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR. b. Based on NSI_SCICMD, NSI_SMICMD, NSI_SERRCMD, and NSI_MCERRCMD register values. Table 5-6. Summary of IMCH NSI Error Conditions Event Type Fatality a Reports viab Notes Table 5-7. Summary of IMCH NSI Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting The NSI_EMASK, NSI_SCICMD, NSI_SMICMD, NSI_SERRCMD, and NSI_MCERRCMD registers enables and masks error reporting. The PCICMD register also enables and masks SERR signals. Logging Details NSI captures error logging information in the following registers:

All errors: NSI_FERR, NSI_NERR, and PCISTS capture event flags.
Poisoned TLP: PCISTS captures event flags.
Received fatal/non-fatal/correctable error messages: NSI_ERRSID. All of the logging information that the NSI captures relates to the “first” error with the exception of NSI_NERR. Reporting Multiple Errors The NSI_NERR register captures “next” errors. This register indicates up to one additional error (beyond the first error) of each type. Data Poisoning NSI passes along error information to poison data. Table 5-8. Summary of IMCH EDMA Error Conditions Event Type Fatality a Reports viab Notes NDAR Addressing Error Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Descriptor pointer is of incorrect type or range for channels 0-3. NDAR Alignment Error Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Descriptor pointer is not aligned to an 8 DW boundary for channels 0-3. Source Address Error Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Source address does not comply with source type or range for channels 0-3.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 147 Intel® EP80579 Integrated Processor Table 5-9 summarizes the capabilities of the EDMA error handling for each of the features that the unit is expected to provide. For additional discussion on the IMCH responses to transactions from the EDMA engine, see Section 10.1, “Overview” and Section 10.2, “IMCH Responses to EDMA Transactions”.

5.3.8 Unit-Level Errors from PCI Express* Ports A0 and A1

The IMCH PCI Express* Port Controllers capture error events from the port A0 and A1 controllers in per-port registers. The register set provides two parallel error reporting mechanisms, one that reports standard errors defined by the PCI Express* specification and a second that reports errors that are specific to the EP80579 PCI Express* implementation (and thus, outside of the standard PCI Express* errors). The PCI Express* controllers capture errors required by the PCI Express* base specification in the UNCERRSTS and CORERRSTS registers. The controllers capture EP80579-specific errors in the PEAUNITERR register. The errors from both sets of errors are aggregated in the PEAFERR and PEANERR registers. The PCI Express* controllers report an error event to the IA-32 core through IA SCI, SMI, SERR, or MCERR signals based on the settings in the PEAERRDOCMD register. Table 5-10 summarizes the error conditions that the PCI-Express can generate. Destination Address Error Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Destination address does not comply with destination type or range for channels 0-3. Parity Error Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Parity error during read of source data from system memory for channels 0-3. Write Error Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Write to RO descriptor registers when DMA in normal mode for channels 0-3. a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR. b. Based on EDMA_SCICMD, EDMA _SMICMD, EDMA_SERRCMD, and EDMA_MCERRCMD register values. Table 5-8. Summary of IMCH EDMA Error Conditions Event Type Fatality a Reports viab Notes Table 5-9. Summary of IMCH EDMA Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting The EDMA_EMASK, EDMA_SCICMD, EDMA_SMICMD, EDMA_SERRCMD, and EDMA_MCERRCMD registers enables and masks error reporting. The PCICMD register also enables and masks SERR signals. Logging Details EDMA does not capture error logging information beyond the event flags in the EDMA_FERR, EDMA_NERR and PCISTS. Reporting Multiple Errors The EDMA_NERR register captures “next” errors. This register indicates up to one additional error (beyond the first error) of each type. Data Poisoning EDMA passes along error information to poison data.

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Table 5-10. Summary of IMCH PCI-Express Error Conditions Event Type Fatality a a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR. Reports viab b. Based on PEAERRDOCMD register value. Notes Unsupported Request Uncorrectable UNCERRSEV c c. Severity is set by the UNCERRSEV register. SCI, MCERR, SMI, or SERR Request type unsupported. ECRC Error Uncorrectable UNCERRSEV c SCI, MCERR, SMI, or SERR Error in ECRC. Malformed TLP Uncorrectable UNCERRSEV c SCI, MCERR, SMI, or SERR Malformed TLP, like it says... Receiver Overflow Uncorrectable UNCERRSEV c SCI, MCERR, SMI, or SERR Overflow on upstream queue. Unexpected Completion Uncorrectable UNCERRSEV c SCI, MCERR, SMI, or SERR Received completion that does not match any outstanding requests. Completer Abort Uncorrectable UNCERRSEV c SCI, MCERR, SMI, or SERR Received request violates programming model. Completion Timeout Uncorrectable UNCERRSEV c SCI, MCERR, SMI, or SERR Timeout. Flow Control Protocol Error Uncorrectable UNCERRSEV c SCI, MCERR, SMI, or SERR Poisoned TLP Uncorrectable UNCERRSEV c SCI, MCERR, SMI, or SERR TLP data payload corrupt. Data Link Protocol Uncorrectable UNCERRSEV c SCI, MCERR, SMI, or SERR ACK/NACK has incorrect sequence number. Unsupported Request Uncorrectable UNCERRSEV c SCI, MCERR, SMI, or SERR Unsupported Request Uncorrectable UNCERRSEV c SCI, MCERR, SMI, or SERR Unsupported Request Uncorrectable UNCERRSEV c SCI, MCERR, SMI, or SERR Replay Timer Correctable Non-Fatal SCI, MCERR, SMI, or SERR Replay timer expired. REPLAY_NUM Rollover Correctable Non-Fatal SCI, MCERR, SMI, or SERR Retry buffer counter rolled over. Bad DLLP Status Correctable Non-Fatal SCI, MCERR, SMI, or SERR Computed DLLP CRC does not match received value. Bad TLP status Correctable Non-Fatal SCI, MCERR, SMI, or SERR Computed TLP CRC does not match received value. Receiver Error Correctable Non-Fatal SCI, MCERR, SMI, or SERR Received 8b/10b error. LLE Protocol Error Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Transaction layer detected protocol error. Link Down Error Uncorrectable Fatal SCI, MCERR, SMI, or SERR Link transitions from DL_UP to DL_DOWN. Downstream Data Queue Parity Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Parity error occurred in downstream data queue. SMB Clock Timeout Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR SMB CLK low greater than 25ms. Unexpected NAK on SMB Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR Unexpected NAK on SMB. SMB Arbitration Uncorrectable Non-Fatal SCI, MCERR, SMI, or SERR SMB lost bus arbitration.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 149 Intel® EP80579 Integrated Processor Table 5-11 summarizes the capabilities of the PCI-Express error handling for each of the features that the unit is expected to provide. See Section 16.4, “PCI Express* Port A Standard and Enhanced Registers: Bus 0, Devices 2 and 3, Function 0” for additional details. For additional discussion on the IMCH responses to transactions from the PCI Express* ports, see Section 10.1, “Overview”.

5.4 Error Reporting by the IICH

The EP80579 IICH devices rely on the PCI error reporting architecture to reporting errors. In this architecture, details on the errors are logged in the PCI status register from the per-device PCI configuration header. A parity or other severe system error causes the device to generate an IA SERR signal. Errors that occur on the NSI bus between the IMCH and IICH report through the NSI_FERR and NSI_NERR infrastructure as Section 5.3.1, “Overview of the First and Next Error Architecture” on page 141 and Section 5.3.6, “Unit-Level Errors from the NSI” on page 145 describe. On the IICH backbone, IICH devices must rely entirely on the SERR signal that the device generates on an error event to report the error. The IICH does not provide any other capability (such as data poisoning) that would allow a consumer of IICH data to note an error. As a result, an IICH device can return erroneous data on a request. The remainder of this section describes the error handling capabilities of the units in the IICH.

5.4.1 SMBus Interface

The IICH provides a SMBus controller that can generate an interrupt or SMI on error events and can also use the PCI SERR infrastructure to report errors. The HCFG register selects either SMI or interrupt signaling; parity and system errors always signal through SERR. Table 5-12 summarizes the error conditions that the controller reports. Table 5-11. Summary of IMCH PCI-Ex press Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting The UNCERRMSK, UNCEDMASK, CORERRMSK, COREDMASK, RPMERRSTS, PEAMASKERR, RPERRCMD, and PEAERRDOCMD registers enables and masks error reporting. The PCICMD register also enables and masks SERR signals. Logging Details PCI Express* controllers captures error logging information in the following registers:

RPMERRSTS errors: ERRSID captures requester IDs.
Errors with Header Capture: HDRLOG0, HDRLOG1, HDRLOG2, and HDRLOG3 captures the first four 32-bit words of the headers. This information is in addition to the status information in UNCERRSTS, CORERRSTS, RPMERRSTS, PEAFERR, and PEANERR. Reporting Multiple Errors The PEANERR and RPERRMSTS registers captures “next” errors. This register indicates up to one additional error (beyond the first error) of each type. Data Poisoning PCI Express* controllers pa ss along error information to poison data.

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Table 5-13 summarizes the capabilities of the SMBus controller error handling for each of the features that the unit is expected to provide. For additional details on error handling in the SMBus controller, see Section 24.0, “SMBus Controller Functional Description: Bus 0, Device 31, Function 3”.

5.4.2 LPC Interface

The IICH provides a LPC interface that uses the PCI SERR infrastructure to report errors. Table 5-14 summarizes the error conditions that the controller reports. Table 5-15 summarizes the capabilities of the LPC interface error handling for each of the features that the unit is expected to provide. Table 5-12. Summary of SMBus Interface Error Conditions Event Type Fatality a a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not. Reports via Notes Device Error Uncorrectable Fatal Interrupt, SMI b b. Based on HCFG register values. Device error. Bus Error Uncorrectable Fatal Interrupt, SMI b Bus error. Failed Bus Transaction Uncorrectable Fatal Interrupt, SMI b Bus transaction failed. Parity Error Uncorrectable Fatal SERR Parity error detected. System Error Uncorrectable Fatal SERR System error detected. Table 5-13. Summary of SMBus Controller Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting The CMD and USBINTR registers enables and masks error reporting. Logging Details The USB 1.1 interface captures the type of event detected in the DSR, HSTS, and AUXS registers. Reporting Multiple Errors The SMBus interface does not capture multiple events. Data Poisoning IICH backbone does not support data poisoning. Table 5-14. Summary of LPC Interface Error Conditions Event Type Fatality a a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not. Reports via Notes Parity Error Uncorrectable Fatal SERR Parity error detected. System Error Uncorrectable Fatal SERR System error detected. Table 5-15. Summary of LPC Interface Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting The CMD register supports error enabling and masking.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 151 Intel® EP80579 Integrated Processor For additional details on error handling in the LPC interface, see Section 19.0, “LPC Interface: Bus 0, Device 31, Function 0”. 5.4.3 USB 1.1 Interface The IICH provides a USB 1.1 controller that can generate an interrupt on error events and can also use the PCI SERR infrastructure to report errors. Table 5-16 summarizes the error conditions that the controller reports. Table 5-17 summarizes the capabilities of the USB 1.1 controller error handling for each of the features that the unit is expected to provide. For additional details on error handling in the USB 1.1 controller, see Section 25.0, “USB (1.1) Controller: Bus 0, Device 29, Function 0”. 5.4.4 USB 2.0 Interface The IICH provides a USB 2.0 controller that can generate an interrupt on error events and can also use the PCI SERR infrastructure to report errors. Table 5-18 summarizes the error conditions that the controller reports. Logging Details The LPC interface captures the type of event detected in the STS register. Reporting Multiple Errors The LPC interface does not capture multiple events. Data Poisoning IICH backbone does not support data poisoning. Table 5-15. Summary of LPC Interface Error Reporting Capabilities Feature Implementation Table 5-16. Summary of USB 1.1 Interface Error Conditions Event Type Fatality a a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not. Reports via Notes Host Controller Process Error Uncorrectable Fatal Interrupt Consistency check by host controller fails while processing a TD. Host System Error Uncorrectable Fatal Interrupt Serious error during host system access involving HC module. USB Error Uncorrectable Fatal Interrupt USB transaction completion ended in error. Parity Error Uncorrectable Fatal SERR Parity error on read completion returned to host controller or UHCI register write. Table 5-17. Summary of USB 1.1 Interface Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting The CMD and USBINTR registers supports error enabling and masking. Logging Details The USB 1.1 interface captures the type of event detected in the DSR and USBSTS registers. Reporting Multiple Errors The USB 1.1 interface does not capture multiple events, error events cause the interface to halt operation until serviced by software. Data Poisoning IICH backbone does not support data poisoning.

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Table 5-19 summarizes the capabilities of the USB 2.0 controller error handling for each of the features that the unit is expected to provide. For additional details on error handling in the USB 2.0 controller, see Section 26.0, “USB 2.0 Host Controller: Bus 0, Device 29, Function 7”.

5.4.5 SATA Interface

The IICH provides a SATA interface that can generate an interrupt on error events and can also use the PCI PERR infrastructure to report errors. Table 5-20 summarizes the error conditions that the controller reports. Table 5-21 summarizes the capabilities of the SATA controller error handling for each of the features that the unit is expected to provide. Table 5-18. Summary of USB 2.0 Interface Error Conditions Event Type Fatality a a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not. Reports via Notes Host System Error Uncorrectable Fatal Interrupt Serious error during host system access involving HC module. USB Error Uncorrectable Fatal Interrupt USB transaction completion ended in error. Parity Error Uncorrectable Fatal SERR Parity error on USB read completion. System Error Uncorrectable Fatal SERR Parity error on address, command, or data, or unsuccessful completion of ECH-initiated read. Table 5-19. Summary of USB 2.0 Interface Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting The CMD and USB20INTR registers supports error enabling and masking. Logging Details The USB 2.0 interface captures the type of event detected in the DSR and USB20STS registers. Reporting Multiple Errors The USB 2.0 interface does not capture multiple events, error events cause the interface to halt operation until serviced by software. Data Poisoning IICH backbone does not support data poisoning. Table 5-20. Summary of SATA Interface Error Conditions Event Type Fatality a a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not. Reports via Notes Host Bus Fatal Error Uncorrectable Fatal Interrupt Unrecoverable host bus error Host Bus Data Error Uncorrectable Fatal Interrupt Uncorrectable data error. Interface Fatal Error Uncorrectable Fatal Interrupt Fatal error on SATA interface. Interface Non- Fatal Error Uncorrectable Non-Fatal Interrupt Non-fatal error on SATA interface. Parity Error Uncorrectable Fatal SERR Parity error detected on interface.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 153 Intel® EP80579 Integrated Processor For additional details on error handling in the SATA interface, see Section 23.0, “SATA: Bus 0, Device 31, Function 2”.

5.4.6 Serial I/O Interface

The IICH provides a serial I/O interface that can generate an interrupt on error events. Table 5-22 summarizes the error conditions that the serial I/O interface captures. Table 5-23 summarizes the capabilities of the thermal sensor error handling for each of the features that the unit is expected to provide. For additional details on error handling in the serial I/O interface, see Section 33.0, “Serial I/O Unit and Watchdog Timer”.

5.5 Error Reporting by the System Memory Controller

The memory controller interfaces with memory to provide data movement to and from DRAM along the AIOC-direct and coherent paths to memory. The memory controller is designed to conform to the IMCH first and next error handling architecture that Section 5.3.1, “Overview of the First and Next Error Architecture” on page 141 describes. The memory controller reports its unit-level first/next error events through the DRAM_FERR and DRAM_NERR registers in the memory controller (see Section 11.5, “Error Handling”). The flow of memory controller errors matches the IMCH behavior for its other errors as Section 5.3.1 describes. Table 5-21. Summary of SATA Interface Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting The CMD and PIE[0-3] registers support error enabling and masking. Logging Details The SATA interface captures the type of event detected in the STS and PIS[0-3] registers. Reporting Multiple Errors The SATA interface does not capture multiple events. Data Poisoning IICH backbone does not support data poisoning. Table 5-22. Summary of Serial I/O Interface Error Conditions Event Type Fatality a a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not. Reports via Notes Framing Error Uncorrectable Fatal Interrupt Received character missing stop bit. Parity Error Uncorrectable Fatal Interrupt Received character has parity error. Overrun Error Uncorrectable Fatal Interrupt Receive buffer over-written. Table 5-23. Summary of Serial I/O Interface Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting The IER and LCR registers supports error enabling and masking. Logging Details The serial I/O interface captures the type of event detected in the IIR and LSR registers. Reporting Multiple Errors The serial I/O interface does not capture multiple events. Data Poisoning N/A

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5.5.1 Handling Out-of-Bounds Addresses

The memory controller does not perform any bounds checking on system addresses that it receives from other agents. As a result, the behavior of the EP80579 in response to an access to a DRAM location that is outside the range of populated memory depends on the source of the transaction and the path it takes through the device. There are two paths of relevance to this discussion: the Coherent path through the IMCH and the AIOC-Direct path directly to the memory controller. Accesses to locations above top of memory along the Coherent path (from either AIOC agents via the AIOC-interface, the IA-32 core, or other agents attached to the CMI through PCI Express*, etc.) will be aborted by the IMCH. The specific manner of the abort depends on whether the transaction originates from the IA-32 core or a AIOC agent. Access to locations above top of memory along the AIOC-Direct path (from the AIOC Memory Target) are not aborted or otherwise trapped by default. The results of such transactions are undefined and may alias onto populated memory regions. As a result, software must program the EP80579 so that it can never generate an AIOC-Direct system address above TOM. The Memory Target provides the ability to log range errors (and optionally halt the AIOC master that generated the transaction).

5.5.2 IMCH - Memory Controller

The memory controller can notify the IA-32 core of memory-related error events through SCI, SMI, SERR, or MCERR signals based on the settings in the DRAM_SCICMD, DRAM_SMICMD, DRAM_SERRCMD, and DRAM_MCERRCMD registers (see Section 11.0, “System Memory Controller”). Software can configure the specific signal used for each error event independently. Table 5-24 summarizes the error conditions that the memory controller captures. Note that the memory controller always reports errors through the non-fatal classification in the error reporting registers. Table 5-25 summarizes the capabilities of the memory controller error handling for each of the features that the unit is expected to provide. Table 5-24. Summary of Memory Controller Error Conditions Event Type Fatality a a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not. This can differ from the fatal/non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR. Reports viab b. Based on DRAM_SCICMD, DRAM_SMICMD, DRAM_S ERRCMD, and DRAM_MCERRCMD register values. Notes Uncorrectable Write Error Uncorrectable Fatal SCI, MCERR, SMI, or SERR Write of poisoned data to DRAM. Uncorrectable Read Error Uncorrectable Fatal SCI, MCERR, SMI, or SERR Error during normal demand reads. Uncorrectable Scrubber Data Error Uncorrectable Fatal SCI, MCERR, SMI, or SERR Memory scrubber encountered an uncorrectable error. Correctable Read Error Correctable Non-Fatal SCI, MCERR, SMI, or SERR Hardware will correct and report if appropriately configured Error Threshold Detect Status Non-Fatal SCI, MCERR, SMI, or SERR Count of single- or double-bit errors exceeds a programmable threshold. Memory Test Complete Status Non-Fatal SCI, MCERR, SMI, or SERR Status event to indicate when memory test hardware completes testing.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 155 Intel® EP80579 Integrated Processor For additional details on error handling in the memory controller, see Section 11.5, “Error Handling”.

5.6 Error Reporting by AIOC Devices

The AIOC devices continue to use the native error reporting infrastructure that each unit provides. Primarily, this infrastructure relies on one or more side-band error signals from each AIOC device that can signal an error along with parity protection on key interfaces. The AIOC native error reporting mechanisms are then bridged into the PCI framework that the EP80579 uses to expose AIOC devices to IA. Although AIOC devices present a PCI interface to IA, they do not implement PCI error reporting capabilities such as SERR. As a result, the native signals from the AIOC devices are bridged onto PCI INTx or MSI signals. This implies that the driver software provides all error handling for AIOC units The following sections describe the error reporting for each of the AIOC units along with transaction responses. The per-unit presentations are organized by the PCI device in which the units materialize.

5.6.1 Gigabit Ethernet MAC

The Gigabit Ethernet MAC units each signal error conditions through three interrupt signals: Functional 0, Functional 1, and Error. Software uses the IMS0, IMS1, and IMS2 configuration registers in a Gigabit Ethernet MAC to map error conditions onto the Functional 0, Functional 1, and Error interrupt signals, respectively. Depending on the configuration, error and functional events may share an interrupt (e.g., software may configure the functional 1 interrupt to signal both error and functional events); typically, software will configure a MAC to deliver its error events separately through only the error interrupt. Table 5-26 summarizes the error conditions that the Gigabit Ethernet MAC captures. Table 5-25. Summary of Memory Controller Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting The DRAM_EMASK, DRAM_SCICMD, DRAM_SMICMD, DRAM_SERRCMD, and DRAM_MCERRCMD registers enable and mask error reporting. Logging Details Memory Controller captures additional error logging information in the following registers:

Uncorrectable read errors: DRAM_DED_ADD.
Uncorrectable scrubber data errors: DRAM_SCRB_ADD.
Correctable read errors: DRAM_SECF_ADD, DRAM_SECF_SYNDROME, DRAM_SECN_ADD, DRAM_SECN_SYNDROME.
Error threshold detect: RANKTHREX, THRESH_SEC0, THRESH_SEC1, THRESH_DED, DRAM_SEC_R0, DRAM_SEC_R1, DRAM_DED_R0, DRAM_DED_R1. Additional logging information is not captured for the remaining errors in Table 5-24. With the exception of DRAM_SECN_ADD and DRAM_SECN_SYNDROME, all of the logging information that the memory controller captures relates to the “first” error. Reporting Multiple Errors The DRAM_NERR register captures the “next” errors seen by the memory controller. This register indicates up to one additional error (beyond the first error) of each type. Data Poisoning Memory Controller passes along error information to poison data both on inbound (from memory) data and outbound (to memory) data. 1. If PCI abstractions such as SERR were used, this would not be the case. Platform and/or O/S software would also be involved in error handling for the devices even if the involvement is limited to generating a blue screen.

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Table 5-27 summarizes the capabilities of the Gigabit Ethernet MAC error handling for each of the features that the unit is expected to provide. See Section 37.6, “GbE Controller Register Summary” and Section 37.5.12, “Error Handling” for additional details.

5.6.2 CAN Interface

The CAN units signal error conditions through two interrupt signals. The CAN unit shares one interrupt between functional signaling duties (e.g., signaling that a message was received) and error reporting, while the second interrupt reports only parity errors. Status and enable registers in the CAN operate and control signaling functionality in the CAN such as error reporting. Table 5-28 summarizes the error conditions that the CAN captures. Table 5-26. Summary of Gigabit Ethernet MAC Error Conditions Event Type Fatality a a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not. Reports viab b. Based on settings in IMS0, IMS1, and IMS2 registers. Notes Statistic Register ECC Error Uncorrectable Fatal ERR, FN0, or FN1 Interrupts Double-bit ECC error in a statistic register. Internal Memory Error Uncorrectable Fatal ERR, FN0, or FN1 Interrupts Parity or double-bit ECC error in an internal memory. DMA Packet Buffer Error Uncorrectable Fatal ERR, FN0, or FN1 Interrupts Double-bit ECC error during read from DMA packet buffer on Tx or Rx. DMA Tx Desc. ECC Error Uncorrectable Fatal ERR, FN0, or FN1 Interrupts Double-bit ECC error during read from DMA transmit descriptor. DMA Rx Desc. ECC Error Uncorrectable Fatal ERR, FN0, or FN1 Interrupts Double-bit ECC error during read from DAM receive descriptor. Table 5-27. Summary of Gigabit Ethernet MAC Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting The IMS0, IMS1, and IMS2 interrupt mask set registers and the IMC0, IMC1, and IMC2 interrupt mask clear registers support error enabling and masking. When software configures the GbE to deliver errors on their own interrupt, the SMIA and SMME registers from the signal target capability in the PCI configuration header for a GbE MAC can also support error enabling and masking. Logging Details The SINT register from the signal target capability in the PCI configuration header for a GbE MAC provides read-only access to the state of the interrupt signals from a GbE MAC. Additional logging information is not captured for the other errors in Table 5-26. Reporting Multiple Errors Individual status bits in the GbE ICR0, ICR1, and ICR2 interrupt cause registers are set as conditions occur. The unit can indicate at most one outstanding error at any time. Data Poisoning GbE passes along e rror information to poison data.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 157 Intel® EP80579 Integrated Processor Table 5-29 summarizes the capabilities of the CAN error handling for each of the features that the unit is expected to provide. See Section 39.6, “Register Summary” and Section 39.5.2, “Error Handling” for additional details.

5.6.3 SSP Interface

The SSP unit signals error conditions through a single interrupt signal. The SSP block shares this interrupt between functional duties (e.g., transmit FIFO service request) and error reporting duties. Software is expected to use status registers in the SSP to determine the cause of a signal. Table 5-30 summarizes the error condition that the SSP captures. Table 5-28. Summary of CAN Error Conditions Event Type Fatality a a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not. Reports via Notes CRC Check Error Uncorrectable Fatal CAN System Interrupt Mismatch between received and computed CRC. Acknowledge Error Uncorrectable Fatal CAN System Interrupt Improperly formatted ACK slot. Form Error Uncorrectable Fatal CAN System Interrupt Improperly formatted fixed-form field. Bit Error Uncorrectable Fatal CAN System Interrupt Mismatch between monitored and sent bit value. Stuff Error Uncorrectable Fatal CAN System Interrupt Improperly formatted message from Start of Frame to CRC delimiter. CAN SRAM Parity Error Uncorrectable Fatal CAN Parity Interrupt Parity error in interface SRAM. Clearing the parity error requires a reset of the CAN interface. Please see section on CAN interrupts in Section 39.2, “Feature List” on page 1569 for more details. Table 5-29. Summary of CAN Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting The CAN interrupt enable register supports error enabling and masking. The SMIA and SMME registers from the signal target capability in the PCI configuration header for the CAN units also supports error enabling and masking. Using these registers to mask the CAN System Interrupt masks both error and functional events since the CAN units use this interrupt to signal both error and functional conditions. Logging Details The SINT register from the signal target capability in the PCI configuration header for a CAN unit provides read-only access to the state of the interrupt signals from a CAN unit. CAN does not log additional details on errors. Reporting Multiple Errors Individual status bits in CAN interrupt status register are set as conditions occur. The unit can indicate at most one outstanding error of each type at any time. Data Poisoning CAN does not require support for data poisoning. Errors during transactions cause the transaction to abort and an error event to be signaled.

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Table 5-31 summarizes the capabilities of the SSP error handling for each of the features that the unit is expected to provide. See Section 40.4, “Register Summary”and Section 40.3.2, “Error Handling” for additional details.

5.6.4 Local Expansion Bus

The Local Expansion Bus unit signals error conditions from the interface into the EP80579 through a single interrupt signal that is used exclusively for errors. In addition, this unit signals errors from the internal bridge through a separate interrupt. Table 5-32 summarizes the error conditions that the local expansion bus captures. Table 5-33 summarizes the capabilities of the local expansion bus error handling for each of the features that the unit is expected to provide. Table 5-30. Summary of SSP Error Conditions Event Type Fatality a a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not. Reports via Notes Functional Receiver Overrun (ROR) Uncorrectable Fatal SSP Interrupt Receive FIFO is full, any incoming data is discarded. Table 5-31. Summary of SSP Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting SSP does not provide the ability to enable or mask the interrupt from an ROR error condition. The SMIA and SMME registers from the signal target capability in the PCI configuration header for the SSP unit also support error enabling and masking. Using these registers to mask the SSP Interrupt masks both error and functional events since the SSP unit uses this interrupt to signal both error and functional conditions. Logging Details The SINT register from the signal target capability in the PCI configuration header for the SSP unit provides read-only access to the state of the interrupt signals from SSP. SSP does not log additional details on its errors. Reporting Multiple Errors SSP can only generate a single error. The unit can indicate at most one outstanding error at any time. Data Poisoning SSP error conditions result in loss of data and system interrupt. There is no need to poison in these cases. Table 5-32. Summary of Local Expansion Bus Error Conditions Event Type Fatality a a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not. Reports via Notes Parity Error Uncorrectable Fatal LEB Parity Error Interrupt Parity error on outbound read from the EP80579.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 159 Intel® EP80579 Integrated Processor See Section 42.5, “Register Summary”.

5.6.5 IEEE 1588, and GCU

The IEEE 1588 and GCU in the AIOC do not signal any non-functional error conditions. § § Table 5-33. Summary of Local Expansion Bus Error Reporting Capabilities Feature Implementation Enabling and Masking Error Reporting LEB device provides the following registers to support error enabling and masking:

Errors from LEB: EXP_TIMING_CS[0-7]. The SMIA and SMME registers from the signal target capability in the PCI configuration header for the LEB also support error masking and enabling. Logging Details The SINT register from the signal target capability in the PCI configuration header for the LEB provides read-only access to the state of the interrupt signals from the LEB. LEB device captures additional error logging information in the following registers:
LEB parity errors: EXP_PARITY_STATUS. Reporting Multiple Errors LEB device reports additional errors as follows:
LEB errors Data Poisoning LEB pass along error information to poison data.

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6.0 Reset and Power Management

This chapter describes the Intel® EP80579 Integrated Processor reset and power management.

6.1 Reset and Powergood Distribution

This section discusses the detailed sequencing of how power and clocking signals must be applied to bring the EP80579 out of reset.

6.1.1 Types of Reset

The EP80579 has four types of reset: Power-good (cold) reset, Hard reset, CPU-only reset, and Targeted I/O subsystem reset(s). Each of these reset subclasses have unique effects and is described in Table 6-1.

6.1.1.1 Powergood Implementation

The initial boot from when the power supplies are energized is facilitated by the Powergood mechanism. The voltage sources from all platform power supplies are routed to a system component which tracks them as they ramp-up, asserting platform powergood (CPU_VRD_PWR_GD and SYS_PWR_OK) after a fixed interval (nominally 99 ms) after the last voltage reference has stabilized. Powergood signals are propagated asynchronously to dedicated IICH, IMCH, and IA-32 core inputs. Generally, the devices on AIOC fabric including the AIOC reset block do not receive a powergood signal. The Table 6-2 summarizes the power wells and external voltages required by the EP80579. More detailed power supply pin information can be found in Table 6-3. Table 6-1. Types of Reset and Wake-up from Power Saving States Type Mechanism Effect of Reset on following blocks CPU IMCH/ IICH AIOC PCI-E DDR Power-good Input pin Reset Reset Reset Reset Reset Hard Input pin Reset Reset Reset Reset Reset Software (SW) Controlled Write to I/O port CF9 Reset Reset Reset Reset Reset CPU-only Internal to the EP80579. Generated by IMCH Reset -N/A -N/A -N/A -N/A S3 -> S0 Wake Event Reset Reset Reset Reset -N/A S4/S5->S0 Wake Event Reset Reset Reset Reset Reset

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6.1.1.2 Hard Reset Implementation

A hard reset is initiated by the IICH via the PLTRST# as a result various S-state wake events or other reset signal assertions. PLTRST# is driven to the IMCH and is propagated from there to the reset block for AIOC fabric. The reset block in the AIOC fabric is responsible for resetting the individual blocks. IMCH propagates a hard reset to the FSB and subordinate PCI Express* subsystems. The FSB components are reset via the CPURST# (internal signal) signal, while the PCI Express* subsystems through PCIRST#.

6.1.1.3 Software Controlled Reset

Software may cause a full system reset through a write to the Reset Control Register located at I/O port CF9. See also Section 6.1.1.4, “CPU Only Reset Implementation” for software controlled CPU only reset mechanisms.

6.1.1.4 CPU Only Reset Implementation

For power management, error conditions and other reasons, the EP80579 supports a targeted CPU only reset semantic. This mechanism eliminates system reset at large when the CPU function (such as clock gearing selection) must be updated during initialization. It only affects the IA-32 core. Other blocks such as IICH, IMCH, AIOC complex are not reset. It is controlled by IMCH. The IA-32 core can also be reset via the assertion of its INIT# pin which may be accomplished by several conditions including a software write to the Reset Control Register in IICH. Asserting the INIT# pin on the IA-32 core invokes a response similar to that of asserting CPURST#. The major difference is that during an INIT, the internal caches, MSRs, MTRRs, and FPU state are left unchanged (although, the TLBs and BTB are invalidated as with a hardware reset). When INIT is signaled while the processor is in virtual-8086 mode, the processor leaves virtual-8086 mode and enters real-address mode. An INIT provides a method for switching from protected to real-address mode while maintaining the contents of the internal caches. Table 6-2. Power Wells and External Voltages Power Well Nominal Voltage Components Core 1.0-1.3 V IA Processor: IA-CPU

1.2 V Core Logic (IMCH, IICH, ASU, SSU, TDM, GbE MAC1, GbE MAC2), SATA pads, PCI-E

pads, Local Expansion Bus 1.8 V PCI-E PLL, DDR2 pads. Note: 0.9V are generated from 1.8V

2.5 V RMII/RGMII

3.3 V SATA, PCI-E

5.0V 5V tolerance reference Suspend

1.2 V IICH, USB pads, DDR2 core logic, GbE MAC0, USB core logic and pads

3.3 V USB pads, RMII/RGMII pads

5.0V 5V sustain reference RTC 3.3 V RTC

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6.1.1.5 S-state Wake Events

Wake events for the various ACPI sleep states cause a hard reset to the EP80579 (See Section 27.6.3, “Exiting Sleep States” ). Wake on LAN, supported by the GbE MACs, leverages mechanisms provided for GPI and PME wake events.

6.1.1.6 Targeted Reset Implementation

The targeted reset is provided for hot-plug events, as well as for port specific error handling under MCA or SMI software control. A targeted reset may be requested by setting bit six (Secondary Bus Reset) of the Bridge Control register (D2, F0, offset 3Eh) in the target root port device. Setting this bit crashes the Link Training and Status State machine (LTSSM) of the target port to the reset state, where it issues at least 1024 TS1 ordered sets with the reset bit asserted. This propagates an in-band “hot” reset to the downstream device, and consequently force an equivalent reset to any devices further downstream. This reset is identical to a general hard reset from the perspective of destination PCI Express* device.

6.1.2 Platform Reset and Powergood

This section describes the reset and powergood external platform interfaces.

6.1.2.1 Platform Powergood

The EP80579 receives two powergood signals from the platform. The first is CPU_VRD_PWR_GD and the other is SYS_PWR_OK. SYS_PWR_OK is asserted after a fixed delay from the time that CPU_VRD_PWR_GD goes active and indicates that power has been stable for at least 99 ms. The EP80579 inputs PWRGD, PWROK, and SYS_PWR_OK are connected to the SYS_PWR_OK platform signal. CPU_VRD_PWR_GD and SYS_PWR_OK distribution inside the EP80579 is discussed in Section 6.1.2.3, “Reset and Powergood Distribution”. Refer to Figure 6-1 for the block diagram showing CPU_VRD_PWR_GD and SYS_PWR_OK interfaces.

6.1.2.2 Platform Reset

The EP80579 receives two reset signals from the platform. The first one is SYS_RESET which includes the reset button on the platform. The second is Resume Reset which is used for resetting the IICH resume well after power is restored from a power failure. Reset distribution inside the EP80579 is discussed in Section 6.1.2.3, “Reset and Powergood Distribution”. Refer to the Figure 6-1, for a block diagram showing the reset interface.

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6.1.2.3 Reset and Powergood Distribution

The EP80579 reset follows a general path through the IICH to the IMCH and out to the rest of the chip.

6.1.2.3.1 IICH

IICH plays the central role in reset and powergood distribution to the whole chip. IICH receives two powergood signals from the platform (CPU_VRD_PWR_GD and SYS_PWR_OK). The assertion of these signals starts the reset sequence for the EP80579. IICH generates the central reset signal (known as PLTRST#) that initiates the reset of the rest of the chip. PLTRST# is received by IMCH. IICH also generates PCIRST# signal for resetting the PCI device. PCIRST# is similar to PLTRST# except that PCIRST# can be asserted using a CSR. IICH also generates the powergood (CPUPWRGD#) signal for IA-32 core. Figure 6-1. Powergood and Reset Interface EP80579 WDT_NPWRBTN_N RSMRST_N SYS_REST_N PCIRST_N PLTRST_N PWROK VRMPWRGD PWRGD RSTIN_N NC8 RTEST_N PWRON_BTN FP_PWRON# RTCRST# RTC RESET_BTN FP_RESET# RSMRST# GLUE 4 CPU_VRD_PWR_GD SYS_PWR_OK FWH LAI SIO LPC P80 PCI-E x4 conn PCI-E x8 conn ITP/XDP SYS_PWR_OK GBE_AUX_PWR_GOOD GBE_PME_WAKE GBE_aux_pwr_good Wake signal TPM 1.0V/1.3V IA-32 core Ready CK410 2.5V for GbE 1.2V Logic Core Ready SILVERBOX_PWROK GBE Powergood 2ms Delay 100ms Delay PWRGD DDR2 1.8V PME_N 0 ohm empty PCI-E switch Vccsus25 2.5V Vccpsus 3.3V Vccsus1 1.2V EN EN DB800 inverter VSBY3_3

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 165 Intel® EP80579 Integrated Processor IICH Signals Inputs VRMPWRGD - Voltage Regulator PowerGood: This signal is directly connected to the platform signal, CPU_VRD_PWR_GD and signifies that the voltage regulator is stable. PWROK - IICH Power Okay: This signal is directly connected to the platform signal, SYS_PWR_OK. When asserted, PWROK is an indication to the IICH that power has been stable for at least 99 ms and that PCICLK has been stable for at least 1 mS. PWROK can be driven asynchronously. When PWROK is inactive, the IICH asserts PLTRST#. SYS_RESET# - System Reset: This signal initiates a system reset and causes PLTRST# to go active. SYS_RESET# must be asserted for at least 100ms. System reset cannot occur again until SYS_RESET# has been detected inactive, and the system is back to a full S0 state with PLTRST# inactive. If bit 3 of the Reset Control Register is set then the assertion of SYS_RESET# will result in a full power cycle reset. RSMRST# - Resume Well Reset: This signal resets the IICH resume power plane logic when power is reapplied after a power failure. If the AFTERG3_EN bit in the General Power Management Configuration 3 Register (D31 F0 Offset A4) is set to 0, IICH transitions the system from G3 (mechanical off) to S0 state and causes the assertion of the PLTRST# output. If AFTERG3_EN is 1, the system will transition to S5 state. RTEST# - RTC Well Test: This signal is tied to the platform RTCRST# signal. Normally it is held high (to VccRTC), but can be driven low on the tester or motherboard to test the RTC well. RTEST# resets some bits in the RTC well that are otherwise not reset by PLTRST# or RSMRST#. An external RC circuit on the RTCRST# signal creates a time delay such that RTCRST# will go high some time after the battery voltage is valid. The RC time delay must be in the 10-20 ms range. This allows detection when a new battery has been installed. Unless entering a XOR Chain test mode, the RTEST# input must always be high when all other non-RTC power planes are on. Outputs CPUPWRGD - CPU PowerGood: This signal is the logical AND of the IICH VRMPWRGD and PWROK input signals. This signal is connected to the processor's powergood input to indicate when the processor power is valid. PLTRST# - Platform Reset: This signal is asserted by SYS_RESET#, RSMRESET#, or software. The IICH asserts PLTRST# to reset devices on the platform (e.g., SIO, FWH, LAN, IMCH, IDE, TPM, etc.) during power-up (CPU_PWRGD de-asserted) and when software initiates a hard reset sequence through the Reset Control register. The IICH drives PLTRST# active a minimum of 1 ms when initiated through the Reset Control register. The IICH de-asserts PLTRST# a minimum of 1 ms after CPU_PWRGD is driven high. PCIRST# - PCI Reset: This is the secondary PCI bus reset signal. This signal is asserted a small number of PCI clocks after PLTRST# or can be asserted independently by the Secondary Bus Reset bit.

6.1.2.3.2 IMCH

IMCH plays a crucial role in the reset sequence for IA-32 core. IMCH receives the powergood signal (SYS_PWR_OK) from the platform. The IICH PLTRST# drives the IMCH RSTIN# input. IMCH drives the CPURST# (internal signal) while it is in the reset. IMCH works with IICH to initialize the NSI link between IICH and IMCH. Once the central reset (PLTRST#) is de-asserted, IMCH de-asserts the CPURST# (internal signal).

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IMCH can also configure some aspects of the IA-32 core at Power On. IMCH drives these configuration settings before CPURST# (internal signal) assertion based on the contents of its Power-On Configuration Register (D8, F0, offset C0h). IMCH Signals Inputs PWRGD - IMCH PowerGood: This signal is directly connected to the platform signal, SYS_PWR_OK. When asserted, PWRGD is an indication to the IMCH that power has been stable for at least 99 ms. When PWRGD is inactive, the IMCH asserts its CPURST# (internal signal) outputs. RSTIN# - IMCH Reset: This signal is directly connected to the IICH PLTRST# output. When RSTIN is active, the IMCH asserts its CPURST# (internal signal) output.

6.1.2.3.3 IA-32 core

Early in the cold reset (powergood) sequence, the IA-32 core voltage regulator drives a default voltage to the IA-32 core to read the fuses containing the IA-32 core FSB frequency requirements. The EP80579 then drives its BSEL pin to the appropriate value which is latched by the platform when it is known to be stable. The platform uses the BSEL information to update the IA-32 core voltage regulator to the appropriate operating voltage prior to the assertion of CPU_VRD_PWR_GD. The platform also uses the value of BSEL to drive the clock generator to the correct reference clock (BCLK) frequency. Reset and configuration for IA-32 core is done by IICH and IMCH. Reset for IA-32 core starts when IMCH asserts CPURST# (internal signal) and IICH asserts CPUPWRGD. The assertion of both of these signals initiates the PLL locking process for the IA-32 core. All the flops and internal states are reset during the reset process. The processor’s PLL locks before CPURST# (internal signal) is de-asserted. CPURST# (internal signal) needs to be asserted for at least 1ms and not more than 10ms (processor spec).The IA-32 core receives power-on configuration values on its address pins during CPURST# (internal signal).

6.1.2.3.4 IMCH

The IMCH receives the central reset (PLTRST#) from IICH. Clocks to DIMMs are disconnected till BIOS configures the DIMMs. Memory controller core logic boots at the default frequency as driven by the BSEL pin. Based on the DDR type and frequency memory controller needs to re-lock itself at the DDR frequency once BIOS has read the DDR.

6.1.2.3.5 GbE MAC

There are three GbE MAC devices. Each GbE receives the internal system reset. Each GbE also receives a power OK signal from the platform that is also used as a reset. GbE0 receives this signal via the GBE_AUX_PWR_GOOD external pin. GbE1 and GbE2 receive this signal via the SYS_PWR_OK external pin. The SYS_PWR_OK pin is connected to the SYS_PWR_OK platform signal which is also connected to the PWROK and PWRGD pins. The GBE_AUX_PWR_GOOD pin should be connected to SYS_PWR_OK when no auxiliary power supply is used. If an auxiliary supply is used for GbE0, then GBE_AUX_PWR_GOOD should be connected to the power good signal from that power supply (this signal is subject to the timing requirements documented in Figure 6-4, “Power Rail Sequence Timings (Sustain Well Power Management)” on page 170). Under all circumstances, GbE0 MUST be powered by either the system supply or the auxiliary supply. Likewise, GBE_AUX_PWR_GOOD MUST be connected to the corresponding power good signal. GbE0 must be powered to enable operation of either GbE1 or GbE2.

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6.1.3 EP80579 Power Sequencing and Reset Sequence

The following diagrams show the reset sequencing. 1. The EP80579 receives power and drives its BSEL and V_SEL pins. CPU_VRD_PWR_GD, SYS_PWR_OK (platform signals) are not asserted. PLTRST#, and CPURST# (internal signal) are asserted. 2. CPU_VRD_PWR_GD is asserted (Platform signal). Internal signal name is VRMPWRGD. 3. External Reference Clock provided from platform is stable, and is supplied to the EP80579 internal PLLs to generate required internal clocks. Voltage regulator output is modified to correspond to BSEL and V_SEL values. 4. The EP80579 CRU PLL locks. 5. SYS_PWR_OK (platform signal) == PWROK/PWRGD internal signal asserted 6. IO and Core PLLs lock on the CPU. 7. IICH de-asserts PLTRST# 8. IMCH de-asserts udrstb (internal reset unit). All EP80579 blocks except the IA-32 core come out of reset. 9. IMCH de-asserts CPURST# (internal signal) CPU executes the reset micro-code Figure 6-2. Reset Sequence Power Applied to EP80579 Reference Clock Stable (from clock generator) PWROK PWRGD (from platform) CRU Clock PLTRST# de-asserted All the blocks except the IA CPU come out of reset udrst CPURST# de-asserted de-asserted Reset Microcode Execution Re-steer to BIOS Memory Controller Initialization DDR Initialization IICH IMCH CPU EP80579 IMCH (from platform) VRMPWRGD Stable IICH CPU_PWRGD asserted CPU FSB and Core Clocks Stable

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Table 6-3. EP80579 Power Supply Pins Nominal Voltage Voltage Tolerance Package Pin Supply Types Description WELL = CORE

0.9 V (DDR2) +/-5% VTTDDR DDR DDR termination voltage

1.0V@600MHz 1.3V@1066/ 1200MHz +/-2% VCCVC IA-32 core IA-32 core power

1.2 V +/-5%

VCCA[1] IA-32 core IA-32 core PLL1 power VCCA[2] IA-32 core IA-32 core PLL2 power VCC CRU, CRU_PAD, DDR, Expansion, Bus, GBE, IMCH_PAD, MISC IO, PCI, Express, SATA Core power VCCUSB12 USB2 Digital power VCCAUSB12 USB2 Analog power VCCAHPLL CRU Analog PLL power VCCAPE0PLL12 PCI-Express PLL digital power VCCAPLL SATA Analog PLL power VCCAPE PCI-Express Receiver analog power VCCAPE PCI-Express Receiver analog power VCCAPE PCI-Express Transmitter analog power VCCARX SATA Analog receiver power VCCATX SATA Analog transmitter power VCCRPE PCI-Express Receiver digital power VCCSATA SATA SATA power

1.8 V (DDR2) +/-5%

VCCTMP18 Thermal Sensor Thermal sensor power VCCAPE0PLL18 PCI-Express PLL VRM power

2.5 V +/-5% VCC25 GBE GBE IO

3.3 V +/-5%

CRU_PAD, Expansion Bus, IMCH_PAD, MISC IO IO power VCCGBE33 GBE 3.3V tolerance reference VCCSATA33 SATA SATA power VCCABG3P3_USB USB2 Analog bandgap power VCCABGP033 PCI-Express Bandgap analog power VCCASATABG3P3 SATA Analog bandgap power

5 V +/-5% VCC50

Expansion Bus, MISC IO, CRU_PAD, IMCH_PAD 5V tolerance reference WELL = SUSPEND

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 169 Intel® EP80579 Integrated Processor Figure 6-3 illustrates the sequence that power rails should follow as they are brought up at Power On. Figures 6-4, 6-5, 6-6, and 6-7 accompanied by Table 6-4, Table 6-5, and Table 6-6 show the relationship between the power supply rails and key reset signals upon EP80579 power-up. In Figures 6-4 and 6-5, the terms “Core” and “Suspend” refer to the power wells that Table 6-2 on page 162 describes. VCC1P2_USBSUS USB2 1.2V USB sustain power VCCSUS1 IMCH_PAD RTC core sustain power VCCSUS1 GBE Core GBE sustain power

2.5 V +/-5% VCCSUS25 GBE Sustain GBE power

VCCPSUS USB2, IMCH_PAD USB and RTC IO sustain power VCCGBEPSUS GBE Sustain 3.3V tolerance reference

5 V +/-5% VCC50_SUS IMCH_PAD, USB2 5V sustain reference

WELL = RTC 3.3 +/-5% VCCPRTC IMCH_PAD Real Time Clock power Table 6-3. EP80579 Power Supply Pins Nominal Voltage Voltage Tolerance Package Pin Supply Types Description Figure 6-3. EP80579 Rail Power On Sequence Suspend 3. 3V Suspend 5. 0V Suspend 1.2V IA-32 core 1.0V - 1.3V Cor e 3. 3V Cor e 2. 5V Cor e 1. 8V VTTDDR Core 1. 2V Cor e 5. 0V PS_ON# 2 Suspend 2. 5V VCCPRTC 1

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Figure 6-4. Power Rail Sequence Timings (Sustain Well Power Management) VCCPRTC Core 2. 5 V Suspend 3. 3 V RTCRST# RSMRST# t200 t201 Suspend 5 V Core 5 V SYS_PWR _OK Core 3. 3 V Suspend 1. 2 V t205 t204 t209 t213 t202 t212 VRMPWRGD/ CPU_VRD_PWR_GD t 210 IA- 32 core 1.0-1. 3 V Core 1. 2 V t211 Suspend 2. 5 V t203 Core 1. 8 V, VTTDDR t206 GBE_ AUX_ PWR_ GOOD

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 171 Intel® EP80579 Integrated Processor Figure 6-5. Power Rail Sequence Timing (No Sustain Well Power Management) VRMPWRGD/ CPU_VRD_PWR_GD SYS_PWROK GBE_AUX_PWR_GOOD Table 6-4. Power Rail Sequence Signal Timings Sym Parameter Min Max Units Notes t200 VCCPRTC active to RTCRST# inactive 18 – ms t201 Suspend 5 V active to Suspend 3.3 V active 0 – ms 1 t202 Suspend 3.3 V active to Suspend 2.5 V active 0 – ms 2 t203 Suspend 2.5 V active to Suspend 1.2 V active 0 – ms 3 t204 Suspend supplies active to RSMRST# inactive 10 – ms t205 VCCPRTC supply active to Suspend supplies active 0 – ms 4 t209 Core 5 V active to Core 3.3 V active 0 – ms 1 NOTES: 1. The 5 V supply must power up before its associated 3.3 V supply within 0.3 V, and must power down after the 3.3 V supply within 0.3V. 4. The VccSus supplies must never be active while the VCCPRTC supply is inactive. power down before Core 3.3 V or after Core 3.3 V within 0.3 V. down before Core 2.5 V or after Core 2.5 V within 0.3 V.

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t210 Core 3.3 V active to Core 2.5 V active 0 – ms 5 t211 Core 2.5 V active to Core 1.2 V active 0 ms 6 t212 Suspend supplies active to Core supplies active 0 – ms 4 t213 All core supplies active to SYS_PWR_OK (platform signal) active 99 – ms Table 6-4. Power Rail Sequence Signal Timings Sym Parameter Min Max Units Notes NOTES: 1. The 5 V supply must power up before its associated 3.3 V supply within 0.3 V, and must power down after the 3.3 V supply within 0.3V. 4. The VccSus supplies must never be active while the VCCPRTC supply is inactive. power down before Core 3.3 V or after Core 3.3 V within 0.3 V. down before Core 2.5 V or after Core 2.5 V within 0.3 V. Figure 6-6. Powergood Reset Sequence B6548-01 Power Rails BSEL CPU+VRD_PWR_GD/ VRMPWRGD Reference Clock SYS_PWR_OK/ PWROK/PWRGD CPU_PWRGD PLTRST#/RSTIN# PCIRST# CPU Power-On Configuration CPURST# ab c d f i j

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 173 Intel® EP80579 Integrated Processor Table 6-5. Powergood Reset Timings Timing Description Value Tab VRMPWRGD/ CPU_VRD_PWR_GD assertion to Reference Clock Stable 2 ms Tac VRMPWRGD/ CPU_VRD_PWR_GD assertion to SYS_PWR_OK (platform signal) assertion 99 ms Tcd SYS_PWR_OK (platform signal) assertion to CPU_PWRGD assertion (CPU_PWRGD is logical AND of VRMPWRGD/ CPU_VRD_PWR_GD and SYS_PWR_OK) logic delay Tdf CPU_PWRGD assertion to PLTRST# de-assertion 1 ms Tfi RSTIN# deassertion to CPURST# (internal signal) de-assertion 1 ms + CPU_RST_DONE transaction delay (max 10,000 PCI- e clocks) + CPU_RST_DONE capture timer (min 2000 reference clocks) Tij CPURST# (internal signal) de-assertion to POC invalid 2 reference clocks Figure 6-7. Hard Reset Sequence B6549-01 Reference Clock SYS_PWR_OK/PWROK/ PWRGD/CPU_PWRGD SYS_RESET# PLTRST#/RSTIN# CPU Power-On Configuration CPURST# ad g h

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Table 6-6. Hard Reset Timings Timing Description Value Tad Minimum SYS_RESET assertion duration 100 ms Tdg RSTIN# deassertion to CPURST# (internal signal) de-assertion 1 ms + CPU_RST_DONE transaction delay (max 10,000 PCI-e clocks) + CPU_RST_DONE capture timer (min 2000 reference clocks) T gh CPURST# (internal signal) de-assertion to POC invalid 2 reference clocks

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6.2 BIOS Boot Flow (Initialization)

After hardware reset of the EP80579 and once IA -32 core has executed the reset micro-code, the IA 32 core resteers to reset vector (0xFFFF_FFF0) and starts fetching from BIOS code boot rom. BIOS starts execution from the reset vector regardless of whether wake is from S3, S4, or S5. To determine that it is S3 resume, BIOS checks the SUS_TYP field in the power management controller. If it is not S3, then normal boot occurs. If it is S3, then BIOS also checks the power failure bits (PWRBTNOR_STS, PWR_FLR, PWROK_FLR). If these are set to one, then memory contents cannot be relied on and normal boot is followed. If it is an S3 resume and the power failure bits are not set, then the S3 boot path is followed. The normal boot path is that used for cold reset and for S4/S5 resume. From a BIOS perspective there is no difference between S4 and S5. The following steps describe the boot sequence after reset before handover to OS. Figure 6-8. BIOS Boot Flow (Cold Boot, S3/S4->S0) 1) Select BSP Hard Reset This step is automatic and precedes any software influence on chipset configuration. Power-On-Configuration is propagated across the FSB, BREQ0# is asserted to select a boot-strap CPU, and MCH strapping options are sampled. 5) Configure PCI- Express Ports. * For cold reset, BIOS reads the PCI-Express port configuration register and configure ports which are successfully trained. * For S3/S4->S0, BIOS retrieves the expected PCI-Express port configuration from NVRAM/Disk. BIOS must then read the PCI-Express port status registers, configure the ports which successfully trained, and update the MCH configuration map (device present bits) to reflect MCH environment. 3) Initialize Memory * On cold reset, BIOS calibrates and configures IMCH and DDR. BIOS may also run diagnostic tests on populated memory at this point to verify no ill-effects from reset. Initialize all populated memory to all "0"s with good ECC codes. If desired, BIOS may also run diagnostic tests on populated memory at this point to verify no ill-effects from reset. * On S3->S0, BIOS retrieves the prior configuration. 4) Shadow BIOS BIOS copies required BIOS code up from the FWH via ICH to the desired location in main memory. Program the PAM registers to reflect the correct shadowing settings. 6) Enumerate PCI BIOS execute a standard PCI scan in incrementing BUS and DEVICE number order, program primary/secondary/subordinate bus# registers, and aggregate the total memory required for each logical PCI-Express port. At the end of this step, the PCI IO, M, PM, TOLM, and HPCIM registers should be properaly configured to reflect allocated I/O and MMIO space. 8) Interrogate and Clear Error Regs At this point BIOS has access to all the error reporting information in the system. 10) Enable SMM BIOS programs the desired SMM size, location, and configuration. At the end of this step, set the MCH control register bit to lock-down the memory map. This prevents viruses from reprogramming the memory confi guration to compromise SMM space. 9) APIC Configuration BIOS programs the APIC configuration registers in the MCH to allocate message space in the processor/chipset reserved space. Identical configuration must be propagated to all capable expander devices found during enumeration. Pass to OS (cold reset) or context recovery (S3/S4- >S0) 2) Read/Retrieve Memory CFG * On cold reset, BIOS reads the SPD registers in DIMM via SMBus. BIOS finds the DDR type, DDR frequency and configures the gearing ratio. BIOS uses the information to programDRA, DRB, DRC and DRT registers in IMCH. BIOS enables the DDR clock. * On S3->S0, BIOS retrieves the memory table intact from non-volatile memory, and uses that information directly to program DRA, DRB, DRC, and DRT registers. CPU POC

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6.2.1 Memory Configuration

As described in the flow chart, one of the first actions of the BIOS is to configure main memory. This section describes the memory configuration sequence of BIOS. At reset the memory controller disables the output clock reference drivers for all DIMM slots, which prevents them from locking at the wrong frequency, and then relocking after this step in the initialization process. Memory controller core logic boots at a factory set default frequency as is indicated by the BSEL Pin. The BIOS must first set the DDR frequency and ratio via the DRC register because the memory controller needs to re-lock itself at the desired DDR frequency. BIOS configures the DDR frequency by reading the FSB frequency value from a processor internal MSR and DDR2 circuitry and sets the DDR Speed bits [3:0] of the DRC register (d0, f0, offset 7Ch). Once the correct frequencies have been selected BIOS updates CKDIS (d0, f0, offset 8Ch), such that only populated ranks of populated DIMM slots receive output clocks from the memory controller. Using the DDR SPD data, BIOS programs the IMCH DRA and DRB registers for proper translation of physical addresses to DDR row, bank, and column addresses. BIOS further configures the DDR configuration, timing, and impedance compensation settings to enable reliable communication between the IMCH and the DDR DIMM devices. The DRT registers (d0, f0, offsets 78h and 64h) defaults settings can be found in Section 11.0, “System Memory Controller”. BIOS further performs DDR calibration, memory initialization, and optional MemBIST. At this stage BIOS is aware of the total amount of memory populated in the system, and may generate the starting value for the top of memory (TOM) register setting. BIOS will generally want to complete at least a rudimentary memory test sequence (next step) prior to finalizing the memory size information reported to the operating system. For memory initialization details refer to Section 11.0, “System Memory Controller”. Wake from S3/S4/S5 are also described in the Figure 6-8

6.2.2 Memory Initialization

At this point in the boot sequence memory contains random data from power-on, and would therefore generate non-deterministic ECC errors on read accesses. To zero-out memory and initialize all locations with good ECC, the memory controller provides a hardware engine which will walk all populated DRAM space issuing cache-line sized writes with all zeroes as data.

6.2.3 Boot from Network

Booting from network on Intel platforms is supported by PXE. PXE (Preboot eXecution Environment) is an existing open industry specification for network clients to automatically download software images and configuration parameters. The PXE client software is typically implemented as a BIOS Option ROM that is executed during the preboot phase of the client system. This Option ROM (OpROM) implements a sufficient network stack to perform all of the necessary network operations to boot an operating system. This OpROM image is written assuming IA-32 architecture and instruction set. Also, each OpROM image is modified specifically for a given Network Interface Controller (NIC).

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 177 Intel® EP80579 Integrated Processor The BIOS must first establish an environment suitable for execution of the PXE OpROM. This environment must provide the following:

System memory sufficient for C-code execution. This memory will be used to load/ execute OpROM code, implement a call stack and data storage. In addition system memory must be available for loading/execution of OS.
BIOS runtime services sufficient for OpROM execution. These services are typically provided by system BIOS and allow the PXE OpROM to be implemented for platform independence.
The PCI sub-system is enumerated with allocation of system memory space, IO space and interrupts completed. This will establish the address location of resources accessed by the OpROM code during execution. After OpROM initialization, the code remains in memory and waits until the BIOS reaches the point at which the OS-boot process begins. When a GbE is selected for boot, code in the OpROM will be used to initiate communication with a server to supply the images required for boot. After these images are loaded execution control passes from the BIOS to the images loaded in memory. This transition concludes the Preboot phase and enters in to the OS-boot phase.

6.3 Power Management

6.3.1 Power Management States

From a user-visible level, the system can be thought of as being in one of the states shown in Figure 6-9. In general use, computers alternate between the Working and Sleeping states. In the Working state, the computer is used to do work. User-mode application threads are dispatched and running. Individual devices can be in low-power (Dx) states and processors can be in low-power (Cx) states if they are not being used. Figure 6-9. Global System Power States and Transitions

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Any device the system turns off because it is not actively in use can be turned on with short latency. (What “short” means depends on the device. An LCD display needs to come on in sub-second times, while it is generally acceptable to wait a few seconds for a printer to wake.) Precise definitions for Gx, Dx, Sx and Cx states are given in Table 6-7, Table 6-8, Table 6-9, and Table 6-10. Table 6-7. Global Power States Global Power State Description Mechanical Off A computer state that is entered and left by a mechanical means (for example, turning off the system's power through the movement of a large red switch). Various government agencies and countries require this operating mode. It is implied by the entry of this off state through a mechanical means that no electrical current is running through the circuitry and that it can be worked on without damaging the hardware or endangering service personnel. The OS must be restarted to return to the Working state. No hardware context is retained. Except for the real- time clock, power consumption is zero. G2/S5 Soft Off A computer state where the computer consumes a minimal amount of power. No user mode or system mode code is run. This state requires a large latency in order to return to the Working state. The system's context will not be preserved by the hardware. The system must be restarted to return to the Working state. It is not safe to disassemble the machine in this state. G1 Sleeping A computer state where the computer consumes a small amount of power, user mode threads are not being executed, and the system “appears” to be off (from an end user's perspective, the display is off, and so on). Latency for returning to the Working state varies on the wake environment selected prior to entry of this state (for example, whether the system should answer phone calls). Work can be resumed without rebooting the OS because large elements of system context are saved by the hardware and the rest by system software. It is not safe to disassemble the machine in this state. G0 Working A computer state where the system dispatches user mode (application) threads and they execute. In this state, peripheral devices (peripherals) are having their power state changed dynamically. The user can select, through some UI, various performance/power characteristics of the system to have the software optimize for performance or battery life. The system responds to external events in real time. It is not safe to disassemble the machine in this state. Table 6-8. Device States Device State Description D3 Off Power has been fully removed from the device. The device context is lost when this state is entered, so the OS software will reinitialize the device when powering it back on. Since device context and power are lost, devices in this state do not decode their address lines. Devices in this state have the longest restore times. All classes of devices define this state. The meaning of the D2 Device State is defined by each device class. Many device classes may not define D2. In general, D2 is expected to save more power and preserve less device context than D1 or D0. Buses in D2 may cause the device to lose some context (for example, by reducing power on the bus, thus forcing the device to turn off some of its functions). The meaning of the D1 Device State is defined by each device class. Many device classes may not define D1. In general, D1 is expected to save less power and preserve more device context than D2. D0 Fully-On This state is assumed to be the highest level of power consumption. The device is completely active and responsive, and is expected to remember all relevant context continuously.

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6.3.2 Power Management Support

As a system on a chip with embedded I/O devices and many SKUs, the EP80579 power management needs to perform multiple functions (typically under ACPI and/or BIOS system software control):

Minimize power consumption of software-disabled interfaces/units.
Transition between defined ACPI states as defined in Table 6-11.
Support system wake-up from GPIO, PCI Express* devices and GbE MAC ports (Wake-on-LAN). Table 6-9. Sleeping States Sleeping State Description S0 Fully Active S1 The S1 sleeping state is a low wake latency sleeping state. In this state, no system context is lost (CPU or chip set) and hardware maintains all system context. The S2 sleeping state is a low wake latency sleeping state. This state is similar to the S1 sleeping state except that the CPU and system cache context is lost (the OS is responsible for maintaining the caches and CPU context). Control starts from the processor's reset vector after the wake event. The S3 sleeping state is a low wake latency sleeping state where all system context is lost except system memory. CPU, cache, and chip set context are lost in this state. Hardware maintains memory context and restores some CPU and L2 configuration context. Control starts from the processor's reset vector after the wake event. The S4 sleeping state is the lowest power, longest wake latency sleeping state supported by ACPI. In order to reduce power to a minimum, it is assumed that the hardware platform has powered off all devices. Platform context is maintained. S5 Soft Off The S5 state is similar to the S4 state except that the OS does not save any context. The system is in the “soft” off state and requires a complete boot when it wakes. Software uses a different state value to distinguish between the S5 state and the S4 state to allow for initial boot operations within the BIOS to distinguish whether or not the boot is going to wake from a saved memory image. Table 6-10. CPU States Processor Power State Description C0 - Full On Processor core is active. All clocks are running. Processor can maintain cache coherency via snoops. Processor responds to interrupt. C1 - Auto Halt Processor Core is not active after executing an Auto-Halt instruction. Processor Core clock is internally gated. Processor can maintain cache coherency via snoops. Processor responds to interrupts. Aside from putting the processor in a non-executing power state, this state has no other software-visible effects. C2 - Stop Grant Processor Core is not active after its STPCLK# input is asserted. Processor Core clock is internally gated. Processor can maintain cache coherency via snoops. Processor responds to interrupts. Aside from putting the processor in a non-executing power state, this state has no other software-visible effects. C3 - Deep Sleep Processor Core is not active after its SLP# input is asserted. Processor Core clock is gated and PLLs are disabled. Processor does not respond to snoops or interrupts. While in the C3 state, the processor's caches maintain state but ignore any snoops. The operating software is responsible for ensuring that the caches maintain coherency. The EP80579 does not support C3 while functioning in S0 state, however, while in S1 state, The EP80579 will put the processor in Deep Sleep state through the assertion on the SLP# signal.

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Support cold and warm reset for the whole chip. Table 6-11. ACPI States ACPI State IICH IMCH IA-32 core AIOC S0 Full On Full On C0, C1, C2 Full On S1 Full On Full On Deep Sleep Full On S2 Not Supported Not Supported Not Supported Not Supported S3-hot Not Supported Not Supported Not Supported Not Supported S3-cold (Suspend To RAM) Sections stay on, Standby wells DDR IO Power on but interface not active Power Down D3 (Stop Clock and Power Down, Except GbE MAC Wake-on LAN) (Suspend To Disk) Sections stay on, Standby wells Sections stay on, Standby wells Power Down Power Down S5 Soft Off Sections stay on, Standby wells Sections stay on, Standby wells Power Down Power Down Table 6-12. Power Wells Status for Su pported ACPI States* (Sheet 1 of 2) Power Well Supply Pin(s) S0 S1 S3-cold S4 S5 Core VTTDDR On On On a Off Off VCCVC VCCA[1] VCCA[2] On On Off Off Off VCC VCCUSB12 VCCAUSB12 VCCAHPLL VCCAPE0PLL12 VCCAPLL VCCAPE VCCARX VCCATX VCCRPE VCCSATA On On Off Off Off VCC18 VCCTMP18 VCCAPE0PLL18 On On On b Off Off VCC25 On On Off Off Off VCC33 VCCGBE33 VCCSATA33 VCCABG3P3_USB VCCABGP033 VCCASATABG3P3 On On Off Off Off VCC50 On On Off Off Off

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6.3.2.1 Transitioning Between Power States

The EP80579 uses a cooperative power-down that is driven by software. To transition from S0 into the S3 or S4 state under ACPI/BIOS/OS/device driver control, system software is required to: 1. Suspend acceleration and security service application-level threads. 2. Place ASU and SSU devices into quiescent idle state, by completing all outstanding work requests, saving internal state to memory, then disabling ASU/SSU interrupts. 3. Quiesce I/O interfaces by disabling Rx of new traffic, finalizing outstanding Tx operations, disabling interrupts, and saving snap-shot of internal state to memory. 4. Save internal IMCH and IICH state to memory. 5. If transitioning to S4, move DRAM image to disk. 6. Drain all outstanding IMCH updates to DRAM. 7. Signal IICH to power-down the IA-32 core, the AIOC, the IMCH and the IICH. In case of S3, the memory interface is placed into self-refresh mode. In S3/S4 state, the GbE MAC, GPIO and LPC interfaces remain powered to process wake events. An external wake event from GPIO, GbE MAC (received Wake-on-LAN packet) or PCI Express* signals the IICH to initiate a complete reset sequence that transitions the EP80579 back into the S0 state as follows: 1. All internal states outside of the IICH Resume Well are fully reset. 2. On resume from S3, BIOS does not reinitialize memory. Please refer to Section 6.2, “BIOS Boot Flow (Initialization)” for details. 3. On resume from S3 or S4, all EP80579 device drivers (including ASU and SSU drivers) are expected to restore internal device state from their memory resident save area. 4. On resume from S3 or S4, resume acceleration and security service application- level threads. Note: There is no support for wake from USB when in S3/S4/S5.

6.3.2.2 Power State Transition Timing Diagrams

For power state transition timing details, refer to Section 49.5.1.2, “Power Management AC Characteristics”. Suspend VCC1P2_USBSUS VCCSUS1 On On On On On VCCSUS25 On On On On On VCCPSUS VCCGBEPSUS On On On On On VCC50_SUS On On On On On R T C V C C P R T C O nO nO nO nO n a. VTTDR, can optionally be powered off during S3, but typically is derived from and tracks DDR IO voltage, VCC18, to avoid the complexity involved in timing the VTTDDR power up with the exit of S3. b. VCCTMP18 and VCCAPE0PLL18 can optionally be powered off in S3 state. They are feed areas that consume very little power and are grouped with VCC18, which must be on in S3, to avoid requiring an additional power supply to support them. Table 6-12. Power Wells Status for Supported ACPI States* (Sheet 2 of 2) Power Well Supply Pin(s) S0 S1 S3-cold S4 S5

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6.3.3 Thermal Sensor

The EP80579 has an on-die thermal sensor. It helps to control the silicon temperature by monitoring the silicon thermal status and activating the thermal control sequence when the silicon reaches its maximum operating temperature. See Chapter 50.0, “Thermal Specifications and Design Considerations” for details.

6.3.4 ACPI Implementation

The PCI device tree for the EP80579 is shown in Figure 3-4, “Overview of PCI infrastructure for On-die Devices” on page 121. The EP80579 follows the ACPI specification (http://www.acpi.info/DOWNLOADS/ACPIspec30a.pdf) which implies that all the PCI devices implement the standard PCI/ACPI registers: 1. PCI Power Management Block 2. Capability ID 3. Next Item Pointer 4. Power Management Capabilities (PMC) 5. Power Management Control and Status Register (PMCSR) § §

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7.0 Register Summary

7.1 Overview of Register Descriptions and Summaries

This chapter presents summary tables for the registers and MMIO spaces that the components of the EP80579 define. In addition, this chapter describes how to read the standard register description that is used throughout this document to describe the functionality of individual registers. The register summaries in this document follow a general formatting structure that includes, for each register, its name, default value, offsets, and a cross-reference to its detailed register description. Locations that are not associated with a register in the summary table should be assumed to be reserved. The summaries in this chapter are organized by functional unit and describe the EP80579 registers that are visible from the IA platform perspective (e.g., PCI registers, PCI memory-mapped I/O registers, fixed IA I/O space registers, etc.).

7.1.1 Register Description Tables

In addition to the summaries in this chapter, this document uses a standard tabular format to describe the operation of each register in the device. These descriptions are cross-referenced from summary tables and cover the specific content and functionality of a register. The information in a register description table can be broken down into three major areas:

Materialization information that establishes how the register appears to software.
Global information that lists the size, default, value, power well, etc. for the register.
Field definitions that list the name, description, default value, and attributes of all the fields in the register. The register definition can describe a unique register entity in the design or serve as a template that describes several register entities are instantiated in the design. The materialization information in the register description table can handle common scenarios with minimal duplication of content:
A single physical register that materializes at multiple “addresses” in the system (i.e., a double- or triple-mapped register).
Multiple physical registers that share the same definition but materialize within different “device” instances.
Multiple physical registers that share the same definition but materialize repeatedly within a single “device”. The register description table format handles the first two scenarios through “views” that make up the bulk of the materialization information in a register description table and handles the final scenario through a set of “repeated register” conventions.

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The materialization information in a table includes specification of one or more “views”. Each view consists of a view “type” along with several type-specific fields that serve to specify the “address” of the register in the system from a particular perspective. For example, a PCI “view” includes, in part, the PCI bus number as a parameter since this information is necessary to specify the location of the register. In a register description table, each view specification occupies one row of the table. A register description table includes one or more views depending on how the register materializes to software. There are a number of different views that this document uses to describe how EP80579 registers materialize to software. Table 7-1 defines the views that this document uses along with the type-specific fields that each view includes. Table 7-1. Definition of the Views Used in Register Description Tables View Type Describes Registers in Type-Specific Fields Name Description PCI PCI configuration space or memory/ IO spaces that are mapped via PCI BARs B:D:F PCI Bus, Device, and Function number that the register is associated with through PCI configuration, memory-mapped, or I/O-mapped spaces (see BAR). BAR PCI base address register in B:D:F that the register is referenced from. This field is “Configuration” for registers that materialize in PCI configuration space. Otherwise, the field is the name of the BAR register in B:D:F that provides the base address. The register materializes in memory space unless the BAR field contains “(IO)”; i.e., views with a BAR of “FOOBAR” and “FOOBAR (IO)” materialize in memory and I/O spaces, respectively. Offset Start Starting offset from BAR. The offset is in bytes unless the field contains “(2B)”, “(4B)”, and “(8B)” to indicate a single-, double-, or quad-word offset, respectively Offset End Ending offset of register from BAR. The offset is in bytes unless the field contains “(2B)”, “(4B)”, and “(8B)” to indicate a single-, double-, or quad-word offset, respectively IA F General “fixed” location in IA memory or I/O spaces Base Address Base address. Typically, this field contains a number or register name. It may contain a comma-separated list if the register can materialize at one of several possible bases (for example, “100h, 200h based on FOOREG”). The register materializes in memory space unless the base address field contains “(IO)”; i.e., views with a base address of “0000h” and “0000h (IO)” are in memory and I/O space, respectively. Offset Start Starting address or offset from base address field. The offset is in bytes unless the field contains “(2B)”, “(4B)”, and “(8B)” to indicate a single-, double-, or quad-word offset, respectively Offset End Ending address or offset from base address field. The offset is in bytes unless the field contains “(2B)”, “(4B)”, and “(8B)” to indicate a single-, double-, or quad-word offset, respectively

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 185 Intel® EP80579 Integrated Processor The register description tables adopt the convention that Table 7-2 and Table 7-3 describe for view and register name information to distinguish the three scenarios mentioned above (single physical register, multiple physical registers in the same device, and multiple physical registers in different devices). Table 7-2 describes how to interpret the combination of register views and name. This table elides the type-specific fields and simply lists the types of views for brevity. IA I Indirect location accessed via index/window register pair Win:Idx Name of the window and index registers that expose the indirect register(s). For example, W:I of “FOO:BAR” indicates that accesses to FOO indirectly access the register that is located at the index (i.e., offset) in BAR. Offset Start Starting offset to put in the index register to access the indirect register. The index is in bytes unless the field contains “(2B)”, “(4B)”, and “(8B)” to indicate a single-, double-, or quad-word offset, respectivelya. Offset End Ending address or offset from base address field. The offset is in bytes unless the field contains “(2B)”, “(4B)”, and “(8B)” to indicate a single-, double-, or quad-word offset, respectivelya. a. In this usage, words, double words, and quad words are 16-, 32-, and 64-bits, respectively. Table 7-1. Definition of the Views Used in Register Description Tables View Type Describes Registers in Type-Specific Fields Name Description Table 7-2. View Convention to Describe Single Versus Multiple Physical Registers Scenario Register Name Example Views from Register Table Interpretation Single FOO PCI PCI IA F IA F This example shows a single physical register FOO. FOO materializes in two different PCI devices and at two different “fixed” memory locations that the PCI and IA M views describe.

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When describing multiple physical registers of the same “format” that materialize in the same device, the tables use the convention that Table 7-3 describes to denote the offsets1. The remainder of this section presents several examples that illustrates how to read register definition tables. These examples are intended to illustrate how to interpret a register definition table, not describe actual registers in the EP80579. As a result, some of the examples may be contrived from the perspective of an implementation. Multiple (Different Devices, Same name) BAZ PCI 1 PCI 2 IA F 1 IA F 2 All views for the register include a numeric suffix that corresponds to the physical instance of the register. Views with the same suffix address the same physical register. This example shows two physical registers matching the description of BAZ. The first instance of BAZ materializes in the PCI device and at the memory location that the PCI 1 and IA F 1 views describe, while the second instance of BAZ materializes in PCI 2 and at IA F 2. Multiple (Different Devices and Names) BAZ{2:0} PCI 0 PCI 1 PCI 2 IA F 0 IA F 1 IA F 2 Like the Multiple scenario above, the views also include a numeric suffix that, in this case, maps to different register names. The {m:n} notation in the register name indicates that each physical instance of the register has a different name that includes the instance number. An instance number i is an integer such that . This implies that there are m - n + 1 distinct instances of the register. This example shows three physical registers matching the description of BAZ: BAZ0, BAZ1, and BAZ2. BAZ0 materializes in the PCI device and at the memory location that the PCI 0 and IA F 0 views describe, BAZ1 materializes in PCI 1 and at IA F 1, and BAZ2 materializes in PCI 2 and at IA F 2. Multiple (Same Device) BLEH[1-3] PCI PCI IA F IA F The register name has a suffix indicating the number of physical instances of the register. The format of the suffix is “[m-n]” where m and n are integers and implies that there are n - m + 1 distinct instances of the register. This example shows three physical registers matching the description of BLEH: BLEH[1], BLEH[2], and BLEH[3]. Each register materializes in two different PCI devices and at two different “fixed” memory locations that the PCI and IA M views describe. Table 7-2. View Convention to Describe Single Versus Multiple Physical Registers Scenario Register Name Example Views from Register Table Interpretation nim≤≤ 1. In this scenario, it is the offset that distinguishes the different materialization points of the registers; the remaining view fields should be the same since this scenario applies to registers in the same “device”. Table 7-3. Offset Convention to Describe Multiple Physical Registers in the Same Device Register Name Offset in View(s) (Start or End) Interpretation BLEH[1-3] 10h, 38h, 70h Three BLEH registers whose offsets match the elements of the comma- separated list. The offsets are BLEH[1] = 10h, BLEH[2] = 38h, BLEH[3] = 70h. BAZ[1-2] 103h at 2h Two BAZ registers whose offsets stride by 2h starting from 103h. The offsets are BAZ[1] = 103h, BAZ[2] = 105h.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 187 Intel® EP80579 Integrated Processor Given the conventions outlined above, Table 7-4 presents an example definition for the register EG_SINGLE which corresponds to a single physical register. This register materializes at offset E0h in the configuration space for PCI device 4, at double-word (i.e., 32-bit) offset 100h in the memory region defined by FOOBAR of PCI device 12, and at the fixed offset 0A0h in IA I/O space In the table, the materialization information includes the rows starting with “View” and the title; the field definitions includes all rows below the row starting with “Bit Range”, and the rows beginning “Description” and “Size” encompass the global information. Table 7-5 presents an example definition for the register EG_MULTI_DIFF which corresponds to two physical registers that materialize in different “devices”. The first instance materializes at offset D0h in the configuration space for PCI device 20 and at the fixed offset FFEF01B0h in IA memory space. The second instance materializes at offset D0h in the configuration space for PCI device 21 and at the fixed offset FFEF11C0h in IA memory space. Both registers have the same name, EG_MULTI_DIFF. 1. Recall that offsets are in bytes unless otherwise specified with “(2B)”, “(4B)”, or “(8B)”. Table 7-4. EG_SINGLE: Example Single Register with Different Views Description: A single physical register that materializes at multiple locations. View: PCI BAR: Configuration Bus:Device:Function: 0:4:0 Offset Start: Offset End: E0h E1h View: PCI BAR: FOOBAR Bus:Device:Function: 0:12:0 Offset Start: Offset End: 100h (4B) 101h (4B) View: IA F Base Address: 0000h (IO) Offset Start: Offset End: A0h A1h Size: 16 bit Default: 8086h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 00 MAGIC Magic Stuff: This field contains a magic number, 8086h. 8086h RO Table 7-5. EG_MULTI_DIFF: Example Multiple Registers in Different Devices with Different Views Description: A set of two physical registers that materialize in different devices. View: PCI 1 BAR: Configuration Bus:Device:Function: 0:20:0 Offset Start: Offset End: D0h D3h View: PCI 2 BAR: Configuration Bus:Device:Function: 0:21:0 Offset Start: Offset End: D0h D3h View: IA F 1 Base Address: 00000000h Offset Start: Offset End: FFEF01B0h FFEF01B3h View: IA F 2 Base Address: 00000000h Offset Start: Offset End: FFEF11C0h FFEF11C3h Size: 32 bit Default: DEADBEEFh Power Well: Core, Reset Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 00 BMAGIC Black Magic Stuff: This field contains a magic number. DEADBEEFh RO

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This table illustrates how the global information can be tied to a particular register in multiple register cases. In this table, the first and second instances of EG_MULT_DIFF are in the “Core” and “Reset” power wells, respectively. Typically, this notation is only be used for the power well. It is also possible to incorporate the instance number in the name as Table 7-2 describes. Using the name EG_MULTI{2:1}_DIFF in Table 7-5 would identify two physical registers with different names. The first, EG_MULTI2_DIFF, materializes according to the PCI 2 and IA F 2 views, while the second, EG_MULTI1_DIFF, materializes according to the PCI 1 and IA F 1 views. Table 7-6 presents an example definition for the register EG_MULTI_SAME which corresponds to two physical registers that materialize in the same “device”. The instance EG_MULT_SAME[1] materializes at offset ACE0h in the I/O region defined by BLAHBAR of PCI device 16 and at the fixed offset 100h in IA I/O space. The instance EG_MULT_SAME[2] materializes at offset ACE4h in the I/O region defined by BLAHBAR of PCI device 16 and at the fixed offset 120h in IA I/O space. Note that in this example, the strides do not need to be the same across the different views. Finally, Table 7-7 presents an example definition for the register EG_INDEX which corresponds to a physical registers that materialize indirectly. To access the EG_INDEX register, the starting offset 0100h (in double words of 32-bits) is written to the APIC_IDX index register to select EG_INDEX which is then accessed through the APIC_WND window registers. The offsets should always fit within the index register. Table 7-6. EG_MULTI_SAME[1-2]: Example Multiple Registers in Same Device with Different Views Description: A set of two physical registers that materialize in the same device. View: PCI BAR: BLAHBAR (IO) Bus:Device:Function: 0:16:0 Offset Start: Offset End: ACE0h at 4h ACE3h at 4h View: IA F Base Address: 0000h (IO) Offset Start: Offset End: 100h, 120h 103h, 123h Size: 32 bit Default: DEAD8086h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 00 BRMAGIC Blacker Magic Stuff: This field contains a magic number. DEAD8086h RO Table 7-7. EG_INDEX: Example Single Indexed Register Description: A single indexed register. View: IA I Win:Idx APIC_WND:APIC_IDX Offset Start: Offset End: 0100h (4B) 0100h (4B) Size: 32 bit Default: 0ACEFACEh Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 00 MAGIC Magic Stuff: This field contains a magic number. 0ACEFACEh RO

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7.1.2 Register Field Access Attributes

Table 7-8 describes the register field access attribute acronyms that this document uses in its summaries and descriptions. In some cases, the access attribute for a field may depend on a setting of a fuse or a value in another register. In this case, the access types for the field will be of the form “X or Y”. Readers should consult the description of the field for additional information on the conditions that enable the various access types. For example, a field FOO that is either RO or RW based on the setting of a fuse bit would have an access type of “RO or RW”.

7.1.3 Register Nomenclature and Values

The summary and description tables also include register and field values. In general, a number is given by a string of digits followed by a single-character that identifies the base as decimal, “d”, hexadecimal, “h”, or binary, “b”. Both the digits and base pieces of a number are always case-insensitive 1. That is, beefh and BEEFH represent the same hexadecimal number. A value of 0 (zero) does not require a base character. If a value is non-zero, the default base is assumed to be binary unless stated otherwise. All hexadecimal and decimal numbers must always have a base character. In addition to the legal digits for the base, the digit string can contain “x” to denote undefined values. Typically, Xh is equivalent to XXXXb, XXh is equivalent to XXXXXXXXb. However, a 5-bit wide field that is undefined can be represented as both XXh and XXXXXb; that is, a nibble in a hex representation must be “x” if any of its bits are “x”. Table 7-8. Register Field Access Attributes Attribute Description RV Reserved – A reserved field. RO Read-Only – Software/BIOS can only read this bit. Contents are either hardwired or set by hardware. WO Write-Only – Not supported as a bit. The write causes a hardware event to take place. WRC Write/Read to Clear – Writes and reads clear. See bit descriptions. RC Read to Clear – Cleared automatically when read. RW Read/Write – Software/BIOS can read and write this bit. RWC Read/Write-Clear – Software/BIOS can read this bit and must write to a 1 to clear this bit. RCWC Read-Clear/Write-Clear – Cleared when read or Write one to clear. RW0C Read/Write zero to Clear – Software/BIOS can read this bit, and must write to a 0 to clear this bit. R0/W Read zero/Write – This register will only read 0. Must read register description for write actions. RO/RWC Read only/Read-Write-Clear – Attribute de pendent on configuration. See bit description RS/W1C Read-Set/Write-Clear – Read to set, write 1 to clear RWS Read/Write-Set – Software/BIOS can read this bit and write it to a 1. Hardware clears this bit. RWL Read/Write-Lock – Software/BIOS can read and write this bit. Hardware or another configuration bit can lock this bit and prevent it from being updated. RWO Read/Write-Once – Software/BIOS can read this bit, but can only write this bit once. It is a special form of RWL. Once any byte within a register with RWO bits has been written, the RWO bits are locked and only a reset can clear its contents. Any exceptions are clearly documented. 1. The “suggested” convention is that digits are always upper case while the base is always lower case.

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There are three special values that can be used in place of numbers to indicate cases where the value of a register or field is not fixed at design time and depends on other parameters:

Fuse: The setting of one or more fuses determines the value of the register or field.
Strap: The setting of a strap pin determines the value of the register or field.
Variable: The setting of other on-die state determines the value of the register or field. In these cases, the description of the register or field that is not fixed should contain additional information that describes how the EP80579 arrives at the value. Warning: Address locations that are not listed are considered reserved register locations. Reads to reserved registers may return non-zero values. Writes to reserved locations may cause system failure. 7.1.4 “Sticky” Register Fields For each field in a register, the description tables include an indication of whether or not the bits that make up the field are “sticky” or not. Sticky bits in registers will retain their value across a hard reset. Resetting field in a register that is designated as “sticky” to its default/reset value requires a cold reset. Unless explicitly noted, all register fields are assumed to not be sticky.

7.2 IA-32 core Registers

The IA-32 core registers are described in the related documentation for the Intel® Pentium® M Processor .

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7.3 IMCH and IICH Registers

This section summarizes the registers found in the IMCH and the IICH.

7.3.1 IMCH Registers: Bus 0, Device 0, Function 0

The IMCH includes the registers listed in Table 7-9 through Table 7-11. These registers materialize in PCI configuration and memory (via PCI BAR) spaces. See Section 16.1, “IMCH Registers: Bus 0, Device 0, Function 0”, and Section 16.7, “Memory Mapped I/O for NSI Registers” for detailed discussion of these registers. Table 7-9. Bus 0, Device 0, Function 0: Summary of IMCH PCI Configuration Registers (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID – Vendor Identification Register” on page 391 8086h 02h 03h “Offset 02h: DID – Device Identification Register” on page 391 5020h 04h 05h “Offset 04h: PCICMD: PCI Command Register” on page 392 0006h 06h 07h “Offset 06h: PCISTS: PCI Status Register” on page 393 0010h 08h 08h “Offset 8h: RID - Revision Identification Register” on page 394 Variable 0Ah 0Ah “Offset 0Ah: SUBC - Sub-Class Code Register” on page 394 00h 0Bh 0Bh “Offset 0Bh: BCC – Base Class Code Register” on page 394 06h 0Eh 0Eh “Offset 0Eh: HDR - Header Type Register” on page 395 80h 14h 17h “Offset 14h: SMRBASE - System Memory RCOMP Base Address Register” on page 396 00000000h 2Ch 2Dh “Offset 2Ch: SVID - Subsystem Vendor Identification Register” on page 396 0000h 2Eh 2Fh “Offset 2Eh: SID - Subsystem Identification Register” on page 397 0000h 4Ch 4Fh “Offset 4Ch: NSIBAR - Root Complex Block Address Register” on page 397 00000000h 50h 50h “Offset 50h: CFG0- IMCH Configuration 0 Register” on page 398 0Ch 51h 51h “Offset 51h: IMCH_CFG1 – IMCH Configuration 1 Register” on page 399 00000h 53h 53h “Offset 53h: CFGNS1 - Configuration 1 (Non-Sticky) Register” on page 399 00h 58h 58h “Offset 58h: FDHC - Fixed DRAM Hole Control Register” on page 400 00h 59h 59h “Offset 59h: PAM0 - Programmable Attribute Map 0 Register” on page 401 00h 5Ah 5Ah “Offset 5Ah: PAM1: Programmable Attribute Map 1 Register” on page 402 00h 5Bh 5Bh “Offset 5Bh: PAM2 - Programmable Attribute Map 2 Register” on page 403 00h 5Ch 5Ch “Offset 5Ch: PAM3 - Programmable Attribute Map 3 Register” on page 404 00h 5Dh 5Dh “Offset 5Dh: PAM4 - Programmable Attribute Map 4 Register” on page 405 00h 5Eh 5Eh “Offset 5Eh: PAM5 - Programmable Attribute Map 5 Register” on page 406 00h 5Fh 5Fh “Offset 5FH: PAM6 - Programmable Attribute Map 6 Register” on page 407 00h 9Ch 9Ch “Offset 9Ch: DEVPRES - Device Present Register” on page 408 33h 9Dh 9Dh “Offset 9Dh: EXSMRC - Extended System Management RAM Control Register” on page 409 00h 9Eh 9Eh “Offset 9Eh: SMRAM - System Management RAM Control Register” on page 411 02h 9Fh 9Fh “Offset 9Fh: EXSMRAMC - Expansion System Management RAM Control Register” on page 413 07h

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B8h BBh “Offset B8h: IMCH_MENCBASE: IA/ASU Shared Non-Coherent (AIOC-Direct) Memory Base Address Register” on page 413 000FFFFFh BCh BFh “Offset BCh: IMCH_MENCLIMIT - IA/ASU Shared Non-Coherent (AIOC-Direct) Memory Limit Address Register” on page 414 00000000h C4h C5h “Offset C4h: TOLM - Top of Low Memory Register” on page 415 0800h C6h C7h “Offset C6h: REMAPBASE - Remap Base Address Register” on page 416 03FFh C8h C9h “Offset C8h: REMAPLIMIT – Remap Limit Address Register” on page 416 0000h CAh CBh “Offset CAh: REMAPOFFSET - Remap Offset Register” on page 417 0000h CCh CDh “Offset CCh: TOM - Top Of Memory Register” on page 417 0000h CEh CFh “Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced Configuration Base Address Register” on page 418 E000h D8h D8h “Offset D8h: CACHECTL0 - Write Cache Control 0 Register” on page 418 00h DEh DFh “Offset DEh: SKPD - Scratchpad Data Register” on page 419 0000h F6h F6h “Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register” on page 419 00h 60h at 1h 60h at 1h “Offset 60h: DRB[0-3] - DRAM Row [3:0] Boundary Register” on page 421 ffh 70h at 4h 73h at 4h “Offset 70h: DRA[0-1] - DRAM Row [0:1] Attribute Register” on page 422 00000515h 78h 7Bh “Offset 78h: DRT0 - DRAM Timing Register 0” on page 424 242AD280h 64h 67h “Offset 64h: DRT1 - DRAM timing Register 1” on page 431 12110000h 7Ch 7Fh “Offset 7Ch: DRC - DRAM Controller Mode Register” on page 435 00000002h 84h 87h “Offset 84h: ECCDIAG - ECC Detection/Correction Diagnostic Register” on page 437 00000000h 88h 8Bh “Offset 88h: SDRC - DDR SDRAM Secondary Control Register” on page 439 00000002h 8Ch 8Ch “Offset 8Ch: CKDIS - CK/CK# Clock Disable Register” on page 441 00h 8Dh 8Dh “Offset 8Dh: CKEDIS - CKE Clock Enable Register” on page 442 00h 90h 93h “Offset 90h: SPARECTL - SPARE Control Register” on page 443 00000000h B0h B3h “Offset B0h: DDR2ODTC - DDR2 ODT Control Register” on page 444 00000000h Table 7-9. Bus 0, Device 0, Function 0: Summary of IMCH PCI Configuration Registers (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value Table 7-10. Bus 0, Device 0, Function 0: Summary of IMCH Configuration Registers Mapped Through NSIBAR Memory BAR (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00h 03h “Offset 00h: SNSIVCECH - NSI Virtual Channel Enhanced Capability Header Register” on page 680 04010002h 04h 07h “Offset 04h: NSIPVCCAP1 - NSI Port VC Capability Register 1” on page 680 00000000h 08h 0Bh “Offset 08h: NSIPVCCAP2 - Port VC Capability Register 2” on page 681 00000001h 0Ch 0Dh “Offset 0Ch: NSIPVCCTL - NSI Port VC Control Register” on page 682 0000h 10h 13h “Offset 10h: NSIVC0RCAP - NSI VC0 Resource Capability Register” on page 682 00000001h 14h 17h “Offset 14h: NSIVC0RCTL - NSI VC0 Resource Control Register” on page 683 800000FFh 1Ah 1Bh “Offset 1Ah: NSIVC0RSTS - NSI VC0 Resource Status Register” on page 684 0002h

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 193 Intel® EP80579 Integrated Processor 80h 83h “Offset 80h: NSIRCILCECH - NSI Root Complex Internal Link Control Enhanced Capability Header Register” on page 684 00010006h 84h 87h “Offset 84h: NSILCAP - NSI Link Capabilities Register” on page 685 0003A041h Table 7-10. Bus 0, Device 0, Function 0: Summary of IMCH Configuration Registers Mapped Through NSIBAR Memory BAR (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value Table 7-11. Bus 0, Device 0, Function 0: Summary of IMCH SMRBASE Registers (Sheet 1 of Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: NOTESPAD - Note (Sticky) Pad for BIOS Support Register” on page 601 0000h 02h 03h “Offset 02h: NOTEPAD - Note Pad for BIOS Support Register” on page 601 0000h 40h 43h “Offset 40h: DCALCSR – DCAL Control and Status Register” on page 602 00000000h 44h 47h “Offset 44h: DCALADDR - DCAL Address Register” on page 606 00000000h 48h at 1h 48h at 1h “Offset 48h: DCALDATA[0-71] - DRAM Calibration Data Register” on page 607 00000000h 94h 96h “Offset 94h: RCVENAC - Receiver Enable Algorithm Control Register” on page 611 180810h 98h 9Bh “Offset 98h: DSRETC - DRAM Self-Refresh (SR) Extended Timing and Control Register” on page 611 5c141400h 9Ch 9Ch “Offset 9Ch: DQSFAIL1 - DQS Failure Configuration Register 1” on page 612 00h A0h A3h “Offset A0h: DQSFAIL0 - DQS Failure Configuration Register 0” on page 613 00000000h A4h A7h “Offset A4h: DRRTC00 - Receive Enable Reference Output Timing Control Register” on page 615 06060606h A8h ABh “Offset A8h: DRRTC01 - Receive Enable Reference Output Timing Control Register” on page 616 06060606h C4h C4h “Offset C4h: DRRTC02 - Receive Enable Reference Output Timing Control Register” on page 616 06h B4h B7h “Offset B4h: DQSOFCS00 - DQS Calibration Register” on page 617 00000000h B8h BBh “Offset B8h: DQSOFCS01 - DQS Calibration Register” on page 617 00000000h C6h C6h “Offset C6h: DQSOFCS02 - DQS Calibration Register” on page 618 00h BCh BFh “Offset BCh: DQSOFCS10 - DQS Calibration Register” on page 618 00000000h C0h C3h “Offset C0h: DQSOFCS11 - DQS Calibration Register” on page 619 00000000h C7h C7h “Offset C7h: DQSOFCS12 - DQS Calibration Register” on page 619 00h CCh CFh “Offset CCh: WPTRTC0 - Write Pointer Timing Control Register” on page 620 00000000h D0h D0h “Offset D0h: WPTRTC1 - Write Pointer Timing Control 1 Register” on page 621 00h D4h D7h “Offset D4h: DDQSCVDP0 - DQS Delay Calibration Victim Pattern 0 Register” on page 621 aaaa0a05h D8h DBh “Offset D8h: DDQSCVDP1 - DQS Delay Calibration Victim Pattern 1 Register” on page 622 5b339c5dh DCh DFh “Offset DCh: DDQSCADP0 - DQS Delay Calibration Aggressor Pattern 0 Register” on page 622 aaabffffh E0h E3h “Offset E0h: DDQSCADP1 - DQS Delay Calibration Aggressor Pattern 1 Register” on page 623 db339ce1h F0h F3h “Offset F0h: DIOMON - DDR I/O Monitor Register” on page 623 00000000h

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

194 Order Number: 320066-003US

F8h FBh “Offset F8h: DRAMISCTL - Miscellaneous DRAM DDR Cluster Control Register” on page 624 1011h C8h CAh “Offset C8h: DRAMDLLC - DDR I/O DLL Control Register” on page 625 0DB6C0h E8h EBh “Offset E8h: FIVESREG - Fixed 5s Pattern Register” on page 625 55555555h ECh EFh “Offset ECh: AAAAREG - Fixed A Pattern Register” on page 626 AAAAAAAAh 140h 143h “Offset 140h: MBCSR - MemBIST Control Register” on page 626 00000000h 144h 147h “Offset 144h: MBADDR - Memory Test Address Register” on page 629 00h 148h at 4h 14Ch at 4h “Offset 148h: MBDATA[0:9] - Memory Test Data Register” on page 629 00h 19Ch 19Fh “Offset 19Ch: MB_START_ADDR - Memory Test Start Address Register” on page 632 00h 1A0h 1A3h “Offset 1A0h: MB_END_ADDR - Memory Test End Address Register” on page 632 00h 1A4h 1A7h “Offset 1A4h: MBLFSRSED - Memory Test Circular Shift and LFSR Seed Register” on page 633 00h 1A8h 1ABh “Offset 1A8h: MBFADDRPTR - Memory Test Failure Address Pointer Register” on page 633 00h 1B0h 1B3h “Offset 1B0h: MB_ERR_DATA00 - Memory Test Error Data 0” on page 634 00h 1B4h 1B7h “Offset 1B4h: MB_ERR_DATA01 - Memory Test Error Data 0” on page 634 00h 1B8h 1BBh “Offset 1B8h: MB_ERR_DATA02 - Memory Test Error Data 0” on page 634 00h 1BCh 1BFh “Offset 1BCh: MB_ERR_DATA03 - Memory Test Error Data 0” on page 635 00h 1C0h 1C1h “Offset 1C0h: MB_ERR_DATA04 - Memory Test Error Data 0” on page 635 00h 1C4h 1C7h “Offset 1C4h: MB_ERR_DATA10 - Memory Test Error Data 1” on page 635 00h 1C8h 1CBh “Offset 1C8h: MB_ERR_DATA11 - Memory Test Error Data 1” on page 636 00h 1CCh 1CFh “Offset 1CCh: MB_ERR_DATA12 - Memory Test Error Data 1” on page 636 00h 1D0h 1D3h “Offset 1D0h: MB_ERR_DATA13 - Memory Test Error Data 1” on page 636 00h 1D4h 1D5h “Offset 1D4h: MB_ERR_DATA14 - Memory Test Error Data 1” on page 637 00h 1D8h 1DBh “Offset 1D8h: MB_ERR_DATA20 - Memory Test Error Data 2” on page 637 00h 1DCh 1DFh “Offset 1DCh: MB_ERR_DATA21 - Memory Test Error Data 2” on page 637 00h 1E0h 1E3h “Offset 1E0h: MB_ERR_DATA22 - Memory Test Error Data 2” on page 638 00h 1E4h 1E7h “Offset 1E4h: MB_ERR_DATA23 - Memory Test Error Data 2” on page 638 00h 1E8h 1E9h “Offset 1E8h: MB_ERR_DATA24 - Memory Test Error Data 2” on page 638 00h 1ECh 1EFh “Offset 1ECh: MB_ERR_DATA30 - Memory Test Error Data 3” on page 639 00h 1F0h 1F4h “Offset 1F0h: MB_ERR_DATA31 - Memory Test Error Data 3” on page 639 00h 1F4h 1F7h “Offset 1F4h: MB_ERR_DATA32 - Memory Test Error Data 3” on page 639 00h 1F8h 1FBh “Offset 1F8h: MB_ERR_DATA33 - Memory Test Error Data 3” on page 640 00h 1FCh 1FDh “Offset 1FCh: MB_ERR_DATA34 - Memory Test Error Data 3” on page 640 00h 260h 263h “Offset 260h: DDRIOMC0 - DDRIO Mode Register Control Register” on page 641 00000078h 264h 267h “Offset 264h: DDRIOMC1 - DDRIO Mode Register Control Register 1” on page 642 52520000h 268h 26Bh “Offset 268h: DDRIOMC2 - DDRIO Mode Control Register 2” on page 645 039E6000h 284h at 4h 294h at 4h “Offset 284h: WL_CNTL[4:0] - Write Levelization Control Register” on page 647 00000000h 298h 29Bh “Offset 298h: WDLL_MISC - DLL Miscellaneous Control” on page 649 00000000h Table 7-11. Bus 0, Device 0, Function 0: Summary of IMCH SMRBASE Registers (Sheet 2 of Offset Start Offset End Register ID - Description Default Value

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 195 Intel® EP80579 Integrated Processor

7.3.2 IMCH Error Reporting Registers: Bus 0, Device 0, Function 1

The IMCH includes the registers listed in Table 7-12. These registers materialize in PCI configuration space. See Section 16.2, “DRAM Controller Error Reporting Registers: Bus 0, Device 0, Function 1” for detailed discussion of these registers. Table 7-12. Bus 0, Device 0, Function 1: Summary of IMCH Error Reporting PCI Configuration Registers (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID - Vendor Identification Register” on page 447 8086h 02h 03h “Offset 02h: DID - Device Identification Register” on page 447 5021h 04h 05h “Offset 04h: PCICMD - PCI Command Register” on page 448 0000h 06h 07h “Offset 06h: PCISTS - PCI Status Register” on page 448 0000h 08h 08h “Offset 08h: RID - Revision Identification Register” on page 449 Variable 0Ah 0Ah “Offset 0Ah: SUBC - Sub-Class Code Register” on page 449 00h 0Bh 0Bh “Offset 0Bh: BCC - Base Class Code Register” on page 449 FFh 0Dh 0Dh “Offset 0Dh: MLT - Master Latency Timer Register” on page 450 00h 0Eh 0Eh “Offset 0Eh: HDR - Header Type Register” on page 450 00h 2Ch 2Dh “Offset 2Ch: SVID - Subsystem Vendor Identification Register” on page 450 0000h 2Eh 2Fh “Offset 2Eh: SID - Subsystem Identification Register” on page 451 0000h 40h 43h “Offset 40h: GLOBAL_FERR - Global First Error Register” on page 451 00000000h 44h 47h “Offset 44h: GLOBAL_NERR - Global Next Error Register” on page 453 00000000h 48h 4Bh “Offset 48h: NSI_FERR - NSI First Error Register” on page 454 00000000h 4Ch 4Fh “Offset 4Ch: NSI_NERR - NSI Next Error Register” on page 457 00000000h 50h 53h “Offset 50h: NSI_SCICMD - NSI SCI Command Register” on page 459 00000000h 54h 57h “Offset 54h: NSI_SMICMD: NSI SMI Command Register” on page 461 00000000h 58h 5Bh “Offset 58h: NSI_SERRCMD - NSI SERR Command Register” on page 464 00000000h 5Ch 5Fh “Offset 5Ch: NSI_MCERRCMD - NSI MCERR Command Register” on page 466 00000000h 60h 61h “Offset 60h: FSB_FERR - FSB First Error Register” on page 468 0000h 62h 63h “Offset 62h: FSB_NERR - FSB Next Error Register” on page 469 0000h 64h 65h “Offset 64h: FSB_EMASK - FSB Error Mask Register” on page 470 0009h 68h 69h “offset 68h: FSB_SCICMD - FSB SCI Command Register” on page 471 0000h 6Ah 6Bh “Offset 6Ah: FSB_SMICMD - FSB SMI Command Register” on page 472 0000h 6Ch 6Dh “Offset 6Ch: FSB_SERRCMD - FSB SERR Command Register” on page 473 0000h 6Eh 6Fh “Offset 6Eh: FSB_MCERRCMD - FSB MCERR Command Register” on page 474 0000h 70h 70h “Offset 70h: BUF_FERR - Memory Buffer First Error Register” on page 475 00h 72h 72h “Offset 72h: BUF_NERR - Memory Buffer Next Error Register” on page 475 00h 74h 74h “Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register” on page 476 00h 78h 78h “Offset 78h: BUF_SCICMD - Memory Buffer SCI Command Register” on page 477 00h 7Ah 7Ah “Offset 7Ah: BUF_SMICMD - Memory Buffer SMI Command Register” on page 478 00h 7Ch 7Ch “Offset 7Ch: BUF_SERRCMD - Memory Buffer SERR Command Register” on page 479 00h

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

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7Eh 7Eh “Offset 7Eh: BUF_MCERRCMD - Memory Buffer MCERR Command Register” on page 480 00h E4h E7h “Offset E4h: NSIERRINJCTL - NSI Error Injection Control Register” on page 481 00040000h E8h EBh “Offset E8h: BERRINJCTL - Buffer Error Injection Control Register” on page 482 00000000h 80h 81h “Offset 80h: DRAM_FERR - DRAM First Error Register” on page 483 0000h 82h 83h “Offset 82h: DRAM_NERR - DRAM Next Error Register” on page 484 0000h 84h 84h “Offset 84h: DRAM_EMASK - DRAM Error Mask Register” on page 486 00h 88h 88h “Offset 88h: DRAM_SCICMD - DRAM SCI Command Register” on page 487 00h 8Ah 8Ah “Offset 8Ah: DRAM_SMICMD - DRAM SMI Command Register” on page 488 00h 8Ch 8Ch “Offset 8Ch: DRAM_SERRCMD - DRAM SERR Command Register” on page 489 00h 8Eh 8Eh “Offset 8Eh: DRAM_MCERRCMD - DRAM MCERR Command Register” on page 490 00h 98h 99h “Offset 98h: THRESH_SEC0 - Rank 0 SEC Error Threshold Register” on page 491 0000h 9Ah 9Bh “Offset 9Ah: THRESH_SEC1 - Rank 1 SEC Error Threshold Register” on page 491 0000h A0h A3h “Offset A0h: DRAM_SECF_ADD - DRAM First Single Bit Error Correct Address Register” on page 492 00000000h A4h A7h “Offset A4h: DRAM_DED_ADD - DRAM Double Bit Error Address Register” on page 492 00000000h A8h ABh “Offset A8h: DRAM_SCRB_ADD - DRAM Scrub Error Address Register” on page 493 00000000h B0h B1h “Offset B0h: DRAM_SEC_R0 - DRAM Rank 0 SEC Error Counter Register” on page 494 0000h B2h B3h “Offset B2h: DRAM_DED_R0 - DRAM Rank 0 DED Error Counter Register” on page 494 0000h B4h B5h “Offset B4h: DRAM_SEC_R1 - DRAM Rank 1 SEC Error Counter Register” on page 494 0000h B6h B7h “Offset B6h: DRAM_DED_R1 - DRAM Rank 1 DED Error Counter Register” on page 495 0000h C2h C3h “Offset C2h: THRESH_DED - DED Error Threshold Register” on page 495 0000h C4h C5h “Offset C4h: DRAM_SECF_SYNDROME - DRAM First Single Error Correct Syndrome Register” on page 496 0000h C6h C7h “Offset C6h: DRAM_SECN_SYNDROME - DRAM Next Single Error Correct Syndrome Register” on page 496 0000h C8h CBh “Offset C8h: DRAM_SECN_ADD - DRAM Next Single Bit Error Correct Address Register” on page 497 00000000h DCh DDh “Offset DCh: RANKTHREX - Rank Error Threshold Exceeded Register” on page 498 0000h ECh EFh “Offset ECh: DERRINJCTL - DRAM Error Injection Control Register” on page 499 00000000h Table 7-12. Bus 0, Device 0, Function 1: Summary of IMCH Error Reporting PCI Configuration Registers (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 197 Intel® EP80579 Integrated Processor

7.3.3 EDMA Engine Registers: Bus 0, Device 1, Function 0

The EDMA engine includes the registers listed in Table 7-13 and Table 7-14. These registers materialize in PCI configuration and memory (via PCI BAR) spaces. See Section 16.3, “EDMA Registers: Bus 0, Device 1, Function 0” and Section 16.6, “Memory Mapped I/O for EDMA Registers” for detailed discussion of these registers. Table 7-13. Bus 0, Device 1, Function 0: Summary of EDMA PCI Configuration Registers Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID - Vendor Identification Register” on page 502 8086h 02h 03h “Offset 02h: DID - Device Identification Register” on page 502 5023h 04h 05h “Offset 04h: PCICMD - PCI Command Register” on page 503 0000h 06h 07h “Offset 06h: PCISTS - PCI Status Register” on page 504 0010h 08h 08h “Offset 08h: RID - Revision Identification Register” on page 504 Variable 0Ah 0Ah “Offset 0Ah: SUBC - Sub-Class Code Register” on page 505 80h 0Bh 0Bh “Offset 0Bh: BCC - Base Class Code Register” on page 505 08h 0Eh 0Eh “Offset 0Eh: HDR - Header Type Register” on page 505 00h 10h 13h “Offset 10h: EDMALBAR - EDMA Low Base Address Register” on page 506 00000000h 2Ch 2Dh “Offset 2Ch: SVID - Subsystem Vendor Identification Register” on page 506 0000h 2Eh 2Fh “Offset 2Eh: SID - Subsystem Identification Register” on page 507 0000h 34h 34h “Offset 34h: CAPPTR - Capabilities Pointer Register” on page 507 B0h 3Ch 3Ch “Offset 3Ch: INTRLINE - Interrupt Line Register” on page 507 00h 3Dh 3Dh “Offset 3Dh: INTRPIN - Interrupt Pin Register” on page 508 01h 40h 40h “Offset 40h: EDMACTL - EDMA Control Register” on page 508 08h 80h 83h “Offset 80h: EDMA_FERR - EDMA First Error Register” on page 509 00000000h 84h 87h “Offset 84h: EDMA_NERR - EDMA Next Error Register” on page 511 00000000h 88h 88h “Offset 88h: EDMA_EMASK - EDMA Error Mask Register” on page 513 00h A0h A0h “Offset A0h: EDMA_SCICMD - EDMA SCI Command Register” on page 514 00h A4h A4h “Offset A4h: EDMA_SMICMD - EDMA SMI Command Register” on page 515 00h A8h A8h “Offset A8h: EDMA_SERRCMD - EDMA SERR Command Register” on page 516 00h ACh ACh “Offset ACh: EDMA_MCERRCMD - EDMA MCERR Command Register” on page 517 00h B0h B3h “Offset B0h: MSICR - MSI Control Register” on page 518 00020005h B4h B7h “Offset B4h: MSIAR - MSI Address Register” on page 519 FEE00000h B8h B9h “Offset B8h: MSIDR - MSI Data Register” on page 520 0000h Table 7-14. Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers Mapped Through EDMALBAR Memory BAR (Sheet 1 of 3) Offset Start Offset End Register ID - Description Default Value 00h 03h “Offset 00h: CCR0 - Channel 0 Channel Control Register” on page 653 00000000h 04h 07h “Offset 04h: CSR0 - Channel 0 Channel Status Register” on page 656 00000000h

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

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08h 0Bh “Offset 08h: CDAR0 - Channel 0 Current Descriptor Address Register” on page 657 00000000h 0Ch 0Fh “Offset 0Ch: CDUAR0 - Channel 0 Current Descriptor Upper Address Register” on page 658 00000000h 10h 13h “Offset 10h: SAR0 - Channel 0 Source Address Register” on page 658 00000000h 14h 17h “Offset 14h: SUAR0 - Channel 0 Source Upper Address Register” on page 659 00000000h 18h 1Bh “Offset 18h: DAR0 - Channel 0 Destination Address Register” on page 659 00000000h 1Ch 1Fh “Offset 1Ch: DUAR0 - Channel 0 Destination Upper Address Register” on page 660 00000000h 20h 23h “Offset 20h: NDAR0 - Channel 0 Next Descriptor Address Register” on page 661 00000000h 24h 27h “Offset 24h: NDUAR0 - Channel 0 Next Descriptor Upper Address Register” on page 662 00000000h 28h 2Bh “Offset 28h: TCR0 - Channel 0 Transfer Count Register” on page 662 00000000h 2Ch 2Fh “Offset 2Ch: DCR0 - Channel 0 Descriptor Control Register” on page 663 00000000h 40h 43h “Offset 40h: CCR1 - Channel 1 Channel Control Register” on page 665 00000000h 44h 47h “Offset 44h: CSR1 - Channel 1 Channel Status Register” on page 665 00000000h 48h 4Bh “Offset 48h: CDAR1 - Channel 1 Current Descriptor Address Register” on page 665 00000000h 4Ch 4Fh “Offset 4Ch: CDUAR1 - Channel 1 Current Descriptor Upper Address Register” on page 666 00000000h 50h 53h “Offset 50h: SAR1 - Channel 1 Source Address Register” on page 666 00000000h 54h 57h “Offset 54h: SUAR1 - Channel 1 Source Upper Address Register” on page 666 00000000h 58h 5Bh “Offset 58h: DAR1 - Channel 1 Destination Address Register” on page 667 00000000h 5Ch 5Fh “Offset 5Ch: DUAR1 - Channel 1 Destination Upper Address Register” on page 667 00000000h 60h 63h “Offset 60h: NDAR1 - Channel 1 Next Descriptor Address Register” on page 667 00000000h 64h 67h “Offset 64h: NDUAR1 - Channel 1 Next Descriptor Upper Address Register” on page 668 00000000h 68h 6Bh “Offset 68h: TCR1 - Channel 1 Transfer Count Register” on page 668 00000000h 6Ch 6Fh “Offset 6Ch: DCR1 - Channel 1 Descriptor Control Register” on page 668 00000000h 80h 83h “Offset 80h: CCR2 - Channel 2 Channel Control Register” on page 669 00000000h 84h 87h “Offset 84h: CSR2 - Channel 2 Channel Status Register” on page 669 00000000h 88h 8Bh “Offset 88h: CDAR2: Channel 2 Current Descriptor Address Register” on page 669 00000000h 8Ch 8Fh “Offset 8Ch: CDUAR2 - Channel 2 Current Descriptor Upper Address Register” on page 670 00000000h 90h 93h “Offset 90h: SAR2 - Channel 2 Source Address Register” on page 670 00000000h 94h 97h “Offset 94h: SUAR2 - Channel 2 Source Upper Address Register” on page 670 00000000h 98h 9Bh “Offset 98h: DAR2 - Channel 2 Destination Address Register” on page 671 00000000h 9Ch 9Fh “Offset 9Ch: DUAR2 - Channel 2 Destination Upper Address Register” on page 671 00000000h A0h A3h “Offset A0h: NDAR2 - Channel 2 Next Descriptor Address Register” on page 671 00000000h A4h A7h “Offset A4h: NDUAR2 - Channel 2 Next Descriptor Upper Address Register” on page 672 00000000h A8h ABh “Offset A8h: DCR2 - Channel 2Transfer Control Register” on page 672 00000000h ACh AFh “Offset ACh: DCR2 - Channel 2 Descriptor Control Register” on page 672 00000000h C0h C3h “Offset C0h: CCR3 - Channel 3 Channel Control Register” on page 673 00000000h C4h C7h “Offset C4h: CSR3 - Channel 3 Channel Status Register” on page 673 00000000h Table 7-14. Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers Mapped Through EDMALBAR Memory BAR (Sheet 2 of 3) Offset Start Offset End Register ID - Description Default Value

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 199 Intel® EP80579 Integrated Processor C8h CBh “Offset C8h: CDAR3 - Channel 3 Current Descriptor Address Register” on page 67300000000h CCh CFh “Offset CCh: CDUAR3 - Channel 3 Current Descriptor Upper Address Register” on page 674 00000000h D0h D3h “Offset D0h: SAR3 - Channel 3 Source Address Register” on page 674 00000000h D4h D7h “Offset D4h: SUAR3 - Channel 3 Source Upper Address Register” on page 674 00000000h D8h DBh “Offset D8h: DAR3 - Channel 3 Destination Address Register” on page 675 00000000h DCh DFh “Offset DCh: DUAR3 - Channel 3 Destination Upper Address Register” on page 675 00000000h E0h E3h “Offset E0h: NDAR3 - Channel 3 Next Descriptor Address Register” on page 675 00000000h E4h E7h “Offset E4h: NDUAR3 - Channel 3 Next Descriptor Upper Address Register” on page 676 00000000h E8h EBh “Offset E8h: TCR3 - Channel 3 Transfer Count Register” on page 676 00000000h ECh EFh “Offset ECh: DCR3 - Channel 3 Descriptor Control Register” on page 677 00000000h 100h 103h “Offset 100h: DCGC - EDMA Controller Global Command” on page 677 00000000h 104h 107h “Offset 104h: DCGS - EDMA Controller Global Status” on page 678 00000000h Table 7-14. Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers Mapped Through EDMALBAR Memory BAR (Sheet 3 of 3) Offset Start Offset End Register ID - Description Default Value

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

200 Order Number: 320066-003US

7.3.4 PCI Express* Port A Registers: Bus 0, Device 2, Function 0

The PCI Express* Port A includes the registers listed in Table 7-15. These registers materialize in PCI configuration spaces. See Section 16.4, “PCI Express* Port A Standard and Enhanced Registers: Bus 0, Devices 2 and 3, Function 0” for detailed discussion of these registers. Table 7-15. Bus 0, Device 2, Function 0: Summary of PCI Express Port A Standard and Enhanced PCI Configuration Registers (Sheet 1 of 3) Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID - Vendor Identification Register” on page 527 8086h 02h 03h “Offset 02h: DID - Device Identification Register” on page 527 5024h 04h 05h “Offset 04h: PCICMD - PCI Command Register” on page 528 0000h 06h 07h “Offset 06h: PCISTS - PCI Status Register” on page 530 0010h 08h 08h “Offset 08h: RID - Revision Identification Register” on page 531 Variable 0Ah 0Ah “Offset 0Ah: SUBC - Sub-Class Code Register” on page 532 04h 0Bh 0Bh “Offset 0Bh: BCC - Base Class Code Register” on page 532 06h 0Ch 0Ch “Offset 0Ch: CLS - Cache Line Size Register” on page 533 00h 0Eh 0Eh “Offset 0Eh: HDR - Header Type Register” on page 533 01h 18h 18h “Offset 18h: PBUSN - Primary Bus Number Register” on page 534 00h 19h 19h “Offset 19h: SBUSN - Secondary Bus Number Register” on page 534 00h 1Ah 1Ah “Offset 1Ah: SUBUSN: Subordinate Bus Number Register” on page 535 00h 1Ch 1Ch “Offset 1Ch: IOBASE - I/O Base Address Register” on page 535 F0h 1Dh 1Dh “Offset 1Dh: IOLIMIT - I/O Limit Address Register” on page 536 00h 1Eh 1Fh “Offset 1Eh: SECSTS - Secondary Status Register” on page 536 0000h 20h 21h “Offset 20h: MBASE - Memory Base Address Register” on page 538 FFF0h 22h 23h “Offset 22h: MLIMIT - Memory Limit Address Register” on page 539 0000h 24h 25h “Offset 24h: PMBASE - Prefetchable Memory Base Address Register” on page 540 FFF1h 26h 27h “Offset 26h: PMLIMIT - Prefetchable Memory Limit Address Register” on page 540 0001h 28h 28h “Offset 28h: PMBASU - Prefetchable Memory Base Upper Address Register” on page 541 0Fh 2Ch 2Ch “Offset 2Ch: PMLMTU - Prefetchable Memory Limit Upper Address Register” on page 541 00h 34h 34h “Offset 34h: CAPPTR - Capabilities Pointer Register” on page 542 50h 3Ch 3Ch “Offset 3Ch: INTRLINE - Interrupt Line Register” on page 542 00h 3Dh 3Dh “Offset 3Dh: INTRPIN - Interrupt Pin Register” on page 543 01h 3Eh 3Eh “Offset 3Eh: BCTRL - Bridge Control Register” on page 543 00h 44h 44h “Offset 44h: VSCMD0 - Vendor Specific Command Byte 0 Register” on page 545 00h 45h 45h “Offset 45h: VSCMD1 - Vendor Specific Command Byte 1 Register” on page 546 00h 46h 46h “Offset 46h: VSSTS0 - Vendor Specific Status Byte 0 Register” on page 547 00h 47h 47h “Offset 47h: VSSTS1 - Vendor Specific Status Byte 1 Register” on page 547 00h 48h 48h “Offset 48h: VSCMD2 - Vendor Specific Command Byte 2 Register” on page 548 00h 50h 50h “Offset 50h: PMCAPID - Power Management Capabilities Structure Register” on page 548 01h

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 201 Intel® EP80579 Integrated Processor 51h 51h “Offset 51h: PMNPTR - Power Management Next Capabilities Pointer Register” on page 549 58h 52h 53h “Offset 52h: PMCAPA - Power Management Capabilities Register” on page 549 C822h 54h 55h “Offset 54h: PMCSR - Power Management Status and Control Register” on page 550 0000h 56h 56h “Offset 56h: PMCSRBSE - Power Management Status and Control Bridge Extensions Register” on page 551 00h 58h 58h “Offset 58h: MSICAPID - MSI Capabilities Structure Register” on page 551 05h 59h 59h “Offset 59h: MSINPTR - MSI Next Capabilities Pointer Register” on page 552 64h 5Ah 5Bh “Offset 5Ah: MSICAPA - MSI Capabilities Register” on page 553 0002h 5Ch 5Fh “Offset 5Ch: MSIAR - MSI Address for PCI Express Register” on page 553 FEE00000h 60h 61h “Offset 60h: MSIDR - MSI Data Register” on page 554 0000h 64h 64h “Offset 64h: PEACAPID - PCI Express Features Capabilities ID Register” on page 555 10h 65h 65h “Offset 65h: PEANPTR - PCI Express Next Capabilities Pointer Register” on page 556 00h 66h 67h “Offset 66h: PEACAPA - PCI Express Features Capabilities Register” on page 556 0041h 68h 6Bh “Offset 68h: PEADEVCAP - PCI Express Device Capabilities Register” on page 557 00000001h 6Ch 6Dh “Offset 6Ch: PEADEVCTL - PCI Express Device Control Register” on page 558 0000h 6Eh 6Fh “Offset 6Eh: PEADEVSTS - PCI Express Device Status Register” on page 560 0000h 70h 73h “Offset 70h: PEALNKCAP - PCI Express Link Capabilities Register” on page 561 0203E481h 74h 75h “Offset 74h: PEALNKCTL - PCI Express Link Control Register” on page 562 0001h 76h 77h “Offset 76h: PEALNKSTS - PCI Express Link Status Register” on page 564 1001h 78h 7Bh “Offset 78h: PEASLTCAP - PCI Express Slot Capabilities Register” on page 565 00000000h 7Ch 7Dh “Offset 7Ch: PEASLTCTL - PCI Express Slot Control Register” on page 568 01C0h 7Eh 7Fh “Offset 7Eh: PEASLTSTS - PCI Express Slot Status Register” on page 569 0040h 80h 83h “Offset 80h: PEARPCTL - PCI Express Root Port Control Register” on page 570 00000000h 84h 87h “Offset 84h: PEARPSTS - PCI Express Root Port Status Register” on page 571 00000000h 100h 103h “Offset 100h: ENHCAPST - Enhanced Capability Structure Register” on page 571 00010001h 104h 107h “Offset 104h: UNCERRSTS - Uncorrectable Error Status Register” on page 572 00000000h 108h 10Bh “Offset 108h: UNCERRMSK - Uncorrectable Error Mask Register” on page 574 00000000h 10Ch 10Fh “Offset 10Ch: UNCERRSEV - Uncorrectable Error Severity Register” on page 575 00062010h 110h 113h “Offset 110h: CORERRSTS - Correctable Error Status Register” on page 576 00000000h 114h 117h “Offset 114h: CORERRMSK - Correctable Error Mask Register” on page 578 00000000h 118h 11Bh “Offset 118h: AERCACR - Advanced Error Capabilities and Control Register” on page 579 00000000h 11Ch 11Fh “Offset 11Ch: HDRLOG0 - Header Log DW 0 (1st 32 bits) Register” on page 580 00000000h 120h 123h “Offset 120h: HDRLOG1 - Header Log DW 1 (2nd 32 bits) Register” on page 580 00000000h 124h 127h “Offset 124h: HDRLOG2 - Header Log DW 2 (3rd 32 bits) Register” on page 581 00000000h 128h 12Bh “Offset 128h: HDRLOG3 - Header Log DW 3 (4th 32 bits) Register” on page 581 00000000h 12Ch 12Fh “Offset 12Ch: RPERRCMD - Root (Port) Error Command Register” on page 582 00000000h Table 7-15. Bus 0, Device 2, Function 0: Summary of PCI Express Port A Standard and Enhanced PCI Configuration Registers (Sheet 2 of 3) Offset Start Offset End Register ID - Description Default Value

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130h 133h “Offset 130h: RPERRMSTS - Root (Port) Error Message Status Register” on page 583 00000000h 134h 137h “Offset 134h: ERRSID - Error Source ID Register” on page 585 00000000h 140h 143h “Offset 140h: PEAUNITERR - PCI Express Unit Error Register” on page 586 00000000h 144h 147h “Offset 144h: PEAMASKERR - PCI Express Unit Mask Error Register” on page 588 0000E000h 148h 14Bh “Offset 148h: PEAERRDOCMD - PCI Express Error Do Command Register” on page 589 00000000h 14Ch 14Fh “Offset 14Ch: UNCEDMASK - Uncorrectable Error Detect Mask Register” on page 591 00000000h 150h 153h “Offset 150h: COREDMASK - Correctable Error Detect Mask Register” on page 592 00000000h 158h 15Bh “Offset 158h: PEAUNITEDMASK - PCI Express Unit Error Detect Mask Register” on page 594 00000000h 160h 163h “Offset 160h: PEAFERR - PCI Express First Error Register” on page 595 00000000h 164h 167h “Offset 164h: PEANERR - PCI Express Next Error Register” on page 597 00000000h 168h 16Bh “Offset 168h: PEAERRINJCTL - Error Injection Control Register” on page 597 00000000h Table 7-15. Bus 0, Device 2, Function 0: Summary of PCI Express Port A Standard and Enhanced PCI Configuration Registers (Sheet 3 of 3) Offset Start Offset End Register ID - Description Default Value

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7.3.5 PCI Express* Port A1 Registers: Bus 0, Device 3, Function 0

The PCI Express* Port A1 includes the registers listed in Table 7-16. These registers materialize in PCI configuration space. See Section 16.4, “PCI Express* Port A Standard and Enhanced Registers: Bus 0, Devices 2 and 3, Function 0” for detailed discussion of these registers. Table 7-16. Bus 0, Device 3, Function 0: Summary of PCI Express Port A1 Standard and Enhanced PCI Configuration Registers (Sheet 1 of 3) Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID - Vendor Identification Register” on page 527 8086h 02h 03h “Offset 02h: DID - Device Identification Register” on page 528 5025h 04h 05h “Offset 04h: PCICMD - PCI Command Register” on page 528 0000h 06h 07h “Offset 06h: PCISTS - PCI Status Register” on page 530 0010h 08h 08h “Offset 08h: RID - Revision Identification Register” on page 531 Variable 0Ah 0Ah “Offset 0Ah: SUBC - Sub-Class Code Register” on page 532 04h 0Bh 0Bh “Offset 0Bh: BCC - Base Class Code Register” on page 532 06h 0Ch 0Ch “Offset 0Ch: CLS - Cache Line Size Register” on page 533 00h 0Eh 0Eh “Offset 0Eh: HDR - Header Type Register” on page 533 01h 18h 18h “Offset 18h: PBUSN - Primary Bus Number Register” on page 534 00h 19h 19h “Offset 19h: SBUSN - Secondary Bus Number Register” on page 534 00h 1Ah 1Ah “Offset 1Ah: SUBUSN: Subordinate Bus Number Register” on page 535 00h 1Ch 1Ch “Offset 1Ch: IOBASE - I/O Base Address Register” on page 535 F0h 1Dh 1Dh “Offset 1Dh: IOLIMIT - I/O Limit Address Register” on page 536 00h 1Eh 1Fh “Offset 1Eh: SECSTS - Secondary Status Register” on page 536 0000h 20h 21h “Offset 20h: MBASE - Memory Base Address Register” on page 538 FFF0h 22h 23h “Offset 22h: MLIMIT - Memory Limit Address Register” on page 539 0000h 24h 25h “Offset 24h: PMBASE - Prefetchable Memory Base Address Register” on page 540 FFF1h 26h 27h “Offset 26h: PMLIMIT - Prefetchable Memory Limit Address Register” on page 540 0001h 28h 28h “Offset 28h: PMBASU - Prefetchable Memory Base Upper Address Register” on page 541 0Fh 2Ch 2Ch “Offset 2Ch: PMLMTU - Prefetchable Memory Limit Upper Address Register” on page 541 00h 34h 34h “Offset 34h: CAPPTR - Capabilities Pointer Register” on page 542 50h 3Ch 3Ch “Offset 3Ch: INTRLINE - Interrupt Line Register” on page 542 00h 3Dh 3Dh “Offset 3Dh: INTRPIN - Interrupt Pin Register” on page 543 01h 3Eh 3Eh “Offset 3Eh: BCTRL - Bridge Control Register” on page 543 00h 44h 44h “Offset 44h: VSCMD0 - Vendor Specific Command Byte 0 Register” on page 545 00h 45h 45h “Offset 45h: VSCMD1 - Vendor Specific Command Byte 1 Register” on page 546 00h 46h 46h “Offset 46h: VSSTS0 - Vendor Specific Status Byte 0 Register” on page 547 00h 47h 47h “Offset 47h: VSSTS1 - Vendor Specific Status Byte 1 Register” on page 547 00h 48h 48h “Offset 48h: VSCMD2 - Vendor Specific Command Byte 2 Register” on page 548 00h 50h 50h “Offset 50h: PMCAPID - Power Management Capabilities Structure Register” on page 548 01h

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51h 51h “Offset 51h: PMNPTR - Power Management Next Capabilities Pointer Register” on page 549 58h 52h 53h “Offset 52h: PMCAPA - Power Management Capabilities Register” on page 549 C822h 54h 55h “Offset 54h: PMCSR - Power Management Status and Control Register” on page 550 0000h 56h 56h “Offset 56h: PMCSRBSE - Power Management Status and Control Bridge Extensions Register” on page 551 00h 58h 58h “Offset 58h: MSICAPID - MSI Capabilities Structure Register” on page 551 05h 59h 59h “Offset 59h: MSINPTR - MSI Next Capabilities Pointer Register” on page 552 64h 5Ah 5Bh “Offset 5Ah: MSICAPA - MSI Capabilities Register” on page 553 0002h 5Ch 5Fh “Offset 5Ch: MSIAR - MSI Address for PCI Express Register” on page 553 FEE00000h 60h 61h “Offset 60h: MSIDR - MSI Data Register” on page 554 0000h 64h 64h “Offset 64h: PEACAPID - PCI Express Features Capabilities ID Register” on page 555 10h 65h 65h “Offset 65h: PEANPTR - PCI Express Next Capabilities Pointer Register” on page 556 00h 66h 67h “Offset 66h: PEACAPA - PCI Express Features Capabilities Register” on page 556 0041h 68h 6Bh “Offset 68h: PEADEVCAP - PCI Express Device Capabilities Register” on page 557 00000001h 6Ch 6Dh “Offset 6Ch: PEADEVCTL - PCI Express Device Control Register” on page 558 0000h 6Eh 6Fh “Offset 6Eh: PEADEVSTS - PCI Express Device Status Register” on page 560 0000h 70h 73h “Offset 70h: PEA1LNKCAP - PCI Express Link Capabilities Register” on page 561 0303E441h 74h 75h “Offset 74h: PEALNKCTL - PCI Express Link Control Register” on page 562 0001h 76h 77h “Offset 76h: PEALNKSTS - PCI Express Link Status Register” on page 564 1001h 78h 7Bh “Offset 78h: PEA1SLTCAP - PCI Express Slot Capabilities Register” on page 566 00000000h 7Ch 7Dh “Offset 7Ch: PEASLTCTL - PCI Express Slot Control Register” on page 568 01C0h 7Eh 7Fh “Offset 7Eh: PEASLTSTS - PCI Express Slot Status Register” on page 569 0040h 80h 83h “Offset 80h: PEARPCTL - PCI Express Root Port Control Register” on page 570 00000000h 84h 87h “Offset 84h: PEARPSTS - PCI Express Root Port Status Register” on page 571 00000000h 100h 103h “Offset 100h: ENHCAPST - Enhanced Capability Structure Register” on page 571 00010001h 104h 107h “Offset 104h: UNCERRSTS - Uncorrectable Error Status Register” on page 572 00000000h 108h 10Bh “Offset 108h: UNCERRMSK - Uncorrectable Error Mask Register” on page 574 00000000h 10Ch 10Fh “Offset 10Ch: UNCERRSEV - Uncorrectable Error Severity Register” on page 575 00062010h 110h 113h “Offset 110h: CORERRSTS - Correctable Error Status Register” on page 576 00000000h 114h 117h “Offset 114h: CORERRMSK - Correctable Error Mask Register” on page 578 00000000h 118h 11Bh “Offset 118h: AERCACR - Advanced Error Capabilities and Control Register” on page 579 00000000h 11Ch 11Fh “Offset 11Ch: HDRLOG0 - Header Log DW 0 (1st 32 bits) Register” on page 580 00000000h 120h 123h “Offset 120h: HDRLOG1 - Header Log DW 1 (2nd 32 bits) Register” on page 580 00000000h 124h 127h “Offset 124h: HDRLOG2 - Header Log DW 2 (3rd 32 bits) Register” on page 581 00000000h 128h 12Bh “Offset 128h: HDRLOG3 - Header Log DW 3 (4th 32 bits) Register” on page 581 00000000h 12Ch 12Fh “Offset 12Ch: RPERRCMD - Root (Port) Error Command Register” on page 582 00000000h Table 7-16. Bus 0, Device 3, Function 0: Summary of PCI Express Port A1 Standard and Enhanced PCI Configuration Registers (Sheet 2 of 3) Offset Start Offset End Register ID - Description Default Value

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 205 Intel® EP80579 Integrated Processor 130h 133h “Offset 130h: RPERRMSTS - Root (Port) Error Message Status Register” on page 583 00000000h 134h 137h “Offset 134h: ERRSID - Error Source ID Register” on page 585 00000000h 140h 143h “Offset 140h: PEAUNITERR - PCI Express Unit Error Register” on page 586 00000000h 144h 147h “Offset 144h: PEAMASKERR - PCI Express Unit Mask Error Register” on page 588 0000E000h 148h 14Bh “Offset 148h: PEAERRDOCMD - PCI Express Error Do Command Register” on page 589 00000000h 14Ch 14Fh “Offset 14Ch: UNCEDMASK - Uncorrectable Error Detect Mask Register” on page 591 00000000h 150h 153h “Offset 150h: COREDMASK - Correctable Error Detect Mask Register” on page 592 00000000h 158h 15Bh “Offset 158h: PEAUNITEDMASK - PCI Express Unit Error Detect Mask Register” on page 594 00000000h 160h 163h “Offset 160h: PEAFERR - PCI Express First Error Register” on page 595 00000000h 164h 167h “Offset 164h: PEANERR - PCI Express Next Error Register” on page 597 00000000h 168h 16Bh “Offset 168h: PEAERRINJCTL - Error Injection Control Register” on page 597 00000000h Table 7-16. Bus 0, Device 3, Function 0: Summary of PCI Express Port A1 Standard and Enhanced PCI Configuration Registers (Sheet 3 of 3) Offset Start Offset End Register ID - Description Default Value

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7.3.6 USB (1.1) Controller: Bus 0, Device 29, Functions 0 The USB 1.1 controller includes the registers listed in Table 7-17 and Table 7-18. These registers materialize in PCI configuration and I/O spaces (via PCI I/O BAR), respectively. See Chapter 25.0, “USB (1.1) Controller: Bus 0, Device 29, Function 0” for detailed discussion of these registers. Table 7-17. Bus 0, Device 29, Functions 0, Summary of USB (1.1) Controller PCI Configuration Registers Offset Start Offset End Register ID - Description Default Value 00h 03h “ID - Identifiers Register” on page 942 50338086h 04h 05h “PCICMD - Command Register” on page 942 0000h 06h 07h “PCISTS - Device Status Register” on page 943 0280h 08h 08h “RID - Revision ID Register” on page 944 Variable 0Ah 0Ah “SUBC - Sub Class Code Register” on page 945 03h 0Bh 0Bh “BCC - Base Class Code Register” on page 945 0Ch 0Dh 0Dh “MLT - Master Latency Timer Register” on page 945 00h 0Eh 0Eh “HDR - Header Type Register” on page 946 Variable 20h 23h “USBIOBAR - Base Address Register” on page 946 00000001h 2Ch 2Dh “USBx_SVID - USB Subsystem Vendor ID Register” on page 947 0000h 2Eh 2Fh “USBx_SID - USB Subsystem ID Register” on page 947 0000h 3Ch 3Ch “INTL - Interrupt Line Register” on page 948 00h 3Dh 3Dh “INTP - Interrupt Pin Register” on page 948 Variable 60h 60h “SBRN - Serial Bus Release Number Register” on page 948 10h C0h C1h “USBLKMCR - USB Legacy Keyboard/Mouse Control Register” on page 949 2000h C4h C4h “USBREN - USB Resume Enable Register” on page 951 00h C8h C8h “USBCWP - USB Core Well Policy Register” on page 951 00h F8h FBh “MANID - Manufacturer ID Register” on page 952 00010F90h Table 7-18. Summary of USB (1.1) Controller Configuration Registers Mapped Through USBIOBAR I/O BAR Offset Start Offset End Register ID - Description Default Value 00h 01h “USBCMD: USB Command Register” on page 954 0000h 02h 03h “USBSTS: USB Status Register” on page 957 0020h 04h 05h “USBINTR: USB Interrupt Enable Register” on page 959 0000h 06h 07h “FRNUM: Frame Number Register” on page 959 0000h 08h 0Bh “FRBASEADD: Frame List Base Address Register” on page 960 XXXXX000h 0Ch 0Ch “SOFMOD: Start of Frame Modify Register” on page 961 40h 10h 11h “PSCR - Port Status and Control Register” on page 962 0080h 12h 13h “PSCR - Port Status and Control Register” on page 962 0080h

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 207 Intel® EP80579 Integrated Processor 7.3.7 USB (2.0) Controller: Bus 0, Device 29, Function 7 The USB 2.0 controller includes the registers listed in Table 7-19 and Table 7-20. These registers materialize in PCI configuration and I/O spaces (via PCI I/O BAR), respectively. See Chapter 26.0, “USB 2.0 PCI Configuration Registers” for detailed discussion of these registers. Table 7-19. Bus 0, Device 29, Function 7: Summary of USB (2.0) Controller PCI Configuration Registers Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID - Vendor ID Register” on page 979 8086h 02h 03h “Offset 02h: DID - Device Identification Register” on page 979 5035h 04h 05h “Offset 04h: CMD - Command Register” on page 980 0000h 06h 07h “Offset 06h: DSR - Device Status Register” on page 981 0290h 08h 08h “Offset 08h: RID - Revision ID Register” on page 983 Variable 09h 09h “Offset 09h: PI - Programming Interface Register” on page 983 20h 0Ah 0Ah “Offset 0Ah: SCC - Sub Class Code Register” on page 983 03h 0Bh 0Bh “Offset 0Bh: BCC - Base Class Code Register” on page 984 0Ch 0Dh 0Dh “Offset 0Dh: MLT - Master Latency Timer Register” on page 984 00h 10h 13h “Offset 10h: MBAR - Memory Base Address Register” on page 985 00000000h 2Ch 2Dh “Offset 2Ch: SSVID - USB 2.0 Subsystem Vendor ID Register” on page 985 XXXXh 2Eh 2Fh “Offset 2Eh: SSID - USB 2.0 Subsystem ID Register” on page 986 XXXXh 34h 34h “Offset 34h: CAP_PTR - Capabilities Pointer Register” on page 986 50h 3Ch 3Ch “Offset 3Ch: ILINE - Interrupt Line Register” on page 987 00h 3Dh 3Dh “Offset 3Dh: IPIN - Interrupt Pin Register” on page 987 Variable 50h 50h “Offset 50h: PM_CID - PCI Power Management Capability ID Register” on page 98701h 51h 51h “Offset 51h: PM_NEXT - Next Item Pointer #1 Register” on page 988 58h 52h 53h “Offset 52h: PM_CAP - Power Management Capabilities Register” on page 989 C9C2h 54h 55h “Offset 54h: PM_CS - Power Management Control/Status Register” on page 990 0000h 58h 58h “Offset 58h: DP_CID - Debug Port Capability ID Register” on page 991 0Ah 59h 59h “Offset 59h: DP_NEXT - Next Item Pointer #2 Register” on page 991 00h 5Ah 5Bh “Offset 5Ah: DP_BASE - Debug Port Base Offset Register” on page 991 20A0h 60h 60h “Offset 60h: SBRN - Serial Bus Release Number Register” on page 992 20h 61h 61h “Offset 61h: FLA - Frame Length Adjustment Register” on page 992 20h 62h 63h “Offset 62h: PWC - Port Wake Capability Register” on page 993 01FFh 64h 65h “Offset 64h: CUO - Classic USB Override Register” on page 994 0000h 68h 6Bh “Offset 68h: ULSEC - USB 2.0 Legacy Support Extended Capability Register” on page 994 00000001h 6Ch 6Fh “Offset 6Ch: ULSCS - USB 2.0 Legacy Support Control/Status Register” on page 995 00000000h 70h 73h “Offset 70h: ISU2SMI - Intel Specific USB 2.0 SMI Register” on page 997 00000000h 80h 80h “Offset 80h: AC - Access Control Register” on page 999 00h F8h FBh “Offset F8h: MANID - Manufacturer ID Register” on page 1000 00010F90h

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Table 7-20. Bus 0, Device 29, Function 7: Summary of USB (2.0) Controller Configuration Registers Mapped Through MBAR Memory BAR Offset Start Offset End Register ID - Description Default Value 00h 00h “Offset 00h: CAPLENGTH - Capability Length Register” on page 1002 20h 02h 03h “Offset 02h: HCIVERSION - Host Controller Interface Version Number Register” on page 1003 0100h 04h 07h “Offset 04h: HCSPARAMS - Host Controller Structural Parameters Register” on page 1003 01001202h 08h 0Bh “Offset 08h: HCCPARAMS - Host Controller Capability Parameters Register” on page 1004 00006871h 20h 23h “Offset 20h: USB2CMD - USB 2.0 Command Register” on page 1007 00080000h 24h 27h “Offset 24h: USB2STS - USB 2.0 Status Register” on page 1009 00001000h 28h 2Bh “Offset 28h: USB2INTR - USB 2.0 Interrupt Enable Register” on page 1012 00000000h 2Ch 2Fh “Offset 2Ch: FRINDEX - Frame Index Register” on page 1013 00000000h 30h 33h “Offset 30h: CTRLDSSEGMENT - Control Data Structure Segment Register” on page 1014 00000000h 34h 37h “Offset 34h: PERIODICLISTBASE - Periodic Frame List Base Address Register” on page 1014 00000XXXh 38h 3Bh “Offset 38h: ASYNCLISTADDR - Current Asynchronous List Address Register” on page 1015 00000000h 60h 63h “Offset 60h: CONFIGFLAG - Configure Flag Register” on page 1015 00000000h 64h 67h “Offset 64h: PORTSC - Port N Status and Control Register” on page 1016 00003000h 68h 6Bh “Offset 64h: PORTSC - Port N Status and Control Register” on page 1016 00003000h A0h A3h “Offset A0h: CNTL_STS - Control/Status Register” on page 1037 00000000h A4h A4h “Offset A4h: USBPID - USB PIDs Register” on page 1039 00000000h A8h AFh “Offset A8h: DATABUF - Data Buffer Bytes 7:0” on page 1039 00000000000 00000h B0h B0h “Offset B0h: CONFIG - Configuration Register” on page 1040 00007F01h

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7.3.8 Root Complex: Bus 0, Device 31, Function 0

The Root Complex includes the registers listed in Table 7-21. These registers materialize in memory space (via PCI memory BAR), respectively. See Chapter 17.0, “Bridging and Configuration” for detailed discussion of these registers. Table 7-21. Bus 0, Device 31, Function 0: Summary of Root Complex Configuration Registers Mapped Through RCBA Memory BAR Offset Start Offset End Register ID - Description Default Value 0000h 0003h “Offset 0000h: VCH - Virtual Channel Capability Header Register” on page 691 10010002h 0004h 0007h “Offset 0004h: VCAP1 - Virtual Channel Capability 1 Register” on page 691 0801h 0008h 000Bh “Offset 0008h: VCAP2 - Virtual Channel Capability 2 Register” on page 692 0001h 000Ch 000Dh “Offset 000Ch: PVC - Port Virtual Channel Control Register” on page 692 0h 000Eh 000Fh “Offset 000Eh: PVS -Port Virtual Channel Status Register” on page 693 0h 0010h 0013h “Offset 0010h: V0CAP - Virtual Channel 0 Resource Capability Register” on page 693 00000001h 0014h 0017h “Offset 0014h: V0CTL - Virtual Channel 0 Resource Control Register” on page 694 800000FFh 001Ah 001Bh “Offset 001Ah: V0STS - Virtual Channel 0 Resource Status Register” on page 695 0h 0100h 0103h “Offset 0100h: RCTCL - Root Complex Topology Capabilities List Register” on page 696 1A010005h 0104h 0107h “Offset 0104h: ESD - Element Self Description Register” on page 696 00000102h 0110h 0113h “Offset 0110h: ULD - Upstream Link Description Register” on page 697 0001h 0118h 011Fh “Offset 0118h: ULBA - Upstream Link Base Address Register” on page 697 00000000000 00000h 01A0h 01A3h “Offset 01A0h: ILCL - Internal Link Capabilities List Register” on page 698 00010006h 01A4h 01A7h “Offset 01A4h: LCAP - Link Capabilities Register” on page 698 0012441h 01A8h 01A9h “Offset 01A8h: LCTL - Link Control Register” on page 699 0h 01AAh 01ABh “Offset 01AAh: LSTS - Link Status Register” on page 700 0041h 3108h 310Bh “Offset 3108h: D29IP - Device 29 Interrupt Pin Register” on page 702 10004321h 3140h 3141h “Offset 3140h: D31IR - Device 31 Interrupt Route Register” on page 702 3210h 3144h 3145h “Offset 3144h: D29IR - Device 29 Interrupt Route Register” on page 703 3210h 31FFh 31FFh “Offset 31FFh: OIC - Other Interrupt Control Register” on page 704 0h 3400h 3403h “Offset 3400h: RC - RTC Configuration Register” on page 704 0h 3404h 3407h “Offset 3404h: HPTC - High Performance Precision Timer Configuration Register” on page 705 0h 3410h 3413h “Offset 3410h: GCS - General Control and Status Register” on page 706 Variable 3414h 3417h “Offset 3414h: BUC - Backed Up Control Register” on page 708 Variable 3418h 341Bh “Offset 3418h: FD - Function Disable Register” on page 709 00000080h 341Ch 341Fh “Offset 341Ch: PRC - Power Reduction Control Register Clock Gating” on page 711 0h

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7.3.9 LPC Interface: Bus 0, Device 31, Function 0

The LPC interface includes the registers listed in Table 7-22 through Table 7-26. These registers materialize in PCI configuration and I/O spaces (via PCI I/O BAR). See Chapter 19.0, “LPC Interface: Bus 0, Device 31, Function 0”, Chapter 27.0, “Power Management”, Chapter 18.0, “System Management”, and Chapter 22.0, “General Purpose I/O: Bus 0, Device 31, Function 0” for detailed discussion of these registers. Table 7-22. Bus 0, Device 31, Function 0: Summary of LPC Interface PCI Configuration Registers Offset Start Offset End Register ID - Description Default Value 00h 03h “Offset 00h: ID: Vendor Identification Register” on page 734 50318086h 04h 05h “Offset 04h: CMD: Device Command Register” on page 735 0007h 06h 07h “Offset 06h: STS: Status Register” on page 736 0200h 08h 08h “Offset 08h: RID: Revision ID Register” on page 737 Variable 09h 0Bh “Offset 09h: CC: Class Code Register” on page 737 060100h 0Dh 0Dh “Offset 0Dh: MLT: Master Latency Timer Register” on page 737 00h 0Eh 0Eh “Offset 0Eh: HTYPE: Header Type Register” on page 738 80H 2Ch 2Fh “Offset 2Ch: SID: Subsystem Identifiers Register” on page 738 00000000h 40h 43h “Offset 40h: ABASE: ACPI Base Address Register” on page 739 00000001h 44h 47h “Offset 44h: ACTL: ACPI Control Register” on page 739 00h 48h 48h “Offset 48h: GBA: GPIO Base Address Register” on page 740 00000001h 4Ch 4Ch “Offset 4Ch: GC: GPIO Control Register” on page 741 00h 60h 60h “Offset 60h: PARC: PIRQA Routing Control Register” on page 741 80h 61h 61h “Offset 61h: PBRC: PIRQB Routing Control Register” on page 742 80h 62h 62h “Offset 62h: PCRC: PIRQC Routing Control Register” on page 742 80h 63h 63h “Offset 63h: PDRC: PIRQDQ Routing Control Register” on page 743 80h 64h 64h “Offset 64h: SCNT: Serial IRQ Control Register” on page 744 10h 68h 68h “Offset 68h: PERC: PIRQEQ Routing Control Register” on page 745 80h 69h 69h “Offset 69h: PFRC: PIRQF Routing Control Register” on page 745 80h 6Ah 6Ah “Offset 6Ah: PGRC: PIRQG Routing Control Register” on page 746 80h 6Bh 6Bh “Offset 6Bh: PHRC: PIRQH Routing Control Register” on page 747 80h 80h 81h “Offset 80h: IOD: I/O Decode Ranges Register” on page 747 0000h 82h 83h “Offset 82h: IOE: I/O Enables Register” on page 749 0000h 84h 85h “Offset 84h: LG1: LPC Generic Decode Range 1 Register” on page 750 0000h 88h 88h “Offset 88h: LG2: LPC Generic Decode Range 2 Register” on page 751 0000h D0h D3h “Offset D0h: FS1: FWH ID Select 1 Register” on page 752 00112233h D4h D5h “Offset D4h: FS2: FWH ID Select 2 Register” on page 753 4567h D8h DBh “Offset D8h: FDE: FWH Decode Enable Register” on page 754 FFCFh DCh DCh “Offset DCh: BC: BIOS Control Register” on page 756 00h F0h F3h “Offset F0h: RCBA: Root Complex Base Address Register” on page 757 00000000h F8h FBh “Offset F8h: MANID: Manufacturer ID Register” on page 757 00010F90h

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 211 Intel® EP80579 Integrated Processor Table 7-23. Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management PCI Configuration Registers Offset Start Offset End Register ID - Description Default Value A0h A0h “Offset A0h: GEN_PMCON_1 - General PM Configuration 1 Register” on page 1048 0200h A2h A2h “Offset A2h: GEN_PMCON_2 - General PM Configuration 2 Register” on page 1049 00h A4h A4h “Offset A4h: GEN_PMCON_3 - General PM Configuration 3 Register” on page 1051 00h B8h BBh “Offset B8h: GPI_ROUT - GPI Routing Control Register” on page 1053 00000000h Table 7-24. Bus 0, Device 31, Function 0: Summary of TCO Configuration Registers Mapped Through TCOBASE I/O BAR“ Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: TRLD - TCO Timer Reload and Current Value Register” on page 715 0000h 02h 02h “Offset 02h: TDI - TCO Data In Register” on page 715 00h 03h 03h “Offset 03h: TDO - TCO Data Out Register” on page 716 00h 04h 04h “Offset 04h: TSTS1 - TCO 1 Status Register” on page 716 0000h 06h 07h “Offset 06h: TSTS2 - TCO 2 STS Register” on page 718 0000h 08h 09h “Offset 08h: TCTL1 - TCO 1 Control Register” on page 720 0000h 0Ah 0Bh “Offset 0Ah: TCTL2 - TCO 2 Control Register” on page 721 0008h 0Ch at 01h 0Ch at 01h “Offset 0Ch: TMSG[1-2] - TCO MESSAGE Register” on page 721 00h 0Eh 0Eh “Offset 0Eh: TWDS - TCO Watchdog Status Register” on page 722 00h 10h 10h “Offset 10h: LE - Legacy Elimination Register” on page 722 03h 12h 13h “Offset 12h: TTMR - TCO Timer Initial Value Register” on page 723 0004h Table 7-25. Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management General Configuration Registers Mapped Through PMBASE I/O BAR (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00h 00h “Offset 00h: PM1_STS – Power Management 1 Status Register” on page 1056 0000h 02h 02h “Offset 02h: PM1_EN - Power Management 1 Enables Register” on page 1058 0000h 04h 04h “Offset 04h: PM1_CNT - Power Management 1 Control Register” on page 1059 0000h 08h B8h “Offset 08h: PM1_TMR - Power Management 1 Timer Register” on page 1060 00000000h 10h 10h “Offset 10h: PROC_CNT - Processor Control Register” on page 1060 00000000h 14h 14h “Offset 14h: LV2 - Level 2 Register” on page 1063 00h 28h 28h “Offset 28h: GPE0_STS - General Purpose Event 0 Status Register” on page 1063 00000000h 2Ch 2Ch “Offset 2Ch: PMBASE_GPE0_EN - General Purpose Event 0 Enables Register” on page 1067 00000000h

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30h 30h “Offset 30h: SMI_EN - SMI Control and Enable Register” on page 1068 00000000h 34h 34h “Offset 34h: SMI_STS - SMI Status Register” on page 1071 00000000h 38h 38h “Offset 38h: ALT_GPI_SMI_EN - Alternate GPI SMI Enable Register” on page 1073 0000h 3Ah 3Ah “Offset 3Ah: ALT_GPI_SMI_STS - Alternate GPI SMI Status Register” on page 10740000h 44h 44h “Offset 44h: DEVTRAP_STS - DEVTRAP_STS Register” on page 1074 0000h Table 7-25. Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management General Configuration Registers Mapped Through PMBASE I/O BAR (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value Table 7-26. Bus 0, Device 31, Function 0: Summary of General Purpose I/O Configuration Registers Mapped Through GBA BAR IO BAR Offset Start Offset End Register ID - Description Default Value 00h 03h “Offset 00h: GPIO_USE_SEL1 - GPIO Use Select 1 {31:0} Register” on page 807 Variable 04h 07h “Offset 04h: GP_IO_SEL1 - GPIO Input/Output Select 1 {31:0} Register” on page 808 E400FFFFh 0Ch 0Fh “Offset 0Ch: GP_LVL1 - GPIO Level 1 for Input or Output {31:0} Register” on page 809 FF3F0000h 18h 1Bh “Offset 18h: GPO_BLINK - GPIO Blink Enable Register” on page 810 00040000h 2Ch 2Fh “Offset 2Ch: GPI_INV - GPIO Signal Invert Register” on page 812 00000000h 30h 33h “Offset 30h: GPIO_USE_SEL2 - GPIO Use Select 2 {63:32} Register” on page 813 Variable 34h 37h “Offset 34h: GP_IO_SEL2 - GPIO Input/Output Select 2 {63:32} Register” on page 813 00000300h 38h 3Bh “Offset 38h: GP_LVL2 - GPIO Level for Input or Output 2 {63:32} Register” on page 814 00030207h

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 213 Intel® EP80579 Integrated Processor

7.3.10 SATA Controller: Bus 0, Device 31, Function 2

The SATA controller includes the registers listed in Table 7-27, Table 7-28, and Table 7-29. These registers materialize in PCI configuration, I/O, and memory spaces (via PCI I/O and memory BARs). See Chapter 23.0, “SATA: Bus 0, Device 31, Function 2” for detailed discussion of these registers. Table 7-27. Bus 0, Device 31, Function 2: Summary of SATA Controller PCI Configuration Registers (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00h 03h “Offset 00h: ID – Identifiers Register” on page 819 Variable 04h 05h “Offset 04h: CMD - Command Register” on page 819 0000h 06h 07h “Offset 06h: STS - Device Status Register” on page 820 02B0h 08h 08h “Offset 08h: RID - Revision ID Register” on page 821 Variable 0Ah 0Bh “Offset 0Ah: CC - Class Code Register” on page 823 Variable 0Dh 0Dh “Offset 0Dh: MLT – Master Latency Timer Register” on page 823 00h 10h 13h “Offset 10h: PCMDBA – Primary Command Block Base Address Register” on page 824 00000001h 14h 17h “Offset 14h: PCTLBA – Primary Control Block Base Address Register” on page 824 00000001h 18h 1Bh “Offset 18h: SCMDBA – Secondary Command Block Base Address Register” on page 825 00000001h 1Ch 1Fh “Offset 1Ch: SCTLBA – Secondary Control Block Base Address Register” on page 825 00000001h 20h 23h “Offset 20h: LBAR – Legacy Bus Master Base Address Register when SCC is SATA with AHCI PI” on page 826 00000001h 24h 27h “Offset 24h: ABAR – AHCI Base Address Register” on page 826 00000000h 2Ch 2Fh “Offset 2Ch: SS - Sub System Identifiers Register” on page 827 00000000h 34h 34h “Offset 34h: CAP – Capabilities Pointer Register” on page 827 80h 3Ch 3Dh “Offset 3Ch: INTR - Interrupt Information Register” on page 828 Variable 40h 41h “Offset 40h: PTIM – Primary Timing Register” on page 829 0000h 44h 44h “Offset 44h: D1TIM – Device 1 IDE Timing Register” on page 830 00h 48h 48h “Offset 48h: SYNCC – Synchronous DMA Control Register” on page 831 00h 4Ah 4Bh “Offset 4Ah: SYNCTIM – Synchronous DMA Timing Register” on page 832 0000h 54h 57h “Offset 54h: IIOC – IDE I/O Configuration Register” on page 833 00000000h 70h 71h “Offset 70h: PID – PCI Power Management Capability ID Register” on page 834 Variable 72h 73h “Offset 72h: PC – PCI Power Management Capabilities Register” on page 834 4002h 74h 77h “Offset 74h: PMCS – PCI Power Management Control And Status Register” on page 835 0000h 80h 81h “Offset 80h: MID – Message Signaled Interrupt Identifiers Register” on page 836 7005h 82h 83h “Offset 82h: MC – Message Signaled Interrupt Message Control Register” on page 837 0000h 84h 87h “Offset 84h: MA – Message Signaled Interrupt Message Address Register” on page 838 00000000h 88h 89h “Offset 88h: MD – Message Signaled Interrupt Message Data Register” on page 838 0000h 90h 90h “Offset 90h: MAP – Port Mapping Register” on page 839 00h

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92h 92h “Offset 92h: PCS – Port Control and Status Register” on page 840 00h A8h ABh “Offset A8h: SATACR0 – Serial ATA Capability Register 0” on page 841 00100012h ACh AFh “Offset ACh: SATACR1 – Serial ATA Capability Register 1” on page 841 00000048h C0h C0h “Offset C0h: ATC – APM Trapping Control Register” on page 842 00h C4h C4h “Offset C4h: ATS – ATM Trapping Status Register” on page 843 00h D0h D3h “Offset D0h: SP – Scratch Pad Register” on page 844 00000000h E0h E3h “Offset E0h: BFCS – BIST FIS Control/Status Register” on page 844 00000000h E4h E7h “Offset E4h: BFTD1 – BIST FIS Transmit Data 1 Register” on page 846 00000000h E8h EBh “Offset E8h: BFTD2 – BIST FIS Transmit Data 2 Register” on page 846 0h F8h FBh “Offset F8h: MANID – Manufacturing ID Register” on page 847 Variable Table 7-27. Bus 0, Device 31, Function 2: Summary of SATA Controller PCI Configuration Registers (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value Table 7-28. Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration Registers Mapped Through LBAR I/O BAR Offset Start Offset End Register ID - Description Default Value 00h 00h “Offset 00h: PCMD – Primary Command Register” on page 848 00h 02h 02h “Offset 02h: PSTS – Primary Status Register” on page 849 00h 04h 07h “Offset 04h: PDTP – Primary Descriptor Table Pointer Register” on page 849 Variable 10h 13h “Offset 10h: INDEX – AHCI Index Register” on page 850 00000000h 14h 17h “Offset 14h: DATA – AHCI Data Register” on page 851 Variable Table 7-29. Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration Registers Mapped Through ABAR Memory BAR (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00h 03h “Offset 00h: HCAP – HBA Capabilities Register” on page 853 Variable 04h 07h “Offset 04h: GHC – Global HBA Control Register” on page 855 00000000h 08h 0Bh “Offset 08h: IS – Interrupt Status Register” on page 856 00000000h 0Ch 0Fh “Offset 0Ch: PI – Ports Implemented Register” on page 856 00000000h 10h 13h “Offset 10h: VS – AHCI Version Register” on page 857 00010100h A0h A3h “Offset A0h: SGPO -SPGIO Control Register” on page 857 00000000h 100h, 180h 17Fh, 1FFh “Offset 100h: PxCLB[0-1] – Port [0-1] Command List Base Address Register” on page 858 Variable 104h, 184h 107h, 187h “Offset 104h: PxCLBU[0-1] – Port [0-1] Command List Base Address Register” on page 858 Variable 108h, 188h 10Bh, 18Bh “Offset 108h: PxFB[0-1] – Port [0-1] FIS Base Address Register” on page 859 Variable

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 215 Intel® EP80579 Integrated Processor 10Ch, 18Ch 10Fh, 18Fh “Offset 10Ch: PxFBU[0-1] – Port [0-1] FIS Base Address Upper 32-bits Register” on page 859 Variable 110h, 190h 113h, 193h “Offset 110h: PxIS[0-1] – Port [0-1] Interrupt Status Register” on page 860 00000000h 114h, 194h 117h, 197h “Offset 114h: PxIE[0-1] – Port [0-1] Interrupt Enable Register” on page 861 00000000h 118h, 198h 11Bh, 19Bh “Offset 118h: PxCMD[0-1] – Port [0-1] Command Register” on page 863 Variable 120h, 1A0h 123h, 1A3h “Offset 120h: PxTFD[0-1] – Port [0-1] Task File Data Register” on page 866 0000007Fh 124h, 1A4h 127h, 1A7h “Offset 124h: PxSIG[0-1] – Port [0-1] Signature Register” on page 867 FFFFFFFFh 128h, 1A8h 12Bh, 1ABh “Offset 128h: PxSSTS[0-1] – Port [0-1] Serial ATA Status Register” on page 868 Variable 12Ch, 1ACh 12Fh, 1AFh “Offset 12Ch: PxSCTL[0-1] – Port [0-1] Serial ATA Control Register” on page 869 00000000h 130h, 1B0h 133h, 1B3h “Offset 130h: PxSERR[0-1] – Port [0-1] Serial ATA Error Register” on page 870 00000000h 134h, 1B4h 137h, 1B7h “Offset 134h: PxSACT[0-1] – Port [0-1] Serial ATA Active Register” on page 872 00000000h 138h, 1B8h 13Bh, 1BBh “Offset 138h: PxCI[0-1] – Port [0-1] Command Issue Register” on page 872 00000000h 13Ch, 1BCh 13Fh, 1BFh “Offset 13Ch: PxSNTF[0-1] – Port [0-1] SNotification Register” on page 873 00000000h Table 7-29. Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration Registers Mapped Through ABAR Memory BAR (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value

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7.3.11 SMBus Controller: Bus 0, Device 31, Function 3

The SMBus controller includes the registers listed in Table 7-30 and Table 7-31. These registers materialize in PCI configuration and I/O spaces (via PCI I/O BAR), respectively. See Chapter 24.0, “SMBus Controller Functional Description: Bus 0, Device 31, Function 3” for detailed discussion of these registers. Table 7-30. Bus 0, Device 31, Function 3: Summary of SMBus Controller PCI Configuration Registers Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID: Vendor ID Register” on page 897 8086h 02h 03h “Offset 02h: DID: Device ID Register” on page 897 5032h 04h 05h “Offset 04h: CMD: Command Register” on page 897 0000h 06h 07h “Offset 06h: DS – Device Status Register” on page 898 0280h 08h 08h “Offset 08h: RID: Revision ID Register” on page 899 Variable 09h 09h “Offset 09h: PI: Programming Interface Register” on page 900 00h 0Ah 0Ah “Offset 0Ah: SCC: Sub Class Code Register” on page 900 05h 0Bh 0Bh “Offset 0Bh: BCC: Base Class Code Register” on page 900 0Ch 20h 23h “Offset 20h: SM_BASE: SMB Base Address Register” on page 901 00000001h 2Ch 2Dh “Offset 2Ch: SVID: SVID Register” on page 901 0000h 2Eh 2Fh “Offset 2Eh: SID: Subsystem Identification Register” on page 902 0000h 3Ch 3Ch “Offset 3Ch: INTLN: Interrupt Line Register” on page 902 00h 3Dh 3Dh “Offset 3Dh: NTPN: Interrupt Pin Register” on page 903 Variable 40h 40h “Offset 40h: HCFG: Host Configuration Register” on page 903 00h F8h FBh “Offset F8h: MANID: Manufacturer ID Register” on page 904 00010F90h Table 7-31. Bus 0, Device 31, Function 3: Summary of SMBus Controller Configuration Registers Mapped Through SM_BASE I/O BAR Offset Start Offset End Register ID - Description Default Value 00h 00h “Offset 00h: HSTS: Host Status Register” on page 906 00h 02h 02h “Offset 02h: HCTL: Host Control Register” on page 908 00h 03h 03h “Offset 03h: HCMD: Host Command Register” on page 912 00h 04h 04h “Offset 04h: TSA: Transmit Slave Address Register” on page 912 00h 05h 05h “Offset 05h: HD0: Data 0 Register” on page 913 00h 06h 06h “Offset 06h: HD1: Data 1 Register” on page 913 00h 07h 07h “Offset 07h: HBD: Host Block Data Register” on page 914 00h 08h 08h “Offset 08h: PEC: Packet Error Check Data Register” on page 915 00h 0Ch 0Ch “Offset 0Ch: AUXS: Auxiliary Status Register” on page 915 00h 0Dh 0Dh “Offset 0Dh: AUXC: Auxiliary Control Register” on page 916 00h 0Eh 0Eh “Offset 0Eh: SMLC: SMLINK_PIN_CTL Register” on page 916 07h 0Fh 0Fh “Offset 0Fh: SMBC: SMBUS_PIN_CTL Register” on page 917 07h

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 217 Intel® EP80579 Integrated Processor

7.3.12 IA-32 Core Interface I/O-Mapped Register

7.3.13 IMCH PCI Configuration

The PCI configuration interface includes the registers listed in Table 7-33. These registers materialize at fixed locations in I/O space.

7.3.14 APIC

The APIC includes the registers listed in Table 7-34 and Table 7-35 These registers materialize at fixed locations in memory space and are indexed, respectively. See Chapter 30.0 for detailed discussion of these registers. Table 7-32. Summary of IA-32 Core Interface Registers Mapped in I/O Space Offset Start Offset End Register ID - Description Default Value 61h 61h “Offset 61h: NMI_STS_CNT - NMI Status and Control Register” on page 1098 00h 70h 70h “Offset 70h: NMI_EN - NMI Enable (and Real Time Clock Index) Register” on page 1099 80h 92h 92h “Offset 92h: PORT92 - Fast A20 and Init Register” on page 1100 00h F0h F0h “Offset F0h: COPROC_ERR - Coprocessor Error Register” on page 1100 00h CF9h CF9h “Offset CF9h: RST_CNT - Reset Control Register” on page 1101 00h Table 7-33. Summary of IMCH PCI Configuration Registers Mapped in I/O Space Offset Start Offset End Register ID - Description Default Value 0CF8h 0CF8h “Offset 0CF8h: CONFIG_ADDRESS: Configuration Address Register” on page 354 00000000h 0CFCh 0CFCh “Offset 0CFCh: CONFIG_DATA: Configuration Data Register” on page 355 00000000h Table 7-34. Summary of APIC Registers Mapped in Memory Space“ Offset Start Offset End Register ID - Description Default Value 0000h (4B) 0000h (4B) “APIC_IDX - Index Register” on page 1135 00h 0010h (4B) 0010h (4B) “APIC_DAT – Data Register” on page 1136 00h 0040h (4B) 0040h (4B) “APIC_EOI - EOI Register” on page 1136 00h

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Table 7-35. Summary of APIC Indexed Registers Offset Start Offset End Register ID - Description Default Value 00h (4B) 00h (4B) “APIC_ID – Identification Register” on page 1138 0000h 01h (4B) 01h (4B) “APIC_VS - Version Register” on page 1138 00170020h 10h at 02h (4B) 11h at 02h (4B) “APIC_RTE[0-39] - Redirection Table Entry” on page 1139 XXXX0000000 1XXXXh

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 219 Intel® EP80579 Integrated Processor 7.3.15 8259 Interrupt Controller (PIC) The 8259 Interrupt Controller includes the registers listed in Table 7-36. These registers materialize at fixed locations in I/O space. See Chapter 30.0, “Interrupts” for detailed discussion of these registers.

7.3.16 APM Power Management

The APM power management includes the registers listed in Table 7-37. These registers materialize at fixed locations in I/O space. See Chapter 27.0, “Power Management” for detailed discussion of these registers. Table 7-36. Summary of 8259 Interrupt Controller (PIC) Registers Mapped in I/O Space Offset Start Offset End Register ID - Description Default Value 020h, 0A0h 020h, 0A0h “ICW1[0-1] - Initialization Command Word 1 Register” on page 1119 0001X0XXb 021h, 0A1h 021h, 0A1h “ICW2[0-1] - Initialization Command Word 2 Register” on page 1120 XXh 21h 21h “MICW3 - Master Initialization Command Word 3 Register” on page 1121 04h A1h A1h “SICW3 - Slave Initialization Command Word 3 Register” on page 1121 00h 21h, 0A1h 21h, 0A1h “ICW4[0-1] - Initialization Command Word 4 Register” on page 1122 01h 021h, 0A1h 021h, 0A1h “OCW1[0-1]- Operational Control Word 1 (Interrupt Mask) Register” on page 1122 00h 020h, 0A0h 020h, 0A0h “OCW2[0-1] - Operational Control Word 2 Register” on page 1123 001XXXXXb 020h, 0A0h 020h, 0A0h “OCW3[0-1] - Operational Control Word 3 Register” on page 1124 001XX10b 4D0h 4D0h “ELCR1 - Master Edge/Level Control Register” on page 1125 00h 4D1h 4D1h “ELCR2 - Slave Edge/Level Control Register” on page 1126 00 Table 7-37. Summary of APM Registers Mapped in I/O Space Offset Start Offset End Register ID - Description Default Value B2h B2h “Offset B2h: APM_CNT - Advanced Power Management Control Port Register” on page 1054 00h B3h B3h “Offset B3h: APM_STS - Advanced Power Management Status Port Register” on page 1054 00h

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

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7.3.17 LPC DMA

The LPC DMA interface includes the registers listed in Table 7-38 through Table 7-40. These registers materialize at fixed locations in I/O space. See Chapter 20.0, “LPC DMA” for detailed discussion of these registers. Table 7-38. Summary of LPC DMA Registers Mapped in I/O Space Offset Start Offset End Register ID - Description Default Value 00h at 02h 10h at 02h “Offset 00h: DMA_BCA[0-3] - DMA Base and Current Address Registers for Channels 0-3” on page 766 XXXX C4h at 04h C5h at 04h “Offset C4h: DMA_BCA[5-7] - DMA Base and Current Address Registers for Channels 5-7” on page 767 XXXX 01h at 02h 11h at 02h “Offset 01h: DMA_BCC[0-3] - DMA Base and Current Count Registers for Channels 0-3” on page 768 XXXX C6h at 04h C7h at 04h “Offset C6h: DMA_BCC[5-7] - DMA Base and Current Count Registers for Channels 5-7” on page 769 XXXX 87h, 83h, 81h, 82h 97h, 93h, 91h, 82h “Offset 87h: DMA_MPL[0-3] - DMA Memory Low Page Registers for Channels 0-3” on page 771 XXXXXXX 8Bh, 89h, 8Ah 9Bh, 99h, 9Ah “Offset 8Bh: DMA_MPL[5-7]: DMA Memory Low Page Registers for Channels 5-7” on page 771 XXXXXXX Table 7-39. 0000h (IO) Base Address Registers in the IA F1 View Offset Start Offset End Register ID - Description Default Value 08h 08h “Offset 08h: DMA_COMMAND - DMA Command Register” on page 770 000X0X00b 18h 18h “Offset 08h: DMA_COMMAND - DMA Command Register” on page 770 000X0X00b 08h 08h “Offset 08h: DMA_STATUS - DMA Status Register” on page 772 XXXXXXXh 18h 18h “Offset 08h: DMA_STATUS - DMA Status Register” on page 772 XXXXXXXh 0Ah 0Ah “Offset 0Ah: DMA_WSM - DMA Write Single Mask Register” on page 773 000001xxb 1Ah 1Ah “Offset 0Ah: DMA_WSM - DMA Write Single Mask Register” on page 773 000001xxb 0Bh 0Bh “Offset 0Bh: DMA_CHM - DMA Channel Mode Register” on page 774 000000XXh 1Bh 1Bh “Offset 0Bh: DMA_CHM - DMA Channel Mode Register” on page 774 000000XXh 0Ch 0Ch “Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register” on page 775 XXXXXXXXh 1Ch 1Ch “Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register” on page 775 XXXXXXXXh 0Dh 0Dh “Offset 0Dh: DMA_MC - DMA Master Clear Register” on page 775 XXXXXXXXh 1Dh 1Dh “Offset 0Dh: DMA_MC - DMA Master Clear Register” on page 775 XXXXXXXXh 0Eh 0Eh “Offset 0Eh: DMA_CM - DMA Clear Mask Register” on page 776 XXXXXXXXh 1Eh 1Eh “Offset 0Eh: DMA_CM - DMA Clear Mask Register” on page 776 XXXXXXXXh 0Fh 0Fh “Offset 0Fh: DMA_WAM - DMA Write All Mask Register” on page 777 00001111b 1Fh 1Fh “Offset 0Fh: DMA_WAM - DMA Write All Mask Register” on page 777 00001111b

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 221 Intel® EP80579 Integrated Processor 7.3.18 8254 Timers The 8254 timers include the registers listed in Table 7-41. These registers materialize at fixed locations in I/O space. See Chapter 31.0, “8254 Timers” for detailed discussion of these registers. Table 7-40. 0000h (IO) Base Address Registers in the IA F2 View Offset Start Offset End Register ID - Description Default Value D0h D0h “Offset 08h: DMA_COMMAND - DMA Command Register” on page 770 000X0X00b D1h D1h “Offset 08h: DMA_COMMAND - DMA Command Register” on page 770 000X0X00b D0h D0h “Offset 08h: DMA_STATUS - DMA Status Register” on page 772 XXXXXXXh D1h D1h “Offset 08h: DMA_STATUS - DMA Status Register” on page 772 XXXXXXXh D4h D4h “Offset 0Ah: DMA_WSM - DMA Write Single Mask Register” on page 773 000001xxb D5h D5h “Offset 0Ah: DMA_WSM - DMA Write Single Mask Register” on page 773 000001xxb D6h D6h “Offset 0Bh: DMA_CHM - DMA Channel Mode Register” on page 774 000000XXh D7h D7h “Offset 0Bh: DMA_CHM - DMA Channel Mode Register” on page 774 000000XXh D8h D8h “Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register” on page 775 XXXXXXXXh D9h D9h “Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register” on page 775 XXXXXXXXh DAh DAh “Offset 0Dh: DMA_MC - DMA Master Clear Register” on page 775 XXXXXXXXh DBh DBh “Offset 0Dh: DMA_MC - DMA Master Clear Register” on page 775 XXXXXXXXh DCh DCh “Offset 0Eh: DMA_CM - DMA Clear Mask Register” on page 776 XXXXXXXXh DDh DDh “Offset 0Eh: DMA_CM - DMA Clear Mask Register” on page 776 XXXXXXXXh DEh DEh “Offset 0Fh: DMA_WAM - DMA Write All Mask Register” on page 777 00001111b DFh DFh “Offset 0Fh: DMA_WAM - DMA Write All Mask Register” on page 777 00001111b Table 7-41. Summary of 8254 Timer Registers Mapped in I/O Space Offset Start Offset End Register ID - Description Default Value 43h 43h “Offset 43h: TCW - Timer Control Word Register” on page 1146 XXh 40h at 01h 40h at 01h “Offset 40h: TSB[0-2] - Interval Timer Status Byte Format Register” on page 1147 0XXXXXXXb 40h at 01h 40h at 01h “Offset 40h: TCAP[0-2] - Interval Timer Counter Access Ports Register” on page 1148 XXh

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7.3.19 High Precision Event Timers

The High Precision Event Timers includes the registers listed in Table 7-42. These registers materialize at fixed locations in memory space. See Chapter 32.0, “High Precision Event Timers” for detailed discussion of these registers.

7.3.20 Watchdog Timer and Serial I/O

The Watchdog Timers and Serial I/O units includes the registers listed in Table 7-43 and Table 7-44. These registers materialize at fixed locations in I/O space. See Chapter 33.0, “Serial I/O Unit and Watchdog Timer” for detailed discussion of these registers. Table 7-42. Summary of HPET Registers Mapped in Memory Space Offset Start Offset End Register ID - Description Default Value 000h 007h “Offset 000h: GCAP_ID - General Capabilities and ID Register” on page 1155 0429B17F808 6A201h 010h 017h “Offset 010h: GEN_CONF - General Configuration Register” on page 1156 00000000000 00000h 020h 027h “Offset 020h: GINTR_STA - General Interrupt Status Register” on page 1157 00000000000 00000h 0F0h 0F7h “Offset 0F0h: MAIN_CNT - Main Counter Value Register” on page 1158 Xh 100h at 20h 107h at 20h “Offset 100h: HPTCC[0-2] - Timer n Configuration and Capabilities Register” on page 1159 Xh 108h at 20h 10Fh at 20h “Offset 108h: HPTCV[0-2] - Timer n Comparator Value Register” on page 1163 Xh Table 7-43. Summary of UART Timer registers in I/O space Offset Start Offset End Register ID - Description Default Value 02h 02h “Offset 02h: IIR - Interrupt Identification Register” on page 1179 01h 02h 02h “Offset 02h: FCR - FIFO Control Register” on page 1180 00h 03h 03h “Offset 03h: LCR - Line Control Register” on page 1182 00h 04h 04h “Offset 04h: MCR - Modem Control Register” on page 1184 00h 05h 05h “Offset 05h: LSR - Line Status Register” on page 1186 60h 06h 06h “Offset 06h: MSR - Modem Status Register” on page 1189 00h 07h 07h “Offset 07h: SCR - Scratchpad Register” on page 1190 00h

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7.3.21 Real Time Clock

The Real Time Clock include the registers listed in Table 7-45. These registers materialize at indexed locations. See Chapter 29.0, “Real Time Clock” for detailed discussion of these registers. Table 7-44. Summary of Watchdog Timer Registers in I/O Space Offset Start Offset End Register ID - Description Default Value 00h 00h “Offset 00h: PV1R0 - Preload Value 1 Register 0” on page 1194 FFh 01h 01h “Offset 01h: PV1R1 - Preload Value 1 Register 1” on page 1195 FFh 02h 02h “Offset 02h: PV1R2 - Preload Value 1 Register 2” on page 1195 0Fh 04h 04h “Offset 04h: PV2R0 - Preload Value 2 Register 0” on page 1196 FFh 05h 05h “Offset 05h: PV2R1 - Preload Value 2 Register 1” on page 1196 FFh 06h 06h “Offset 06h: PV2R2 - Preload Value 2 Register 2” on page 1197 0Fh 08h 08h “Offset 08h: GISR - General Interrupt Status Register” on page 1197 00h 0Ch 0Ch “Offset 0Ch: RR0 - Reload Register 0” on page 1198 00h 0Dh 0Dh “Offset 0Dh: RR1 - Reload Register 1” on page 1199 00h 10h 10h “Offset 10h: WDTCR - WDT Configuration Register” on page 1199 00h 18h 18h “Offset 18h: WDTLR - WDT Lock Register” on page 1201 00h Table 7-45. Summary of Real Time Clock Indexed Registers Offset Start Offset End Register ID - Description Default Value 0Ah 0Ah “Offset 0Ah: RTC_REGA - Register A (General Configuration)” on page 1107 XXh 0Bh 0Bh “Offset 0Bh: RTC_REGB - Register B (General Configuration)” on page 1109 X0X00XXXb 0Ch 0Ch “Offset 0Ch: RTC_REGC - Register C (Flag Register)” on page 1110 00X00000b 0Dh 0Dh “Offset 0Dh: RTC_REGD - Register D (Flag Register)” on page 1111 10XXXXXXb

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7.4 AIOC Registers

This section summarizes the registers in the AIOC. The registers are presented as they materialize from a PCI perspective.

7.4.1 PCI-to-PCI Bridge: Bus 0, Device 4, Function 0

The PCI-to-PCI Bridge includes the registers listed in Table 7-46. These registers materialize in PCI configuration space. See Chapter 34.0, “PCI-to-PCI Bridge Detailed Register Descriptions” for detailed discussion of these registers along with alternative materializations. Table 7-46. Bus 0, Device 4, Function 0: Summary of PCI-to-PCI Bridge PCI Configuration Registers (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 0h 1h “Offset 0h: VID: Vendor Identification Register” on page 1217 8086h 2h 3h “Offset 2h: DID: Device Identification Register” on page 1217 5037h 4h 5h “Offset 4h: PCICMD: Device Command Register” on page 1217 0h 6h 7h “Offset 6h: PCISTS: PCI Device Status Register” on page 1218 10h 8h 8h “Offset 8h: RID: Revision ID Register” on page 1219 Variable 9h Bh “Offset 9h: CC: Class Code Register” on page 1219 060400h Ch Ch “Offset Ch: CLS: Cacheline Size Register” on page 1219 00h Dh Dh “Offset Dh: LT: Latency Timer Register” on page 1220 00h Eh Eh “Offset Eh: HDR: Header Type Register” on page 1220 1h 10h 14h “Offset 10h: CSRBAR0: Control and Status Registers Base Address Register” on page 1220 00h 14h 17h “Offset 14h: CSRBAR1: Control and Status Registers Base Address Register” on page 1221 00h 18h 18h “Offset 18h: PBNUM: Primary Bus Number Register” on page 1221 00h 19h 19h “Offset 19h: SECBNM: Secondary Bus Number Register” on page 1221 00h 1Ah 1Ah “Offset 1Ah: SUBBNM: Subordinate Bus Number Register” on page 1222 00h 1Bh 1Bh “Offset 1Bh: SECLT: Secondary Latency Timer Register” on page 1222 00h 1Ch 1Ch “Offset 1Ch: IOB: I/O Base Register” on page 1222 F0 1Dh 1Dh “Offset 1Dh: IOL: I/O Limit Register” on page 1223 0 1Eh 1Fh “Offset 1Eh: SECSTA: Secondary Status Register” on page 1223 0h 20h 21h “Offset 20h: MEMB: Memory Base Register” on page 1224 FFF0 22h 23h “Offset 22h: MEML: Memory Limit Register” on page 1224 0 24h 25h “Offset 24h: PMASE: Prefetchable Memory Base Register” on page 1225 FFF1H 26h 27h “Offset 26h: PMLIMIT: Prefetchable Memory Limit Register” on page 1225 1H 28h 28h “Offset 28h: PMBASU: Memory Limit Register” on page 1226 Fh 2Ch 2Ch “Offset 2Ch: PMLMTU: Prefetchable Memory Limit Upper Register” on page 1226 0 30h 31h “Offset 30h: IOBU: I/O Base Upper Register” on page 1227 0 32h 33h “Offset 32h: IOLU: I/O Limit Upper Register” on page 1227 0 34h 34h “Offset 34h: CP: Capabilities Pointer Register” on page 1227 dch 3Ch 3Ch “Offset 3Ch: IRQL: Interrupt Line Register” on page 1228 0

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 225 Intel® EP80579 Integrated Processor 3Dh 3Dh “Offset 3Dh: IRQP: Interrupt Pin Register” on page 1228 0 3Eh 3Fh “Offset 3Eh: BCTL: Bridge Control Register” on page 1228 0000h DCh DCh “Offset DCh: PCID: Power Management Capability ID Register” on page 1229 01h DDh DDh “Offset DDh: PCP: Power Management Next Capability Pointer Register” on page 1230 00h DEh DFh “Offset DEh: PMCAP: Power Management Capability Register” on page 1230 0023h E0h E1h “Offset E0h: PMCS: Power Management Control and Status Register” on page 1231 0008h E2h E2h “Offset E2h: PMCSE: Power Management Control and Status Extension Register” on page 1232 0000h Table 7-46. Bus 0, Device 4, Function 0: Summary of PCI-to-PCI Bridge PCI Configuration Registers (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value

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7.4.2 Gigabit Ethernet MAC: Bus M, Devices 0, 1, and 2, Function 0

The Gigabit Ethernet MAC includes the registers listed in Table 7-47 through Table 7-44. These registers materialize in PCI configuration, I/O (via PCI BAR), and memory (via PCI BAR) spaces. See Section 35.6, “Gigabit Ethernet MAC Configuration Spaces: Bus M, Device 0-2, Function 0”, Section 35.7, “Gigabit Ethernet MAC I/O Spaces: Bus M, Device 0-2, Function 0”, and Section 37.6, “GbE Controller Register Summary” for detailed discussion of these registers along with alternative materializations. Table 7-47. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet MAC Interface PCI Configuration Registers (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID: Vendor Identification Register” on page 1241 8086h 02h 03h “Offset 02h: DID: Device Identification Register” on page 1241 5040h 04h 05h “Offset 04h: PCICMD: Device Command Register” on page 1243 0000h 06h 07h “Offset 06h: PCISTS: PCI Device Status Register” on page 1244 10h 08h 08h “Offset 08h: RID: Revision ID Register” on page 1245 Variable 09h 0Bh “Offset 09h: CC: Class Code Register” on page 1245 020000h 0Eh 0Eh “Offset 0Eh: HDR: Header Type Register” on page 1246 00h 10h 13h “Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on page 1246 00000000h 14h 17h “Offset 14h: IOBAR: CSR I/O Mapped BAR Register” on page 1247 00000001h 2Ch 2Dh “Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1248 0000h 2Eh 2Fh “Offset 2Eh: SID: Subsystem ID Register” on page 1248 0000h 34h 34h “Offset 34h: CP: Capabilities Pointer Register” on page 1249 DCh 3Ch 3Ch “Offset 3Ch: IRQL: Interrupt Line Register” on page 1249 00h 3Dh 3Dh “Offset 3Dh: IRQP: Interrupt Pin Register” on page 1250 01h DCh DCh “Offset DCh: PCID: Power Management Capability ID Register” on page 1251 01h DDh DDh “Offset DDh: PCP: Power Management Next Capability Pointer Register” on page 1251 E4h DEh DFh “Offset DEh: PMCAP: Power Management Capability Register” on page 1252 X023h E0h E1h “Offset E0h: PMCS: Power Management Control and Status Register” on page 1253 0000h E4h E4h “Offset E4h: SCID: Signal Target Capability ID Register” on page 1254 09h E5h E5h “Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1254 F0h E6h E6h “Offset E6h: SBC: Signal Target Byte Count Register” on page 1255 09h E7h E7h “Offset E7h: STYP: Signal Target Capability Type Register” on page 1255 01h E8h E8h “Offset E8h: SMIA: Signal Target IA Mask Register” on page 1256 0h ECh ECh “Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1257 00h F0h F0h “Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on page 1258 05h F1h F1h “Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on page 1258 00h F2h F3h “Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1259 0000h

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 227 Intel® EP80579 Integrated Processor F4h F7h “Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1259 00000000h F8h F9h “Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1260 0000h Table 7-47. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet MAC Interface PCI Configuration Registers (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value Table 7-48. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet MAC Interface PCI Configuration Registers (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID: Vendor Identification Register” on page 1241 8086h 02h 03h “Offset 02h: DID: Device Identification Register” on page 1242 5044h 04h 05h “Offset 04h: PCICMD: Device Command Register” on page 1243 0000h 06h 07h “Offset 06h: PCISTS: PCI Device Status Register” on page 1244 10h 08h 08h “Offset 08h: RID: Revision ID Register” on page 1245 Variable 09h 0Bh “Offset 09h: CC: Class Code Register” on page 1245 020000h 0Eh 0Eh “Offset 0Eh: HDR: Header Type Register” on page 1246 00h 10h 13h “Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on page 1246 00000000h 14h 17h “Offset 14h: IOBAR: CSR I/O Mapped BAR Register” on page 1247 00000001h 2Ch 2Dh “Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1248 0000h 2Eh 2Fh “Offset 2Eh: SID: Subsystem ID Register” on page 1248 0000h 34h 34h “Offset 34h: CP: Capabilities Pointer Register” on page 1249 DCh 3Ch 3Ch “Offset 3Ch: IRQL: Interrupt Line Register” on page 1249 00h 3Dh 3Dh “Offset 3Dh: IRQP: Interrupt Pin Register” on page 1250 01h DCh DCh “Offset DCh: PCID: Power Management Capability ID Register” on page 1251 01h DDh DDh “Offset DDh: PCP: Power Management Next Capability Pointer Register” on page 1251 E4h DEh DFh “Offset DEh: PMCAP: Power Management Capability Register” on page 1252 X023h E0h E1h “Offset E0h: PMCS: Power Management Control and Status Register” on page 1253 0000h E4h E4h “Offset E4h: SCID: Signal Target Capability ID Register” on page 1254 09h E5h E5h “Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1254 F0h E6h E6h “Offset E6h: SBC: Signal Target Byte Count Register” on page 1255 09h E7h E7h “Offset E7h: STYP: Signal Target Capability Type Register” on page 1255 01h E8h E8h “Offset E8h: SMIA: Signal Target IA Mask Register” on page 1256 0h ECh ECh “Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1257 00h F0h F0h “Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on page 1258 05h F1h F1h “Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on page 1258 00h F2h F3h “Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1259 0000h

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F4h F7h “Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1259 00000000h F8h F9h “Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1260 0000h Table 7-48. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet MAC Interface PCI Configuration Registers (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value Table 7-49. Bus M, Device2, Function 0: Summary of Gigabit Ethernet MAC Interface PCI Configuration Registers (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID: Vendor Identification Register” on page 1241 8086h 02h 03h “Offset 02h: DID: Device Identification Register” on page 1242 5048h 04h 05h “Offset 04h: PCICMD: Device Command Register” on page 1243 0000h 06h 07h “Offset 06h: PCISTS: PCI Device Status Register” on page 1244 10h 08h 08h “Offset 08h: RID: Revision ID Register” on page 1245 Variable 09h 0Bh “Offset 09h: CC: Class Code Register” on page 1245 020000h 0Eh 0Eh “Offset 0Eh: HDR: Header Type Register” on page 1246 00h 10h 13h “Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on page 1246 00000000h 14h 17h “Offset 14h: IOBAR: CSR I/O Mapped BAR Register” on page 1247 00000001h 2Ch 2Dh “Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1248 0000h 2Eh 2Fh “Offset 2Eh: SID: Subsystem ID Register” on page 1248 0000h 34h 34h “Offset 34h: CP: Capabilities Pointer Register” on page 1249 DCh 3Ch 3Ch “Offset 3Ch: IRQL: Interrupt Line Register” on page 1249 00h 3Dh 3Dh “Offset 3Dh: IRQP: Interrupt Pin Register” on page 1250 01h DCh DCh “Offset DCh: PCID: Power Management Capability ID Register” on page 1251 01h DDh DDh “Offset DDh: PCP: Power Management Next Capability Pointer Register” on page 1251 E4h DEh DFh “Offset DEh: PMCAP: Power Management Capability Register” on page 1252 X023h E0h E1h “Offset E0h: PMCS: Power Management Control and Status Register” on page 1253 0000h E4h E4h “Offset E4h: SCID: Signal Target Capability ID Register” on page 1254 09h E5h E5h “Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1254 F0h E6h E6h “Offset E6h: SBC: Signal Target Byte Count Register” on page 1255 09h E7h E7h “Offset E7h: STYP: Signal Target Capability Type Register” on page 1255 01h E8h E8h “Offset E8h: SMIA: Signal Target IA Mask Register” on page 1256 0h ECh ECh “Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1257 00h F0h F0h “Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on page 1258 05h F1h F1h “Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on page 1258 00h F2h F3h “Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1259 0000h

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 229 Intel® EP80579 Integrated Processor F4h F7h “Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1259 00000000h F8h F9h “Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1260 0000h Table 7-49. Bus M, Device2, Function 0: Summary of Gigabit Ethernet MAC Interface PCI Configuration Registers (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value Table 7-50. Bus M, Device 0, Function 0: Gigabit Ethernet MAC I/O Spaces Registers Offset Start Offset End Register ID - Description Default Value 0000h 0003h “Offset 0000h: IOADDR - IOADDR Register” on page 1263 0000000h 0004h 0007h “Offset 0004h: IODATA - IODATA Register” on page 1264 0000000h Table 7-51. Bus M, Device 1, Function 0: Gigabit Ethernet MAC I/O Spaces Registers Offset Start Offset End Register ID - Description Default Value 0000h 0003h “Offset 0000h: IOADDR - IOADDR Register” on page 1263 0000000h 0004h 0007h “Offset 0004h: IODATA - IODATA Register” on page 1264 0000000h Table 7-52. Bus M, Device 2, Function 0: Gigabit Ethernet MAC I/O Spaces Registers Offset Start Offset End Register ID - Description Default Value 0000h 0003h “Offset 0000h: IOADDR - IOADDR Register” on page 1263 0000000h 0004h 0007h “Offset 0004h: IODATA - IODATA Register” on page 1264 0000000h Table 7-53. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped Through CSRBAR Memory BAR (Sheet 1 of 4) Offset Start Offset End Register ID - Description Default Value 0000h 0003h “CTRL: Device Control Register” on page 1438 00000A09h 0008h 000Bh “STATUS: Device Status Register” on page 1441 0000XXXXh 0018h 001Bh “CTRL_EXT: Extended Device Control Register” on page 1442 00000000h 00E0h 00E3h “CTRL_AUX: Auxiliary Device Control Register” on page 1444 00000100h 0010h 0013h “EEPROM_CTRL - EEPROM Control Register” on page 1446 00000X1Xh 0014h 0017h “EEPROM_RR – EEPROM Read Register” on page 1448 XXXXXX00h 0028h 002Bh “FCAL: Flow Control Address Low Register” on page 1449 00c28001h 002Ch 002Fh “FCAH: Flow Control Address High Register” on page 1450 00000100h

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

230 Order Number: 320066-003US

0030h 0033h “FCT: Flow Control Type Register” on page 1451 00008808h 0038h 003Bh “VET: VLAN EtherType Register” on page 1452 00008100h 0170h 0173h “FCTTV: Flow Control Transmit Timer Value Register” on page 1452 00000000h 1000h 1003h “PBA: Packet Buffer Allocation Register” on page 1453 00100030h 00C0h 00C3h “ICR0: Interrupt 0 Cause Read Register” on page 1454 00000000h 00C4h 00C7h “ITR0: Interrupt 0 Throttling Register” on page 1457 00000000h 00C8h 00CBh “ICS0: Interrupt 0 Cause Set Register” on page 1458 00000000h 00D0h 00D3h “IMS0: Interrupt 0 Mask Set/Read Register” on page 1459 00000000h 00D8h 00DBh “IMC0: Interrupt 0 Mask Clear Register” on page 1460 00000000h 08C0h 08C3h “ICR1: Interrupt 1Cause Read Register” on page 1462 00000000h 08C8h 08CBh “ICS1: Interrupt 0 Cause Set Register” on page 1464 00000000h 08D0h 08D3h “IMS1: Interrupt 1 Mask Set/Read Register” on page 1466 00000000h 08D8h 08DBh “IMC1: Interrupt 1 Mask Clear Register” on page 1467 00000000h 08E0h 08E3h “ICR2: Error Interrupt Cause Read Register” on page 1469 00000000h 08E8h 08EBh “ICS2: Error Interrupt Cause Set Register” on page 1471 00000000h 08F0h 08F3h “IMS2: Error Interrupt Mask Set/Read Register” on page 1472 00000000h 08F8h 08FBh “IMC2: Error Interrupt Mask Clear Register” on page 1473 00000000h 0100h 0103h “RCTL: Receive Control Register” on page 1474 00000000h 2160h 2163h “FCRTL: Flow Control Receive Threshold Low Register” on page 1478 00000000h 2168h 216Bh “FCRTH: Flow Control Receive Threshold High Register” on page 1479 00000000h 2800h 2803h “RDBAL: Receive Descriptor Base Address Low Register” on page 1480 XXXXXXX0h 2804h 2807h “RDBAH: Receive Descriptor Base Address High Register” on page 1480 XXXXXXXXh 2808h 280Bh “RDLEN: Receive Descriptor Length Register” on page 1481 00000000h 2810h 2813h “RDH: Receive Descriptor Head Register” on page 1481 00000000h 2818h 281Bh “RDT: Receive Descriptor Tail Register” on page 1482 00000000h 2820h 2823h “RDTR: RX Interrupt Delay Timer (Packet Timer) Register” on page 1483 00000000h 2828h 282Bh “RXDCTL: Receive Descriptor Control Register” on page 1483 00010000h 282Ch 282Fh “RADV: Receive Interrupt Absolute Delay Timer Register” on page 1485 00000000h 2C00h 2C03h “RSRPD: Receive Small Packet Detect Interrupt Register” on page 1486 00000000h 5000h 5003h “RXCSUM: Receive Checksum Control Register” on page 1487 00000000h 5200h at 4h 5203h at 4h “MTA[0-127] – 128 Multicast Table Array Registers” on page 1488 XXXX_XXXXh 5400h at 8h 5403h at 8h “RAL[0-15] - Receive Address Low Register” on page 1488 XXXXXXXXh 5404h at 8h 5407h at 8h “RAH[0-15] - Receive Address High Register” on page 1489 000XXXXXh 5600h at 4h 5603h at 4h “VFTA[0-127] - 128 VLAN Filter Table Array Registers” on page 1490 XXXXXXXXh 0400h 0403h “TCTL: Transmit Control Register” on page 1491 00000008h 0410h 0413h “TIPG: Transmit IPG Register” on page 1493 00602008h 0458h 045Bh “AIT: Adaptive IFS Throttle Register” on page 1495 00000000h 3800h 3803h “TDBAL: Transmit Descriptor Base Address Low Register” on page 1496 XXXXXXX0h 3804h 3807h “TDBAH: Transmit Descriptor Base Address High Register” on page 1496 XXXXXXXXh Table 7-53. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped Through CSRBAR Memory BAR (Sheet 2 of 4) Offset Start Offset End Register ID - Description Default Value

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 231 Intel® EP80579 Integrated Processor 3808h 380Bh “TDLEN: Transmit Descriptor Length Register” on page 1497 00000000h 3810h 3813h “TDH: Transmit Descriptor Head Register” on page 1497 00000000h 3818h 381Bh “TDT: Transmit Descriptor Tail Register” on page 1498 00000000h 3820h 3823h “TIDV: Transmit Interrupt Delay Value Register” on page 1499 00000000h 3828h 382Bh “TXDCTL: Transmit Descriptor Control Register” on page 1500 00000000h 382Ch 382Fh “TADV: Transmit Absolute Interrupt Delay Value Register” on page 1502 00000000h 3830h 3833h “TSPMT: TCP Segmentation Pad And Minimum Threshold Register” on page 1504 01000400h 4000h 4003h “CRCERRS: CRC Error Count Register” on page 1505 00000000h 4004h 4007h “ALGNERRC: Alignment Error Count Register” on page 1506 00000000h 400Ch 400Fh “RXERRC: Receive Error Count Register” on page 1506 00000000h 4010h 4013h “MPC: Missed Packet Count Register” on page 1507 00000000h 4014h 4017h “SCC: Single Collision Count Register” on page 1507 0000h 4018h 401Bh “ECOL: Excessive Collisions Count Register” on page 1508 00000000h 401Ch 401Fh “MCC: Multiple Collision Count Register” on page 1508 00000000h 4020h 4023h “LATECOL: Late Collisions Count Register” on page 1509 00000000h 4028h 402Bh “COLC: Collision Count Register” on page 1509 00000000h 4030h 4033h “DC: Defer Count Register” on page 1510 00000000h 4034h 4037h “TNCRS: Transmit with No CRS Count Register” on page 1510 00000000h 403Ch 403Fh “CEXTERR: Carrier Extension Error Count Register” on page 1511 00000000h 4040h 4043h “RLEC: Receive Length Error Count Register” on page 1511 00000000h 4048h 404Bh “XONRXC: XON Received Count Register” on page 1512 00000000h 404Ch 404Fh “XONTXC: XON Transmitted Count Register” on page 1512 00000000h 4050h 4053h “XOFFRXC: XOFF Received Count Register” on page 1513 00000000h 4054h 4057h “XOFFTXC: XOFF Transmitted Count Register” on page 1513 00000000h 4058h 405Bh “FCRUC: FC Received Unsupported Count Register” on page 1514 00000000h 405Ch 405Fh “PRC64: Good Packets Received Count (64 Bytes) Register” on page 1514 00000000h 4060h 4063h “PRC127: Good Packets Received Count (65-127 Bytes) Register” on page 1515 00000000h 4064h 4067h “PRC255: Good Packets Received Count (128-255 Bytes) Register” on page 1515 00000000h 4068h 406Bh “PRC511 - Good Packets Received Count (256-511 Bytes) Register” on page 1516 00000000h 406Ch 406Fh “PRC1023: Good Packets Received Count (512-1023 Bytes) Register” on page 1516 00000000h 4070h 4073h “PRC1522: Good Packets Received Count (1024 to Max Bytes) Register” on page 1517 00000000h 4074h 4077h “GPRC: Good Packets Received Count (Total) Register” on page 1518 00000000h 4078h 407Bh “BPRC: Broadcast Packets Received Count Register” on page 1518 00000000h 407Ch 407Fh “MPRC: Multicast Packets Received Count Register” on page 1519 00000000h 4080h 4083h “GPTC: Good Packets Transmitted Count Register” on page 1519 00000000h 4088h 408Ah “GORCL: Good Octets Received Count Low Register” on page 1520 00000000h 408Ch 408Fh “GORCH: Good Octets Received Count High Register” on page 1521 00000000h 4090h 4093h “GOTCL: Good Octets Transmitted Count Low Register” on page 1522 00000000h Table 7-53. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped Through CSRBAR Memory BAR (Sheet 3 of 4) Offset Start Offset End Register ID - Description Default Value

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

232 Order Number: 320066-003US

4094h 4097h “GOTCH: Good Octets Transmitted Count High Register” on page 1522 00000000h 40A0h 40A3h “RNBC: Receive No Buffers Count Register” on page 1523 00000000h 40A4h 40A7h “RUC: Receive Undersize Count Register” on page 1523 00000000h 40A8h 40ABh “RFC: Receive Fragment Count Register” on page 1524 00000000h 40ACh 40AFh “ROC: Receive Oversize Count Register” on page 1524 00000000h 40B0h 40B3h “RJC: Receive Jabber Count Register” on page 1525 00000000h 40C0h 40C3h “TORL: Total Octets Received Low Register” on page 1526 00000000h 40C4h 40C7h “TORH: Total Octets Received High Register” on page 1526 00000000h 40C8h 40CFh “TOTL: Total Octets Transmitted Low Register” on page 1527 00000000h 40CCh 40CFh “TOTH: Total Octets Transmitted High Register” on page 1528 00000000h 40D0h 40D3h “TPR: Total Packets Received Register” on page 1528 00000000h 40D4h 40D7h “TPT: Total Packets Transmitted Register” on page 1529 00000000h 40D8h 40DBh “PTC64 - Packets Transmitted Count (64 Bytes) Register” on page 1529 00000000h 40E0h 40E3h “PTC255: Packets Transmitted Count (128-255 Bytes) Register” on page 1530 00000000h 40E4h 40E7h “PTC511: Packets Transmitted Count (256-511 Bytes) Register” on page 1530 00000000h 40E8h 40EBh “PTC1023: Packets Transmitted Count (512-1023 Bytes) Register” on page 1531 00000000h 40ECh 40EFh “PTC1522: Packets Transmitted Count (1024-1522 Bytes) Register” on page 1531 00000000h 40F0h 40F3h “MPTC: Multicast Packets Transmitted Count Register” on page 1532 00000000h 40F4h 40F7h “BPTC: Broadcast Packets Transmitted Count Register” on page 1532 00000000h 40F8h 40FBh “TSCTC: TCP Segmentation Context Transmitted Count Register” on page 1533 00000000h 40FCh 40FFh “TSCTFC: TCP Segmentation Context Transmit Fail Count Register” on page 1533 00000000h 5800h 5803h “WUC - Wake Up Control Register (0x05800; RW)” on page 1534 00000000h 5808h 580Bh “WUFC - Wake Up Filter Control Register (0x05808; RW)” on page 1535 00000000h 5810h 5813h “WUS - Wake Up Status Register (0x05810; RW)” on page 1536 00000000h 5838h 583Bh “IPAV - IP Address Valid Register (0x05838; RW)” on page 1537 00000000h 5840h at 8h 5843h at 8h “IP4AT (0x5840 - 0x5858; RW)[0-3]: IPv4 Address Table Registers” on page 1538 XXXXXXXXh 5880h 5883h “IPV6_ADDR0BYTES_1_4 – IPv6 Address Table Register (0x5880), Bytes 1 - 4” on page 1539 XXXXXXXXh 05884h 5887h “IPV6_ADDR0BYTES_5_8 – IPv6 Address Table Register, Bytes 5 - 8” on page 1539XXXXXXXXh 5888h 588Bh “IPV6_ADDR0BYTES_9_12 – IPv6 Address Table Register, Bytes 9 - 12” on page 1540 XXXXXXXXh 588Ch 588Fh “IPV6_ADDR0BYTES_13_16 – IPv6 Address Table Register, Bytes 13 - 16” on page 1541 XXXXXXXXh 5F00h at 8h 5F03h at 8h “FFLT[0-3] - Flexible Filter Length Table Registers (0x5F00 - 0x5F18; RW)” on page 1542 00000000h 9000h at 8h 9003h at 8h “FFMT[0-127] - Flexible Filter Mask Table Registers (0x9000 - 0x93F8; RW)” on page 1543 0000000Xh 9800h at 8h 9803h at 8h “FFVT[0-127]: Flexible Filter Value Table Registers” on page 1544 XXXXXXXXh 0510h 0513h “INTBUS_ERR_STAT - Internal Bus Error Status Register” on page 1544 00000000h 0900h 0903h “MEM_TST - Memory Error Test Register” on page 1546 00000000h 0904h 0907h “MEM_STS - Memory Error Status Register” on page 1547 007F0000h Table 7-53. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped Through CSRBAR Memory BAR (Sheet 4 of 4) Offset Start Offset End Register ID - Description Default Value

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 233 Intel® EP80579 Integrated Processor Table 7-54. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped Through CSRBAR Memory BAR (Sheet 1 of 4) Offset Start Offset End Register ID - Description Default Value 0000h 0003h “CTRL: Device Control Register” on page 1438 00000A09h 0008h 000Bh “STATUS: Device Status Register” on page 1441 0000XXXXh 0018h 001Bh “CTRL_EXT: Extended Device Control Register” on page 1442 00000000h 00E0h 00E3h “CTRL_AUX: Auxiliary Device Control Register” on page 1444 00000100h 0010h 0013h “EEPROM_CTRL - EEPROM Control Register” on page 1446 00000X1Xh 0014h 0017h “EEPROM_RR – EEPROM Read Register” on page 1448 XXXXXX00h 0028h 002Bh “FCAL: Flow Control Address Low Register” on page 1449 00c28001h 002Ch 002Fh “FCAH: Flow Control Address High Register” on page 1450 00000100h 0030h 0033h “FCT: Flow Control Type Register” on page 1451 00008808h 0038h 003Bh “VET: VLAN EtherType Register” on page 1452 00008100h 0170h 0173h “FCTTV: Flow Control Transmit Timer Value Register” on page 1452 00000000h 1000h 1003h “PBA: Packet Buffer Allocation Register” on page 1453 00100030h 00C0h 00C3h “ICR0: Interrupt 0 Cause Read Register” on page 1454 00000000h 00C4h 00C7h “ITR0: Interrupt 0 Throttling Register” on page 1457 00000000h 00C8h 00CBh “ICS0: Interrupt 0 Cause Set Register” on page 1458 00000000h 00D0h 00D3h “IMS0: Interrupt 0 Mask Set/Read Register” on page 1459 00000000h 00D8h 00DBh “IMC0: Interrupt 0 Mask Clear Register” on page 1460 00000000h 08C0h 08C3h “ICR1: Interrupt 1Cause Read Register” on page 1462 00000000h 08C8h 08CBh “ICS1: Interrupt 0 Cause Set Register” on page 1464 00000000h 08D0h 08D3h “IMS1: Interrupt 1 Mask Set/Read Register” on page 1466 00000000h 08D8h 08DBh “IMC1: Interrupt 1 Mask Clear Register” on page 1467 00000000h 08E0h 08E3h “ICR2: Error Interrupt Cause Read Register” on page 1469 00000000h 08E8h 08EBh “ICS2: Error Interrupt Cause Set Register” on page 1471 00000000h 08F0h 08F3h “IMS2: Error Interrupt Mask Set/Read Register” on page 1472 00000000h 08F8h 08FBh “IMC2: Error Interrupt Mask Clear Register” on page 1473 00000000h 0100h 0103h “RCTL: Receive Control Register” on page 1474 00000000h 2160h 2163h “FCRTL: Flow Control Receive Threshold Low Register” on page 1478 00000000h 2168h 216Bh “FCRTH: Flow Control Receive Threshold High Register” on page 1479 00000000h 2800h 2803h “RDBAL: Receive Descriptor Base Address Low Register” on page 1480 XXXXXXX0h 2804h 2807h “RDBAH: Receive Descriptor Base Address High Register” on page 1480 XXXXXXXXh 2808h 280Bh “RDLEN: Receive Descriptor Length Register” on page 1481 00000000h 2810h 2813h “RDH: Receive Descriptor Head Register” on page 1481 00000000h 2818h 281Bh “RDT: Receive Descriptor Tail Register” on page 1482 00000000h 2820h 2823h “RDTR: RX Interrupt Delay Timer (Packet Timer) Register” on page 1483 00000000h 2828h 282Bh “RXDCTL: Receive Descriptor Control Register” on page 1483 00010000h 282Ch 282Fh “RADV: Receive Interrupt Absolute Delay Timer Register” on page 1485 00000000h

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

234 Order Number: 320066-003US

2C00h 2C03h “RSRPD: Receive Small Packet Detect Interrupt Register” on page 1486 00000000h 5000h 5003h “RXCSUM: Receive Checksum Control Register” on page 1487 00000000h 5200h at 4h 5203h at 4h “MTA[0-127] – 128 Multicast Table Array Registers” on page 1488 XXXX_XXXXh 5400h at 8h 5403h at 8h “RAL[0-15] - Receive Address Low Register” on page 1488 XXXXXXXXh 5404h at 8h 5407h at 8h “RAH[0-15] - Receive Address High Register” on page 1489 000XXXXXh 5600h at 4h 5603h at 4h “VFTA[0-127] - 128 VLAN Filter Table Array Registers” on page 1490 XXXXXXXXh 0400h 0403h “TCTL: Transmit Control Register” on page 1491 00000008h 0410h 0413h “TIPG: Transmit IPG Register” on page 1493 00602008h 0458h 045Bh “AIT: Adaptive IFS Throttle Register” on page 1495 00000000h 3800h 3803h “TDBAL: Transmit Descriptor Base Address Low Register” on page 1496 XXXXXXX0h 3804h 3807h “TDBAH: Transmit Descriptor Base Address High Register” on page 1496 XXXXXXXXh 3808h 380Bh “TDLEN: Transmit Descriptor Length Register” on page 1497 00000000h 3810h 3813h “TDH: Transmit Descriptor Head Register” on page 1497 00000000h 3818h 381Bh “TDT: Transmit Descriptor Tail Register” on page 1498 00000000h 3820h 3823h “TIDV: Transmit Interrupt Delay Value Register” on page 1499 00000000h 3828h 382Bh “TXDCTL: Transmit Descriptor Control Register” on page 1500 00000000h 382Ch 382Fh “TADV: Transmit Absolute Interrupt Delay Value Register” on page 1502 00000000h 3830h 3833h “TSPMT: TCP Segmentation Pad And Minimum Threshold Register” on page 1504 01000400h 4000h 4003h “CRCERRS: CRC Error Count Register” on page 1505 00000000h 4004h 4007h “ALGNERRC: Alignment Error Count Register” on page 1506 00000000h 400Ch 400Fh “RXERRC: Receive Error Count Register” on page 1506 00000000h 4010h 4013h “MPC: Missed Packet Count Register” on page 1507 00000000h 4014h 4017h “SCC: Single Collision Count Register” on page 1507 0000h 4018h 401Bh “ECOL: Excessive Collisions Count Register” on page 1508 00000000h 401Ch 401Fh “MCC: Multiple Collision Count Register” on page 1508 00000000h 4020h 4023h “LATECOL: Late Collisions Count Register” on page 1509 00000000h 4028h 402Bh “COLC: Collision Count Register” on page 1509 00000000h 4030h 4033h “DC: Defer Count Register” on page 1510 00000000h 4034h 4037h “TNCRS: Transmit with No CRS Count Register” on page 1510 00000000h 403Ch 403Fh “CEXTERR: Carrier Extension Error Count Register” on page 1511 00000000h 4040h 4043h “RLEC: Receive Length Error Count Register” on page 1511 00000000h 4048h 404Bh “XONRXC: XON Received Count Register” on page 1512 00000000h 404Ch 404Fh “XONTXC: XON Transmitted Count Register” on page 1512 00000000h 4050h 4053h “XOFFRXC: XOFF Received Count Register” on page 1513 00000000h 4054h 4057h “XOFFTXC: XOFF Transmitted Count Register” on page 1513 00000000h 4058h 405Bh “FCRUC: FC Received Unsupported Count Register” on page 1514 00000000h 405Ch 405Fh “PRC64: Good Packets Received Count (64 Bytes) Register” on page 1514 00000000h 4060h 4063h “PRC127: Good Packets Received Count (65-127 Bytes) Register” on page 1515 00000000h 4064h 4067h “PRC255: Good Packets Received Count (128-255 Bytes) Register” on page 1515 00000000h Table 7-54. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped Through CSRBAR Memory BAR (Sheet 2 of 4) Offset Start Offset End Register ID - Description Default Value

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 235 Intel® EP80579 Integrated Processor 4068h 406Bh “PRC511 - Good Packets Received Count (256-511 Bytes) Register” on page 1516 00000000h 406Ch 406Fh “PRC1023: Good Packets Received Count (512-1023 Bytes) Register” on page 1516 00000000h 4070h 4073h “PRC1522: Good Packets Received Count (1024 to Max Bytes) Register” on page 1517 00000000h 4074h 4077h “GPRC: Good Packets Received Count (Total) Register” on page 1518 00000000h 4078h 407Bh “BPRC: Broadcast Packets Received Count Register” on page 1518 00000000h 407Ch 407Fh “MPRC: Multicast Packets Received Count Register” on page 1519 00000000h 4080h 4083h “GPTC: Good Packets Transmitted Count Register” on page 1519 00000000h 4088h 408Ah “GORCL: Good Octets Received Count Low Register” on page 1520 00000000h 408Ch 408Fh “GORCH: Good Octets Received Count High Register” on page 1521 00000000h 4090h 4093h “GOTCL: Good Octets Transmitted Count Low Register” on page 1522 00000000h 4094h 4097h “GOTCH: Good Octets Transmitted Count High Register” on page 1522 00000000h 40A0h 40A3h “RNBC: Receive No Buffers Count Register” on page 1523 00000000h 40A4h 40A7h “RUC: Receive Undersize Count Register” on page 1523 00000000h 40A8h 40ABh “RFC: Receive Fragment Count Register” on page 1524 00000000h 40ACh 40AFh “ROC: Receive Oversize Count Register” on page 1524 00000000h 40B0h 40B3h “RJC: Receive Jabber Count Register” on page 1525 00000000h 40C0h 40C3h “TORL: Total Octets Received Low Register” on page 1526 00000000h 40C4h 40C7h “TORH: Total Octets Received High Register” on page 1526 00000000h 40C8h 40CFh “TOTL: Total Octets Transmitted Low Register” on page 1527 00000000h 40CCh 40CFh “TOTH: Total Octets Transmitted High Register” on page 1528 00000000h 40D0h 40D3h “TPR: Total Packets Received Register” on page 1528 00000000h 40D4h 40D7h “TPT: Total Packets Transmitted Register” on page 1529 00000000h 40D8h 40DBh “PTC64 - Packets Transmitted Count (64 Bytes) Register” on page 1529 00000000h 40E0h 40E3h “PTC255: Packets Transmitted Count (128-255 Bytes) Register” on page 1530 00000000h 40E4h 40E7h “PTC511: Packets Transmitted Count (256-511 Bytes) Register” on page 1530 00000000h 40E8h 40EBh “PTC1023: Packets Transmitted Count (512-1023 Bytes) Register” on page 1531 00000000h 40ECh 40EFh “PTC1522: Packets Transmitted Count (1024-1522 Bytes) Register” on page 1531 00000000h 40F0h 40F3h “MPTC: Multicast Packets Transmitted Count Register” on page 1532 00000000h 40F4h 40F7h “BPTC: Broadcast Packets Transmitted Count Register” on page 1532 00000000h 40F8h 40FBh “TSCTC: TCP Segmentation Context Transmitted Count Register” on page 1533 00000000h 40FCh 40FFh “TSCTFC: TCP Segmentation Context Transmit Fail Count Register” on page 1533 00000000h 5800h 5803h “WUC - Wake Up Control Register (0x05800; RW)” on page 1534 00000000h 5808h 580Bh “WUFC - Wake Up Filter Control Register (0x05808; RW)” on page 1535 00000000h 5810h 5813h “WUS - Wake Up Status Register (0x05810; RW)” on page 1536 00000000h 5838h 583Bh “IPAV - IP Address Valid Register (0x05838; RW)” on page 1537 00000000h 5840h at 8h 5843h at 8h “IP4AT (0x5840 - 0x5858; RW)[0-3]: IPv4 Address Table Registers” on page 1538 XXXXXXXXh 5880h 5883h “IPV6_ADDR0BYTES_1_4 – IPv6 Address Table Register (0x5880), Bytes 1 - 4” on page 1539 XXXXXXXXh Table 7-54. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped Through CSRBAR Memory BAR (Sheet 3 of 4) Offset Start Offset End Register ID - Description Default Value

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

236 Order Number: 320066-003US

05884h 5887h “IPV6_ADDR0BYTES_5_8 – IPv6 Address Table Register, Bytes 5 - 8” on page 1539XXXXXXXXh 5888h 588Bh “IPV6_ADDR0BYTES_9_12 – IPv6 Address Table Register, Bytes 9 - 12” on page 1540 XXXXXXXXh 588Ch 588Fh “IPV6_ADDR0BYTES_13_16 – IPv6 Address Table Register, Bytes 13 - 16” on page 1541 XXXXXXXXh 5F00h at 8h 5F03h at 8h “FFLT[0-3] - Flexible Filter Length Table Registers (0x5F00 - 0x5F18; RW)” on page 1542 00000000h 9000h at 8h 9003h at 8h “FFMT[0-127] - Flexible Filter Mask Table Registers (0x9000 - 0x93F8; RW)” on page 1543 0000000Xh 9800h at 8h 9803h at 8h “FFVT[0-127]: Flexible Filter Value Table Registers” on page 1544 XXXXXXXXh 0510h 0513h “INTBUS_ERR_STAT - Internal Bus Error Status Register” on page 1544 00000000h 0900h 0903h “MEM_TST - Memory Error Test Register” on page 1546 00000000h 0904h 0907h “MEM_STS - Memory Error Status Register” on page 1547 007F0000h Table 7-54. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped Through CSRBAR Memory BAR (Sheet 4 of 4) Offset Start Offset End Register ID - Description Default Value Table 7-55. Bus M, Devices 2, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped Through CSRBAR Memory BAR (Sheet 1 of 4) Offset Start Offset End Register ID - Description Default Value 0000h 0003h “CTRL: Device Control Register” on page 1438 00000A09h 0008h 000Bh “STATUS: Device Status Register” on page 1441 0000XXXXh 0018h 001Bh “CTRL_EXT: Extended Device Control Register” on page 1442 00000000h 00E0h 00E3h “CTRL_AUX: Auxiliary Device Control Register” on page 1444 00000100h 0010h 0013h “EEPROM_CTRL - EEPROM Control Register” on page 1446 00000X1Xh 0014h 0017h “EEPROM_RR – EEPROM Read Register” on page 1448 XXXXXX00h 0028h 002Bh “FCAL: Flow Control Address Low Register” on page 1449 00c28001h 002Ch 002Fh “FCAH: Flow Control Address High Register” on page 1450 00000100h 0030h 0033h “FCT: Flow Control Type Register” on page 1451 00008808h 0038h 003Bh “VET: VLAN EtherType Register” on page 1452 00008100h 0170h 0173h “FCTTV: Flow Control Transmit Timer Value Register” on page 1452 00000000h 1000h 1003h “PBA: Packet Buffer Allocation Register” on page 1453 00100030h 00C0h 00C3h “ICR0: Interrupt 0 Cause Read Register” on page 1454 00000000h 00C4h 00C7h “ITR0: Interrupt 0 Throttling Register” on page 1457 00000000h 00C8h 00CBh “ICS0: Interrupt 0 Cause Set Register” on page 1458 00000000h 00D0h 00D3h “IMS0: Interrupt 0 Mask Set/Read Register” on page 1459 00000000h 00D8h 00DBh “IMC0: Interrupt 0 Mask Clear Register” on page 1460 00000000h 08C0h 08C3h “ICR1: Interrupt 1Cause Read Register” on page 1462 00000000h 08C8h 08CBh “ICS1: Interrupt 0 Cause Set Register” on page 1464 00000000h 08D0h 08D3h “IMS1: Interrupt 1 Mask Set/Read Register” on page 1466 00000000h 08D8h 08DBh “IMC1: Interrupt 1 Mask Clear Register” on page 1467 00000000h

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 237 Intel® EP80579 Integrated Processor 08E0h 08E3h “ICR2: Error Interrupt Cause Read Register” on page 1469 00000000h 08E8h 08EBh “ICS2: Error Interrupt Cause Set Register” on page 1471 00000000h 08F0h 08F3h “IMS2: Error Interrupt Mask Set/Read Register” on page 1472 00000000h 08F8h 08FBh “IMC2: Error Interrupt Mask Clear Register” on page 1473 00000000h 0100h 0103h “RCTL: Receive Control Register” on page 1474 00000000h 2160h 2163h “FCRTL: Flow Control Receive Threshold Low Register” on page 1478 00000000h 2168h 216Bh “FCRTH: Flow Control Receive Threshold High Register” on page 1479 00000000h 2800h 2803h “RDBAL: Receive Descriptor Base Address Low Register” on page 1480 XXXXXXX0h 2804h 2807h “RDBAH: Receive Descriptor Base Address High Register” on page 1480 XXXXXXXXh 2808h 280Bh “RDLEN: Receive Descriptor Length Register” on page 1481 00000000h 2810h 2813h “RDH: Receive Descriptor Head Register” on page 1481 00000000h 2818h 281Bh “RDT: Receive Descriptor Tail Register” on page 1482 00000000h 2820h 2823h “RDTR: RX Interrupt Delay Timer (Packet Timer) Register” on page 1483 00000000h 2828h 282Bh “RXDCTL: Receive Descriptor Control Register” on page 1483 00010000h 282Ch 282Fh “RADV: Receive Interrupt Absolute Delay Timer Register” on page 1485 00000000h 2C00h 2C03h “RSRPD: Receive Small Packet Detect Interrupt Register” on page 1486 00000000h 5000h 5003h “RXCSUM: Receive Checksum Control Register” on page 1487 00000000h 5200h at 4h 5203h at 4h “MTA[0-127] – 128 Multicast Table Array Registers” on page 1488 XXXX_XXXXh 5400h at 8h 5403h at 8h “RAL[0-15] - Receive Address Low Register” on page 1488 XXXXXXXXh 5404h at 8h 5407h at 8h “RAH[0-15] - Receive Address High Register” on page 1489 000XXXXXh 5600h at 4h 5603h at 4h “VFTA[0-127] - 128 VLAN Filter Table Array Registers” on page 1490 XXXXXXXXh 0400h 0403h “TCTL: Transmit Control Register” on page 1491 00000008h 0410h 0413h “TIPG: Transmit IPG Register” on page 1493 00602008h 0458h 045Bh “AIT: Adaptive IFS Throttle Register” on page 1495 00000000h 3800h 3803h “TDBAL: Transmit Descriptor Base Address Low Register” on page 1496 XXXXXXX0h 3804h 3807h “TDBAH: Transmit Descriptor Base Address High Register” on page 1496 XXXXXXXXh 3808h 380Bh “TDLEN: Transmit Descriptor Length Register” on page 1497 00000000h 3810h 3813h “TDH: Transmit Descriptor Head Register” on page 1497 00000000h 3818h 381Bh “TDT: Transmit Descriptor Tail Register” on page 1498 00000000h 3820h 3823h “TIDV: Transmit Interrupt Delay Value Register” on page 1499 00000000h 3828h 382Bh “TXDCTL: Transmit Descriptor Control Register” on page 1500 00000000h 382Ch 382Fh “TADV: Transmit Absolute Interrupt Delay Value Register” on page 1502 00000000h 3830h 3833h “TSPMT: TCP Segmentation Pad And Minimum Threshold Register” on page 1504 01000400h 4000h 4003h “CRCERRS: CRC Error Count Register” on page 1505 00000000h 4004h 4007h “ALGNERRC: Alignment Error Count Register” on page 1506 00000000h 400Ch 400Fh “RXERRC: Receive Error Count Register” on page 1506 00000000h 4010h 4013h “MPC: Missed Packet Count Register” on page 1507 00000000h 4014h 4017h “SCC: Single Collision Count Register” on page 1507 0000h 4018h 401Bh “ECOL: Excessive Collisions Count Register” on page 1508 00000000h Table 7-55. Bus M, Devices 2, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped Through CSRBAR Memory BAR (Sheet 2 of 4) Offset Start Offset End Register ID - Description Default Value

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401Ch 401Fh “MCC: Multiple Collision Count Register” on page 1508 00000000h 4020h 4023h “LATECOL: Late Collisions Count Register” on page 1509 00000000h 4028h 402Bh “COLC: Collision Count Register” on page 1509 00000000h 4030h 4033h “DC: Defer Count Register” on page 1510 00000000h 4034h 4037h “TNCRS: Transmit with No CRS Count Register” on page 1510 00000000h 403Ch 403Fh “CEXTERR: Carrier Extension Error Count Register” on page 1511 00000000h 4040h 4043h “RLEC: Receive Length Error Count Register” on page 1511 00000000h 4048h 404Bh “XONRXC: XON Received Count Register” on page 1512 00000000h 404Ch 404Fh “XONTXC: XON Transmitted Count Register” on page 1512 00000000h 4050h 4053h “XOFFRXC: XOFF Received Count Register” on page 1513 00000000h 4054h 4057h “XOFFTXC: XOFF Transmitted Count Register” on page 1513 00000000h 4058h 405Bh “FCRUC: FC Received Unsupported Count Register” on page 1514 00000000h 405Ch 405Fh “PRC64: Good Packets Received Count (64 Bytes) Register” on page 1514 00000000h 4060h 4063h “PRC127: Good Packets Received Count (65-127 Bytes) Register” on page 1515 00000000h 4064h 4067h “PRC255: Good Packets Received Count (128-255 Bytes) Register” on page 1515 00000000h 4068h 406Bh “PRC511 - Good Packets Received Count (256-511 Bytes) Register” on page 1516 00000000h 406Ch 406Fh “PRC1023: Good Packets Received Count (512-1023 Bytes) Register” on page 1516 00000000h 4070h 4073h “PRC1522: Good Packets Received Count (1024 to Max Bytes) Register” on page 1517 00000000h 4074h 4077h “GPRC: Good Packets Received Count (Total) Register” on page 1518 00000000h 4078h 407Bh “BPRC: Broadcast Packets Received Count Register” on page 1518 00000000h 407Ch 407Fh “MPRC: Multicast Packets Received Count Register” on page 1519 00000000h 4080h 4083h “GPTC: Good Packets Transmitted Count Register” on page 1519 00000000h 4088h 408Ah “GORCL: Good Octets Received Count Low Register” on page 1520 00000000h 408Ch 408Fh “GORCH: Good Octets Received Count High Register” on page 1521 00000000h 4090h 4093h “GOTCL: Good Octets Transmitted Count Low Register” on page 1522 00000000h 4094h 4097h “GOTCH: Good Octets Transmitted Count High Register” on page 1522 00000000h 40A0h 40A3h “RNBC: Receive No Buffers Count Register” on page 1523 00000000h 40A4h 40A7h “RUC: Receive Undersize Count Register” on page 1523 00000000h 40A8h 40ABh “RFC: Receive Fragment Count Register” on page 1524 00000000h 40ACh 40AFh “ROC: Receive Oversize Count Register” on page 1524 00000000h 40B0h 40B3h “RJC: Receive Jabber Count Register” on page 1525 00000000h 40C0h 40C3h “TORL: Total Octets Received Low Register” on page 1526 00000000h 40C4h 40C7h “TORH: Total Octets Received High Register” on page 1526 00000000h 40C8h 40CFh “TOTL: Total Octets Transmitted Low Register” on page 1527 00000000h 40CCh 40CFh “TOTH: Total Octets Transmitted High Register” on page 1528 00000000h 40D0h 40D3h “TPR: Total Packets Received Register” on page 1528 00000000h 40D4h 40D7h “TPT: Total Packets Transmitted Register” on page 1529 00000000h 40D8h 40DBh “PTC64 - Packets Transmitted Count (64 Bytes) Register” on page 1529 00000000h Table 7-55. Bus M, Devices 2, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped Through CSRBAR Memory BAR (Sheet 3 of 4) Offset Start Offset End Register ID - Description Default Value

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 239 Intel® EP80579 Integrated Processor 40E0h 40E3h “PTC255: Packets Transmitted Count (128-255 Bytes) Register” on page 1530 00000000h 40E4h 40E7h “PTC511: Packets Transmitted Count (256-511 Bytes) Register” on page 1530 00000000h 40E8h 40EBh “PTC1023: Packets Transmitted Count (512-1023 Bytes) Register” on page 1531 00000000h 40ECh 40EFh “PTC1522: Packets Transmitted Count (1024-1522 Bytes) Register” on page 1531 00000000h 40F0h 40F3h “MPTC: Multicast Packets Transmitted Count Register” on page 1532 00000000h 40F4h 40F7h “BPTC: Broadcast Packets Transmitted Count Register” on page 1532 00000000h 40F8h 40FBh “TSCTC: TCP Segmentation Context Transmitted Count Register” on page 1533 00000000h 40FCh 40FFh “TSCTFC: TCP Segmentation Context Transmit Fail Count Register” on page 1533 00000000h 5800h 5803h “WUC - Wake Up Control Register (0x05800; RW)” on page 1534 00000000h 5808h 580Bh “WUFC - Wake Up Filter Control Register (0x05808; RW)” on page 1535 00000000h 5810h 5813h “WUS - Wake Up Status Register (0x05810; RW)” on page 1536 00000000h 5838h 583Bh “IPAV - IP Address Valid Register (0x05838; RW)” on page 1537 00000000h 5840h at 8h 5607h at 8h “IP4AT (0x5840 - 0x5858; RW)[0-3]: IPv4 Address Table Registers” on page 1538 XXXXXXXXh 5880h 5883h “IPV6_ADDR0BYTES_1_4 – IPv6 Address Table Register (0x5880), Bytes 1 - 4” on page 1539 XXXXXXXXh 05884h 0588Fh “IPV6_ADDR0BYTES_5_8 – IPv6 Address Table Register, Bytes 5 - 8” on page 1539XXXXXXXXh 5888h 588Bh “IPV6_ADDR0BYTES_9_12 – IPv6 Address Table Register, Bytes 9 - 12” on page 1540 XXXXXXXXh 588Ch 588Fh “IPV6_ADDR0BYTES_13_16 – IPv6 Address Table Register, Bytes 13 - 16” on page 1541 XXXXXXXXh 5F00h at 8h 5F03h at 8h “FFLT[0-3] - Flexible Filter Length Table Registers (0x5F00 - 0x5F18; RW)” on page 1542 00000000h 9000h at 8h 9003h at 8h “FFMT[0-127] - Flexible Filter Mask Table Registers (0x9000 - 0x93F8; RW)” on page 1543 0000000Xh 9800h at 8h 9803h at 8h “FFVT[0-127]: Flexible Filter Value Table Registers” on page 1544 XXXXXXXXh 0510h 0513h “INTBUS_ERR_STAT - Internal Bus Error Status Register” on page 1544 00000000h 0900h 0903h “MEM_TST - Memory Error Test Register” on page 1546 00000000h 0904h 0907h “MEM_STS - Memory Error Status Register” on page 1547 007F0000h Table 7-55. Bus M, Devices 2, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped Through CSRBAR Memory BAR (Sheet 4 of 4) Offset Start Offset End Register ID - Description Default Value

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

240 Order Number: 320066-003US

7.4.3 GCU: Bus M, Device 3, Function 0

The GCU includes the registers listed in Table 7-56 and Table 7-57. These registers materialize in PCI configuration and memory (via PCI BAR) spaces. See Section 35.8, “GCU Configuration Space: Bus M, Device 3, Function 0”and Chapter 38.0, “Register Summary” for detailed discussion of these registers along with alternative materializations. Table 7-56. Bus M, Device 3, Function 0: Summary of GCU PCI Configuration Registers Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID: Vendor Identification Register” on page 1265 8086h 02h 03h “Offset 02h: DID: Device Identification Register” on page 1266 503Eh 04h 05h “Offset 04h: PCICMD: Device Command Register” on page 1266 0000h 06h 07h “Offset 06h: PCISTS: PCI Device Status Register” on page 1267 0010h 08h 08h “Offset 08h: RID: Revision ID Register” on page 1268 Variable 09h 0Bh “Offset 09h: CC: Class Code Register” on page 1268 FF0000h 0Eh 0Eh “Offset 0Eh: HDR: Header Type Register” on page 1268 00h 10h 13h “Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on page 1269 00000000h 2Ch 2Dh “Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1269 0000h 2Eh 2Fh “Offset 2Eh: SID: Subsystem ID Register” on page 1270 0000h 34h 34h “Offset 34h: CP: Capabilities Pointer Register” on page 1270 DCh DCh DCh “Offset DCh: PCID: Power Management Capability ID Register” on page 1270 01h DDh DDh “Offset DDh: PCP: Power Management Next Capability Pointer Register” on page 1271 00h DEh DFh “Offset DEh: PMCAP: Power Management Capability Register” on page 1271 0023h E0h E1h “Offset E0h: PMCS: Power Management Control and Status Register” on page 1272 0000h Table 7-57. Bus M, Device 3, Function 0: Summary of GCU Registers Mapped Through CSRBAR Memory BAR (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00000010h 00000013h “Offset 0x00000010h: MDIO_STATUS - MDIO Status Register” on page 1562 00000000h 00000014h 00000017h “Offset 0x00000014h: MDIO_COMMAND - MDIO Command Register” on page 1562 00000000h 00000018h 0000001Bh “Offset 0x00000018h: MDIO_DRIVE - MDIO Drive Register” on page 1563 03030107h 00000020h 00000023h “Offset 0x00000020h: MDC_DRIVE - MDC Drive Register” on page 1563 0303030Fh 00000024h 00000027h “Offset 0x00000024h: GCU_GBE_RC_CTRL - GCU GbE RCOMP Control Register” on page 1564 0031F31Fh 00000044h 00000047h “Offset 0x00000044h: GCU_GBE_RC_STAT - GCU GbE RCOMP Status Register” on page 1564 00000000h 00000050h 00000053h “Offset 0x00000050h: GCU_LEB_RC_STAT - GCU Local Expansion Bus RCOMP Status Register” on page 1565 63000300h

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 241 Intel® EP80579 Integrated Processor 00000054h 00000057h “Offset 0x00000054h: GCU_LEB_RC_CTRL - GCU Local Expansion Bus RCOMP Control Register” on page 1566 000030F301h 00000060h 00000063h “Offset 0x00000060h: SSP_DRIVE - SSP Drive Register” on page 1566 02000200h 00000064h 00000067h “Offset 0x00000064h: TDM_DRIVE_3 - TDM Drive Register for TDM ports 3” on page 1567 02000200h 00000068h 0000006Bh “Offset 0x00000068h: TDM_DRIVE_12 - TDM Drive Register for TDM ports 1 & 2” on page 1567 02000200h 00000028h 0000002Bh “Offset 0x00000028h: CAN_DRIVE - CAN Drive Register” on page 1568 02000200h Table 7-57. Bus M, Device 3, Function 0: Summary of GCU Registers Mapped Through CSRBAR Memory BAR (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

242 Order Number: 320066-003US

7.4.4 CAN Interface: Bus M, Device 4 and 5, Function 0

The CAN interface includes the registers listed in Table 7-58 through Table 7-61. These registers materialize in PCI configuration and memory (via PCI BAR) spaces. See Section 35.9, “CAN Controller Configuration Spaces: Bus M, Device 4-5, Function 0” and Chapter 39.0, “Detailed Register Descriptions” for detailed discussion of these registers along with alternative materializations. Table 7-58. Bus M, Device 4, Function 0: Summary of CAN Interface PCI Configuration Registers Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID: Vendor Identification Register” on page 1275 8086h 02h 03h “Offset 02h: DID: Device Identification Register” on page 1275 5039h 04h 05h “Offset 04h: PCICMD: Device Command Register” on page 1276 0h 06h 07h “Offset 06h: PCISTS: PCI Device Status Register” on page 1277 10h 08h 08h “Offset 08h: RID: Revision ID Register” on page 1278 Variable 09h 0Bh “Offset 09h: CC: Class Code Register” on page 1278 0C0900h 0Eh 0Eh “Offset 0Eh: HDR: Header Type Register” on page 1279 00h 10h 13h “Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on page 1279 00000000h 2Ch 2Dh “Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1280 0000h 2Eh 2Fh “Offset 2Eh: SID: Subsystem ID Register” on page 1280 0000h 34h 34h “Offset 34h: CP: Capabilities Pointer Register” on page 1281 DCh 3Ch 3Ch “Offset 3Ch: IRQL: Interrupt Line Register” on page 1281 00h 3Dh 3Dh “Offset 3Dh: IRQP: Interrupt Pin Register” on page 1282 01h 40h 40h “Offset 40h: CANCTL - CAN Control Register” on page 1282 00h DCh DCh “Offset DCh: PCID: Power Management Capability ID Register” on page 1283 01h DDh DDh “Offset DDh: PCP: Power Management Next Capability Pointer Register” on page 1283 E4h DEh DFh “Offset DEh: PMCAP: Power Management Capability Register” on page 1284 0023h E0h E1h “Offset E0h: PMCS: Power Management Control and Status Register” on page 1284 0000h E4h E4h “Offset E4h: SCID: Signal Target Capability ID Register” on page 1285 09h E5h E5h “Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1285 F0h E6h E6h “Offset E6h: SBC: Signal Target Byte Count Register” on page 1286 09h E7h E7h “Offset E7h: STYP: Signal Target Capability Type Register” on page 1286 01h E8h E8h “Offset E8h: SMIA: Signal Target IA Mask Register” on page 1287 0h ECh ECh “Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1287 00h F0h F0h “Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on page 1288 05h F1h F1h “Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on page 1288 00h F2h F3h “Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1289 0000h F4h F7h “Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1289 00000000h F8h F9h “Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1290 0000h

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 243 Intel® EP80579 Integrated Processor Table 7-59. Bus M, Devices 5, Function 0: Summary of CAN Interface PCI Configuration Registers Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID: Vendor Identification Register” on page 1275 8086h 02h 03h “Offset 02h: DID: Device Identification Register” on page 1276 503Ah 04h 05h “Offset 04h: PCICMD: Device Command Register” on page 1276 0h 06h 07h “Offset 06h: PCISTS: PCI Device Status Register” on page 1277 10h 08h 08h “Offset 08h: RID: Revision ID Register” on page 1278 Variable 09h 0Bh “Offset 09h: CC: Class Code Register” on page 1278 0C0900h 0Eh 0Eh “Offset 0Eh: HDR: Header Type Register” on page 1279 00h 10h 13h “Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on page 1279 00000000h 2Ch 2Dh “Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1280 0000h 2Eh 2Fh “Offset 2Eh: SID: Subsystem ID Register” on page 1280 0000h 34h 34h “Offset 34h: CP: Capabilities Pointer Register” on page 1281 DCh 3Ch 3Ch “Offset 3Ch: IRQL: Interrupt Line Register” on page 1281 00h 3Dh 3Dh “Offset 3Dh: IRQP: Interrupt Pin Register” on page 1282 01h 40h 40h “Offset 40h: CANCTL - CAN Control Register” on page 1282 00h DCh DCh “Offset DCh: PCID: Power Management Capability ID Register” on page 1283 01h DDh DDh “Offset DDh: PCP: Power Management Next Capability Pointer Register” on page 1283 E4h DEh DFh “Offset DEh: PMCAP: Power Management Capability Register” on page 1284 0023h E0h E1h “Offset E0h: PMCS: Power Management Control and Status Register” on page 1284 0000h E4h E4h “Offset E4h: SCID: Signal Target Capability ID Register” on page 1285 09h E5h E5h “Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1285 F0h E6h E6h “Offset E6h: SBC: Signal Target Byte Count Register” on page 1286 09h E7h E7h “Offset E7h: STYP: Signal Target Capability Type Register” on page 1286 01h E8h E8h “Offset E8h: SMIA: Signal Target IA Mask Register” on page 1287 0h ECh ECh “Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1287 00h F0h F0h “Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on page 1288 05h F1h F1h “Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on page 1288 00h F2h F3h “Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1289 0000h F4h F7h “Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1289 00000000h F8h F9h “Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1290 0000h

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

244 Order Number: 320066-003US

Table 7-60. Bus M, Device 4, Function 0: Summary of CAN Registers Mapped Through CSRBAR Memory BAR Offset Start Offset End Register ID - Description Default Value 00000000h 00000003h “Offset 00000000h: Int_Status - Interrupt Status Register” on page 1587 00000000h 00000004h 00000007h “Offset 00000004h: Int_Ebl - Interrupt Enable Register” on page 1588 00000000h 00000008h 0000000Ah “Offset 00000008h: Buffer Status Indicators” on page 1589 00000000h 0000000Ch 0000000Fh “Offset 0000000Ch: ErrorStatus - Error Status Indicators” on page 1590 00000000h 00000010h 00000013h “Offset 00000010h: Command - Operating Modes” on page 1591 00000000h 00000014h 00000017h “Offset 00000014h: Config - CAN Configuration Register” on page 1592 00000000h 00000020h at 10h 00000023h at 10h “Offset 00000020h: TxMessageControl[0-7] - Transmit Message Control and Command” on page 1593 XXXXXXXXh 00000024h at 10h 00000027h at 10h “Offset 00000024h: TxMessageID[0-7] - Transmit Message ID” on page 1595 XXXXXXXXh 00000028h at 10h 0000002Ah at 10h “Offset 00000028h: TxMessageDataHigh[0-7] - Transmit Message Data High” on page 1596 XXXXXXXXh 0000002Ch at 10h 0000002Fh at 10h “Offset 0000002Ch: TxMessageDataLow[0-7] - Transmit Message Data Low” on page 1597 XXXXXXXXh 000000A0h at 20h 000000A3h at 20h “Offset 000000A0h: RxMessageControl[0-15] - Receive Message Command and Control” on page 1598 XXXXXXXXh 000000A4h at 20h 000000A7h at 20h “Offset 000000A4h: RxMessageID[0-15] - Receive Message ID” on page 1600 XXXXXXXXh 000000A8h at 20h 000000ABh at 20h “Offset 000000A8h: RxMessageDataHigh[0-15] - Receive Message Data High” on page 1600 XXXXXXXXh 000000ACh at 20h 000000AFh at 20h “Offset 000000ACh: RxMessageDataLow[0-15] - Receive Message Data Low” on page 1601 XXXXXXXXh 000000B0h at 20h 000000B3h at 20h “Offset 000000B0h: RxMessageAMR[0-15] - Receive Message AMR” on page 1601 XXXXXXXh 000000B4h at 20h 000000B7h at 20h “Offset 000000B4h: RxMessageACR[0-15] - Receive Message ACR” on page 1602 XXXXXXXXh 000000B8h at 20h 000000BBh at 20h “Offset 000000B8h: RxMessageAMR_Data[0-15] - Receive Message AMR Data” on page 1603 XXXXXXXXh 000000BCh at 20h 000000BFh at 20h “Offset 000000BCh: RxMessageACR_Data[0-15] - Receive Message ACR Data” on page 1604 XXXXXXXXh Table 7-61. Bus M, Device 5, Function 0: Summary of CAN Registers Mapped Through CSRBAR Memory BAR (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00000000h 00000003h “Offset 00000000h: Int_Status - Interrupt Status Register” on page 1587 00000000h 00000004h 00000007h “Offset 00000004h: Int_Ebl - Interrupt Enable Register” on page 1588 00000000h 00000008h 0000000Ah “Offset 00000008h: Buffer Status Indicators” on page 1589 00000000h 0000000Ch 0000000Fh “Offset 0000000Ch: ErrorStatus - Error Status Indicators” on page 1590 00000000h 00000010h 00000013h “Offset 00000010h: Command - Operating Modes” on page 1591 00000000h 00000014h 00000017h “Offset 00000014h: Config - CAN Configuration Register” on page 1592 00000000h

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7.4.5 SSP Interface: Bus M, Device 6, Function 0

The SSP interface includes the registers listed in Table 7-62 and Table 7-63. These registers materialize in PCI configuration and memory (via PCI BAR) spaces. See Section 35.10, “SSP Controller Configuration Space: Bus M, Device 6, Function 0” and Table 40.4, “Register Summary” on page 1606 for detailed discussion of these registers along with alternative materializations. 00000020h at 10h 00000023h at 10h “Offset 00000020h: TxMessageControl[0-7] - Transmit Message Control and Command” on page 1593 XXXXXXXXh 00000024h at 10h 00000027h at 10h “Offset 00000024h: TxMessageID[0-7] - Transmit Message ID” on page 1595 XXXXXXXXh 00000028h at 10h 0000002Ah at 10h “Offset 00000028h: TxMessageDataHigh[0-7] - Transmit Message Data High” on page 1596 XXXXXXXXh 0000002Ch at 10h 0000002Fh at 10h “Offset 0000002Ch: TxMessageDataLow[0-7] - Transmit Message Data Low” on page 1597 XXXXXXXXh 000000A0h at 20h 000000A3h at 20h “Offset 000000A0h: RxMessageControl[0-15] - Receive Message Command and Control” on page 1598 XXXXXXXXh 000000A4h at 20h 000000A7h at 20h “Offset 000000A4h: RxMessageID[0-15] - Receive Message ID” on page 1600 XXXXXXXXh 000000A8h at 20h 000000ABh at 20h “Offset 000000A8h: RxMessageDataHigh[0-15] - Receive Message Data High” on page 1600 XXXXXXXXh 000000ACh at 20h 000000AFh at 20h “Offset 000000ACh: RxMessageDataLow[0-15] - Receive Message Data Low” on page 1601 XXXXXXXXh 000000B0h at 20h 000000B3h at 20h “Offset 000000B0h: RxMessageAMR[0-15] - Receive Message AMR” on page 1601 XXXXXXXh 000000B4h at 20h 000000B7h at 20h “Offset 000000B4h: RxMessageACR[0-15] - Receive Message ACR” on page 1602 XXXXXXXXh 000000B8h at 20h 000000BBh at 20h “Offset 000000B8h: RxMessageAMR_Data[0-15] - Receive Message AMR Data” on page 1603 XXXXXXXXh 000000BCh at 20h 000000BFh at 20h “Offset 000000BCh: RxMessageACR_Data[0-15] - Receive Message ACR Data” on page 1604 XXXXXXXXh Table 7-61. Bus M, Device 5, Function 0: Summary of CAN Registers Mapped Through CSRBAR Memory BAR (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value Table 7-62. Bus M, Device 6, Function 0: Summary of SSP Controller PCI Configuration Registers (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID: Vendor Identification Register” on page 1292 8086h 02h 03h “Offset 02h: DID: Device Identification Register” on page 1292 503Bh 04h 05h “Offset 04h: PCICMD: Device Command Register” on page 1292 0000h 06h 07h “Offset 06h: PCISTS: PCI Device Status Register” on page 1293 0010h 08h 08h “Offset 08h: RID: Revision ID Register” on page 1294 Variable 09h 0Bh “Offset 09h: CC: Class Code Register” on page 1295 078000h 0Eh 0Eh “Offset 0Eh: HDR: Header Type Register” on page 1295 00h

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10h 13h “Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on page 1295 00000000h 2Ch 2Dh “Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1296 0000h 2Eh 2Fh “Offset 2Eh: SID: Subsystem ID Register” on page 1296 0000h 34h 34h “Offset 34h: CP: Capabilities Pointer Register” on page 1297 DCh 3Ch 3Ch “Offset 3Ch: IRQL: Interrupt Line Register” on page 1297 00h 3Dh 3Dh “Offset 3Dh: IRQP: Interrupt Pin Register” on page 1297 01h DCh DCh “Offset DCh: PCID: Power Management Capability ID Register” on page 1298 01h DDh DDh “Offset DDh: PCP: Power Management Next Capability Pointer Register” on page 1298 E4h DEh DFh “Offset DEh: PMCAP: Power Management Capability Register” on page 1298 0023h E0h E1h “Offset E0h: PMCS: Power Management Control and Status Register” on page 1299 0000h E4h E4h “Offset E4h: SCID: Signal Target Capability ID Register” on page 1300 09h E5h E5h “Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1300 F0h E6h E6h “Offset E6h: SBC: Signal Target Byte Count Register” on page 1300 09h E7h E7h “Offset E7h: STYP: Signal Target Capability Type Register” on page 1301 01h E8h E8h “Offset E8h: SMIA: Signal Target IA Mask Register” on page 1301 00h ECh ECh “Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1302 00h F0h F0h “Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on page 1302 05h F1h F1h “Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on page 1302 00h F2h F3h “Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1303 0000h F4h F7h “Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1303 00000000h F8h F9h “Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1304 0000h Table 7-62. Bus M, Device 6, Function 0: Summary of SSP Controller PCI Configuration Registers (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value Table 7-63. Bus M, Device 6, Function 0: Summary of SSP CSRs Offset Start Offset End Register ID - Description Default Value 00h 03h “Offset 00h: SSCR0 - SSP Control Register 0 Details” on page 1607 00000000h 04h 07h “Offset 04h: SSCR1 - SSP Control Register 1 Details” on page 1610 00000000h 08h 0Bh “Offset 08h: SSSR - SSP Status Register Details” on page 1614 0000F004h 0Ch 0Fh “Offset 0Ch: SSITR - SSP Interrupt Test Register Details” on page 1617 00000000 10h 13h “Offset 10h: SSDR - SSP Data Register Details” on page 1618 00000000h

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7.4.6 IEEE 1588 Timestamp Unit: Bu s M, Device 7, Function 0

The IEEE 1588 Timestamp Unit includes the registers listed in Table 7-64 and Table 7-65. These registers materialize in PCI configuration and memory (via PCI BAR) spaces. See Section 35.11, “IEEE 1588 Hardware Assist Unit Configuration Space: Bus M, Device 7, Function 0” and Chapter 41.0, “Register Summary” for detailed discussion of these registers along with alternative materializations. Table 7-64. Bus M, Device 7, Function 0: Summary of IEEE 1588 Timestamp Unit PCI Configuration Registers Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID: Vendor Identification Register” on page 1306 8086h 02h 03h “Offset 02h: DID: Device Identification Register” on page 1306 503Ch 04h 05h “Offset 04h: PCICMD: Device Command Register” on page 1306 0000h 06h 07h “Offset 06h: PCISTS: PCI Device Status Register” on page 1307 0010h 08h 08h “Offset 08h: RID: Revision ID Register” on page 1308 Variable 09h 0Bh “Offset 09h: CC: Class Code Register” on page 1308 111000h 0Eh 0Eh “Offset 0Eh: HDR: Header Type Register” on page 1309 00h 10h 13h “Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on page 1309 00000000h 2Ch 2Dh “Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1310 0000h 2Eh 2Fh “Offset 2Eh: SID: Subsystem ID Register” on page 1310 0000h 34h 34h “Offset 34h: CP: Capabilities Pointer Register” on page 1310 DCh 3Ch 3Ch “Offset 3Ch: IRQL: Interrupt Line Register” on page 1311 00h 3Dh 3Dh “Offset 3Dh: IRQP: Interrupt Pin Register” on page 1311 01h DCh DCh “Offset DCh: PCID: Power Management Capability ID Register” on page 1312 01h DDh DDh “Offset DDh: PCP: Power Management Next Capability Pointer Register” on page 1312 E4h DEh DFh “Offset DEh: PMCAP: Power Management Capability Register” on page 1313 0023h E0h E1h “Offset E0h: PMCS: Power Management Control and Status Register” on page 1313 0000h E4h E4h “Offset E4h: SCID: Signal Target Capability ID Register” on page 1314 09h E5h E5h “Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1314 F0h E6h E6h “Offset E6h: SBC: Signal Target Byte Count Register” on page 1314 09h E7h E7h “Offset E7h: STYP: Signal Target Capability Type Register” on page 1315 01h E8h E8h “Offset E8h: SMIA: Signal Target IA Mask Register” on page 1315 00h ECh ECh “Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1316 00h F0h F0h “Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on page 1316 05h F1h F1h “Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on page 1317 00h F2h F3h “Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1317 0000h F4h F7h “Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1318 00000000h F8h F9h “Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1318 0000h

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Table 7-65. Bus M, Device 7, Function 0: Summary of IEEE 1588 TSYNC CSRs (Sheet 1 of Offset Start Offset End Register ID - Description Default Value 00000000h 00000003h “Offset 0000h: TS_Control Register” on page 1639 00000000h 00000004h 00000007h “Offset 0004h: TS_Event Register” on page 1641 0022h 00000008h 0000000Bh “Offset 0008h: TS_Addend Register” on page 1643 0000h 0000000Ch 0000000Fh “Offset 000Ch: TS_Accum Register” on page 1643 0000h 00000010h 00000013h “Offset 0010h: TS_Test Register” on page 1644 0000h 00000014h 00000017h “Offset 0014h: TS_PPS_Compare Register” on page 1646 FFFFFFFFh 00000018h 0000001Bh “Offset 0018h: TS_RSysTimeLo Register” on page 1647 0000h 0000001Ch 0000001Fh “Offset 001Ch: TS_RSysTimeHI Register” on page 1648 0000h 00000020h 00000023h “Offset 0020h: TS_SysTimeLo Register” on page 1649 0000h 00000024h 00000027h “Offset 0024h: TS_SysTimeHi Register” on page 1650 0000h 00000028h 0000002Bh “Offset 0028h: TS_TrgtLo Register” on page 1650 0000h 0000002Ch 0000002Fh “Offset 002Ch: TS_TrgtHi Register” on page 1651 0000h 00000030h 00000033h “Offset 0030h: TS_ASMSLo Register” on page 1652 0000h 00000034h 00000037h “Offset 0034h: TS_ASMSHi Register” on page 1653 0000h 00000038h 0000003Bh “Offset 0038h: TS_AMMSLo Register” on page 1654 0000h 0000003Ch 0000003Fh “Offset 003Ch: TS_AMMSHi Register” on page 1655 0000h 0040h at 20h 0043h at 20h “Offset 0040h: TS_Ch_Control[0-7] - Time Synchronization Channel Control Register (Per Ethernet Channel)” on page 1656 0000h 0044h at 20h 0047h at 20h “Offset 0044h: TS_CH_EVENT[0-7] - Time Synchronization Channel Event Register Per Ethernet Channel)” on page 1658 0000h 0048h at 20h 004Bh at 20h “Offset 0048h: TS_TxSnapLo[0-7] - Transmit Snapshot Low Register (Per Ethernet Channel)” on page 1659 0000h 004Ch at 20h 004Fh at 20h “Offset 004Ch: TS_TxSnapHi[0-7] - Transmit Snapshot High Register (Per Ethernet Channel)” on page 1660 0000h 0050h at 20h 0053h at 20h “Offset 0050h: TS_RxSnapLo[0-7] - Receive Snapshot Low Register (Per Ethernet Channel)” on page 1661 0000h 0054h at 20h 0057h at 20h “Offset 0054h: TS_RxSnapHi[0-7] - Receive Snapshot High Register (Per Ethernet Channel)” on page 1662 0000h 0058h at 20h 005Bh at 20h “Offset 0058h: TS_SrcUUIDLo[0-7] - Source UUID0 Low Register (Per Ethernet Channel)” on page 1663 0000h 005Ch at 20h 005Fh at 20h “Offset 005Ch: TS_SrcUUIDHI[0-7] - SequenceID/SourceUUID High Register (Per Ethernet Channel)” on page 1664 0000h 0140h at 10h 0143h at 10h “Offset 0140h: TS_CANx_Status[0-1] - Time Synchronization Channel Event Register (Per CAN Channel)” on page 1665 0000h 0144h at 10h 0147h at 10h “Offset 0144h: TS_CANSnapLo[0-1] - Transmit Snapshot Low Register (Per CAN Channel)” on page 1666 0000h 0148h at 10h 014Bh at 10h “Offset 0148h: TS_CANSnapHi[0-1] - Transmit Snapshot High Register (Per CAN Channel)” on page 1667 0000h 000001F0h 000001F3h “Offset 01F0h: TS_Aux_TrgtLo Register” on page 1668 0000h 000001F4h 000001F7h “Offset 01F4h: TS_Aux_TrgtHi Register” on page 1668 0000h 00000200h 00000203h “Offset 0200h: L2 EtherType Register” on page 1669 000088F7h

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7.4.7 Local Expansion Bus Interface: Bus M, Device 8, Function 0:

The Local Expansion Bus interface includes the registers listed in Table 7-66 and Table 7-67. These registers materialize in PCI configuration and memory (via PCI BAR) spaces. See Section 35.12, “Expansion Bus Configuration Space: Bus M, Device 8, Function 0”, and Table 42.5, “Register Summary” on page 1696 for detailed discussion of these registers along with alternative materializations. 0000204h 0000207h “Offset 0204h: User Defined EtherType Register” on page 1669 00000000h 00000208h 0000020Bh “Offset 0208h:User Defined Header Offset Register” on page 1670 00000000h 0000020Ch 0000020Fh “Offset 020Ch:User Defined Header Register” on page 1670 00000000h Table 7-65. Bus M, Device 7, Function 0: Summary of IEEE 1588 TSYNC CSRs (Sheet 2 of Offset Start Offset End Register ID - Description Default Value Table 7-66. Bus M, Device 8, Function 0: Summary of Local Expansion Bus PCI Configuration Registers (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID: Vendor Identification Register” on page 1320 8086h 02h 03h “Offset 02h: DID: Device Identification Register” on page 1320 503Dh 04h 05h “Offset 04h: PCICMD: Device Command Register” on page 1321 0000h 06h 07h “Offset 06h: PCISTS: PCI Device Status Register” on page 1321 0010h 08h 08h “Offset 08h: RID: Revision ID Register” on page 1322 Variable 09h 0Bh “Offset 09h: CC: Class Code Register” on page 1323 068000h 0Eh 0Eh “Offset 0Eh: HDR: Header Type Register” on page 1323 00h 10h 13h “Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on page 1323 00000000h 14h 17h “Offset 14h: MMBAR: Expansion Bus Base Address Register” on page 1324 00000000h 2Ch 2Dh “Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1325 0000h 2Eh 2Fh “Offset 2Eh: SID: Subsystem ID Register” on page 1325 0000h 34h 34h “Offset 34h: CP: Capabilities Pointer Register” on page 1326 DCh 3Ch 3Ch “Offset 3Ch: IRQL: Interrupt Line Register” on page 1326 00h 3Dh 3Dh “Offset 3Dh: IRQP: Interrupt Pin Register” on page 1326 01h 40h 43h “Offset 40h: LEBCTL: LEB Control Register” on page 1327 00h DCh DCh “Offset DCh: PCID: Power Management Capability ID Register” on page 1327 01h DDh DDh “Offset DDh: PCP: Power Management Next Capability Pointer Register” on page 1328 E4h DEh DFh “Offset DEh: PMCAP: Power Management Capability Register” on page 1328 0023h E0h E1h “Offset E0h: PMCS: Power Management Control and Status Register” on page 1329 0000h E4h E4h “Offset E4h: SCID: Signal Target Capability ID Register” on page 1329 09h E5h E5h “Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1330 F0h E6h E6h “Offset E6h: SBC: Signal Target Byte Count Register” on page 1330 09h

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§ § E7h E7h “Offset E7h: STYP: Signal Target Capability Type Register” on page 1330 01h E8h E8h “Offset E8h: SMIA: Signal Target IA Mask Register” on page 1331 00h ECh ECh “Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1331 00h F0h F0h “Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on page 1332 05h F1h F1h “Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on page 1332 00h F2h F3h “Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1333 0000h F4h F7h “Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1333 00000000h F8h F9h “Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1334 0000h Table 7-66. Bus M, Device 8, Function 0: Summary of Local Expansion Bus PCI Configuration Registers (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value Table 7-67. Bus M, Device 8, Function 0: Summary of Local Expansion Bus Registers Mapped Through CSRBAR PCI Memory BAR" Offset Start Offset End Register ID - Description Default Value 00000000h 00000003h “EXP_TIMING_CS0 - Expansion Bus Timing Register” on page 1698 BFFF3C40h 00000004h at 00000007h at 4h “EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers” on page 1700 00000000h 00000020h 00000020h “EXP_CNFG0 -Configuration Register 0” on page 1702 00000040h 00000120h 00000123h “EXP_PARITY_STATUS - Expansion Bus Parity Status Register” on page 1703 00000000h

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8.0 IA-32 Core

8.1 Overview

The EP80579system-on-a-chip (SoC) uses an IA-32 core, which is based on the Intel® Pentium® M processor (90 nm). Major features include:

600 MHz, 1066 MHz and 1200 MHz operating frequencies
FSB frequency of 400 MHz and 533 MHz.
Uni-directional FSB interface (on-chip) for SoC applications
32 KByte L1 split instruction and data caches
256 KByte 2-way L2 cache with 64B lines
Soft error protection on L2 cache data and tags (via ECC), soft error protection on L1 cache data and tags (via parity)
New CPU identifier (CPUID) Note the differences between the IA-32 core and the Intel ® Pentium® M processor (90 nm) are:
Core and FSB operating frequencies
Uni-directional FSB instead of bi-directional
Different CPU identifier (CPUID)
Reduced L2 cache size and ways
De-featured Intel SpeedStep ® Technology (no VRM specification required)

8.2 Theory of Operation

This section discusses several operational areas of IA-32 core.

8.2.1 L2 Cache Size

The IA-32 core reduces the size and associativity of the L2 cache on the Pentium M processor (90 nm)from 2MB 8-way to 256KB 2-way.

8.2.2 Platform and JTAG Identifiers

The Platform ID is a project-specific value. It is used solely for selecting a microcode update (i.e., patch) and is tightly-coupled to a specific CPUID number. BIOS and OS software are aware of the Platform ID convention and automatically pick up the appropriate patch. There are two views to the Platform ID: the MSR view and the Patch view: The MSR view is a 3-bit value read out of the processor’s FUSE_MSR[52:50]. This value is determined by three fuses and is unique per CPUID SKU. The Patch view is the binary value which represents two raised to the power of the MSR view value. A microcode update is considered applicable to a specific processor if, and only if, the following condition is true:

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(((Patch.header.cpuid == Processor’s CPUID) && ((Patch.header.platformID & 2^FUSE_MSR[52:50]) != 0)) The MSR view of the EP80579 Platform ID is 100b. Table 8-1 summarizes the format of the processor version identification signature (CPUID).

8.2.3 FSB Physical Interface

The IA-32 core replaces the standard bi-directional, tri-state FSB interface found on the Pentium M processor (90nm) with a uni-directional interface. This uni-directional interface is better suited for SoC applications that use a single core. This modification replaces a single bi-directional wire with two uni-directional wires.

8.2.4 IA-32 Core and FSB Frequency

The EP80579 is targeted to operate with IA-32 core frequencies of 600 MHz, 1066 MHz and 1200 MHz and FSB frequencies of 400 MHz (600 MHz SKU) and 533 MHz (1066 MHz and 1200 MHz SKUs). § § Table 8-1. Processor Version Identification Signature (CPUID) 31 28 27 20 19 16 1 2 11 8 7 4 3 0 Extended Family Extended Model Typ e Family Model Number Stepping ID 00000000000000010000011001010000

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9.0 CMI Introduction

This section details the system architecture supported by the Memory Controller Hub and I/O Controller Hub complex. The Memory Controller Hub and I/O Controller Hub are referred to collectively as the CMI (IMCH and ICH). Subsequent chapters cover the following aspects of the MCH and the ICH:

Description of the CMI architecture.
Descriptions of internal registers.
Descriptions of all external interfaces. The EP80579 is a single chip that integrates the functionality of an IA-32 core, Memory Controller Hub, and an I/O Controller Hub (see Figure 9-1). In this document the Memory Controller Hub and I/O Controller Hub in CMI are referred to as IMCH (Integrated Memory Controller Hub) and IICH (Integrated I/O Controller Hub) respectively. The IMCH and IICH units are connected internally through the NSI (North South Interface). The NSI is an internal bus that is not externally accessible. Figure 9-1. CMI Block Diagram IICH 1X8 PCI Express Configurable as 2X4, 2x1 LPC Bus SMBus Interrupts

2 UART’s

2 CH SATA

36 GPIOs

2 USB-2.0 SMBus DDR2 – (400, 533, 667, 800) Unbuffered and Registered ECC IMCH 4 channel EDMA

2 DIMM Max,

2 Ranks Max

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9.1 System Architecture

CMI implements numerous RASUM (Reliability, Availability, Serviceability, Usability and Manageability) features on multiple interfaces. The IMCH and IICH consist of:

A Memory Controller.
A four-channel, descriptor-chain-based Enhanced DMA (EDMA) controller.
Several I/O devices such as USB, SATA, etc.
One x8 PCI Express* interface, which may be split into a pair of independent x4 or x1 PCI Express* interfaces. Desired I/O Controller Hub (IICH) functions are integrated eliminating the requirement for a legacy I/O bridge. CMI also supports:
Two USB 2.0/1.1 ports
T w o S A T A p o r t s G e n 1 / G e n 2
O n e L P C b u s
O n e S P I p o r t
T w o U A R T p o r t
T w o S M B u s p o r t s For additional information see Section 11.3, “Configurations” on page 291.

9.2 PCI Express*

CMI provides one configurable x8 PCI Express interface with a maximum theoretical bandwidth of 4 GByte/s (aggregate). The x8 PCI Express interface may alternatively be configured as two independent x4 or x1 PCI Express interfaces. CMI is a root-class component as defined in the PCI Express* Interface Specification, Rev 1.0a. The PCI Express interfaces support connection of CMI to a variety of other bridges compliant with the same revision of the PCI Express* Interface Specification, Rev 1.0a. For example, the Intel® 82571EB Gigabit Ethernet adaptor and the Intel PCI Express I/O processor are directly supported on any of these PCI Express ports. Other compatible PCI Express devices implement functionality such as graphics, hardware RAID controllers and TCP/IP off-load engines. These devices are available from Intel and/or third-party vendors. As required by the interface specification, CMI will automatically negotiate for and train a single lane (x1) link if an attached device on any logical port fails to establish a viable x4 or x8 connection. This does not imply a capability for CMI to support more than two independent PCI Express ports of any width simultaneously on the x8 port, nor does it imply that the remaining three lanes of a potential x4 port are useful once the associated link has been established for x1 operation. Similarly, CMI will automatically negotiate for and train a single lane (x1) link if an attached device on any logical port fails to establish a viable x4 connection. External bridge devices such as PCI or PCI-X Gigabit Ethernet or RAID storage devices are directly supported on the PCI Express ports. This does not preclude connection of the IMCH to other bridges compliant with the same revision of the PCI Express Interface Specification.

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9.2.1 Supported PCI Express Configurations

CMI PCI Express ports are setup using a configuration register. This register is “DEVPRES” BDF 000, Offset 9Ch, Bits 2 and 3 which control Device 2 and Device 3 present. Table 9-1 shows all of the valid combinations of this register.

9.2.1.1 Low power SKU with PCI Express ports removed

To enable low power SKU for configurations that do not utilize the PCI Express ports, the user can disable PCI Express ports and configuration bits for power savings.

9.3 Supported Debug and Management Interfaces

The IMCH supports a target SMBus interface for access and control of the IMCH through its configuration registers. A Test Access Port (TAP) interface is also supported for IMCH system debug purposes. The TAP is capable of full read/write access to the entire internal IMCH register space. Platforms based on CMI may also make use of the Inter-Chassis Management Bus (ICMB) architecture to extend SMBus based management throughout a desegregate multi-chassis platform solution.

9.4 Supported IMCH Integrated Features

This section provides a brief overview of internal IMCH features. The subsections are intended for use as an introduction and a quick reference. See Section 9.5 for more detailed descriptions of these features.

9.4.1 EDMA Controller

The IMCH includes an integrated four-channel Enhanced Direct Memory Access (EDMA) controller to perform background data transfers between locations in main memory, or from main memory to a memory-mapped I/O destination. These transfers may be Table 9-1. Supported PCI Express Configurations DEVPRES DEV2 En, DEV3 En DEV2 En, DEV3 Dis DEV2 Dis, DEV3 En DEV2 Dis, DEV3 Dis Strap AUTO Negotiate 1x8, 2x4, lower 1x4, upper 1x4 1x8, lower 1x4 Not supported All Disabled 2x4 2x4 lower 1x4 upper 1x4 All Disabled 1x8 1x8 1x8 Not supported All Disabled

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individually designated to be coherent (snooped on the FSB) or non-coherent (not snooped on the FSB), providing improvements in system performance and utilization when cache coherence is managed by software rather than hardware. Each of the four channels implements an independent set of configuration and status registers, and is capable of fully independent operation. Each channel may operate in a single block transfer mode, or a hardware traversed linked-list scatter/gather mode. The internal EDMA controller only supports transfers between main memory locations, and transfers from a main memory source to an I/O subsystem destination. The internal EDMA controller supports neither transfers between I/O interfaces, nor transfers from an I/O interface source to a main memory destination.

9.4.2 Integrated Memory Init/Test Engine

The IMCH provides hardware-managed ECC memory auto-initialization and testing of all populated DRAM space under software control. Once internal configuration has been updated to reflect the type and size of populated DIMM, the IMCH can traverse the populated address space issuing line-sized writes of all zero data, thereby initializing all locations with good ECC memory. This greatly speeds up the mandatory memory initialization step and frees the CPU to pursue other machine initialization and configuration tasks. Additional features have been added to the initialization engine to support high-speed population and verification of a programmable memory range with one of eight known data patterns, random data, a walking data pattern, or an explicitly specified cache line (data plus ECC). This function facilitates a limited high-speed memory test and provides BIOS-accessible memory testing capability for potential use by management code or by the operating system. For additional information see Section 11.2, “Memory Controller Feature List” on page 289.

9.4.3 Coherent Memory Write Buffer

The IMCH includes an integrated coherent write buffer sized for 16 64-byte cache lines (a total of 1 Kbyte of storage). This feature enables the IMCH to optimize memory read latency, allowing reads to pass less critical writes en-route to the main memory store. The write buffer includes a CAM structure to enforce ordering among conflicting accesses to the same cache line, as well as to provide for read service from the write cache. In the latter case, the access to the main memory store never occurs, which both improves latency and conserves bandwidth on the memory interface. The write buffer is capable of servicing processor read requests directly via a “hit” to the internal location containing the data without initiation of any DDR subsystem accesses. Inbound read requests such as PCI Express, i.e. not processor, which “hit” the write buffer result in a flush of the target data, followed by retrieval via an external read request. Processor writes to shared non-coherent address space with the ASU result in a flush of the current cacheline to main memory. ASU atomics will result in a DW write to the ASU out of the write cache.

9.4.4 RASUM Features

The IMCH is designed to bring enterprise-level reliability, availability, serviceability, usability, and manageability to the embedded platform. All internal SRAM memory arrays are covered by parity. CMI’s PCI Express interface supports detection and automatic recovery for all transient signaling errors. All IMCH internal configuration

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9.4.4.1 SEC-DED ECC

The IMCH supports a standard (72-bit, non-interleaved) single error correction (SEC) and double error detection (DED) ECC mechanism for the DDR memory. The IMCH supports both ECC and non-ECC DIMMs. For additional information see Section 11.2, “Memory Controller Feature List” on page 289.

9.4.4.2 Integrated Memory Scrub Engine

The IMCH includes an integrated engine to walk the populated memory space proactively seeking out soft errors in the memory subsystem. This hardware detects, logs, and corrects any single-bit ECC errors it encounters, and logs any uncorrectable errors it encounters. Both types of errors may be reported via multiple alternate mechanisms under configuration control. The scrub hardware will also execute “demand scrub” writes when correctable errors are encountered during normal operation (on demand reads, rather than scrub-initiated reads). This functionality provides incremental protection against time-based deterioration of soft memory errors from correctable to uncorrectable. An uncorrectable error encountered by the memory scrub engine is a “speculative error.” This designation is applied because no system agent has specifically requested use of the corrupt data, and no real error condition exists in the system until that occurs. It is possible that the error resides in an unmodified page of memory that is simply dropped on a swap back to disk. If that were to occur, the speculative error would simply “vanish” from the system without any adverse consequences.

9.5 IMCH Feature List

This section provides an overview of the major IMCH architectural features. Detailed usage information and operational flows, internal register bit information and other specific details of the implementation are provided later in this document.

9.5.1 Memory Interface

For additional information see Section 11.2, “Memory Controller Feature List” on page 289.

9.5.2 PCI Express Interface in IMCH

Support for one x8 PCI Express dual-simplex, high-speed serial I/O interface with eight striped differential pairs in each direction (outbound and inbound) — The interface may be unpopulated; connected to PCI, Ethernet, I/O Processor, Infiniband* bridge devices, External bridge devices (PCI or PCI-X Gigabit Ethernet or RAID storage devices); or connected to any other device compliant with the same revision of the PCI Express Specification as CMI. — The x8 interface is capable of bifurcation into two logically independent x4 interfaces with full specification compliance at half the bandwidth capability
This interface is referred to throughout this document as the PCI Express Port A (PEA). When configured as x8, the reference is PEA. When in x4 mode there are two available x4 ports referred to as PEA0 and PEA1.

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Raw bit-rate on the data pins of 2.5 Gbit/s. — Maximum theoretical realized bandwidth on the x8 PCI Express interface of 2 GByte/s in each direction simultaneously, for an aggregate of 4 GByte/s. — Maximum theoretical realized bandwidth on the x4 PCI Express interface of 1 GByte/s in each direction simultaneously, for an aggregate of 2 GByte/s per port. — x8 sustainable data bandwidth is approximately 1.6 GByte/s in each direction simultaneously
Plesiochronous operation with automatic clock extraction and phase correction at the receiver.
Hierarchical PCI-compliant configuration mechanism for downstream devices — Support for PCI Express memory-mapped enhanced configuration mechanism, up to 4 Kbyte per device.
64 bit addressing support. — 64 bit upstream addressing (full DAC support), limited to 32 bits internally to/ from system memory (external DDR). — 32 bit downstream addressing support. — Full 36 bit support for peer segment accesses. Note: Only 32-bit addresses can be snooped. Addresses larger than 32 bits will be truncated. e.g. If a 36-bit address is snooped the upper 4 bits are ignored.
Full-speed interface self-test and diagnostic (IBIST) functionality.
Automatic discovery, negotiation, and training of PCI Express ports out of reset. — Automatic detection of widest operational link; x8, x4 or x1.
No support for Hot-plug via an external SMBus connected device.
Run-time detection and recovery for loss of link synchronization.
32 bit CRC (cyclic redundancy checking) on all transaction layer packets with link- level retry on error (recovery from transient errors without software-visible system failure).
16 bit CRC on all link message information
No support for the optional extended CRC (ECRC) mechanism
Aggressive transceiver design to facilitate flexible system topologies
T a r g e t B E R o f 1 0 -12 for physical signaling interface
Support for peer segment destination write traffic (no peer-to-peer read traffic)
Support for coherent and non-coherent transactions through EDMA to PEA to external agent
Support for both coherent and non-coherent traffic to memory within VC#0 — Non-coherent implies a combination of Snoop-Not-Required and Relaxed- Ordering attributes — Coherent traffic implies a combination of Snoop-Required and Strong-Ordering attributes.
Support for lane reversal at all native widths, and for reversed x4 training on any x8 port
Support for peer segment PCI interrupt forwarding to the IICH for boot from I/O — Legacy mode support for level-sensitive interrupt emulation without IOxAPIC support

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APIC and MSI interrupt messaging support DMA internal score-boarding to translate messages into level-sensitive IICH pin semantics — XTPR-based interrupt redirection for APIC messages with lowest priority tie breaking
Support for up to 256B read completion combining
Support for link messaging to facilitate active link and device power state management
Support for ASPM L0s entry, no support for optional L1 ASPM support
No support for inbound configuration or I/O traffic
No support for inbound special cycles or writes requiring completions
No support for downstream special cycle messages requiring completions

9.5.3 EDMA Controller

Four Independent Channels — Dedicated data transfer queue per channel — Full register set for descriptor and transfer handling per channel
Support for transfer between main memory locations, and from memory to the I/O subsystem
Supports PCI Express traffic class to allow external prioritization of traffic
Supports transfers only between two Physical Addresses — 32 bit (4 GB) addressing range on the Local System Memory Interface — 32 bit addressing range on the Memory Mapped I/O Subsystem Interface
Maximum transfer of 16 Mbyte transfers per block
Fully programmable by the host CPU — Configuration space mapping for DMA engine capability and control — Memory-mapped space for DMA channel-specific register sets
Chain mode DMA transfer with automatic data chaining for scattering/gathering of data blocks — DMA chaining continued until a “null” Descriptor Pointer is encountered — Support for appending a block to the end of current DMA chain — Automated descriptor retrieval from DDR during chaining – single read
Programmable independent alignment between source and destination — Byte aligned transfer on the DDR Memory Interface — Byte aligned transfer on the I/O Subsystem Interface
Support for non-coherent transfers both to and from system memory on a per descriptor basis — Independent control of coherency for source and destination
Programmable support for interrupt generation on block–by-block basis — Selectable MSI or legacy level-sensitive interrupt function — End of current block transfer — End of current chain — For any error causing a transfer to abort

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Increment of the source and destination address for standard transfers
Increment of the destination and decrement of the source address to enable byte stream reversal.
Constant address mode for the destination address based on the transfer granularity to enable targeting of memory mapped I/O FIFO devices
Buffer/Memory Initialization Mode

9.5.4 Coherent Memory Write Buffer

Support for 16 64-byte cache-lines of write data
Fully associative conflict detection for accesses targeting memory
Read around write support (non-conflicting) for all traffic to memory
Read-hit support for CPU traffic to memory — Direct data service from buffer without generation of memory traffic
Write-hit support for memory traffic with address conflicts — Hardware-based merging to collapse down to a single memory write
Opportunistic and demand (buffer full) mode processing of pending writes — Configurable “watermark” mechanism for hardware-based prioritization — Flush on demand via software configuration mechanism
Parity protection on all data
Data poisoning capability in the main store for data received with errors
Processor writes to shared non-coherent address space with the ASU result in a flush of the current cacheline to main memory
ASU atomics will result in a DW write to the ASU out of the write cache

9.5.5 Integrated Memory Scrub Engine

For additional information see Section 11.2, “Memory Controller Feature List” on page 289.

Periodic (programmable) read-modify-write algorithm
Support for the SEC-DED mode of operation
Automatic correction of encountered SEC errors
Logging of detected errors with granularity to isolate DRAM device — Support for logging of both first and next subsequent error — Count of errors beyond the first two which are logged
Support for on-demand hardware scrub of SEC errors detected during normal operation
Programming interface permits software suspend/resume of scrub in progress

9.5.6 Hardware Memory Initialization Engine

Available via BIOS for hardware memory initialization and/or test
Provides fast WHQL initialization of all populated DRAM space to “0” with good ECC
Target region may be a single location, an entire rank, or all populated ranks
Algorithm optimized for speed, runs at DDR channel saturation rate

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Test extensions permit high-speed population of a target range with a known pattern — Selectable hardware-generated fixed patterns: 0, 3, 5, 6, 9, A, C, F — Hardware generated random pattern capability — Explicitly stipulated data pattern including ECC
High speed verification capability — Selectable write-only, verify-only, or write-read-verify per location — Logs error location, optional stop and escalate on error detection
May be made available to the operating system via BIOS for security “clear to 0” function

9.5.7 System Management Functions

Full SMBus target support
Support for remote chassis management via the ICMB architecture
Serial presence detect of memory devices via standard I 2C protocol (accessed via IICH)
ACPI and PCI-PM compatible power management — Includes PME support comprehending PCI Express extensions
MSI interrupt messaging and redirection support
Hardware relay of PCI Express legacy mode PCI interrupt messages to IICH — Supports boot from I/O when IOxAPIC functions are unavailable

9.5.8 RASUM

SEC/DED ECC protection of external memory DRAM data
Parity protection on internal data propagated through the IMCH
CRC on data packets and hardware link-level retry on NSI to the IICH
32-bit CRC on data packets and hardware link-level retry on PCI Express ports
Hardware memory initialization — True “clear-to-zero” via hardware writes to all populated devices — Support for hardware-based fast initialization of memory with selectable patterns — Support for hardware-based fast verification of memory via accelerated scrub
Hardware periodic memory scrubbing, including demand scrub support
Flexible extended error reporting capabilities
Configurable error containment at I/O interfaces (poison/propagate or stop/ escalate)
Partial access to internal configuration registers via the TAP port
Full access to internal configuration registers via SMBus port

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9.6 IICH Feature List

This section provides a listing of architectural functionality for the major features of the IICH. Detailed usage information and operational flows, internal register bit information, and other specific details of the implementation are provided later in this document.

9.6.1 Low-Pin count (LPC) Interface and Firmware Hub (FWH)

Allows connection of devices such as Super I/O, micro controllers, customer ASICs.
Supports two master/DMA devices.
M e m o r y s i z e u p t o 8 M b i t .

9.6.2 Serial Peripheral Interface (SPI)

Note: Intel recommends using the SPI as your boot interface.

Supports multiple SPI Flash vendors.
Simplified Hardware.
Equivalent to LPC-based Firmware Hubs.

9.6.3 Integrated Serial ATA Host Controllers

Independent DMA operation on two ports. — Two ports in SATA 1.0a and AHCI mode. — Two ports in AHCI mode only.
Data transfer rates up to 300 Mbyte/s.
Support Gen2m electrical spec (cable not exceeding 2m).

9.6.4 USB

One EHCI USB 2.0 Host Controller with a total of two ports (shared with the UHCI ports).
One UHCI Host Controller for a total of two ports (shared with the EHCI ports).
Supports a Debug Port at USB 2.0 transfer rates.

9.6.5 Interrupt Controller

Supports up to 8 PCI interrupt pins.
Two cascaded 82C59 with 15 interrupts.
Integrated I/O APIC supports a total of 40 interrupts (24 interrupts only, when ETR3.GPIO_IRQ_STRAP_STS is 0).
Serial Interrupt input for ISA legacy-compatible and PCI interrupts.
Supports PCI scheme for delivering interrupts as write cycles (rather than via PIRQ[A-H]#).
Front-Side Message Interrupt Delivery.
Supports EOI message.

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9.6.6 Power Management Logic

Power management logic for various environments require updates.

ACPI 2.0 Compliant.
Support for APM-based legacy power management for non-ACPI implementations.
Supports ACPI defined power states S0, S1, S3 cold, S4 and S5 (SOFF).
ACPI Power Management Timer.
S M I # G e n e r a t i o n .
P C I P M E # .

9.6.7 DMA Controller

Two cascaded 8237 DMA Controllers.
S u p p o r t s L P C D M A .

9.6.8 Timers Based on 82C54

System Timer, Refresh Request, Speaker Tone Output.

9.6.9 High Precision Event Timers (HPET)

Three timer comparators provided.
One-shot and periodic interrupts supported.

9.6.10 Real-Time Clock with 256-byte Battery-backed CMOS RAM

Integrated components for the oscillator to reduce problems with incorrect external selections.
Lower Power DC/DC Converter implementation.

9.6.11 System TCO Reduction Circuits

Timers to detect improper CPU reset and to generate SMI# and Reset upon detection of stuck CPU.
Interrupt capability to OS-specific manageability extension and OS capability to call TCO BIOS.
S u p p o r t s C P U B I S T .
Ability to disable external devices.

9.6.12 SMBus

Host interface allows CPU to communicate via SMBus.
Compatible with most 2-wire components that are also I 2C compatible.
Slave interface allows internal or external microcontroller to access system resources.
SMBus 2.0 Compliant.
No ASF support.

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9.6.13 Watchdog Timer

Selectable Prescaler: — Approximately 1 MHz (1 µs to 1 s). — Approximately 1 KHz (1 ms to 10 min.)
33 MHz Clock (30 ns Clock Ticks).
Multiple Modes (WDT and Free-Running).
Free-Running Mode: —O n e S t a g e T i m e r . — Toggles WDT_TOUT# after programmable time.
W D T M o d e : — Two Stage Timer (First Stage generates Interrupt, Second Stage drives WDT_TOUT# low). — First Stage generates an SERIRQ, NMI or SMI interrupt after Programmable time. — Second Stage drives WDT_OUT# low or inverts the previous value. — Used only after first timeout occurs. — Status bit preserved in RTC well for possible error detection and correction. — Drives WDT_TOUT# if OUTPUT is enabled.
Timer can be disabled (default state) or Locked (Hard Reset required to disable WDT).
WDT Automatic Reload of Preload value when WDT Reload Sequence is performed.

9.6.14 Serial Port

Two Full Function 16550 Compatible Serial Ports.
Configurable I/O addresses and interrupts.
16-Byte FIFOs.
Supports up to 115 Kbps.
Programmable Baud Rate Generator.
Modem Control Circuitry.
14.7456 MHz and 48 MHz supported for UART baud clock input.

9.6.15 GPIO

General Purpose I/Os .
There are 36 GPIO pins of which 5 have alternate power on functions. § §

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10.0 System Address Map

10.1 Overview

The IA-32 core addressable memory map is 32 bits or up to 4 GBytes and has 64 KBytes+3 of addressable I/O space. The I/O and memory spaces are divided by system configuration software into non-overlapping regions. The memory ranges are useful either as system memory or as specialized memory, while the I/O regions are used solely to control the operation of devices in the system. There are five basic regions of memory in the system. The regions are shown in Table 10-1. Figure 10-1 illustrates the basic memory regions. Table 10-1. Regions of Memory Ranges Range Description Between top of main memory and 64 GBytes High PCI Memory Range Between 4 GBytes and top of main memory Between TOLM Register and 4 GBytes Low PCI Memory Address Range Between 1 MByte and the TOLM Register Main Memory Address Range Below 1 MByte DOS Legacy Address Range Figure 10-1. Basic Memory Regions 1 MB Top of Low Memory 4 GB 64 GB APIC, PCI Express, and NSI, non overlapping windows Additional Main Memory Address Range Lo PCI Memory Address Range Main Memory Address Range DOS Legacy Address Range Additional Main Memory Address Range

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10.1.1 System Memory Spaces

Table 10-2’s address ranges are always mapped to system memory, regardless of the system configuration. The Top of Low Memory (TOLM) register (see Section 16.1.1.30, “Offset C4h: TOLM - Top of Low Memory Register”) provides a mechanism to carve memory out of the MAINMEM segment for use by System Management Mode (SMM) hardware and software, PCI add-in devices, and other functions. The address of the highest 128 MByte quantity of populated DRAM memory in the system is placed into the DRB3 register, which will match the value in the Top of Memory (TOM) register (see Section 16.1.1.34, “Offset CCh: TOM - Top Of Memory Register”.

10.1.2 VGA and MDA Memory Spaces

Table 10-3 lists the VGA and MDA Memory spaces. Figure 10-2 illustrates the DOS legacy Region. These legacy address ranges are used on behalf of video cards to map a frame buffer or a character-based video buffer into a dedicated location. By default, accesses to these ranges are forwarded to the NSI. However, if the VGAEN bit is set in one of the BCTRL configuration registers (see Section 16.4.1.26, “Offset 3Eh: BCTRL - Bridge Control Register”), then transactions within the VGA and MDA spaces are sent to one of the PCI Express interfaces in IMCH. Note: The VGAEN bit may be set in one and only one of the BCTRL registers. Software must not set more than one VGAEN bit. Table 10-2. System Memory Space From To DOSMEM 0_0000_0000 0_0009_FFFF MEM1_15 0_0010_0000 0_00EF_FFFF MAINMEM 0_0100_0000 TOLM HIGHMEM 1_0000_0000 7_FFFF_FFFF Table 10-3. IMCH VGA and MDA Memory Spaces From To VGAA 0_000A_0000 0_000A_FFFF MDA 0_000B_0000 0_000B_7FFF VGAB 0_000B_8000 0_000B_FFFF

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 269 Intel® EP80579 Integrated Processor If the configuration bit EXSMRC.MDAP (see Section 16.1.1.25, “Offset 9Dh: EXSMRC - Extended System Management RAM Control Register”) is set, then accesses that fall within the MDA range are sent to NSI without regard for the VGAEN bits. Legacy support requires the ability to have a second graphics controller (monochrome display adapter) in the system. In a CMI system with PCI graphics installed via a PCIe to PCI bridge like PXH, accesses in the standard VGA range may be forwarded to any of the logical PCI Express ports (depending on configuration bits). Since the monochrome adapter may be on the NSI (or logical ISA) bus, the IMCH must decode cycles in the MDA range and forward them to NSI. This capability is controlled via the MDAP configuration bit. In addition to the memory range B0000h to B7FFFh, the IMCH decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards them to NSI. An optimization allows the system to reclaim the memory displaced by these regions. If SMM memory space is enabled by EXSMRC.G_SMRAME and either the SMRAM.D_OPEN bit (see Section 16.1.1.25, “Offset 9Dh: EXSMRC - Extended System Management RAM Control Register” and Section 16.1.1.26, “Offset 9Eh: SMRAM - System Management RAM Control Register”) is set or the processor bus receives an SMM-encoded request for code (not data), then the transaction is steered to system memory rather than NSI. Under these conditions, both the VGAEN bits and the MDAP bit are overridden. If any VGAEN bit is set, then all ISAEN bits (see Section 16.4.1.26, “Offset 3Eh: BCTRL - Bridge Control Register”) must be set. The PCI Specification defines VGAEN to be 10- bit decode. Therefore the other peer bridges must also be 10-bit decodes (ISAEN), so that two or more devices don't claim same access. (Bridge C doesn't know bridge B has its VGAEN bit set.) Figure 10-2. DOS Legacy Region Upper, Lower, Expansion Card BIOS and Buffer Area VGAB 1MB 640 KB

768 KB0C0000h

PAM[6:0]. Monchrome Display Adapter Space VGAA Standard PCI/ISA Video Memory (SMM Memory) 0B8000h 0B0000h 736 KB 704 KB Controlled by VGA Enable and MDA enable. = DRAM Key = Optionally DRAM 10 0000h

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The MDA bit may only be set when one of the VGAEN bits is set. If no VGAEN bit is set, then MDA must not be set either. When the VGA range is already mapped onto the NSI interface, the MDA range is included as a subset, and the MDA enable is meaningless.

10.1.3 PAM Memory Spaces

The Address range for the PAM memory space is defined in Table 10-4. The 256 Kbyte Programmable Access Memory (PAM) region is divided into three parts:

ISA expansion region, a 128 Kbyte area between 0_000C_0000h – 0_000D_FFFFh.
Extended BIOS region, a 64 Kbyte area between 0_000E_0000h – 0_000E_FFFFh.
System BIOS region, a 64 Kbyte area between 0_000F_0000h – 0_000F_FFFFh. Specialized programmable hardware in the IMCH supports routing of read and write accesses within the PAM region independently to memory or to NSI. Non-snooped transactions are treated accordingly:
Non-snoop Reads: Memory address 0h. The result is an unsupported request (UR) completion.
Non-snoop Writes: Memory address 0h with byte enables deasserted. The ISA expansion region is divided into eight 16 Kbyte segments. Each segment can be assigned one of four Read/Write memory states: read-only, write-only, read/write, or disabled. These segments are typically set to disabled for memory access, which leaves them routed to NSI for ISA space. Table 10-4. IMCH PAM Memory Address Ranges From To Access Region PAMC0 0_000C_0000 0_000C_3FFF ISA Expansion (16KB/each) PAMC4 0_000C_4000 0_000C_7FFF PAMC8 0_000C_8000 0_000C_BFFF PAMCC 0_000C_C000 0_000C_FFFF PAMD0 0_000D_0000 0_000D_3FFF PAMD4 0_000D_4000 0_000D_7FFF PAMD8 0_000D_8000 0_000D_BFFF PAMDC 0_000D_C000 0_000D_FFFF PAME0 0_000E_0000 0_000E_3FFF Extended BIOS (16KB/each) PAME4 0_000E_4000 0_000E_7FFF PAME8 0_000E_8000 0_000E_BFFF PAMEC 0_000E_C000 0_000E_FFFF PAMF0 0_000F_0000 0_000F_FFFF System BIOS (64KB)

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 271 Intel® EP80579 Integrated Processor The extended System BIOS region is divided into four 16 Kbyte segments. Each segment can be assigned independent read and write attributes so it can be mapped either to main DRAM or to NSI. Typically, this area is used for RAM or ROM. The system BIOS region is a single 64 Kbyte segment. This segment can be assigned independent memory read and write attributes. It is by default (after reset) Read/Write disabled and cycles are forwarded to NSI. By manipulating the Read/Write attributes, the IMCH can “shadow” BIOS into the main DRAM. The term “shadow” is used to describe the condition where ROM memory has been duplicated into main memory; such that reads are serviced from memory, while writes are directed back to the original ROM device. Such a configuration allows low-latency reads of BIOS information from the ROM while preventing malicious or inadvertent alteration of the BIOS information in use. Note: The PAM regions are generally inaccessible from the logical PCI Express ports. All inbound writes from any port that hit the PAM regions are sent to NSI, which prevents corruption of non-volatile data shadowed in main memory. All inbound reads from any port that hit the PAM regions are harmlessly terminated internally; data is returned, but not necessarily from the requested address. Transaction routing is not hardware enforced based on the settings in the PAM configuration registers. Note: The PAM regions are inaccessible from the logical AIOC port. All inbound reads/writes from any port that hit the PAM regions are master aborted by the AIOC preventing them from ever pushed into the IMCH. Figure 10-3. Memory Region from 1 MByte through 4 GBytes Key1_0000_0000 (4GB) Local APIC Space FEF0_0000 FEE0_0000 PEA I/O APIC Space FEC8_6000 Top of Low Memory (TOLM) FEC0_0000 NSI I/O APIC Space FEC8_0000 High BIOS, Optional Extended SMRAM FF00_0000 = Region allowed for MMIO below 4GB PCI Express Enanced Config. Aperture = DRAM Region 00F0_0000 (15 MB) ISA Hole 0100_0000 (16 MB) 0010_0000 (1MB) = Optional DRAM Region =N S I ( a l w a y s ) TSEG SMRAM Space TOLM - TSEG E000_0000 F000_0000 FEC8_2000 Unused I/O APIC Space

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The IMCH allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 Kbyte to 1 Mbyte (C0000h – FFFFFh) and 640 Kbytes to 1 Mbyte address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Not all seven of these registers are identical. PAM0 controls only one segment (high), while PAM[1:6] each control two segments (high and low). Cache ability of these areas is controlled via the MTRR registers in the processor. The following two bits apply to both host accesses and PCI initiator accesses to the PAM areas and are used to specify the memory attributes for each memory segment: These bits apply to both host accesses and PCI initiator accesses to the PAM areas RE Read Enable. When RE = 1, the IA-32 core read accesses to the corresponding memory segment are claimed by the IMCH and directed to main memory. Conversely, when RE = 0, the host read accesses are directed to the IICH’s PCI bus. WE Write Enable. When WE = 1, the host write accesses to the corresponding memory segment are claimed by the IMCH and directed to main memory. Conversely, when WE = 0, the host write accesses are directed to the IICH’s PCI bus. Together, these two bits specify memory attributes (Read-Only, Write Only, Read/Write and Disabled) for each memory segment. These bits only apply to host-initiated access to the PAM areas. The IMCH forwards to main memory any PCI Express initiated accesses to the PAM areas. At the time such PCI Express accesses to the PAM region may occur, the targeted PAM segment must be programmed to Read/Write. It is illegal to issue a PCI Express initiated transaction to a PAM region with the associated PAM register not set to Read/Write. As an example, consider a BIOS that is implemented on the expansion bus. During the initialization process, BIOS can be shadowed to main memory to increase system performance. When BIOS is shadowed to main memory it must be copied to the same address location. To shadow the BIOS, the attributes for that address range must be set to Write-Only. The BIOS is shadowed by first doing a read of that address, which is forwarded to the expansion bus. The host then writes the same address, which is directed to main memory. After BIOS is completely shadowed, the attributes for that memory area are changed to Read-Only so that all writes are forwarded to the expansion bus. Figure 10-4 and Table 10-5 show the PAM registers and the associated attribute bits.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 273 Intel® EP80579 Integrated Processor Figure 10-4. PAM Associated Attribute Bits Table 10-5. PAM Associated Attribute Bits PAM Reg Attribute Bits Memory Segment Comments D0:F0 Offset PAM0 03:00, 07:06 Reserved — Reserved 59h PAM0 05:04 WE RE 0F0000h–0FFFFFh BIOS Area 59h PAM1 03:02, 07:06 Reserved — Reserved 5Ah PAM1 01:00 WE RE 0C0000h–0C3FFFh BIOS Area 5Ah PAM1 05:04 WE RE 0C4000h–0C7FFFh BIOS Area 5Ah PAM2 03:02, 07:06 Reserved — Reserved 5Bh PAM2 01:00 WE RE 0C8000h–0CBFFFh BIOS Area 5Bh PAM2 05:04 WE RE 0CC000h–0CFFFFh BIOS Area 5Bh PAM3 03:02, 07:06 Reserved — Reserved 5Ch PAM3 01:00 WE RE 0D0000h–0D3FFFh BIOS Area 5Ch PAM3 05:04 WE RE 0D4000h–0D7FFFh BIOS Area 5Ch PAM4 03:02, 07:06 Reserved — Reserved 5Dh PAM4 01:00 WE RE 0D8000h–0DBFFFh BIOS Area 5Dh PAM4 05:04 WE RE 0DC000h–0DFFFFh BIOS Area 5Dh PAM5 03:02, 07:06 Reserved — Reserved 5Eh PAM5 01:00 WE RE 0E0000h–0E3FFFh BIOS Extension 5Eh PAM5 05:04 WE RE 0E4000h–0E7FFFh BIOS Extension 5Eh PAM6 03:02, 07:06 Reserved — Reserved 5Fh PAM6 01:00 WE RE 0E8000h–0EBFFFh BIOS Extension 5Fh PAM6 05:04 WE RE 0EC000h–0EFFFFh BIOS Extension 5Fh PAM6 5Fh PAM1 PAM2 PAM3 PAM4 PAM5 5Ah 5Bh 5Ch 5Dh 5Eh Offset WERRRER WE RER 70 123456 Reserved Reserved Write Enable (R/W) 1 = Enable 0 = Disable Read Enable (R/W) 1 = Enable 0 = Disable Reserved Reserved Write Enable (R/W) 1 = Enable 0 = Disable Read Enable (R/W) 1 = Enable 0 = Disable 59hPAM0 HI Segment LO Segment Reserved

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See Section 16.1.1.17, “Offset 59h: PAM0 - Programmable Attribute Map 0 Register” through Section 16.1.1.23, “Offset 5Fh: PAM6 - Programmable Attribute Map 6 Register” for more register information on PAM memory space registers.

10.1.4 TSEG SMM Memory Space

The TSEG SMM space allows system management software to partition a region of main memory just below the top of low memory (TOLM) that is accessible only by system management software. Size 128kB, 256kB, 512kB, or 1 MByte in size, depending upon the must be below 4 GBytes, so it is specified relative to TOLM and not relative to the top of physical memory. Enabling SMM memory is globally enabled by EXSMRC.G_SMRAME (see Section 16.1.1.25). Requests may access SMM system memory when either SMM space is open (see SMRAM.D_OPEN in Section 16.1.1.26) or the IMCH receives an SMM code request on its processor bus. Access In order to access the TSEG SMM space, the TSEG must be these conditions are met, then a processor bus access to the TSEG space (between TOLM-TSEG and TOLM) is sent to system memory. If the high SMRAM is not enabled or if the TSEG is not enabled, then all memory requests from all interfaces are forwarded to system memory. If the TSEG SMM space is enabled, and an agent attempts a non-SMM access to TSEG space, then the transaction is specially terminated. Inbound accesses from NSI or PCI Express ports are not allowed to access SMM space.

10.1.5 PCI Express Enhanced Configuration Aperture

PCI Express defines a memory-mapped aperture mechanism through which to access 4 Kbyte of PCI configuration register space for each possible bus, device, and function number. This 4 Kbyte space includes the compatible 256 B of register offsets that are traditionally accessed via the legacy CF8/CFC configuration aperture mechanism in I/O address space, making the enhanced configuration mechanism a full superset of the legacy mechanism. The enhanced mechanism has the advantage that full destination and type of access is specified in a single memory-mapped uncacheable transaction on the FSB, which is both faster and more robust than the historical I/O-mapped address and data register access pair. Table 10-6. TSEG SMM Memory Space From To TSEGSMM TOLM - TSEG TOLM Table 10-7. PCI Express Enhanced Configuration Aperture From To HECREGION 0_E000_0000 0_EFFF_FFFF

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 275 Intel® EP80579 Integrated Processor CMI places the enhanced configuration aperture at E000_0000h by default, as this is the first contiguous 256 MByte location below the 4 GByte boundary available for such usage. CMI provides for relocation of this aperture via the HECBASE register (see Section 16.1.1.35, “Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced Configuration Base Address Register”, although validation of moving the region is minimal.

10.1.6 IOAPIC Memory Space

The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that may be populated on NSI through PCI-Express port A (PEA). Since it is difficult to relocate an interrupt controller using plug-and-play software, fixed address decode regions have been allocated for them. Processor accesses to the IOAPIC0 region are always sent to NSI. Processor accesses to the IOAPIC2 region are always sent to PEA. These regions are subject to the APIC disable, which are cleared by BIOS after the allocated regions have been reflected down to the base registers of APIC controllers discovered during standard enumeration. Until this step of the initialization sequence has been performed, accesses to these regions are treated as subtractive decode and routed to NSI. The IMCH does not support an IOAPIC range for the EDMA controller or the AIOC, since there is no IOxAPIC device or corresponding register set integrated into the EDMA controller or the AIOC.

10.1.7 FSB Interrupt Memory Space

The FSB Interrupt space is the address range used to deliver interrupts to the FSB. Any device below AIOC, NSI or a PCI Express port may issue a Memory Write to 0FEEx_xxxxh. The IMCH will forward this Memory Write along with its associated data to the FSB as a Message Signaled Interrupt (MSI) transaction. The IMCH terminates the FSB transaction by asserting TRDY# and providing the response. This Memory Write cycle does not go to DRAM. Reads to this address range are aborted by the IMCH. Table 10-8. IOAPIC Memory Space From To IOAPIC0 (NSI) 0_FEC0_0000 0_FEC7_FFFF IOAPIC2 (PEA0) 0_FEC8_0000 0_FEC8_0FFF IOAPIC3 (PEA1) 0_FEC8_1000 0_FEC8_1FFF Table 10-9. FSB Interrupt Memory Space From To FSBINTR 0_FEE0_0000 0_FEEF_FFFF

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10.1.8 High SMM Memory Space

The HIGHSMM space allows cacheable access to the compatible SMM space by remapping valid SMM accesses between 0_FEDA_0000 and 0_FEDB_FFFF to physical accesses between 0_000A_0000 and 0_000B_FFFF. The accesses are remapped when SMRAM space is enabled, an appropriate access is detected on the processor bus, and Inbound SMM memory accesses from any port are specially terminated; reads are provided with data retrieved from address 0, while writes are ignored entirely (all byte enables deasserted).

10.1.9 PCI Device Memory (MMIO)

The IMCH provides two distinct regions of memory that may be mapped to populated PCI devices. The first is the traditional (non-prefetchable) MMIO range, which must lie below the 4 GByte boundary. The registers associated with non-prefetchable MMIO (MBASE/MLIMIT, see Section 16.4.1.17, “Offset 20h: MBASE - Memory Base Address Register”/Section 16.4.1.18, “Offset 22h: MLIMIT - Memory Limit Address Register”) are unchanged from historical 32-bit architecture IMCH implementations. The second is the prefetchable MMIO range, which has been extended in CMI such that it may lie on either side of the 4 GByte boundary. The registers associated with prefetchable MMIO (PMBASE/PMLIMIT, see Section 16.4.1.19, “Offset 24h: PMBASE - Prefetchable Memory Base Address Register”/Section 16.4.1.20, “Offset 26h: PMLIMIT - Prefetchable Memory Limit Address Register”) have been augmented by the PCI defined upper 32- bit base/limit register pair (PMBASU/PMLMTU, see Section 16.4.1.21, “Offset 28h: PMBASU - Prefetchable Memory Base Upper Address Register”/Section 16.4.1.22, “Offset 2Ch: PMLMTU - Prefetchable Memory Limit Upper Address Register”), although only the first nibble of each register is implemented in the IMCH. The MBASE/MLIMIT pair must be programmed to lie between TOLM and 4 GBytes. The PMBASE/PMLIMIT and PMBASU/PMLMTU registers must be programmed to lie between TOLM and 4 GBytes. Because these registers define a PCI memory space, they are subject to the memory access enable (MAE) control bit in the standard PCI command register (see Section 16.4.1.4, “Offset 04h: PCICMD - PCI Command Register”). Note: Using the same address space as both cacheable and non cacheable is discouraged. Also, assigning and writing the same host address space to two independent downstream devices is also discouraged. Although not illegal, both of the above conditions are very difficult to setup intelligently and validate. If 2 devices decide to use the same memory space, and they both send write cycles to it (both either cacheable or uncacheable), there are no guarantees that device 1 data (being older) will get there before device 2 data (being newer) if they do not use a flagging mechanism. Table 10-10.High SMM Memory Space From To HIGHSMM 0_FEDA_0000 0_FEDB_FFFF

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10.1.9.1 Device 2 Memory and Prefetchable Memory

Plug-and-play software configures the PEA a memory window in order to provide enough memory space for the devices behind this virtual PCI-to-PCI bridge. Accesses whose addresses fall within these windows are decoded and forwarded to PEA0 for completion. Note that neither region should overlap with any other fixed or relocate- able area of memory. Also note that PCICMD2 refers to PCICMD for device 2.

10.1.9.2 Device 3 Memory and Prefetchable Memory

Plug-and-play software configures the PEA1 memory window in order to provide enough memory space for the devices behind this virtual PCI-to-PCI bridge. Accesses whose addresses fall within this window are decoded and forwarded to PEA1 for completion. Note that neither region should overlap with any other fixed or relocate- able area of memory. Also note that PCICMD3 refers to PCICMD for device 3. Note: If PCI Express Port A0 is configured to operate in x8 mode, all functional space for PEA1 disappears; effectively collapsing M3/PM3 to match the limit addresses of M2/PM2.

10.1.9.3 Device 4 Memory and Prefetchable Memory

Plug-and-play software configures the PCI memory window in order to provide enough memory space for the devices behind this virtual PCI-to-PCI bridge. Accesses whose addresses fall within this window are decoded and forwarded to PCI for completion. Note that neither region should overlap with any other fixed or relocate-able area of memory. Also note that PCICMD4 refers to PCICMD for device 4. Table 10-11.Device 2 Memory and Prefetchable Memory From To M2 MBASE2 MLIMIT2 PM2 PMBASE2/PMBASU2 PMLIMIT2/PMLMTU2 Table 10-12.Device 3 Memory and Prefetchable Memory From To M3 MBASE3 MLIMIT3 PM3 PMBASE3/PMBASU3 PMLIMIT3/PMLMTU3 Table 10-13.Device 4 Memory and Prefetchable Memory From To M4 MBASE4 MLIMIT4 PM4 PMBASE4/PMBASU4 PMLIMIT4/PMLMTU4

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10.2 IMCH Responses to EDMA Transactions

In the following tables, the term “Abort” implies that the EDMA engine will immediately stop the transfer in progress. The offending access will not be forwarded to the inbound/outbound arbiter at all, an error bit will be set accordingly, and the error will be escalated as specified by the configuration bits controlling interrupts and errors. Note: This behavior is quite different from the and PCI Express inbound ports, as in the latter cases the transaction in question was requested by some other initiator elsewhere in the platform. The EDMA engine is a source of traffic all by itself, which makes error containment much simpler in the case of EDMA traffic.

10.2.1 Fixed Address Spaces (EDMA)

Table 10-14 summarizes IMCH responses to EDMA accesses to the various fixed address spaces.

10.2.2 Relocatable Address Spaces (EDMA)

Table 10-15 summarizes IMCH responses to EDMA accesses to the various relocatable address spaces. Table 10-14.EDMA Accesses to Fixed Address Spaces Address Space Conditions Destination IMCH Response DOSMEM - MainMem Transaction is sent to memory system VGAA VGAB MDA PAMC0… PAMF0 -A b o r t Programmer’s responsibility not to target EDMA accesses in the legacy region between 640KB and 1 MByte MEM1_15 - MainMem Transaction is sent to memory system ISA15 FDHC.HEN = 0 MainMem Hole Disabled: Transaction is sent to memory system FDHC.HEN = 1 Abort Hole Enabled: EDMA will abort on accesses directed to the ISA hole when enabled MAINMEM - MainMem Transaction is sent to memory system (unless address hits an enabled TSEG SMM range. See TSEGSMM) TSEGSMM - Variable Refer to Table 10-16, “Supported SMM Ranges”. IOAPIC[0,2-3] - Abort Programmer’s responsibility to avoid the APIC ranges FSBINTR - Abort Programmer’s responsibility to avoid the FSB interrupt messaging range HIGHSMM - Variable Refer to Table 10-16, “Supported SMM Ranges”. HIGHMEM Address is below the top of memory space defined by TOM and the REMAP registers MainMem Transaction is sent to memory system. Address is above the top of memory Abort Hardware will detect an attempt to access above the populated DRAM space, and will abort.

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10.3 I/O Address Space

The IMCH generates outbound transactions on behalf of all IA-32 core I/O accesses. The IMCH contains two internal registers in the IA-32 core I/O space dedicated to the configuration access mechanism; the Configuration Address Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA). The behavior of the IMCH in response to accesses to these registers is described in Chapter 13.0, “Platform Configuration.” The IA-32 core allows 64 K+3 bytes to be addressed within the I/O space. The IMCH propagates the IA-32 core I/O address without any translation to the targeted destination bus. Note that the upper three locations can be accessed only during I/O address wrap-around; when signal A16# is asserted on the processor bus. A16# is asserted on the processor bus whenever a Dword I/O access is made from address 0FFFDh, 0FFFEh, or 0FFFFh. In addition, A16# is asserted when software attempts a two-byte I/O access from address 0FFFFh. All I/O accesses (read or write) which do not map to internal IMCH registers will receive a DEFER response on the FSB, and be forwarded to the appropriate outbound port. The IMCH never posts an I/O write. The IMCH never responds to inbound transactions to I/O or configuration space initiated on any port. Inbound I/O or configuration transactions requiring a completion are terminated with “master abort” completion packets on the originating port interface. Inbound I/O or configuration write transactions not requiring completion are dropped.

10.3.1 Configuration Window

The I/O addresses 0CF8h and 0CFCh are treated specially, as they define the compatible configuration window. Dword accesses to 0CF8h address the internal IMCH configuration address register. Accesses from 1 to 4 bytes in size to the region from 0CFC-0CFFh are treated as configuration data accesses if configuration space is enabled (bit31 of the configuration address register is set). Refer to Chapter 13.0, “Platform Configuration.” for further details. Table 10-15.EDMA Accesses to Relocatable Address Spaces Address Space Conditions Destination IMCH Response NSI: M NSI: PM - Abort No support for EDMA destination on NSI PEA: M[n] PEA: PM[n] Write, MAE = 1 PEA[n] Transaction forwarded to destination PEA port. Write, MAE = 0 Abort Abort. Memory access disabled. Read Transaction Abort Abort. No support for peer segment reads. NSI_SUB - Abort No support for EDMA destination on NSI PEA: PM[n] Write, MAE = 1 PEA[n] Transaction forwarded to destination PEA port. Write, MAE = 0 Abort Abort. Memory access disabled. Read Transaction Abort Abort. No support for peer segment reads.

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10.3.2 VGA and MDA Regions

Along with the memory space address regions described in Section 10.1.2, “VGA and MDA Memory Spaces”, there are fixed I/O locations associated with both the VGA and the MDA regions. Accesses to these addresses are routed to NSI by default, but this behavior may be modified via the VGAEN, MDAP and MAE configuration settings. Refer to the prior sections for the rules associated with the configuration settings of VGAEN, MDAP and MAE. The MDA region includes I/O space addresses 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh. The VGA region includes I/O space ranges 3B0-3BBh, and 3C0-3DFh. The PCI Specification defines both MDA and VGA to be 10-bit address decode, thus all accesses with A[9:0] matching any of these addresses are subject to the associated routing rules. Address bits A[15:10] are ignored when the check against these fixed addresses are applied. The order of precedence for the routing checks is as follows:

MAE = 0, MDA addresses will route to NSIif MDAP is set, overriding any VGAEN.
MAE = 1, MDA addresses will route to the Peer device if MDAP is set, overriding any VGAEN.
MAE = 0, VGA addresses will route to the NSI
MAE = 1, VGA addresses will route to the PCI Express port with its VGAEN set, if any.
MAE = 0, MDA addresses which fall within VGA regions will route to the NSI if MDAP is clear.
MAE = 1, MDA addresses which fall within VGA regions will follow VGAEN if MDAP is clear.
Both VGA and MDA addresses default to NSI if MDAP and all VGAEN bits are clear. Note: Setting of MDAP or any of the VGAEN bits implies that the ISAEN bit is also set in all virtual P2P bridges, because of the 10-bit decode requirement. Note: AIOC access to this space is not supported. Upstream attempted accesses to this space are programming errors and will result in a master abort.

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10.4 Main Memory Addressing

The “High Memory” and “Extended Memory” address regions are together called “Main Memory.” Main memory is composed of address segments that refer to DDR SDRAM system memory. Main memory addresses are mapped to DDR SDRAM channels, devices, banks, rows, and columns in different ways depending upon the type of memory being used and upon the density or organization of the memory. The process for determining the device and channel IDs for addressed devices is as follows:

The requested address is compared agains t the values of all eight DRB registers. The number of the register whose programmed value is greater than the address and whose previous register is less than the address is the output of the comparison.
The value of the DRB register “below” is subtracted from the address in order to determine the offset into the group.
The offset determines the manner in which the row, column, and bank address bits are extracted from the address.

10.5 System Management Mode (SMM) Space

CMI supports the use of main memory as System Management RAM (SMM RAM) enabling the use of System Management Mode. The IMCH supports three SMM options:

Compatible SMRAM (C_SMRAM)
H i g h S e g m e n t ( H S E G )
Top of Memory Segment (TSEG) System Management RAM space provides an access protected memory area that is available for SMI handler code and data storage. This memory resource is normally hidden from the Operating System so that the processor has immediate access to this memory space upon entry to SMM (cannot be swapped-out).

10.5.1 SMM Addressing Ranges

IMCH provides three SMRAM options:

Below 1 MByte option that supports compatible SMI handlers.
Above 1 MByte option that allows new SMI handlers to execute with write-back cacheable SMRAM.
Optional larger write-back cacheable T_SEG area from 128 Kbyte to 1 MByte in size. The above 1 MByte solutions require changes to compatible SMRAM handler code to properly execute above 1 MByte. Note: The first two options both map legal accesses to the same physical range of memory, while the third defines an independent region of addresses.

10.5.1.1 SMM Space Restrictions

If any of the following conditions are violated, the results of SMM accesses are unpredictable and may cause the system to hang:

The Compatible SMM space must not be set-up as cacheable.
Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as available DRAM. This is a BIOS responsibility.

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BIOS and SMM code must cooperate to properly configure the IMCH in order to ensure reliable operation of the SMM function.

10.5.1.2 SMM Space Definition

SMM space is defined by both its addressed SMM space and its DRAM SMM space. The addressed SMM space is defined as the range of FSB addresses used by the IA-32 core to access SMM space. DRAM SMM space is defined as the range of physical DRAM memory locations containing SMM information. The SMM space can be accessed at one of three transaction address ranges:

C o m p a t i b l e
H i g h
T S E G The Compatible and TSEG SMM space is not remapped and therefore the addressed and DRAM SMM physical addresses are identical. The High SMM space is remapped; thus the addressed and DRAM SMM locations are different. Note that the High DRAM space is the same as the Compatible Transaction Address space. Table 10-16 describes all three unique addressing combinations:
Compatible Transaction Address
High Transaction Address
TSEG Transaction Address Table 10-16. Supported SMM Ranges SMM Space Enabled Transaction Address Space (Adr) DRAM Space (DRAM) Compatible (C) A0000h to BFFFFh A0000h to BFFFFh High (H) 0FEDA0000h to 0FEDBFFFFh A0000h to BFFFFh TSEG (T) (TOLM-TSEG_SZ) to TOLM (TOLM-TSEG_SZ) to TOLM Notes: 1. High SMM: This implementation is consistent with the Intel E7500 and Intel E7501 designs. In prior MCH designs the High segment was the 384 Kbyte region from A_0000h to F_FFFFh. However C_0000h to F_FFFFh was not useful, so it has been deleted in the IMCH design. 2. TSEG SMM: This implementation is consistent with the Intel E7500 and Intel E7501 designs. In prior MCH designs the TSEG address space was offset by 256 MBytes to allow for simpler decoding and the TSEG was remapped to just under the TOLM. In the IMCH the TSEG region is not offset by 256 MBytes and it is not remapped. 3. In Cases where DRAM TOLM is less than TOM TSEG cannot be used for SMM. For this case MENC memory spans consecutive space from above TOLM to below TOLM and will conflict with TSEG space

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10.6 Memory Reclaim Background

The following Memory Mapped I/O devices and ranges are typically located below 4 GBytes:

H i g h B I O S
H - S e g
X A P I C
L o c a l A P I C
FSB Interrupts
PEA0 through PEA1 M, PM and BAR regions In previous generation MCH architectures, the physical DRAM memory overlapped by the logical address space allocated to these Memory Mapped I/O devices was unusable. In server systems the memory allocated to memory mapped I/O devices could easily exceed 1 GByte. This creates the possibility of a large amount of physical memory populated in the system becoming unusable. The IMCH provides the capability to reclaim the physical memory overlapped by the Memory Mapped I/O logical address space via remapping physical memory from the Top of Low Memory (TOLM) boundary up the 4 GBytes boundary (or TOM if less than 4 GBytes) to an equivalent sized logical address range located just above the top of physical memory

10.6.1 Memory Remapping Algorithm

Note: The IA-32 core is not capable of using the remap capability and care must be taken to ensure that no addresses sent to the IA-32 core are greater than TOLM in that it will cause aliasing. The remap capability can be utilized by the AIOC, IICH and PCIe ports. Terminology clarification: Physical Address The address presented to the IMCH is traditionally called a “physical address,” because Intel architecture processors contain both segmentation and paging hardware, and all compatible software differentiates between logical addresses, virtual addresses, and physical addresses. The algorithm for remapping addresses presented to the IMCH to reclaim DRAM address space must be implemented such that the mechanism is invisible to compatible software. System Address The system address applies to the internal IMCH interface to physical DRAM memory, and is not directly visible to software, other than through certain internal logging registers used to store decoded DRAM address information for error isolation. An incoming address (referred to as a physical address) is checked to see if it falls in the memory remap window. The bottom of the remap window is defined by the value in the REMAPBASE register (see Section 16.1.1.31, “Offset C6h: REMAPBASE - Remap Base Address Register”). The top of the remap window is defined by the value in the REMAPLIMIT register (Section 16.1.1.32, “Offset C8h: REMAPLIMIT – Remap Limit Address Register”). An address that falls within this window is remapped to the physical memory starting at the address defined by the TOLM register.

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10.7 IICH Register and Memory Mappings

This section covers CMI’s IICH various address decoding ranges. This section is for background purposes, and must not to be considered by implementers and validators as part of the behavioral definition of CMI. Each decode range is described elsewhere in the section associated with the corresponding function.

10.7.1 I/O Map

The I/O map is divided into separate types. Fixed ranges cannot be moved, but in some cases can be disabled. Variable ranges can be moved and can also be disabled.

10.7.1.1 Fixed I/O Address Ranges

Table 10-17 shows the Fixed I/O decode ranges from the IA-32 core perspective. Note that for each I/O range, there may be separate behavior for reads and writes. Cycles that go to target ranges that are marked as Reserved will not be decoded, and are passed to PCI to PCI Bridge where they are dropped. Address ranges that are not listed or marked reserved are NOT positively decoded by the IICH (unless assigned to one of the variable ranges). In subtractive mode, I/O ranges that are not otherwise decoded are forwarded to PCI to PCI Bridge where they are dropped. Table 10-17. Fixed I/O Ranges Decoded by IICH (Sheet 1 of 3) I/O Address Read Target Write Target Internal Unit Separate Enable/ Disable 00h – 08h DMA Controller DMA Controller DMA None 09h – 0Eh RESERVED DMA Controller DMA None 0Fh DMA Controller DMA Controller DMA None 10h – 18h DMA Controller DMA Controller DMA None 19h – 1Eh RESERVED DMA Controller DMA None 1Fh DMA Controller DMA Controller DMA None 20h – 21h Interrupt Controller Interrupt Controller Interrupt None 24h – 25h Interrupt Controller Interrupt Controller Interrupt None 28h – 29h Interrupt Controller Interrupt Controller Interrupt None 2Ch – 2Dh Interrupt Controller Interrupt Controller Interrupt None 2E – 2F LPC SIO LPC SIO Forwarded to LPC Yes 30h – 31h Interrupt Controller Interrupt Controller Interrupt None 34h – 35h Interrupt Controller Interrupt Controller Interrupt None 38h – 39h Interrupt Controller Interrupt Controller Interrupt None 3Ch – 3Dh Interrupt Controller Interrupt Controller Interrupt None 40h – 42h Timer/Counter Timer/Counter PIT (8254) None 43h RESERVED Timer/Counter PIT None 4E – 4F LPC SIO LPC SIO Forwarded to LPC Yes 50h – 52h Timer/Counter Timer/Counter PIT None 53h RESERVED Timer/Counter PIT None 60h Microcontroller Microcontrolle r Forwarded to LPC Yes w/ 64h

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1 NMI Controller1 IA-32 core Interface Yes, alias to 61h

64h Micocontroller Microcontroller Forwarded to LPC Yes w/ 60h 65h NMI Controller 1 NMI Controller1 IA-32 core Interface Yes, alias to 61h 66h Microcontroller Microcontroller Forwarded to LPC Yes w/ 62h 67h NMI Controller 1 NMI Controller1 IA-32 core Interface Yes, alias to 61h 70h RESERVED NMI and RTC Controller RTC None 71h RTC Controller RTC Controller RTC None 72h RTC Controller NMI and RTC Controller RTC Yes, w/ 73h 73h RTC Controller RTC Controller RTC Yes, w/ 72h 74h RTC Controller NMI and RTC Controller RTC None 75h RTC Controller RTC Controller RTC None 76h RTC Controller NMI and RTC Controller RTC None 77h RTC Controller RTC Controller RTC None 80h DMA Controller, or LPC DMA Controller, or LPC DMA None 81h – 83h DMA Controller DMA Controller DMA None 84h – 86h DMA Controller DMA Controller and LPC DMA None 87h DMA Controller DMA Controller DMA None 88h DMA Controller DMA Controller and LPC DMA None 89h – 8Bh DMA Controller DMA Controller DMA None 8Ch – 8Eh DMA Controller DMA Controller and LPC DMA None 8Fh DMA Controller DMA Controller DMA None 90h – 91h DMA Controller DMA Controller DMA Yes, alias to 8xh 92h Reset Generator Reset Generator IA-32 core Interface None 93h – 9Fh DMA Controller DMA Controller DMA Yes, alias to 8xh A0h – A1h Interrupt Controller Interrupt Controller Interrupt None A4h – A5h Interrupt Controller Interrupt Controller Interrupt None A8h – A9h Interrupt Controller Interrupt Controller Interrupt None ACh – ADh Interrupt Controller Interrupt Controller Interrupt None B0h – B1h Interrupt Controller Interrupt Controller Interrupt None B2h – B3h Power Management Power Management Power Management None B4h – B5h Interrupt Controller Interrupt Controller Interrupt None B8h - B9h Interrupt Controller Interrupt Controller Interrupt None BCh – BDh Interrupt Controller Interrupt Controller Interrupt None C0h – D1h DMA Controller DMA Controller DMA None D2h – DDh RESERVED DMA Controller DMA None DEh – DFh DMA Controller DMA Controller DMA None 170h – 177h SATA SATA SATA Yes Table 10-17.Fixed I/O Ranges Decoded by IICH (Sheet 2 of 3) I/O Address Read Target Write Target Internal Unit Separate Enable/ Disable

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10.7.1.2 Variable I/O Decode Ranges

Table 10-18 shows the Variable I/O Decode Ranges. They are set using Base Address Registers (BARs) or other configuration bits in the various configuration spaces. The PnP software (PCI or ACPI) can use their configuration mechanisms to set and adjust these values. Warning: The Variable I/O Ranges must not be set to conflict with the Fixed I/O Ranges. If the configuration software allows conflicts to occur, it may produce unpredictable results. There are no checks for conflicts. 1F0h – 1F7h SATA SATA SATA Yes 200 – 207h Gameport Low Gameport Low Forwarded to LPC Yes 208 – 20Fh Gameport High Gameport High Forwarded to LPC Yes 376h SATA SATA SATA Yes 3F6h SATA SATA SATA Yes 4D0h – 4D1h Interrupt Controller Interrupt Controller Interrupt None CF9h Reset Generator Reset Generator IA-32 core Interface None Notes: 1. Only if the Port 61 Alias Enable bit (GCS.P61AE) bit is set. Otherwise, the target is dropped. Table 10-17. Fixed I/O Ranges Decoded by IICH (Sheet 3 of 3) I/O Address Read Target Write Target Internal Unit Separate Enable/ Disable Table 10-18. Variable I/O Decode Ranges Range Name Mappable Size (Bytes) Target ACPI Anywhere in 64K I/O Space 64 Power Management USB #1 Anywhere in 64K I/O Space (See Note 1) 32 USB1 Host Controller 1 SMBus Anywhere in 64K I/O Space 32 SMB Unit TCO 96 bytes above ACPI base 32 TCO Unit GPIO Anywhere in 64K I/O space 64 GPIO Unit Parallel Port 3 ranges in 64K I/O Space 8 2 LPC Peripheral Serial Port 1 8 Ranges in 64K I/O Space 8 LPC Peripheral Serial Port 2 8 Ranges in 64K I/O Space 8 LPC Peripheral Floppy Disk Controller 2 Ranges in 64K I/O Space 8 LPC Peripheral LPC Generic 1 Anywhere in 64K I/O Space 128 LPC Peripheral LPC Generic 2 Anywhere in 64K I/O Space 16 LPC Peripheral I/O Trapping Ranges Anywhere in 64K I/O Space 1 to 256 Bytes Trap on Internal I/O Data Bus Notes: 1. These ranges are decoded directly. 2. There is also an alias 400h above the parallel port range that is used for ECP parallel ports.

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10.7.2 Memory Map

Table 10-19 shows (from the IA-32 core perspective) the memory ranges that are decoded. Cycles that arrive that are not directed to any of the internal memory targets that decode (see Table 10-19)are dropped. Software must not attempt locks to the IICH’s memory-mapped I/O ranges for USB 2.0, and HPET (High Precision Event Timer). If attempted, the lock is not honored which means potential deadlock conditions may occur. Table 10-19.IICH Memory Decode Ranges (from IA-32 core Perspective) Memory Range Target Dependency/Comments 000E0000 - 000EFFFF FWH Bit 6 in FWH Decode Enable Register is set. 000F0000 - 000FFFFF FWH Bit 7 in FWH Decode Enable Register is set FEC00000 - FEC0 0040 I/O(x)APIC inside IICH FFC0 0000 - FFC7 FFFF FF80 0000 - FF87 FFFF FWH Bit 8 in FWH Decode Enable Register FFC8 0000 – FFCF FFFF FF88 0000 - FF8F FFFF FWH Bit 9 in FWH Decode Enable Register FFD0 0000 - FFD7 FFFF FF90 0000 - FF97 FFFF FWH Bit 10 in FWH Decode Enable Register is set FFD8 0000 – FFDF FFFF FF98 0000 - FF9F FFFF FWH Bit 11 in FWH Decode Enable Register is set FFE0 000 - FFE7 FFFF FFA0 0000 - FFA7 FFFF FWH Bit 12 in FWH Decode Enable Register is set FFE8 0000 – FFEF FFFF FFA8 0000 – FFAF FFFF FWH Bit 13 in FWH Decode Enable Register is set FFF0 0000 - FFF7 FFFF FFB0 0000 - FFB7 FFFF FWH Bit 14 in FWH Decode Enable Register is set FFF8 0000 – FFFF FFFF FFB8 0000 – FFBF FFFF FWH Always enabled. The top two 64KB blocks in this range can be swapped by the IICH. See Section 10.5 for details. FF70 0000 - FF7F FFFF FF30 0000 - FF3F FFFF FWH Bit 3 in FWH Decode Enable 2 Register is set FF60 0000 - FF6F FFFF FF20 0000 - FF2F FFFF FWH Bit 2 in FWH Decode Enable 2 Register is set FF50 0000 - FF5F FFFF FF10 0000 - FF1F FFFF FWH Bit 1 in FWH Decode Enable 2 Register is set FF40 0000 - FF4F FFFF FF00 0000 - FF0F FFFF FWH Bit 0 in FWH Decode Enable 2 Register is set 1KB anywhere in 4GB range USB 2.0 Host Controller Enable via standard PCI mechanism (Device 29, Function 7) FED0 X000h-FED0 X3FFh HPET BIOS determines “fixed” location which is one of four 1KB ranges where X (in the first column) is 0h, 1h, 2h, or 3h. All other N/A Master aborted

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10.7.3 Boot-Block Update Scheme

The IICH supports a “Top-Block Swap” mode that swaps the top block in the FWH (the boot block) with another location. This allows for safe update of the Boot Block (even if a power failure occurs). When the “top-swap” enable bit is set, inverts A16 for cycles going to the upper two 64 Kbyte blocks in the FWH. Specifically, in this mode, accesses to FFFF_0000h-FFFF_FFFFh are directed to FFFE_0000h-FFFE_FFFFh and vice versa. When the Top Swap Enable bit is 0, the IICH will not invert A16. This bit is automatically set to 0 by RTEST#, but not by PLTRST#. The scheme is based on the concept that the top block is reserved as the “boot” block, and the block immediately below the top block is reserved for doing boot-block updates. The algorithm is: 1. Software copies the top block to the block immediately below the top. 2. Software checks that the copied block is correct. This could be done by performing a checksum calculation. 3. Software sets the “Top-Block Swap” bit. This will invert A16 for cycles going to the FWH. 4. Software erases the top block. 5. Software writes the new top block. 6. Software checks the new top block. 7. Software clears the top-block swap bit. 8. Software sets the Top_Swap Lock-Down bit. If a power failure occurs at any point after step 3, the system is able to boot from the copy of the boot block that is stored in the block below the top. This is because the top- swap bit is backed in the RTC well. Note: The top-block swap mode may be forced by an external strapping option (see Chapter 16.0, “IMCH Registers.”). When top-block swap mode is forced in this manner, the TOP_SWAP bit cannot be cleared by software. A reboot with the strap removed will be required to exit a forced top-block weap mode. Note: Top-block swap mode only affects accesses to the Firmware Hub space, not feature space. Note: The top-block swap mode has no effect on accesses below FFFE_0000h. § §

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11.0 System Memory Controller

11.1 Overview

The memory controller is responsible for controlling the off-chip DRAM devices. The unit scheduler, control and protocol state machines access DRAM devices over a wide range of speed bins using DDR2 DRAM technology. The EP80579 supports one memory channel.

11.2 Memory Controller Feature List

The memory controller supports the following features

Supports 1 DIMM — DDR2 — 64 and 32-bit mode. — Single rank (64 or 32-bit mode) or Dual rank (64 bit mode) device. — DDR2-400, DDR2-533, DDR2-667, DDR2-800. — See to “Rules for Populating DIMM Slots” for more details.
Supports dual DIMMs — DDR2 and 64 bit mode only — Registered Dual DIMM support with 1T command/address timing. Unbuffered Dual DIMM support with 2T command/address timing. Please refer to “2T Timing Mode” for details. — 32-bit mode dual DIMM is not supported — Restrictions on speed, number of ranks and modes in 2 DIMM mode, refer to “Rules for Populating DIMM Slots” for details. — DDR2-400 is supported. — DDR2-533 and DDR2-667 are also supported with special design guidelines. Refer to Table 11-5 for more details.
Supports 32-bit mode — 32-bit mode is for memory-down configuration, thus the following modes are not supported: dual DIMM, dual rank, registered
Supports 256 Mb, 512 Mb, 1 Gb and 2 Gb density parts in the x8 configuration. Table 11-1 shows the various DDR2 device densities and widths supported. Table 11-2 and Table 11-3 shows the various memory capacity configurations supported using these parts in the 64 bit and 32-bit modes. — Memory Controller does not support 4 Gb density — See Section 11.3, “Configurations” for more details.
Supports 4-bank devices — 256 Mb and 512 Mb DDR2 parts

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Supports 8-bank devices. — 1 Gb and 2 Gb DDR2 parts
Supports unbuffered and registered DIMMs
Supports discrete memory components soldered on the board — supports 2 DQ loads similar to the double sided DIMM configuration.
One 72b wide DRAM interface, 64b data + 8b ECC. — The 64b data interface can optionally configured to be a 32b interface with 8b ECC. The 32b option provides half the total bandwidth compared to the 64b interface, and meets the requirements for systems that are cost sensitive and want to populate small memory footprint soldered on the mother board.
Supports burst-of-4 mode with a minimum access size of 32B for the 64b interface. — On the 64b interface accesses longer than 32B are serviced as multiple burst- of-4 transactions without closing the page. — On the 32b interface, the controller supports burst-of-8 for a minimum access size that is still 32B.
Optional error protection using ECC bits and error code that supports SEC/DED (single bit error correction/double bit error detection). Please see “Offset 7Ch: DRC – DRAM Controller Mode Register” for details. — On a single bit error, the memory controller corrects the error bit and writes back the correct data value to DRAM, if enabled by software selection. — Does not support DED (double-bit error detect) retries.
Supports maximum of 4 GB DRAM capacity as shown in Table 11-2. — One memory channel
Support for demand scrub in hardware — Refer to Section 16.1.1.45, “Offset 88h: SDRC – DDR SDRAM Secondary Control Register” on page 439 for details.
Support for background scrubbing in hardware. — Programmable hardware scrub engine that allows background scrub at a wide range of rates, including, but not limited to: up to 4 GB every hour, day, week, or very fast rates, mainly used for validation purposes. The memory controller supports the following transactions
Simple read transactions. — Supported lengths - 1-7B, 8B, 16B, 24B, 32B, 64B — Read transactions smaller than 32B will result in a full 32B read on the interface
Simple write transactions. — Supported lengths - 8B, 16B, 24B, 32B, 64B — Writes of lengths 8B, 16B and 24B will take the same time on the interface as a 32B write, the actual bytes that are written are specified by the DQ masks — Writes of length 40B, 48B, 56B will be treated as a 32B write followed by an 8B, 16B or 24B write — Writes that are smaller than 8B (i.e 1-7B) require a read-modify-write operation and these will be supported upstream in the pipeline in other units. The memory controller will not support read-modify-write operation.
CSR reads and writes

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The memory controller does not support any atomic operations. Other units upstream support atomic operations.
All memory controller operations are aligned on a 64B boundary
The memory controller interleaves the memory across banks on a 64B boundary — Any transaction that crosses a 64B alignment boundary or is larger than 64B must be split by the upstream agent.
Supports external DIMMs or SO-DIMMs.

11.3 Configurations

Table 11-1 shows the various DDR2 device densities and widths supported by the memory controller. Table 11-2 shows the various capacity configurations supported in 64b mode. The first column shows the total DRAM capacity on the channel. The rest of the columns indicate the DRAM devices features, densities and the number of devices required to achieve the given capacity. A single sided DIMM is indicated by no parts populated on side B. Double sided DIMM has parts populated on both sides. For each configuration, an additional DRAM part per side is required to support ECC bits. A x8 part provides all the bits required for ECC. Note that memory system can be built without ECC enabled. In the 64b configuration, the minimum capacity supported is 256 MB and the maximum capacity supported is 4 GB. Table 11-1. Supported DDR2 Device Densities and Width Density (Mb) DDR2x8

256 Supported

512 Supported

1024 Supported

2048 Supported

4096 Not Supported

Table 11-2. Supported DRAM Capacity for 64b Mode Total DRAM Capacity DRAM Density DRAM Part Width Total # of parts on side A (w/o ECC) Total # of parts on side B (w/o ECC)

256 MB 256 Mb x8 8 0

256 Mb x8 8 8

512 Mb x8 8 0

512 Mb x8 8 8

1 Gb x8 8 0

1 Gb x8 8 8

2 Gb x8 8 0

4 GB 2 Gb x8 8 8

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Table 11-3 shows the various configurations supported in the 32b mode.In the 32-bit mode only single rank DDR2 devices are supported. In this mode, the minimum capacity supported is 128 MB and the maximum capacity supported is 1 GB. Note: The EP80579 supports only single ranks in 32-bit mode. Table 11-4 shows the supported DIMM raw cards in the registered and unbuffered formats. Table 11-5 shows the supported DDR2device speed grades for single and Dual DIMMs. Dual DIMM support uses 2N or 2T command/address timing. Table 11-3. Supported DRAM Capacity for 32b Mode Total DRAM Capacity DRAM Density DRAM Part Width Total # of parts on side A (w/o ECC) Total # of parts on side B (w/o ECC)

128 MB 256 Mb x8 4 0

512 MB 1 Gb x8 4 0

1 GB 2 Gb x8 4 0Table 11-4. Raw Cards Supported by the EP80579 Raw Card Number of DDR2 SDRAMs SDRAM Organization Number of Ranks x8, planar, single row RDIMM F9 1 B1 8 2 G1 8 2 D8 1 UDIMM F9 1 E1 6 2 G1 8 2 Table 11-5. Supported DDR2 Data Speeds DDR Speed 1 DIMM 1 rank

1 DIMM

2 DIMMs

DDR2-400 R = 1T UB = 1T R = 1T UB = 1T R = 1T UB = 2T DDR2-533 R = 1T UB = 1T R = 1T UB = 1T R = 1T UB = 2T DDR2-667 R = 1T UB = 1T R = 1T UB = 1T R = 1T UB = 2T DDR2-800 R = 1T UB = 2T R = 1T UB = 2T Not supported R = Registered UB = Unbuffered 1T = 1T Address/Command Timing 2T = 2T Address/Command Timing

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11.3.1 Rules for Populating DIMM Slots

In all configurations, the speed and timing will be the lowest among the 2 DIMMs, as determined by the SPD registers on the DIMMs 2. Dual DIMM mode supports a subset of the DDR2 data speeds as shown in Table 11-5. 3. Table 11-6 shows the supported DIMM population of the 2 ranks. All of configurations not shown in Table 11-6 are not supported.The rank configurations supported are one or two ranks on a single DIMM or one rank on each of the 2 DIMMs. Two ranks in each of the 2 DIMMs (i.e., 4 ranks) is not supported. 4. Table 11-7 shows the supported rank configurations when using 2 ranks for the single and dual DIMM. Table 11-6. Supported DIMM Populations DIMM 1 DIMM 0 Rank 0 Rank 1 Rank 0 Rank 1 1 - Single Rank Empty Empty DRB0 CS0 ODT0 Empty 1 - Dual Rank Empty Empty DRB0 CS0 ODT0 DRB2 CS1 ODT1 2 - Single Rank DRB2 CS1 ODT1 Empty DRB0 CS0 ODT0 Empty TABLE KEY: ODT0/ODT1: ODT pins. Please refer to Section 11.4.2 for more information. CS0/CS1: Chip Selects DRB: Dram Row Boundary Register Table 11-7. Supported Rank Configurations in Single and Dual DIMM mode Single DIMM (DDR2) (64 bits - rank 0 & rank 1) (32 bits - rank 0 only) Dual DIMM (DDR2, 64 bit only) Rank 0 Rank 1 Rank 0, DIMM 0 Rank 0, DIMM 1 128 MB (32 bit only) NA NA NA

256 MB 256 MB 256 MB 256 MB, 512 MB, 1 GB,

512 MB 512 MB 512 MB 256 MB, 512 MB, 1 GB,

1 GB 1 GB 1 GB 256 MB, 512 MB, 1 GB,

2 GB 2 GB 2 GB 256 MB, 512 MB, 1 GB,

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There are additional restrictions when 2 ranks are used. Both the ranks need to be: — Either registered or unbuffered. No mixing of registered and unbuffered ranks. — 64 bit mode only. 32-bit mode is not supported in dual rank. 6. For 32-bit mode, only discrete components of single rank are supported. Two ranks in 32-bit mode is not supported. Table 11-3 shows the supported configurations in the 32-bit mode.

11.3.2 DRAM Addressing

Table 11-8, Table 11-9, Table 11-10 and Table 11-11 show the DRAM device addressing for the various DDR2 device densities supported by the memory controller. Note that:

x4 and x 16 devices are not supported.
4Gb and higher device density parts are not supported.
See Table 11-7 for the supported device densities and widths. Table 11-8. 256Mb Addressing Configuration DDR2

32 Mb x 8

# of Banks 4 Bank Address BA0, BA1 Auto Precharge A10 Row Address A0-A12 Column Address A0-A9 Page Size 1KB Table 11-9. 512Mb Addressing Configuration DDR2

64 Mb x 8

# of Banks 4 Bank Address BA0, BA1 Auto Precharge A10 Row Address A0-A13 Column Address A0-A9 Page Size 1KB Table 11-10. 1Gb Addressing Configuration DDR2

128 Mb x 8

# of Banks 8 Bank Address BA0-BA2 Auto Precharge A10

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11.3.3 Memory Address Translation Tables

Section 11.3.3.1 shows the address bit translation from the system address to the DRAM row/column/bank address for the different DDR2 configurations supported by the memory controller.

256 Mb, 512 Mb, 1024 Mb and 2048 Mb DRAM device densities are shown but please

refer to Table 11-1 for supported DDR2 device densities and widths. The memory capacity that can be achieved for each device density in the single and dual rank mode is also shown in the address mapping tables.

11.3.3.1 DDR2 Address Translation Tables

Figure 11-1 shows the translation tables for 64 bit, burst size 4 devices in x8 width. Note: only burst 4 is supported for a DDR2 64 data bit interface. Figure 11-2 shows the translation tables for 32 bit, burst size 8 devices in x8 width. Note: only burst 8 is supported for a DDR2 32 data bit interface. For a list of memory controller supported DDR2 device types and widths see Table 11-1. Row Address A0-A13 Column Address A0-A9 Page Size 1KB Table 11-11.2Gb Addressing Configuration DDR2

256 Mb x 8

# of Banks 8 Bank Address BA0-BA2 Auto Precharge A10 Row Address A0-A14 Column Address A0-A9 Page Size 1KB Table 11-10.1Gb Addressing Configuration DDR2

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11.3.4 DRAM Timings

The EP80579 is highly configurable in its DRAM timing configuration, but only a limited subset of the setting combinations possible are verified by Intel. The approved and expected settings for the various flavors of supported memory are listed in Table 11-12. For more information on the DRT register see “Offset 78h: DRT0 - DRAM Timing Register 0” and “Offset 64h: DRT1 – DRAM Timing Register 1”. Figure 11-1. Memory Address Tables for 64 Bit, Burst Size 4 and x8 DDR2 Devices Total Cap (M B) Single Rank Device densty (M b) Dev ice widt h Bus Wi d th R/C/B addr lines B A 2B A 1B A 0A 1 4A 1 3A 1 2A 1 1A 1 0A 0 9A 0 8A 0 7A 0 6A 0 5A 0 4A 0 3A 0 2A 0 1 A 0 0 R o w 0 7 6 0 0 2 62 52 42 32 22 12 01 91 81 71 61 5 1 4 C o l 0000 A P 2 7 1 3 1 2 1 1 1 0 9850 0 Row 0 7 6 0 28 26 25 24 23 22 21 20 19 18 17 16 15 14 C o l 0000 A P 2 7 1 3 1 2 1 1 1 0 9850 0 Row 8 7 6 0 28 26 25 24 23 22 21 20 19 18 17 16 15 14 C o l 0000 A P2 71 31 21 11 0 9 2 9 5 0 0 Row 8 7 6 30 28 26 25 24 23 22 21 20 19 18 17 16 15 14 C o l 0000 A P2 71 31 21 11 0 9 2 9 5 0 0 256 512 1024 64 15x10x32048 512 8 1024 8 2048 8 64 14x10x2 64 14x10x3 256 8 64 13x10x2 Figure 11-2. Memory Address Tables for 32 Bit, Burst Size 8 and x8 DDR2 Devices Device densty (M b) Dev ice wi dt h Bus Wi d th R/C/B addr lines BA2 BA1 BA0 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 R o w 07600 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 C o l 0000 A P 1 3 5 1 2 1 1 1 0 9800 0 R o w 0760 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 C o l 0000 A P 1 3 5 1 2 1 1 1 0 9800 0 R o w 8760 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 C o l 0000 A P 1 3 5 1 2 1 1 1 0 9 2 8 00 0 Row 8 7 6 29 27 26 25 24 23 22 21 20 19 18 17 16 15 14 C o l 0000 A P 1 3 5 1 2 1 1 1 0 9 2 8 00 0 256 8 32 13x10x2 512 8 32 14x10x2 1024 8 32 14x10x3 2048 8 32 15x10x3 Table 11-12. Supported DRAM Timings Memory Speed CL (CAS latency) tRCD (RAS-CAS delay) tRP (RAS Precharge) DDR2-400a 333 DDR2-400b 444 DDR2-533 4 4 4 DDR2-667 5 5 5 DDR2-800 555 666 a: 3-3-3 is not supported for systems which require ODT b: May be accomplished by programming 3-3-3 parts to 4-4-4

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11.3.5 DQ/DQS Mapping

The data signal (DQ) to data strobe (DQS) relationship is controlled by the setting in the DRAM Row Attribute (DRA) registers (see Section 16.1.1.40, “Offset 70h: DRA[0-1] – DRAM Row [0:1] Attribute Register” for details). Bits 7:6 and 3:2 of these registers respectively define the device width for the odd and even rows, which is also used in the mapping of DQS signals to DQ signals. Table 11-13 shows the mapping of DQS to DQ in general terms. Table 11-14 gives the exact relationship. 11.3.6 32-Bit Mode DQ[31:0] and the associated DQS[3:0] are connected to the DIMMs in 32-bit mode. Operation in 32-bit mode is invisible to software and on-chip memory controller interfaces.

11.4 DDR2 Features

The DDR2 generation of technology introduces some new features beyond standard DDR. This section highlights those supported.

11.4.1 Interface Signalling Voltage

The memory controller supports 1.8 V signaling for DDR2-400, DDR2-533, DDR2-667 and DDR2-800 DIMMs. Table 11-13. DRA Mapping for DQS Bits Definition DQS per DQ

00 Reserved NA

01 x8 DDR 1 DQS strobe per data byte

10 Reserved NA

11 Reserved NA

Table 11-14. DQS to DQ Mapping for x8 Devices x8 devices DQ Byte DQS bit

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11.4.2 On-DIMM Die Termination (ODT)

The JEDEC DDR2 DRAM Specification requires that DDR2 DIMM devices provide selectable on-DieDIMM Termination (ODT) as an alternative to traditional discrete termination on the motherboard. The On-DIMM termination ODT feature is enabled via the DDR extended memory register select (EMRS) command ODTENA and supports both 75 and 150 terminations activated dynamically via dedicated On-DIMM termination ODT interface signals on the DIMM. The EP80579 implements two ODT pins to control the behavior of the termination on the two ranks of DRAM devices. The mapping of the CS & ODT pins for the various DIMM configurations is shown in Table 11-6. The behavior of these ODT signals can controlled by setting the appropriate bits in the Section 16.1.1.49, “Offset B0h: DDR2ODTC - DDR2 ODT Control Register”. The EP80579 controls operation of DDR2 devices with or without on-DIMMDie termination enabled, but is verified by Intel only in On-Die (ODT) enabled mode of operation. ODT can be disabled by setting the appropriate bits in DRAMODT bit in Section 16.1.1.43, “Offset 7Ch: DRC – DRAM Controller Mode Register”. Table 11-15 shows the ODT related timing parameters. The EP80579 supports operation of DDR2 devices with or without on-DIMMDie termination enabled, but is verified by Intel only in the On-Die (ODT) enabled mode of operation. ODT can be disabled by setting the DRAMODT bit in Section 16.1.1.43, “Offset 7Ch: DRC – DRAM Controller Mode Register”. Table 11-15.ODT Timing Parameters Parameter Description Value tCK Clock Period 5, 3.75, 3, 2.5ns tOND ODT turn on delay 2 tCK tOFD ODT turn off delay 2.5 tCK CL CAS Latency 3, 4, 5, 6 RL Read Latency CL WL Write Latency (RL - 1) CL - 1 BL Burst Length 4, 8 ODT_RD_on Assertion of ODT pin to inactive slot during reads = RL - tOND - 1 = RL - 3 ODT_RD_ontime Time for which the ODT pin is asserted = tOND+1+BL/2+0.5-tONF = 2+1+BL/2+0.5-2.5 = BL/2+1 ODT_WR_on Assertion of ODT pin to inactive slot during writes = WL - tOND - 1 = WL - 3 ODT_WR_ontime Time for which the ODT pin is asserted = tOND+1+BL/2+0.5-tONF = 2+1+BL/2+0.5-2.5 = BL/2+1

For WL = 2 (CL = 3), the ODT_WR_on = -1. This requires the controller to enable ODT 1 tCK before the Write command is issued. EP80579 memory controller will not support asserting the ODT pin before it issues the write command. The result is that for CL=3, the termination in the inactive slot will be turned on at the same time the DQ bus is being driven by the memory controller.
The ODT turn on and off timings will be calculated by the hardware based on the DRAM configuration parameters: CL and BL.

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11.4.2.1 ODT Control of Reads

During a read command in a 2 slot configuration as shown in Figure 11-4, the memory controller will enable ODT on the inactive slot. The ODT pin will be asserted by the controller such that the termination in the inactive slot will be enabled 1 tCK before the active slot starts driving the DQ bus. The termination will be turned-off by the controller ½ tCK after the last DQ is driven by the active slot as show in Figure 11-4. There is no assertion of the ODT signal to the DRAM device in a 1 slot configuration. Please refer the Section 16.1.1.49, “Offset B0h: DDR2ODTC - DDR2 ODT Control Register” for more details on the CSR that needs to be programmed by BIOS so that the memory controller drives the proper ODT control signals.

11.4.2.2 ODT Control of Writes

During a write command in a 2 slot configuration as shown in Figure 11-5, the EP80579 memory controller will enable ODT on the inactive slot. The ODT pin will asserted by the controller such that the termination in the inactive slot will be enabled 1 tCK before the controller starts driving the DQ bus (except for configurations where CL = 3). The termination will be turned-off by the controller ½ tCK after the last DQ is driven by the controller to the active slot as shown in Figure 11-5. During a write command in a one slot configuration, the memory controller will enable ODT to the active slot such that the termination is enabled 1 tCK before the controller starts driving the DQ bus (except for configurations where CL = 3, see note below). Figure 11-4. ODT Timing on Back-to-Back Reads to Different Slots 0 1 2 3 4 5 6 7 8 Termination ON Slot 2 Read A Slot 1 ODT Slot 2 tOND = 2 tCK CL = 4 BL = 4 tONF = 2.5 tCK Read A Slot 2 BL = 4CL = 4 Termination ON Slot 1 tOND = 2 tCK tONF = 2.5 tCK ODT Slot 1 DQ Slot 2 Rtt Slot 1 Rtt

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 301 Intel® EP80579 Integrated Processor Please refer the Section 16.1.1.49, “Offset B0h: DDR2ODTC - DDR2 ODT Control Register” for more details on the CSR that needs to be programmed by BIOS so that the memory controller drives the proper ODT control signals. Note: The memory controller will not enable ODT before the write command is issued on the DRAM interface (See Table 11-15 for more details). For configurations with CL=3, WL=2 the controller will assert the ODT pin along with the write command. This will result in the termination in the inactive slot to be enabled at the same time the controller starts driving the DQ data bus.

11.4.3 On-Die Termination (ODTZ) on the EP80579

The EP80579 supports ODT (referred to as ODTZ to differentiate it from the On- DIMMDie Termination, ODT that is implementation on the DRAM devices) on the DQ/ DQS buffers to improve signal integrity on the inbound path (read data from DRAM). ODTZ will be enabled on read accesses to the DRAM devices and can be in one of the 3 states - 60ohms, 120ohms or off. ODTZ will be automatically disabled when the EP80579 DQ/DQS buffers are enabled for a write access to the DRAM device. There are no timing parameters implemented to control this functionality and the DDRIO pads are responsible for ensuring that ODTZ is in the disabled state when issuing writes to the DRAM devices. The termination value for ODTZ can be set by programming the ODTZENA bit in Section 16.1.1.45, “Offset 88h: SDRC – DDR SDRAM Secondary Control Register”. Figure 11-5. ODT Timing on Back-to-Back Writes to Different Slots 0 1 2 3 4 5 6 7 8 Termination ON Slot 2 Write A Slot 1 ODT Slot 2 tOND = 2 tCK WL = 3 BL = 4 tONF = 2.5 tCK Write A Slot 2 BL = 4WL = 3 Termination ON Slot 1 tOND = 2 tCK tONF = 2.5 tCK ODT Slot 1 DQ Slot 2 Rtt Slot 1 Rtt

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11.4.4 Refresh

The EP80579 supports generation of the refresh commands (REF) that are necessary for the DRAM devices to retain its data. When the refresh cycle is launched by memory controller an address counter, internal to the DRAM device, supplies the bank address during the refresh cycle. No control of the address bus is required for a refresh cycle. When the refresh cycle has completed, all banks of the DDR2 device will be in the precharged (idle) state. A delay between the Refresh command and the next activate command or subsequent Refresh command must be greater than or equal to the Refresh cycle time (tRFC). There are 3 mechanisms through which the EP80579 memory controller will generate the refresh commands: 1. Programmable counter: The refresh engine can be programmed to generate refresh commands at programmable time intervals. The choice of intervals are meant to cover DDR2 device tREFI specifications. Please refer to Section 16.5.1.3, “Offset 40h: DCALCSR – DDR Calibration Control and Status Register” details on programming the refresh engine. 2. Programmable OPCODE generation: A single refresh command can be generated under software control using the available opcodes in Section 16.5.1.3, “Offset 40h: DCALCSR – DDR Calibration Control and Status Register”. 3. Self-Refresh exit state machine: The self-refresh exit engine will issue one refresh command to each rank after it brings them out of self refresh. Note: The EP80579 does not support posted refresh cycles.

11.4.5 Self-Refresh

The EP80579 supports the generation of self-refresh commands that can be used to retain data in the DRAM devices without any support from the memory controller. The DRAM device has built-in counters timers to accommodate the self-refresh operation. There are 2 mechanisms to enter and exit the self-refresh mode: 1. Self-Refresh Entry a. S3: The memory controller will issue a self-refresh entry command at the end of the S3 sequence. b. Programmable OPCODE generation: A self-refresh entry command can be generated under software control using the available opcodes Section 16.5.1.3, “Offset 40h: DCALCSR – DDR Calibration Control and Status Register”. 2. Self-Refresh Exit a. Power up after S3 event: The memory controller implements a self-refresh exit engine which under software control can bring the DRAM devices out of self- refresh. Refer to Table 16-226, “Rules about issuing Self-Refresh and Refresh commands using DCALCSR.OPCODE” on page 604 for details on the rules that software should follow when using this mechanism. b. Writing to DRC.CKE[1:0] register bits: By writing to the DRC.CKE[1:0] registers, software can assert the CKE pins to the DRAM devices bringing them out of self-refresh.Please refer to Section 16.5.1.59, “Offset 1F4h: MB_ERR_DATA32 - Memory Test Error Data 3” for more details. The de-emphasis feature on the command/clock pins should be disabled before entering self-refresh. Please see the DEMCA bit in Section 16.5.1.63, “Offset 264h: DDRIOMC1 - DDR IO Mode Control Register 1” for more details.

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11.4.6 RCOMP

The EP80579 supports RCOMP for the DDR pads. RCOMP control is implemented for 2 groups of DDR pads. The RCOMP used for the 2 groups can either be static or dynamic based on DDRIOMC2.LEGOVERRIDE[5:4]. For more details on how to control the RCOMP for the 2 groups of DDR pads please see Section 16.5.1.64, “Offset 268h: DDRIOMC2 - DDR IO Mode Control Register 2”. The final values that are used for Group 1 and Group 2 drivers can be viewed using the bits in Section 16.5.1.29, “Offset F0h: DIOMON - DDR I/O Monitor Register”.

Group1: Data, data mask and data strobes: — DDRIOMC2.LEGOVERRIDE[4:0] bits can be used in dynamic mode to achieve the target impedance on the group 1 DDR pads. In dynamic RCOMP mode, these CSR bits control several pull-up devices that are binary sized. The pull-up devices are tuned using an external resistor (Rext). In Static mode, DDRIOMC2.LEGOVERRIDE[3:0] determines the RCOMP value used by the Group 1 DDRIO pads.
Group2: Command, Address and Clock: — In dynamic RCOMP mode the digital control for these group of DDR pads is derived by multiplying the group 1 digital control by a factor determined by DDRIOMC2.LEGOVERRIDE[6:9]. In static RCOMP mode, DDRIOMC2.LEGOVERRIDE[6:9] directly controls the RCOMP value used by the Group 2 DDRIO pads.

11.4.7 DDR2 MR and EMR settings

Table 11-16 shows the supported settings of DDR2 mode register (MR) and extended mode register (EMR). Note that only the architecturally relevant settings of the MR and EMR are listed in this table. These registers can be updated using the MRS and EMRS commands. Please see Section 16.5.1.3, “Offset 40h: DCALCSR – DDR Calibration Control and Status Register” and Section 16.5.1.4, “Offset 44h: DCALADDR - DDR Calibration Address Register” for more details on generation of MRS and EMRS commands. Table 11-16.Supported DDR2 MR and EMR settings MR/EMR Feature EP80579 Support Burst Type Sequential only Burst Length 4 (64-bit mode) and 8 (32-bit mode) Write Recovery for Auto-precharge Supported. Settings based on speed bins. Please see Section 16.0, “IMCH Registers” for details. CAS Latency 3, 4, 5 and 6 depending upon Speed bin. Please see Table 11-12 and Section 16.0, “IMCH Registers” for more details. ODT (EMR) Supported. Please see Section 11.4.2 for more details. OCD Calibration (EMR) Not Supported. Additive Latency (EMR) Not Supported.

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11.4.8 Scrubbing Support

The memory controller will support both demand scrubbing and background scrubbing in hardware. This section provide details of the scrubbing mechanism.

11.4.8.1 Demand Scrubbing

When the controller detects a single bit error on a DRAM read, the ECC logic fixes the single bit error and returns the corrected data to the requester. The controller also writes the corrected data back into DRAM using the demand scrub operation.

11.4.8.2 Background Scrubbing

The controller supports a simple state machine that periodically injects read transactions into the stream. The scrub rate meets a general requirement for scrubbing a 4GB memory capacity every 24 hours. It can also be programmed to scrub the entire DDR at faster rates, if that is desired. Rates available extend from an entire scrub every few days, to every day, every hour, every minute, and even very fast rates, mainly used for validation purposes. Data for a background scrub read operation is discarded if no error is detected on the read. When a single bit error is detected on a background scrub read transaction, the mechanism specified in Figure 11.4.8.1 is used to correct the single bit error in DRAM. The read data is dropped. When a double bit error is detected on a background scrub read transaction, the controller log the error and interrupts the IA-32 core.

11.5 Error Handling

The memory controller accesses may encounter data with ECC violations and/or parity errors.

For writes with bad parity, as indicated on bits in the command from either AIOC memory target (MT) or IMCH, the memory controller will execute the write, poisoning the data as it writes it to DDR. Please see Table 11-17 for the granularity of poisoned data. Poisoning is accomplished by inverting each bit of ECC calculated for that particular write, based on the bad write data sent to the memory controller from AIOC or IMCH.
For reads from DDR with single bit parity errors, the memory controller will correct all correctable errors, and return the data, to either requestor, corrected, and without a bad parity indication. Status logging, as discussed above, will be done.
For reads from DDR with multiple bit, uncorrectable ECC violations, the memory controller will return the data to either requestor, however, a bad parity indication will be driven back with the data. Please see Table 11-17 for the granularity of poisoned data. AIOC memory target (MT) or IMCH should poison the data when seeing the bad parity bit set, along with the read data returned.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 305 Intel® EP80579 Integrated Processor For compatibility with accepted IA platform algorithms and mechanisms, the memory controller will follow general IA error logging and reporting mechanisms as closely as possible with the following exception:

The memory controller does not implement uncorrectable retries (DED retries). Therefore all registers and bit definitions that support uncorrectable retries are not implemented in the memory controller. § § Table 11-17.Poisoning Granularity Command Error Source Command Source Memory Controller Action Read from DRAM DRAM (DED) IMCH Poison parity bits on 32B granularity and return read data to IMCH. Read from DRAM DRAM (DED) AIOC MT Poison parity bits on 8B granularity and return read data to AIOC memory target (MT). Write to DRAM IA or IO Device including AIOC (Parity Error) IMCH Poison ECC bits on 16B granularity and write to DRAM. Write to DRAM AIOC (Parity Error) AIOC MT Poison ECC bits on 8B granularity and write to DRAM.
ECC can be enabled by setting the DDIM bit in Section 16.1.1.43, “Offset 7Ch: DRC – DRAM Controller Mode Register”.
Poisoning of write data to DRAM can be enabled using the MEMPEN bit in Section 16.1.1.44, “Offset 84h: ECCDIAG – ECC Detection/Correction Diagnostic Register”.
Poisoning of read data from DRAM to IMCH or AIOC MT can be enabled by using ENDP bit in Section 16.1.1.43, “Offset 7Ch: DRC – DRAM Controller Mode Register”.

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12.0 Enhanced Direct Memory Access Controller

(EDMA) The IMCH includes an integrated four-channel Enhanced Direct Memory Access (EDMA) controller to facilitate “push model” block transfers without IA-32 core intervention for higher overall system performance. This section details the operating modes, setup, interfaces, register set, and high-level implementation of the EDMA controller.

12.1 Overview

The EDMA engine provides a highly efficient means to move data within local system memory or from the local system memory to the I/O subsystem. Each EDMA channel provides low-latency, high-throughput data transfer capability with minimal IA-32 core intervention. For the IA-32 core, it is a “fire and forget” type of memory transfer, with a doorbell starting mechanism and interrupt capability for signaling completion. Each channel optimizes block transfers of data through a linked-list descriptor chaining mechanism that supports scatter/gather operations. Each channel is responsible for providing the EDMA programming interface, executing the data transfers, and handling any errors encountered during operation. Each channel initiates traffic on both the local system memory and outbound traffic arbiter interfaces, and is designed such that each independent channel is capable of generating at least 1 GB/s of traffic during data hauls. In the absence of competition from other traffic sources, multiple channels could theoretically saturate the local memory interface. See Figure 12-1. Each channel is independently enabled by setting the Start bit in the Control Configuration Register. The Start bit is cleared after power-up or reset and consequently the EDMA controller is disabled until software explicitly turns each one on.

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12.1.1 Features

The following features are supported by the EDMA controller:

Four independent channels (see Figure 12-2) — Dedicated data transfer queue per channel — Full register set for descriptor and transfer handling per channel
Support for transfer between main memory locations, and from memory to the I/O subsystem
PCI Express* support of traffic class to provide external prioritization of traffic
Supports transfers only between two physical addresses — 32-bit (4 GB) addressing range on the local system memory interface Figure 12-1. Concept Diagram of EDMA Data Path B6119-01 CMACH0 CMACH2 CMACH3 CMACH1 EDMA Arbiter EP80579 EDMA Engine Memory PCI Express Interface Port A Memory-to-Memory EDMA Data Path Memory-to-I/O EDMA Data PathTransaction Requests PCI Express Port A Links

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 309 Intel® EP80579 Integrated Processor — 32-bit addressing range on the Memory Mapped I/O Subsystem Interface (no NSI access)

Maximum transfer of 16 MB transfers per descriptor
Fully programmable by the IA-32 core — Configuration space mapping for EDMA engine capability and control — Memory-mapped space for EDMA channel-specific register sets
Chain Mode EDMA transfer with automatic data chaining for scattering/gathering of data blocks — EDMA chaining continued until a “null” descriptor pointer is encountered — Support for appending a block to the end of current EDMA chain — Automated descriptor retrieval from local memory during chaining – single read
Programmable independent alignment between source and destination — Byte aligned transfer on the local system memory interface — Byte aligned transfer on the I/O subsystem interface
Support for non-coherent transfers both to and from system memory on a per descriptor basis — Independent control of coherency for source and destination
Programmable support for interrupt generation on block–by-block basis — Selectable MSI or legacy level-sensitive interrupt function — End of current block transfer — End of current chain — For any error causing a transfer to abort
Increment of the source and destination address for standard transfers
Increment of the destination and decrement of the source address to enable byte stream reversal
Constant address mode for the destination address based on the transfer granularity to enable targeting of memory mapped I/O FIFO devices
Buffer/memory initialization mode

12.1.2 Logical Block Diagram

Figure 12-2 shows the conceptual interface of the EDMA channels to different l interfaces.

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12.2 Channel Programming Interface

The EDMA channel programming interface is accessible from the IA-32 core via a combination of chain descriptors (shown in Figure 12-3) written to main memory and a memory-mapped internal register set. The EDMA controller provides four channels, each of which can be independently used to transfer data within the local system memory or from the local system memory to the I/O subsystem. Each channel has its own set of 12 registers. Refer to “Memory Mapped I/O for EDMA Registers” on page 651 for a description of the channel register set. The channel programming interface is accessible from the IA-32 core via a combination of descriptors written to main memory and a memory-mapped internal register set. Each channel is programmed independently. Each channel supports full chaining capability. The chain descriptors can be cascaded together in system memory to form a linked list. Each chain descriptor contains all the information necessary for transferring a block of data, as well as a pointer to the next chain descriptor in the list. The next descriptor pointer of the last chain descriptor in a linked list will be a null pointer (address zero), indicating the end of that chain. Figure 12-2. Conceptual Diagram of Four Channel EDMA Engine EDMA Channel1 EDMA Channel0 EDMA Arbiter REQs GNTs PCI Express Interface Memory Interface FSB Interface Cfg/TAP Interface System Arbiter EDMA Channel2 EDMA Channel3

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 311 Intel® EP80579 Integrated Processor Throughout this document, all register references are made using the name of the lower 32-bit register, irrespective of whether the target is a 32-bit or 64-bit register with lower and upper halves.

12.3 Chaining Operation

An EDMA access transfers a block of data from one address to another. The desired transfer is specified by setting up a linked list of chain descriptors in the local system memory, and initiated by programming the first chain descriptor start address into the Next Descriptor Address Registers (NDAR/NDUAR) of the EDMA channel and setting the Start bit of the Channel Control Register (CCR). Each block of the transfer is defined by a descriptor in main memory containing the source address, destination address, transfer length and control values. Setting the Start bit of the Channel Control Register (CCR) causes the channel to fetch the current chain descriptor information and place it into its corresponding register set. Once all the register information has been fetched, the actual data transfer starts. Note: The Start bit will be ignored unless the Channel Status Register (CSR) is in an appropriate state. Software must ensure that the status bits for end of chain, stopped, aborted, and active are all clear prior to attempting to initiate a new transfer with the start function.

12.3.1 Chain Descriptor Definition

All EDMA transfers are controlled by chain descriptors in the local system memory. A single block transfer will specify only a single chain descriptor. Chain descriptors can be linked together to form a linked list, providing a capability for complex EDMA scatter/ gather operations. Figure 12-3 shows the format of a chain descriptor. Each chain descriptor consists of eight contiguous DWords (32-bits) in the local system memory, and must be naturally aligned to an eight Dword boundary. All eight DWords must be defined and are required for the proper operation of the EDMA engine.

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12.3.2 DMA Chain Descriptor in Memory

Each chain descriptor is composed of eight Dwords. Each Dword in the chain descriptor in the local memory is analogous to the corresponding EDMA channel register value. The bit definitions in the chain descriptor in memory are identical to those of the corresponding channel register. Refer to the EDMA channel-specific register definitions in “Memory Mapped I/O for EDMA Registers” on page 651 for descriptions of the fields defined by a chain descriptor. After a transfer has been requested, the EDMA channel reads the specified chain descriptor from local system memory and updates its own corresponding channel registers automatically.

12.3.3 Chain Descriptor Usage

A linked list of chain descriptors may be built in the local system memory to transfer data within the local system memory or from local system memory to I/O subsystem memory. An application may build multiple chain descriptors to transfer many blocks with differing source addresses, destination addresses, data transfer counts, alignments, and coherence attributes. The application may connect these chain descriptors using the Next Descriptor Address in a sequence of chain descriptors, creating a linked list of EDMA transfers, all of which may complete without any processor intervention. Figure 12-4 shows a linked list of transfers built in local system memory and illustrates how they are “chained” together. Figure 12-3. Chain Descriptor in Memory Lower 32-bit Source Memory Address Register B4483-01 Upper 32-bit Source Memory Address Register Lower 32-bit Destination Memory Address Register Upper 32-bit Address of Next Chain Descriptor Register Lower 32-bit Address of Next Chain Descriptor Register Upper 32-bit Address of Next Chain Descriptor Register Number of Bytes to Transfer Register Descriptor Control Register Source Upper Address (SUAR) Destination Address (DAR) Destination Upper Address (DUAR) Source Address (SAR) Next Descriptor Address (NDAR) Next Descriptor Upper Address (NDAUR) Transfer Count (TCR) Descriptor Control (DCR) Chain Descriptor in Memory Description

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 313 Intel® EP80579 Integrated Processor It is possible but unexpected that the source and destination address ranges defined by chain descriptors may overlap in physical memory. While there are scenarios where this may produce no errors in the resulting memory image, the software must ensure that no failure results from such usage. Hardware checks are not built into the EDMA mechanism to ensure that source and destination physical address ranges do not overlap. Similarly, there are no hardware interlocks to ensure that independent channels are not programmed to modify the same address range simultaneously. If software were to create such a situation, the resultant memory image would be indeterminate, since there are no guarantees as to the relative access ordering among simultaneously active channels. Figure 12-4. Chaining Mechanism Source Address (SAR) Source Upper Address (SUAR) Destination Address ( DAR) Destination Upper Address (DUAR) Next Descriptor Address (NDAR) Next Descriptor Upper Address ( NDUAR) Descriptor Control (DCR) Next Descriptor Address Register (32-bit or 64-bit) Source Address (SAR) Source Upper Address (SUAR) Destination Address (DAR) Destination Upper Address (DUAR) Next Descriptor Address (NDAR) Next Descriptor U pper Address (NDUAR) Descriptor Control (DCR) Source Address (SAR) Source Upper Address (SUAR) Destination Address (DAR) Destination Upper Address (DUAR) Next Descriptor Up per A ddress (NDUAR) Descriptor Control (DCR) First Block Transfer Second Block Transfer Nth Block Transfer End of Chain (Null Value) Linked Descriptors in Memory Next Descriptor Address (NDAR) Transfer Count (TCR) Transfer Count (TCR) Transfer Count (TCR)

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12.3.4 Scatter/Gather Transfer

The EDMA descriptors in memory may be defined such that they cause the channel to perform typical scatter/gather data transfers. To “gather” data, software may create a linked list of descriptors that will move non-contiguous source blocks of data into a contiguous set of destination blocks. To “scatter” data, software may create a linked list of descriptors that will move contiguous blocks of source data to non-contiguous destination blocks. It is even possible to program the EDMA transfer descriptors in such a way that some blocks of source data within a single chain are moved to new memory locations, while other blocks are moved out to the I/O subsystem. There is no hardware restriction limiting the nature of source and destination address ranges, other than that the source and destination types (memory or I/O subsystem) must match the descriptor address mappings. The IMCH aborts the EDMA operation and reports a programming error if this requirement is not met.

12.3.5 Appending to a Descriptor Chain

After an EDMA channel has started processing a linked list of descriptors, the application software may need to append a chain descriptor to the end of the current chain without tearing down the transfer in progress. Such an operation requires a mechanism to guarantee that a descriptor is never in the process of modification by the IA-32 core while being retrieved by the EDMA channel (This would result in a hybrid descriptor loaded into the corresponding EDMA channel register set, and spurious operation). The suspend function of the EDMA controller is defined to facilitate this type of usage. The preferred mechanism for appending to a linked list currently being processed is to suspend the current transfer, modify the terminal chain descriptor to update its Next Descriptor Address field(s), and then allow the transfer to resume. This is accomplished by first setting the Suspend bit in the Channel Control Register (CCR) followed by a read of the Channel Status Register (CSR) to verify that the suspend has taken effect.The Next Descriptor Address fields of the terminal chain descriptor in the current linked list are updated with the address of the first descriptor to be appended. After this update has occurred, software then clears the Suspend bit, sets the Channel Resume bit and allows execution to proceed. Note: A single write to the CCR may update both bits simultaneously. This append algorithm covers the following cases:

The EDMA channel has completed execution of the terminal descriptor in the original chain, and is idle. The EDMA channel examines the Channel Resume bit when the Channel Control Register (CCR) is written. If the bit is set, the EDMA channel will automatically clear the bit and re-read the last chain descriptor (as indicated by CDAR/CDUAR), which updates NDAR with the appended chain descriptor address. A non-null value in NDAR will result in a fetch of the target chain descriptor, and resumed execution. (If the resulting NDAR/NDUAR pair remains null, the EDMA channel will remain idle.)
The EDMA channel is executing a descriptor prior to the terminal chain descriptor in the linked list. Regardless of whether the channel completes execution of its current descriptor prior to the CCR write to clear Suspend and set Channel Resume, the channel will re-read the current chain descriptor in response to the Channel Resume bit. The next chain descriptor in the chain will be fetched from the address indicated by NDAR/NDUAR, and the channel will continue execution. The appended chain descriptor (or descriptors) will be executed after the channel reaches the end of the original chain.
The channel is executing the terminal chain descriptor at the time of the suspend command. The channel will complete the final chain descriptor of the original linked

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 315 Intel® EP80579 Integrated Processor list and examine the state of the Channel Resume bit when the Suspend bit is cleared. As in the prior case, the channel will re-read the current chain descriptor to update NDAR/NDUAR, load the first appended chain descriptor, and resume execution. The only difference in this case is that the re-read operation on the current chain description was required for proper execution (in the prior case it was wasted effort, but did not result in erroneous behavior). If the channel had completed execution of the terminal chain descriptor and set the “end of chain” status bit, this bit is automatically cleared when the channel resumes operation.

If the current transfer had a non-fatal error, it follows one of the above cases. If the error is fatal, the channel will abort, and the software must take proper action and restart the EDMA transfer. Note that the channel will ignore the state of the Channel Resume bit if the abort status has not been cleared from the CSR. This simplifies the case of linked list append, as software need not take extra steps to verify that no errors exist prior to setting the Channel Resume bit. The normal polling or interrupt mechanism may handle the error without interacting with the append routine. Note: Software is at liberty to modify the Next Descriptor Address fields of the terminal chain descriptor at any time after setting the Suspend bit in the CCR – there is no requirement that software verify that the channel has gone idle prior to modifying the memory image. Also, software does not need to verify that the channel has completed execution of the current chain descriptor and acknowledged Suspend EDMA prior to issuing the final update to CSR that sets the Channel Resume bit. The hardware interlock will cover the case where the end of the chain descriptor is reached during the append sequence, but proper operation is guaranteed regardless of whether the interlock is exercised. A further simplification to the linked list append sequence is possible in the case of chain descriptors located strictly below the 4 GB boundary in memory; that is, in the case where NDUAR of the terminal descriptor is zero and only NDAR contains asserted bits. Under these conditions, it is safe to issue the NDAR write cycle without first suspending operation, because there is no risk of a hybrid NDAR/NDUAR pair retrieved by the channel. If desired, software could take the simplified approach of issuing the descriptor update followed by a CCR write to set the Channel Resume bit. In all cases, this will result in successful execution of the appended chain irrespective of current execution status.

12.3.6 Splicing a Descriptor Chain into a Linked List

Software may utilize a slight modification of the algorithm described in “Appending to a Descriptor Chain” on page 314 to splice a new descriptor or chain of descriptors into the chain already executing. Such an operation would be useful to provide service to a higher priority EDMA transfer without aborting work already in progress. The steps required to splice into a chain are as follows: 1. Write to the CCR to set the Suspend EDMA bit. 2. Read the CDAR/CDUAR pair to determine which chain descriptor the EDMA channel is currently executing. 3. Read the Next Descriptor Address field of the current chain descriptor, and write the retrieved address into the Next Descriptor Address field of the terminal chain descriptor in the linked list to be spliced-in. 4. Write the address of the descriptor (or lead descriptor of the chain) to be spliced-in into the Next Descriptor Address field of the current descriptor (in memory). 5. Write to the CCR to clear the Suspend bit and set the Channel Resume bit.

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The hardware interlock of the suspend function will guarantee that the channel will not proceed beyond the current chain descriptor until the Suspend bit has been cleared in the CCR, and the Channel Resume function will guarantee that the current chain descriptor will be re-read to retrieve the modified NDAR/NDUAR value pointing to the spliced chain descriptor. The channel will resume execution with the head of the spliced linked list, and will traverse that linked list back to its original list of chain descriptors. Note: The channel must refrain from updating CDAR/CDUAR from NDAR/NDUAR in addition to dropping the returned data. Were the channel to update its CDAR/CDUAR values, it would “skip” the entire spliced chain in response to Channel Resume, because software would have spliced in the new descriptor chain at a position “behind” the new value for CDAR/CDUAR in the original chain.

12.4 Transfer Types

The EDMA controller is optimized to perform high throughput data transfers between local memory locations, and from local memory to I/O subsystem memory. Supported transfer types are summarized in the following subsections.

12.4.1 Local Memory to Local Memory

The local memory to local memory transfer will move blocks of data specified by descriptors from one region in main memory to another. The channel control hardware will issue read cycles to the local memory interface using an incrementing or decrementing source address, and place the retrieved data into a channel buffer. It will then issue write cycles back to the memory interface using an incrementing or constant destination address. Each EDMA channel supports pipelining making it possible for a single channel to have multiple read and write cycles active at the same time. All read requests to memory are a full cache-line in length (64 B), so the EDMA channel must discard data as needed to realign the initial read in a transfer to the alignment specified by the source address. The number of cache-line reads issued by the controller in any given internal arbitration cycle is dependent upon the number of available cache-line spaces in the data queue, and upon the configuration of the inbound/outbound arbiter, but is limited to a maximum of two cache-line requests. All write requests to memory are also a full cache-line in length, although not all bytes must be enabled for every write. The EDMA channel is responsible for translating the alignment specified by the destination address registers and the destination alignment bit in DCR into a corresponding set of byte enables for the initial write in a transfer. Once the initial alignment has been enforced, the rest of the transfer on behalf of any given descriptor is contiguous.

12.4.2 Local Memory to I/O Subsystem Memory

The local memory to I/O memory transfer will move blocks of data specified by chain descriptors from a source region in main memory to a destination region in the I/O subsystem. The channel control hardware will issue read cycles to the local memory interface using an incrementing or decrementing source address, and place the retrieved data into a channel buffer. It will then issue write cycles to the I/O subsystem using an incrementing or constant destination address. Each EDMA channel supports pipelining for this transfer type as well, thus multiple read and write requests may be outstanding from the same EDMA channel at any given time during a block transfer. All read and write requests are full cache-line size (64 B), irrespective of alignment and length specified in the descriptors; it is up to the EDMA channel to discard read data and calculate write byte enables to enforce the descriptor alignment specified.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 317 Intel® EP80579 Integrated Processor The number of reads issued by each EDMA channel in any given internal arbitration cycle is dependent upon the number of available cache-line spaces in the data queue, and upon the configuration of the inbound/outbound arbiter, but is limited to a maximum of two cache-line requests. The number of writes issued in any given arbitration cycle is dependent upon the number of cache-lines waiting in the data queue, and upon the CCR configuration, but is limited to a maximum of two cache-line requests. The EDMA controller never speculatively issues a write in anticipation of data returning from the memory subsystem.

12.4.3 I/O Memory to Local Memory

The I/O memory to local memory transfer is not supported.

12.4.4 I/O Memory to I/O Memory

The I/O memory to I/O memory transfer is not supported.

12.5 Addressing

Each EDMA is capable of 36-bit addressing on both source and destination interfaces. Alignment specification is independent for source and destination. Transfers may be specified to be aligned to any byte boundary except in destination constant address modes where the granularity is greater than 1-byte. Each EDMA channel uses direct addressing for both the source and destination interfaces. There is no internal support for any virtual address translation. Each EDMA channel will attempt to compensate for misalignment between source and destination. At a minimum, misalignment will result in decreased performance at either end of the transfer, where a second read is required prior to the first write, or vice- versa.

12.5.1 Address Coherence

Each EDMA channel provides support for non-coherent access specification to improve bandwidth and provide more consistent average latency, as well as to free the FSB for simultaneous IA-32 core traffic. The source and destination addresses for each DMA channel may be independently specified on a chain descriptor granularity via bit settings in the DCR to be either coherent or non-coherent. For non-coherent accesses, no FSB snoop cycle is issued on behalf of EDMA memory accesses to snoop processor caches. The software must verify that snoops of IA-32 core caches are not required for proper system operation prior to setting either of the non-coherent bits in any given descriptor. Non-coherent accesses are used for un-cacheable memory regions, or for cacheable regions where software can guarantee no modified state in any IA-32 core cache by some other means. The non-coherent attribute further implies relaxed posted write ordering as defined by PCI/PCI-X. A non-coherent write may pass coherent posted writes en route to memory. Software should verify that snoops of IA-32 core caches are not required for proper system operation prior to setting either of the non-coherent bits in the DCR field of any given descriptor. Software need not take special steps to accommodate the relaxed ordering behavior, because each channel will only generate a single stream of output per descriptor, and no ordering is defined between competing I/O subsystem traffic sources. Non-coherent access may be used for uncacheable memory regions, or for cacheable regions where software can guarantee the IA-32 core cache state has not been modified by other means.

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An example usage model for non-coherent accesses is management of data block areas reserved for use by an EDMA-capable peripheral device, such as a network interface controllers (NIC). The NIC writes data directly into a buffer in memory allocated for the exclusive use of that device. Each EDMA channel would then execute a block transfer from that buffer to an area allocated for IA-32 core use. Both integrity verification and security functions executed by the IA-32 core could follow such a model. As long as software ensures that the IA-32 core never traverses the device-allocated memory, the block transfer could be accomplished using non-coherent source address reads followed by coherent destination address writes. Note: I/O subsystem destination addresses are always treated as non-coherent or coherent based on the bit setting in the DCR. Setting the destination coherency bit will result in the PCI-Express snoop not required attribute bit being clear, snoop required. Example: Setting BDF 010 Offset 2C DCRx register bit 7 Destination non-coherent = 0 => Snoop not required attribute bit = 1 Destination coherent = 1 => Snoop not required attribute bit = 0

12.5.2 Addressing Modes

Many different addressing modes are available, including standard byte movement mode, byte reversal mode, constant address mode, and memory and buffer initialization modes. In the examples shown for each of the following modes, a 64-bit interface is used for simplicity. The interface could be the memory interface or an external device on an expansion bus. Internally, the EDMA data path is significantly wider.

12.5.2.1 Standard Byte Movement Mode

Standard byte movement mode is the most common method in which data is transferred within the memory sub-system. In this mode, the source and destination are specified down to the byte address. The source address is incremented as data is read and the destination address is incremented as data is written. Transfers can be memory to memory or memory to memory mapped I/O. Figure 12-5 illustrates a memory to memory data transfer between unaligned 64-bit, source and destination addresses.

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12.5.2.2 Decrement/Byte Reversal Mode

Decrement/byte reversal mode is useful when an entire data stream needs to be reversed at the byte level. This must not be confused with endian swapping, as this implies a specific word size. In this mode, the source and destination are specified down to the byte address. The source data is read in reverse order and written to the destination in increasing order. Transfers can be memory to memory or memory to memory mapped I/O. Figure 12-6 illustrates a memory to memory data transfer between unaligned 64-bit, source and destination addresses when the source is in decrement mode and the destination is in increment mode. Figure 12-5. Source and Destination in Increment Mode Transfer ADDRESS B4484-01 7 6 5 4 3 2 1 15 14 13 12 11 10 9 20 19 18 17 9 8 7 6 5 4 3 17 16 15 14 13 12 11 20 19 A000 0200H A000 0208H A000 0210H 4001 0300H 4001 0308H 4001 0310H 4001 0318H LSBMSB Memory 64-bit Source Data Block Transfer 10Programmed Values 0000 0088H A000 0201H 4001 0307H 0000 0014H 0000 001FH EDMACTL SUAR/SAR DUAR/DAR TCR DCR SOURCE QWORD load@A0000200 QWORD load@A0000208 QWORD load@A0000210 DESTINATION Byte store@40010307 QWORD store@40010308 QWORD store@40010310 3-Byte store@40010318 64-bit Destination byte number Bus Operation

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12.5.2.3 Constant Address Modes

In constant address mode, there is built-in support for “mailbox” destinations in the memory mapped I/O subsystem. A mailbox is a single or limited set of addresses used to collect information for dispersal later to their actual destination addresses by the receiving device. In constant address mode, one, two, or four bytes will be sent repeatedly until the byte count is satisfied. The source address can be byte aligned; however, unlike other transfer modes, in constant address Mode the destination address must be aligned to the granularity size. No errors will be flagged if the destination address is not matched to the granularity, but the required lower address bits will be ignored. Additionally, software must ensure that the transfer byte count is an integer multiple of the granularity size. No error will be flagged if the transfer byte count is not an integer multiple and the remaining bytes in the requested granularity will be padded and transferred. Figure 12-6. Source in Decrement and Destination in Increment Mode Transfer (Byte Reversal) ADDRESS byte number B4485-01 7 6 5 4 3 2 1 15 14 13 12 11 10 9 20 19 18 12 13 14 15 16 17 4 5 6 7 8 9 10 1 2 A000 0200H A000 0208H A000 0210H 4001 0300H 4001 0308H 4001 0310H 4001 0318H LSBMSB Memory 64-bit Source Data Block Transfer 10Programmed Values 0000 0088H A000 0214H 4001 0307H 0000 0014H 0000 101FH EDMACTL SUAR/SAR DUAR/DAR TCR DCR SOURCE QWORD load@A0000210 QWORD load@A0000208 QWORD load@A0000200 DESTINATION Byte store@40010307 QWORD store@40010308 QWORD store@40010310 3-Byte store@40010318 64-bit Destination Bus Operation

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Figure 12-8. Source in Increment and Destination in 2-Byte Granularity Constant Mode Transfer ADDRESS B4487-01 7 6 5 4 3 2 1 15 14 13 12 11 10 9 20 19 18 17 A000 0200H A000 0208H A000 0210H 4001 0300H 4001 0300H 4001 0300H 4001 0300H LSBMSB Memory 64-bit Source Data Block Transfer 10Programmed Values 0000 0088H A000 0201H 4001 0306H 0000 0014H 0002 403FH EDMACTL SUAR/SAR DUAR/DAR TCR DCR SOURCE QWORD load@A0000200 QWORD load@A0000208 QWORD load@A0000210 DESTINATION 2-Byte store@40010306 (10 times) 64-bit Destination byte number Bus Operation

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Figure 12-10.Source in Decrement and Destination in 1-Byte Granularity Constant Mode Transfer ADDRESS B4489-01 7 6 5 4 3 2 1 15 14 13 12 11 10 9 20 19 18 17 A000 0200H A000 0208H A000 0210H 4001 0300H 4001 0300H 4001 0300H 4001 0300H LSBMSB Memory 64-bit Source Data Block Transfer 10Programmed Values 0000 0088H A000 0214H 4001 0307H 0000 0014H 0000 503FH EDMACTL SUAR/SAR DUAR/DAR TCR DCR SOURCE QWORD load@A0000200 QWORD load@A0000208 QWORD load@A0000210 DESTINATION Byte store@40010307 (20 times) 64-bit Destination byte number Bus Operation

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 325 Intel® EP80579 Integrated Processor Figure 12-11.Source in Decrement and Destination in 2-Byte Granularity Constant Mode Transfer byte number EDMACTL SUAR/SAR DUAR/DAR TCR DCR Programmed Values 0000 0088H A000 0214H 4001 0306H 0000 0014H 0002 503FH ADDRESS A000 0200H A000 0208H A000 0210H 4001 0300H 4001 0300H 4001 0300H64-bit Destination LSBMemory 12 11 10 9 8 7 6 5 4 3 2 1 MSB 64-bit Source Data Block Transfer 20 19 18 17 16 15 14 13 4001 0300H1 ... Bus operation QWORD load@ A0000210 QWORD load@ A0000208 QWORD load@ A0000200 2-Byte store@ 40010306 SOURCE DESTINATION (10 times)

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12.5.2.4 Buffer and Memory Initialization Modes

The EDMA can be used to write a constant value to local memory or to memory mapped I/O. As with normal transfers, descriptors are used to specify the memory blocks to which the data contained in the Source Address Register is written. When buffer or memory initialization modes are selected, the data in the SAR is sent to the destination address. No data is fetched. Data is transferred in 32-bit replicated chunks to the destination. The transfers will continue until the byte count register is satisfied.

12.5.2.4.1 Memory Initialization Mode

Memory initialization mode transfers can be to memory or to memory mapped I/O. In this mode, the destination can be specified down to the byte address. Figure 12-13 illustrates memory initialization to an arbitrary destination address. Figure 12-12.Source in Decrement and Destination in 4-Byte Granularity Constant Mode Transfer byte number EDMACTL SUAR/SAR DUAR/DAR TCR DCR Programmed Values 0000 0088H A000 0214H 4001 0304H 0000 0014H 0004 503FH ADDRESS A000 0200H A000 0208H A000 0210H 4001 0300H 4001 0300H 4001 0300H64-bit Destination LSBMemory 12 11 10 9 8 7 6 5 4 3 2 1 MSB 64-bit Source Data Block Transfer 20 19 18 17 16 15 14 13 4001 0300H1 Bus operation QWORD load@ A0000210 QWORD load@ A0000208 QWORD load@ A0000200 DWORD store@ 40010304 SOURCE DESTINATION (5 times)

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12.5.2.4.2 Buffer Initialization Mode

Buffer initialization mode transfers will logically only be to memory mapped I/O and will utilize the constant destination mode and granularity fields of the DCR. The address granularity is dictated by the granularity field in the DCR. No errors will be flagged if the destination address is not matched to the granularity, but the required lower address bits will be ignored. Figure 12-14 though Figure 12-16 illustrate buffer initialization mode to an arbitrary destination address. Figure 12-13.Source in Memory Initialization and Destination in Increment Mode Transfer value XX Bus operation Byte store@ 40010307 QWORD store@ 40010308 QWORD store@ 40010310 DESTINATION 4001 0300H 4001 0308H 4001 0310H64-bit Destination LSBMemory A5 81 BC E6 A5 81 BC E6

81 BC E6

81 BC E6 4001 0318H

3-Byte store@ 40010318 EDMACTL SUAR/SAR DUAR/DAR TCR DCR Programmed Values 0000 0088H A581 BCE6H 4001 0307H 0000 0014H 0000 201FH

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Figure 12-14.Source in Buffer Initialization and Destination in 1-Byte Granularity Constant Mode Transfer Figure 12-15.Source in Buffer Initialization and Destination in 2-Byte Granularity Constant Mode Transfer byte number EDMACTL SUAR/SAR DUAR/DAR TCR DCR Programmed Values 0000 0088H A581 BCE6H 4001 0307H 0000 0014H 0000 503FH ADDRESS 4001 0300H 4001 0300H 4001 0300H64-bit Destination LSBMemory MSB 4001 0300HA5 ... Bus operation Byte store@ 40010307 DESTINATION (20 times) byte number EDMACTL SUAR/SAR DUAR/DAR TCR DCR Programmed Values 0000 0088H A581 BCE6H 4001 0306H 0000 0014H 0002 503FH ADDRESS 4001 0300H 4001 0300H 4001 0300H64-bit Destination LSBMemory MSB 4001 0300HA5 ... Bus operation 2-Byte store@ 40010306 DESTINATION (10 times)

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12.5.3 PCI Express Traffic Class

To provide traffic shaping and quality of service within the system fabric, the EDMA contains the traffic class field within the DCR. Traffic class is provided to the external switches, bridges, and other fabric devices to allow one transaction to pass another based on a software generated priority map. The three bit field in the DCR is directly copied to the transaction traffic class field in the PCI-Express header as write transactions are generated to PCI-Express. This field is ignored for all other destinations.

12.6 Channel Data Queuing

Each channel contains a data buffer that is four cache-lines in size (256 bytes). The data buffer holds data temporarily to facilitate pipelining and hide latency, improving the throughput of data transfers between the source and destination.

12.7 Error Conditions

Any of several possible error conditions may arise during a transfer depending on which interfaces the transfer utilizes. The interfaces covered are the EDMA controller interface, the memory interface, and the I/O subsystem destination port interface. All error conditions are reported by setting the corresponding error bits in the Channel Status Register (CSR). The subsections below describe all possible errors at each interface that the EDMA controller must detect and report. For those errors resulting in a channel abort, the response to the error is highly configurable. The controller may be configured to Figure 12-16.Source in Buffer Initialization and Destination in 4-Byte Granularity Constant Mode Transfer byte number EDMACTL SUAR/SAR DUAR/DAR TCR DCR Programmed Values 0000 0088H A581 BCE6H 4001 0304H 0000 0014H 0004 503FH ADDRESS 4001 0300H 4001 0300H 4001 0300H64-bit Destination LSBMemory MSB 4001 0300HA5 ... BC BC BC Bus operation DWORD store@ 40010304 DESTINATION (5 times)

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generate a IA-32 core interrupt upon detection of an error. Beyond this mechanism, errors detected and logged in the CSR may be escalated as described in the chapter on RASUM and exception handling. Refer to the EDMA access disposition tables in Chapter 10.0, “System Address Map,” for an overview of defined ranges in the memory map and associated EDMA access treatment.

12.7.1 Controller Interface Error

The following errors may be reported for any EDMA initiated access, regardless of target interface:

Illegal NDAR address — The descriptor pointer in NDAR is not naturally eight Dword aligned — The value in NDAR does not point to a valid memory location
Illegal source address — Address does not comply with the Source Type bit in the DCR — Address out of range
Illegal destination address — Address does not comply with the Destination Type bit in the DCR — Address out of range — Accesses to any IICH address region via the NSI
Data parity error (corrupt data) returned by memory read retrieving descriptor information All controller interface errors are fatal to the transfer in process and will result in channel abort. Note: This includes data parity errors, since an error in reading a descriptor implies a corrupt descriptor in main memory, and in this case, it is impossible for the channel to determine precisely what part of the descriptor is damaged. The automatic abort upon detection of a corrupt descriptor is necessary to prevent any further data corruption as a result of its execution.

12.7.2 Memory Interface Error

The following errors may be reported for a EDMA initiated access (read or write) on the local memory interface:

Addressing error (source or destination) — Physical EDMA address above REMAPLIMIT (see Section 10.6.1) — Physical address not allocated to memory (including PAM destination mapping) — Physical address specified an illegal memory destination (e.g., protected SMM range)
Data parity error in reading data from the EDMA Data Queue
Data parity error (poisoned data) retu rned by memory read for payload data There is no time-out mechanism associated with transfers. The EDMA channel assumes that all reads to memory will eventually return, although they may return corrupt data, and will wait indefinitely for an outstanding read.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 331 Intel® EP80579 Integrated Processor Addressing errors are fatal and will result in a EDMA channel abort, logged in CSR bit 4. The channel response to data errors is configurable; the channel may be programmed to abort, or to propagate the bad data to its destination.

12.7.3 I/O Interface Error

The following errors may be reported for a EDMA initiated access (write) on an I/O interface:

Address crossed into a memory destination range (checked on each write access)
Address crossed to a new destination port during a transfer (checked at 4 KB boundaries) The latter error will result if poorly formed destination descriptor information specifies a length plus address combination that crosses the addressing boundary between independent outbound ports on the I/O subsystem. Any transfer with a destination range crossing an aligned 4 KB boundary in address space may encounter this error. Addressing errors are fatal and will result in a channel abort. Channel response to data errors is configurable; each channel may be programmed to abort, or to propagate the corrupt data to its destination.

12.8 Channel Arbitration

Arbitration among the four independent channels occurs in two stages. Each channel has an independent bus request/grant pair to the arbiter internal to the controller. The controller in turn has a single request/grant pair to the main arbiter. The arbiter within the controller handles the fairness among channels, while the inbound/outbound arbiter handles fairness between the EDMA channels and other competing traffic sources. The internal arbiter uses a strict round-robin policy, with the added modification of an optional “high priority” designation for one channel at any given time. Thus a set of competing channels will achieve balanced bandwidth performance during normal operation. The inbound/outbound arbiter provides a programmable single or double “grant duration” for the EDMA controller. Thus the channel that “wins” internal arbitration may be allowed to issue one or two access requests back-to-back in a single arbitration cycle. The second request is accepted if the inbound/outbound arbiter is programmed to a grant count of 2 the requesting channel has two consecutive requests of the same type targeting the same destination ready to send, and there are sufficient command and data resources available for the second request.

12.8.1 Normal Arbitration Scheme

A fully connected round-robin arbiter provides a distinctive balanced service among competing requestors. Each of the actively competing channels will receive an equal fraction of the bandwidth service provided by the inbound/outbound arbiter on behalf of each EDMA channel. In the absence of any competition from the IA-32 core, PCI Express ports, or other I/O, each EDMA channel will be allowed to saturate the memory interface. For example, given a memory interface “saturation point” of 4 GB/s, the round-robin scheme would be equally distributed between the competing EDMA channels.

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12.8.2 Prioritized Arbitration Scheme

The high priority option in the arbitration scheme provides for a single “high priority” channel to receive favorable latency and bandwidth service in the face of multiple competing “normal priority” channels. This is accomplished by designating the high priority channel using a priority enable bit and a two-bit field (to select one of four channels) in the EDMA control register. The internal EDMA controller arbiter modifies its arbitration algorithm to provide a grant to the priority channel between the grants for each of the other channels, which retain their round-robin prioritization relative to each other. For example, given a hypothetical memory interface bandwidth of 4 GB/s, the priority-modified scheme would result in 2 GB/s (half the available bandwidth) for the designated priority channel, and the remaining 2 GB/s split equally among the other competing channels. The limitation that a single channel at a time be designated as the priority channel is an acknowledgement that quality of service differences, given multiple “priority” channels, would be slight in this implementation with two-level arbitration and only four competing channels. It is anticipated that software will be able to determine when an application is particularly sensitive to service level, has been allocated a channel, and will manage the assignment of priority accordingly. If more than one such “sensitive” application is in flight at the same time, it is perceived to be more efficacious to allow fair competition between those sources, and let the kernel or device driver software attempt to manage competition for resources at the system level to prevent service level problems. Each EDMA channel supports dynamic modification to the priority channel settings (while one or more channels are active). A write to the control register that changes the priority channel configuration takes affect at the next arbitration decision point after the write has completed. There is no direct interlock between the arbiter configuration and any of the active channels. Such an event is effectively an environment change, orthogonal to work in progress on any given channel.

12.9 Configuration

The EDMA controller uses memory-mapped configuration registers for the majority of its per channel register sets. The controller is software compatible with standard PCI device configuration and implements a standard PCI header in its configuration- mapped register set as shown in Figure 12-1. The memory-mapped register space associated with the controller is identified by a 32-bit memory Base Address Register (BAR). Table 12-1 provides an overview of the memory-mapped register set for a representative channel of the controller. Table 12-1. Channel 0 Memory-mapped Register Set Memory Mapped I/O for EDMA Channel 0 Memor y offset Access Size Default Sticky Channel Control Register (CCR0) 00-3h RW 32 bits 0000_0000h No Channel Status Register (CSR0) 04-07h RWC, RO 32 bits 0000_0000h No Current Descriptor Addr Reg (CDAR0) 08-0Bh RO 32 bits 0000_0000h No Current Descriptor Upper Addr Reg (CDUAR0) 0C-0Fh RO 32 bits 0000_0000h No Source Address Register (SAR0) 10-13h RO 32 bits 0000_0000h No Source Upper Address Register (SUAR0) 14-17h RO 32 bits 0000_0000h No Destination Address Register (DAR0) 18-1Bh RO 32 bits 0000_0000h No Destination Upper Address Register (DUAR0) 1C-1Fh RO 32 bits 0000_0000h No

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 333 Intel® EP80579 Integrated Processor All internal registers are accessible through host-initiated configuration space accesses or SMBus interface accesses. Internal registers are not accessible from the I/O subsystem interfaces.

12.9.1 Power Up/Default Status

Upon power-up or hardware reset, the channel registers are initialized to their default values. All reserved and unimplemented registers and bits in the device return zero on reads and are unaffected by writes.

12.9.2 Channel-Specific Register Definitions

Each channel has twelve 32-bit memory-mapped registers for its independent operation. Eight of these registers (refer to the descriptions below) are loaded automatically from their corresponding fields in the chain descriptor when a new descriptor is fetched from local memory during normal operation. The format of the corresponding descriptor fields in memory is identical to the format defined for the channel-specific registers. Refer to “Memory Mapped I/O for EDMA Registers” on page 651 for bit definitions. Read/write access is available only to the following:

Channel Control Register (CCR)
Channel Status Register (CSR)
Next Descriptor Address Register (NDAR)
Next Descriptor Upper Address Register (NDUAR) The remaining registers are read-only and are automatically loaded with new values defined by the chain descriptor whenever the channel reads a chain descriptor from local system memory. Note: Automatic loading of the channel-specific registers occurs after the memory read completion returns the descriptor data (32 B), and verification has taken place. Verification includes checking parity on the data returned and checking that the channel is properly configured to receive new descriptor data. (If a suspend is in progress, the descriptor data will be dropped in honor of the suspend.)

12.9.2.1 Channel Control Register – CCR

The Channel Control Register (CCR) specifies the overall operating environment for the channel. This is a read/write register, and is cleared to zero on power-on or system reset (contains no sticky bits). Application software initializes this register only after initializing the chain descriptors in system memory and updating the Next Address Registers with the location of the first chain descriptor in memory. The CCR may be written when the channel is active to modify channel operation (stop, suspend, etc.) while the channel is active. Next Descriptor Address Register (NDAR0) 20-23h RWL 32 bits 0000_0000h No Next Descriptor Upper Address Register (NDUAR0) 24-27h RWL 32 bits 0000_0000h No Transfer Count Register (TCR0) 28-2Bh RO 32 bits 0000_0000h No Descriptor Control Register (DCR0) 2C-2Fh RO 32 bits 0000_0000h No Table 12-1. Channel 0 Memory-mapped Register Set

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The following bits are defined in the CCR:

Start: initiate a new transfer (requires that the CSR be appropriately cleared)
Stop: abort the current transfer (immediately)
Suspend: suspend the current transfer (upon completion of the current descriptor)
Channel Resume: resume a suspended transfer (retrieve the descriptor indicated by NDAR/NDUAR from local memory, and proceed with execution per the value returned). Requires that the stopped and abort status bits in the CSR be clear to take effect and will automatically clear end of chain and end of transfer flags. Refer to “Offset 00h: CCR0 - Channel 0 Channel Control Register” on page 653 for the format of the CCR.

12.9.2.2 Channel Status Register – CSR

Channel Status Register (CSR) contains flags to indicate the channel status. The register is read by application software to get the current channel status and to determine the source of interrupts. CSR is cleared to zero on power-on or system reset. This is a read/write register. The following bits are defined in CSR:

Channel Active: transfer in progress
Aborted: transfer encountered an error
Stopped: transfer stopped via software request (Stop bit detected)
Suspended: transfer suspended via software request (Suspend bit detected)
End of Transfer: channel has completed execution of (at least one) descriptor
End of Chain: channel has completed execution of the terminal descriptor (null NDAR/NDUAR) Refer to “Offset 04h: CSR0 - Channel 0 Channel Status Register” on page 656 for the format of CSR.

12.9.2.3 Current Descriptor Address Register – CDAR

The Current Descriptor Address Register (CDAR) contains the lower 32-bits of the address for the current chain descriptor in local system memory. The CDAR is cleared to zero on power-on or system reset, and is loaded automatically with the value from the Next Descriptor Address Register (NDAR) when a new block transfer is initiated. This register is read-only, and may be polled by software to monitor the progress of the channel as it traverses the descriptor chain.

12.9.2.4 Current Descriptor Upper Address Register – CDUAR

The upper address will not be used in the EP80579, which is limited to 32-bit addressing. The Current Descriptor Upper Address Register (CDUAR) contains the upper 32-bits of the address of the current chain descriptor in local system memory. The CDUAR is cleared to zero on power-on or system reset and is loaded automatically with the value from the Next Descriptor Upper Address Register (NDUAR) when a new block transfer is initiated. This register is read-only. 1. Note that the IMCH does not provide an interlock to guar antee that consecutive reads to the CDAR/CDUAR pair return portions of the same descriptor in the event of a collision between the read accesses and a descriptor load operation. If software requires knowledge of the current descriptor, the “Suspend” function must be invoked prior to polling these registers.

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12.9.2.5 Source Address Register – SAR

The Source Address Register (SAR) contains the lower 32-bits of the source address for the current transfer. The SAR is cleared to zero on power-on or system reset and is loaded automatically with the Source Address field of the chain descriptor (first DWord) when a new chain descriptor is read from memory. The address can be aligned to any byte boundary. The system destination for reads to this address range must match the Source Type setting of the DCR or the transfer will abort.

12.9.2.6 Source Upper Address Register – SUAR

The upper address will not be used in the EP80579, which is limited to 32-bit addressing. The Source Upper Address Register (SUAR) contains the upper 32-bits of the source address for the current transfer. The SUAR is cleared to zero on power-on or system reset and is loaded automatically with the Source Upper Address field of the chain descriptor (second DWord) when a new chain descriptor is read from memory.

12.9.2.7 Destination Address Register – DAR

The Destination Address Register (DAR) contains the lower 32-bits of the destination address for the current transfer. The DAR is cleared to zero on power-on or system reset and is loaded automatically with the Destination Address field of the chain descriptor (third DWord) when a new chain descriptor is read from memory. The address can be aligned to any byte boundary. The system destination for writes to this address range must match the Destination Type setting of the DCR or the transfer will abort.

12.9.2.8 Destination Upper Address Register – DUAR

The upper address will not be used in the EP80579, which is limited to 32-bit addressing. The Destination Upper Address Register (DUAR) contains the upper 32-bits of the destination address for the current transfer. The DUAR is cleared to zero on power-on or system reset and is loaded automatically with the Destination Upper Address field of the chain descriptor (fourth DWord) when a new chain descriptor is read from memory.

12.9.2.9 Next Descriptor Address Register – NDAR

The Next Descriptor Address Register (NDAR) contains the lower 32-bit address of the next descriptor chain in the local system memory. The NDAR is cleared to zero on power-on or system reset and is loaded automatically with the Next Descriptor Address field of the chain descriptor (fifth DWord) when a new chain descriptor is read from memory. This address must be aligned to an 8-DWord address boundary. A value of zero implies the end of chain if the value of Next Descriptor Upper Address (loaded into the NDUAR) is also zero. Application software writes this register with the address of the first chain descriptor in memory prior to initiating a transfer. Note: The application software must make sure that the Start bit in the CCR and the Channel Active bit in the CSR are clear prior to writing to the NDAR. The IMCH protects this register from being written when these bits are not clear. If the NDAR and NDUAR are zero when the Start bit is set, no transfer will be initiated.

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12.9.2.10 Next Descriptor Upper Address Register – NDUAR

The upper address will not be used in the EP80579, which is limited to 32-bit addressing. The Next Descriptor Upper Address Register (NDUAR) contains the upper 32-bit address of the next descriptor chain in the local system memory. All address bits above bit 35 must be zero or the transfer will abort and an error will be reported. A value of zero implies the end of chain if the value of Next Descriptor Address (loaded into the NDAR) is also zero. NDUAR is cleared to zero on power-on or system reset and is loaded automatically with the Next Descriptor Upper Address field of the chain descriptor (sixth DWord) when a new chain descriptor is read from memory. Application software (likely the device driver) writes this register with the address of the first chain descriptor in the memory prior to initiating a transfer. Note: The application software must make sure that the Start bit in the CCR and the Channel Active bit in the CSR are clear prior to writing to the NDUAR. The IMCH protects this register from being written when these bits are not clear. If the NDAR and NDUAR are zero when the Start bit is set, no transfer will be initiated.

12.9.2.11 Transfer Count Register – TCR

The Transfer Count Register (TCR) contains the length of the current transfer in bytes. The TCR is cleared to zero on power-on or system reset and is loaded automatically with the Transfer Count field of the chain descriptor (seventh DWord) when a new chain descriptor is read from memory. The TCR allows for a maximum transfer of 16 MB, commensurate with current operating system capabilities. A value of zero is valid and results in no data being transferred and no cycles generated on the source or destination buses. It also results in completion bits being set after successful completion “same as if it were a no zero length transfer”.

12.9.2.12 Descriptor Control Register – DCR

The Descriptor Control Register (DCR) contains control values for the transfer on a per descriptor basis. The DCR is cleared to zero on power-on or system reset and is loaded automatically with the Descriptor Control field of the chain descriptor (eighth DWord) when a new chain descriptor is read from memory. The values in the DCR may vary for different descriptors within a single chain. Note: The descriptor control register value stipulates coherence attributes for both the source and destination addresses defined by this chain descriptor. Independent bits are also defined to specify whether the source and destination address ranges are to be treated as “coherent” or “non-coherent” by the IMCH. When the DCR value stipulates that one or both of the source and destination are to be treated as “non-coherent” space, the IMCH will rely on software to maintain system memory coherency and will not issue FSB cycles during the block transfer to snoop processor caches on behalf of the corresponding address range(s). The following bits are defined in the CCR:

Destination Address Mode: two bits specify destination address as increment or constant
Granularity of the transfer in destination constant address mode: two bits (1B, 2B, or 4B)
PCI-Express Destination Traffic Class: three bits define this traffic class
Source Address Mode: two bits specify source address as increment, decrement, or buffer/memory initialization
Buffer/Memory Initialization Mode: Specifies a write to fill an area of memory

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Destination Coherency: specifies whether destination addresses should be snooped on the FSB
Source Coherency: specifies whether source addresses should be snooped on the FSB
Destination Type: specifies whether the destination is local memory or the I/O subsystem
Source Type: specifies whether the source is local memory or the I/O subsystem (defined only for symmetry, I/O subsystem source addresses are not supported)
Abort Interrupt Enable: specifies whether to generate an interrupt on abort
Stop Interrupt Enable: specifies whether to generate an interrupt on stop
Suspend Interrupt Enable: specifies whether to generate an interrupt on suspend
End of Transfer Interrupt Enable: specifies whether to generate an interrupt on EOT
End of Chain Interrupt Enable: specifies whether to generate an interrupt on EOC Refer to Chapter , “Offset 2Ch: DCR0 - Channel 0 Descriptor Control Register,” for the format of the DCR.

12.10 Interrupts

Each EDMA channel can be configured to generate interrupts to the processor interface. The interrupt enable bits for end of transfer and end of chain in the Descriptor Control Register (DCR) determine if the channel generates an interrupt upon successful error- free completion of a transfer. The Abort Interrupt Enable bit in the DCR determines if the channel generates an interrupt upon encountering an error. Refer to “Error Conditions” on page 329 for details on errors on both the source and destination interface. Table 12-2 summarizes the status flags, and the conditions under which interrupts will be generated. Each chain descriptor can independently set or clear the various interrupt enable bits in the Descriptor Control Register. This level of control for interrupt generation permits flexibility in synchronization between application software and transfers in progress. If interrupts are not enabled, synchronization can be achieved by polling the status bits in the Channel Status Register (CSR). Note: “-” In the table below equates to a non valid combination

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12.10.1 Interrupt Routing Mechanisms

Two different mechanisms are available to route interrupts generated by channels to the IA-32 core. Note that the interrupt mechanism itself is not channel-specific; all channels generating interrupts share the same interrupt vector and handler. This is in line with the expectation that a single device driver controls each EDMA channel at large, rather than independent drivers per channel. The first interrupt mechanism uses the integrated IOxAPIC and 8259 emulation hardware. All interrupts from the channels are logically OR’ed and routed to the interface controller for propagation via the in-band Assert_Intx and Deassert_Intx special cycles, emulating a level-sensitive interrupt output. The IMCH tracks these special cycles, and forwards the signaled interrupt to the IA-32 core. If the APIC enable bit is set, an interrupt will result in an APIC message. If the APIC enable bit is clear (unanticipated but possible), an interrupt will result in a legacy mode 8259-style level sensitive interrupt directly to the IA-32 core socket. The second interrupt mechanism uses Message Signaled Interrupt (MSI) generation functionality integrated into the EDMA. Internal interrupt messaging utilizes the PCI message capability structure and does not support external interrupt input routing. Table 12-2. Interrupt Summary Interrupt Conditions Channel Status Register (CSR) Flags DCR Bit Settings (INTR Enable Bits) Channel Active Stopped Suspended End of Transfer End of Chain Channel Aborted (Error) Stop INTR Enable Suspend INTR Enable EOT INTR Enable EOC INTR Enable Abort INTR Enable Stopped 01 0 2 --- 1 4 ---- Suspended 00 2 11 3 ---1--- End of Transfer 1--1----1-- End of Chain 0--11----1- Channel Abort1 0--001----1 Notes: 1. The IMCH ensures that any aborted transfer will be reported via the Channel Abort status bit and that this bit will never be accompanied by an End of Transfer or End of Chain indication. This ensures that software never mistakes an aborted transfer for a successfully completed transfer – even if the error is not detected until the final write to the final destination address of the terminal chain descriptor. 2. The Stop and Suspend functions are mutually exclusive, and only one of the two status bits will ever be asserted by the IMCH. In the event that software asserts both controls in the CCR, the Stop function will take precedence. 3. The EDMA Suspend function causes the channel to suspend operation at the completion of the current descriptor. The EOT status bit will always accompany the suspended status bit. Note that even if interrupts are enabled for both EOT and suspend, only a single interrupt event will result. 4. The Stop function causes the channel to abort the transfer in progress immediately. It is recommended that software read back the channel status register to verify that a stop command has taken effect, since this will be much faster than setting the interrupt enable for stop and waiting for the interrupt to occur.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 339 Intel® EP80579 Integrated Processor (That is, the limited MSI functionality described here is dedicated to the EDMA channel.) This second mechanism is preferred for interrupt signaling, but is only available in platforms running an MSI-capable operating system. Selection between these two mechanisms is automatic in the IMCH. If MSI messaging is enabled, as indicated by the enable bit in the MSI control register, then the MSI interrupt mechanism is used. If MSI message generation is disabled, any initiated interrupt will use the dedicated pin legacy mechanism. For both interrupt mechanisms, the interrupt service routine (ISR) must service all interrupts for all channels. The memory-mapped EDMA Controller Global Status Register must be statused before returning from the ISR to ensure no additional interrupts have occurred. Failure to address interrupts in all channels will result in potential system starvation.

12.10.2 Message Signaled Interrupt (MSI)

The EDMA controller is capable of generating upstream interrupt messages (MSI) directly to the IA-32 core. An MSI is signaled via a Memory Write to address 0FEEx_xxxxh. Three 32-bit registers are required in the controller to support this mechanism. The default values of these registers are compatible with the default value of the IOxAPIC specification. The three registers are the MSI Control Register (MSICR), MSI Address Register (MSIAR), and MSI Data Register (MSIDR). Software must program these registers to appropriate values prior to enabling internal MSI functionality. Note: It is unsafe to enable the integrated MSI APIC function of the controller in environments under control of a non MSI-capable operating system. The MSI mechanism supports differentiation between interrupts generated during normal operation (EOT, EOC, stop, and suspend) and interrupts due to errors (abort). This extra level of granularity is unavailable via the legacy interrupt mechanism. To facilitate use of a single device driver for the entire EDMA function, a single MSI register set services all channels. The support for two different messages on behalf of the controller is included in the MSI register set. Refer to “EDMA Registers: Bus 0, Device 1, Function 0” on page 501 for the format of these registers. Note: The integrated APIC functionality will not support level-sensitive interrupt emulation requiring the use of broadcast EOI cycles from the FSB. No path is provided to handle such traffic from IA-32 core to EDMA control engine. Thus the only supported MSI type is the edge-triggered variety. The following subsections describe the register set for MSI support.

12.10.2.1 MSI Control Register – MSICR

The MSI Control Register (MSICR) contains control information for MSI interrupt capability. The multiple-message enable field and MSI enable are contained in this register.

12.10.2.2 MSI Address Register – MSIAR

The MSI Address Register (MSIAR) contains address information specifying the message destination address for MSI interrupts.

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12.10.2.3 MSI Data Register – MSIDR

The MSI Data Register (MSIDR) contains routing and priority data for generation of MSI interrupts.

12.10.3 Interrupt Ordering

To support MSI signaling as transfers complete, the IMCH must take special steps in hardware to ensure that IA-32 core accesses to memory in response to MSI do not experience producer/consumer ordering failures. Specifically, the chip must internally guarantee functionality equivalent to a logical “FENCE” operation between the MSI and subsequent IA-32 core traffic from the FSB.

12.10.3.1 Interrupt Ordering for Memory Destination

The failure to be prevented for interrupts signaled at the end of transfers to memory destinations is as follows:

Each EDMA channel is programmed to move a single cache-line of data and issue an MSI upon completion. This is a special case, for illustrative purposes; a similar scenario arises for the last few writes of a multi-line transfer.
As soon as the write data is posted into the inbound/outbound arbiter headed for the memory interface, the MSI is issued directly to the FSB. Note that the transfer to memory may be issued without an accompanying FSB snoop cycle (non- coherent), thus the data and interrupt message are logically traversing independent traffic paths.
In response to the MSI, the IA-32 core i ssues a memory read to retrieve the data from memory. In the absence of an internal interlock, this read may proceed to the memory controller before the posted write data is accepted into the memory controller from the inbound/outbound arbiter. This is where the error occurs, because the memory controller will not have any information regarding the relative issue order of the write and the read – if the read gets there first, it will retrieve stale data. To prevent such a failure, the inbound/outbound arbiter includes specialized hardware to guarantee that all posted write data received ahead of an MSI are forwarded out of the arbiter before the MSI message will be forwarded to the FSB. A similar interlock in the inbound/outbound arbiter prevents failures in the non- interrupt case. When software is polling the Channel Status Register (CSR) to detect transfer completion, specialized hardware guarantees that the read completion stalls until all prior posted write data is forwarded out of the arbiter.

12.10.3.2 Interrupt Ordering for Outbound Destination

The failure to be prevented for interrupts signaled at the end of transfers to outbound port destinations is as follows:

Each EDMA channel is programmed for a single block transfer to an I/O device, with interrupt notification enabled at the completion of that transfer. For this example, MSI generation is disabled.
When the final write of the transfer is posted into the inbound/outbound arbiter, a level-sensitive interrupt is signaled directly to the interrupt output pin, bypassing all internal queue structures.
If the integrated IOxAPIC is enabled, the response to the interrupt pin will be an APIC message received. If the APIC is disabled, a sideband interrupt is signaled directly to the IA-32 core via a level sensitive output.

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For either case, the likely software response to the interrupt will be a posted write “door-bell” access to a memory mapped control register in the EDMA destination device to communicate completion of the transfer. (Semantic: EDMA transfer completed without errors, you have all the data, GO.)
In the absence of internal interlocks as described above, multiple failures are possible. The APIC message could bypass EDMA data pending within the inbound/ outbound arbiter, and the IA-32 core doorbell write could do the same. This would result in stale data “executed” in response to the doorbell. The internal IMCH hardware interlock prevents APIC messages from being forwarded to the FSB while posted data remains pending in the inbound/outbound arbiter. This prevents most of the problematic behavior in this case. If the APIC is disabled, the IA- 32 core must retrieve the interrupt vector from the 8259 emulator, and the read completion interlock will then guarantee that all posted write data has cleared the arbiter. Another potential issue is relaxed write ordering within a system agent en route to the EDMA destination device. If the hardware were to issue EDMA outbound posted writes and IA-32 core posted writes with differing stream ID codes, an intermediary component may allow the IA-32 core doorbell access to move around posted EDMA data. This would again result in stale data “executed” by the destination device. The IMCH could solve this problem by issuing an explicit FENCE between the final EDMA write and the interrupt, preventing subsequent IA-32 core accesses from reordering en route to the destination. A simpler (but more limited) solution is to utilize the same stream ID for all outbound traffic regardless of source. This makes transactions initiated by each EDMA channel indistinguishable from those initiated by any of the IA- 32 core threads. With no stream ID information to determine reordering legality, an intermediary device must necessarily enforce strong ordering for all accesses outbound. The single initiator ID in concert with the internal interlock for APIC messages and read completions is sufficient to guarantee proper behavior. The implementation guarantees that any flag write or data read to the destination port will necessarily push the EDMA transfer data ahead of it, ensuring correct producer/consumer operation.

12.11 Initiating an EDMA Transfer

The following subsections detail the steps the software must take in programming a channel to initiate a transfer (or chain of transfers). The steps covered include channel initialization, transfer start, and suspend or stop. Each channel is designed to have independent control of interrupt enabling and generation, and independent transfer attribute controls; this provides the greatest flexibility to the application program.

12.11.1 Setup and Initiation

Initializing a channel begins with constructing one or more chain descriptors in local system memory. Each chain descriptor takes the form described in Section 12.3.1, “Chain Descriptor Definition” on page 311. Once the descriptors are defined, the following steps are required to initiate a transfer: 1. Ensure the EDMA channel is enabled and in Normal Mode by setting the EDMA Enable and Mode bits of the EDMA Control Register. 2. The channel must be inactive/idle prior to starting a transfer. This may be verified by reading the Channel Active bit in the Channel Status Register (CSR), which is clear when the channel is inactive/idle. 3. Update the Next Descriptor Address Register (NDAR/NDUAR) with the address of the first chain descriptor in local system memory.

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Clear the Channel Status Register (CSR) of any asserted error or status bits. Each EDMA channel will not initiate a new transfer when an error condition remains in the CSR. 5. Clear the Suspend bit and set the Start bit in the Channel Control Register (CCR). Since this is the start of a new transfer and not the resumption of a previous transfer, the Channel Resume bit in the CCR must be clear. (Resume overrides start.) 6. The channel starts the transfer by fetching the chain descriptor at the address contained in the Next Descriptor Address Register (NDAR/NDUAR). The channel moves the NDAR/NDUAR values into the CDAR/CDUAR, and loads the chain descriptor values into their corresponding internal registers. If the load completes without any error, the actual data transfer begins. The Current Descriptor Address Register (CDAR/CDUAR) now contains the address of the chain descriptor just fetched and the Next Descriptor Address Register (NDAR/NDUAR) now contains the descriptor address of the next descriptor in the chain, if any. 7. When the current EDMA transfer has completed without any errors, the channel fetches the next chain descriptor from the address contained in the Next Descriptor Address Register (NDAR/NDUAR) automatically without any software intervention, and proceeds with the next block transfer (provided the value in the NDAR/NDUAR pair is non-zero). The last descriptor in the chain list has a null value in the Next Descriptor Address field, specifying the end of the chain. The null value in the Next Descriptor Address Register (NDAR/NDUAR) notifies the channel not to read additional chain descriptors from local system memory, and the channel goes idle.

12.11.2 Suspend Function

Software may temporarily suspend execution of a descriptor chain by setting the Suspend bit in the Channel Control Register (CCR). The target channel will complete execution of the current descriptor and suspend operation without losing current status. Software may later cause the channel to resume execution of the descriptor chain by writing to the CCR to clear the Suspend bit and set the Resume bit. In response, the channel will initiate a descriptor fetch from the NDAR/NDUAR, and resume the suspended operation. Software does not need to re-program the channel configuration after a suspend sequence.

12.11.3 Stop Function

Software may intentionally abort a transfer by setting the Stop bit in the Channel Control Register (CSR). Once aborted, the transfer cannot be resumed. In response to the Stop bit, the target channel will immediately cease fetching source data, drain any buffered destination data, and go idle. Usage of this mechanism will result in assertion of the Stopped status bit in the CSR, and will generate an interrupt if so enabled. (Note that the stop function is sufficiently fast in the IMCH that reading back the channel status register is preferred over utilizing the interrupt on stop function.) Usage of the Stop mechanism will not result in assertion of the Abort status bit, nor will it generate an “interrupt on abort” indication if so enabled. The channel differentiates an abort on error from an abort on software command, and will ensure that all error status bits remain clear. If the MSI mechanism is in use for interrupt generation, and independent messages are defined for abort on error and normal run-time interrupts, the latter message type will be utilized on behalf of the stop function.

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12.11.4 EDMA Process Flow

Figure 12-17 provides a high-level flow chart of the EDMA initialization sequence. Figure 12-18 provides a similar view of the EDMA completion sequence. Figure 12-17.Initiation Flow Chart Initiate EDMA Transfer B4492-01 Program EDMA Appending to Existing Chain Is Channel Active Set? Return No Yes Yes Set Suspend EDMA Bit Update Terminal Descriptor in Memory Set Channel Resume bit, clear Suspend bit Wait Time Out? No No Error Return Yes Program EDMA Clear Channel Status Register 1. Set Next Descriptor Address Register (64b) 2. Set Channel Control Register (Start EDMA bit and other Control bits) Return

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§ § Figure 12-18.Completion Flow Chart Transfer Over Interrupt Received B4493-01 Release Current Descriptor Interrupt Expected? End of Chain? Return Yes No No Initiate EDMA Transfer Yes Polled Transfer Over Is Channel Status Good? Clear Completion Status and Interrupt / EOI Error Return No Yes

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13.0 Platform Configuration

13.1 RASUM Features - SMBus Access

Configuration registers are accessible from either the IA-32 core or from the SMBus. The IA-32 core will be able to access all configuration registers through host configuration cycles. Access via SMBus is read/write to the IMCH configuration registers. The SMBus cannot use the IMCH's SM-port target interface to access any register in the IICH or outside of CMI. Each device must have its own SMBus target port. CMI does not shadow the RASUM registers for the SMBus. To clear these registers, a write access will need to be performed. The IMCH SMBus has full read/write access to the IMCH PCI legacy registers. The IMCH global RASUM register set and those registers applicable to logical bus#0 and memory are implemented in Function 1 of Device 0. RASUM registers specific to other internal devices appear in the register map for the associated device. The IMCH error control registers are in Function 1, and are read/write accessible by the processor and through the SMBus. The IMCH error logging registers are also available to the processor and SMB master in Function 1. The IMCH RASUM control register and the “CMD” registers (SERRCMD, SMICMD, etc.) which control generation of SERR#, SMI#, and SCI# are read/write accessible by the processor and through the SMBus. FSB-initiated accesses to configuration space registers are serviced through configuration ring. It is perfectly legal for an SMBus access to be requested while an FSB-initiated access is already in progress. In other words, SMBus configuration accesses and processor configuration cycles may occur at the same time. The IMCH supports “wait your turn” arbitration to resolve all collisions and overlaps, such that the access that reaches the configuration ring arbiter first is serviced first while the conflicting access is held off. An absolute tie at the arbiter is resolved in favor of the FSB.

13.2 Platform Configuration Structure Conceptual Overview

The IMCH and IICH are physically connected by an internal interface called NSI (North South Interface). From a configuration standpoint, NSI is logically PCI bus #0. As a result, all devices internal to the IMCH and IICH, except host switch devices appear to be on PCI bus #0. The system's primary PCI expansion bus is physically attached to the IICH and, from a configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge and therefore has a programmable Bus number. The PCI Express ports appear to system software to be real PCI buses behind PCI-to-PCI bridges that reside as devices on PCI bus #0. CMI decodes multiple PCI Device numbers. The configuration registers for the devices are mapped as devices residing on PCI bus #0 except for host switch devices. Each Device Number may contain multiple functions. See Table 13-1, “PCI Devices and Functions on Bus 0” for device and function assignments.

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13.2.1 IMCH PCI Devices

The PCI predefined header has five fields that deal with device identification. All devices are required to implement these fields. Generic configuration software is able to easily determine the device available for use. These registers are read only. The five fields are vendor ID, device ID, revision ID, header type, and class code:

The 16-bit vendor ID is assigned by PCI SIG and has a value of 8086h for Intel.
The 16-bit device ID is assigned by the vendor.
The 8-bit revision ID is chosen by the vendor to indicate the different steppings of a device. The value 00h designates an A0 stepping. The value 01h designates an B0 stepping.
The header type specifies the structure of the second half of the header, and also whether or not the device has multiple functions. The value 80h indicates a multi- function device.
The class-code field identifies the generic function of the device. The class-code is further broken into three sub-fields, base class, sub-class, and programming interface. CMI proper has a base class code of 06h indicating a bridge device. The sub-class value of 00h indicates a host bridge. A disabled or non-existent IMCH device’s configuration register space is hidden, returning all 1’s for reads and dropping writes just as if the cycle terminated with a Master Abort on PCI. If one or more IICH devices or some of their functions are not supported on the platform, each can be disabled individually. When a device or function is disabled, it does not appear at all to the software: No responses to any register reads and no responses to any register writes. This is intended to prevent software from thinking that a device or function is present (and reporting it to the end-user). When a PCI Express interface is unpopulated or fails to train, the associated configuration register space is hidden, returning all ones for all registers just as if the cycle terminated with a Master Abort on PCI. Also, if PCI Express port PEA0 is configured for x8 operation rather than x4, the corresponding PCI Express port PEA1 configuration space will be hidden. Table 13-1. PCI Devices and Functions on Bus 0 Device Function Function Description

00 I M C H

0 1 IMCH, error status

10 I M C H E D M A e n g i n e

2 0 IMCH PCI Express Port A0 X8 or X4 unit 8 0 IMCH Test and Device 0 Overflow 31 0 IICH LPC Interface 31 2 IICH SATA Controller 31 3 IICH SMBus Controller 31 5 Reserved 31 6 Reserved 29 0 IICH USB Controller #1 29 7 IICH USB 2.0 Controller

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13.2.2 IICH PCI Devices

Logically, the IICH appears as multiple PCI devices within a single physical component also residing on PCI bus #0. One of the IICH devices is a PCI-to-PCI bridge. Logically, the primary side of the bridge resides on PCI #0 while the secondary is a standard PCI expansion bus. Note: The internal devices in the IMCH and IICH (except host switch devices) logically constitute as PCI Bus #0 to configuration software (see Figure 13-1).

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Figure 13-1. Bus 0 Device Map CPU PCI Config Window in I/O Space NSI Interface IMCH PCI Express Bridge Bus #0, Dev #2 PCI Express Bridge Bus #0, Dev #3 NSI, DDR2, FSB Bus #0, Dev #0 NSI Interface SATA Bus 0, Device 31 Function 2 IICH NSI (Logical PCI Bus #0) 8/4bit PCI Express PCI-to-PCI Bridge 4bit PCI Express USB Classic Host Bus 0, Device 29 Function 0 USB2 Host Bus 0, Device 29 Function 7 SMBus Controller Bus 0, Device 31 Function 3 LPC Bridge Bus 0, Device 31 Function 0 PCI Express Enchanced Config Window in Mem Space EDMA registers Bus #0, Dev #1 Bus M

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13.3 Routing Configuration Accesses

The IMCH supports up to two x4 PCI Express interfaces:

P E A 0
P E A 1 These two interfaces can be combined to form a x8 interface, PEA. The IMCH is responsible for routing PCI configuration cycles to the proper interface. PCI configuration cycles to IICH internal devices and downstream devices are routed to the IICH via the internal NSI bus. PCI configuration cycles to the IMCH PCI Express interfaces are routed to PEA(0:1). Routing of configuration accesses to PEA(0:1) is controlled via the standard PCI-to-PCI bridge mechanism using information contained within the PRIMARY BUS NUMBER, the SECONDARY BUS NUMBER, and the SUBORDINATE BUS NUMBER registers of the corresponding PCI-to-PCI bridge device. A detailed description of the mechanism for translating IA-32 core I/O bus cycles to configuration cycles on one of the buses is described below. Note: The IMCH supports a variety of connectivity options. When any of the IMCH’s interfaces are disabled, the associated interface’s device registers are hidden. All configuration cycles (reads and writes) to disabled devices on bus #0 are forwarded to the NSI where they will Master Abort.

13.3.1 Standard PCI Bus Configuration Mechanism

The PCI Bus defines a slot based “configuration space” that allows each device to contain up to eight functions with each function containing up to 256 8-bit configuration registers. The PCI Specification defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the IA-32 core. Configuration space is supported by a mapping mechanism implemented within the IMCH. The PCI Specification defines two mechanisms to access configuration space, Mechanism #1 and Mechanism #2. CMI supports Mechanism #1. The configuration access mechanism makes use of the CONFIG_ADDRESS Register and CONFIG_DATA Register. To reference a configuration register a Dword (32-bit) I/O write cycle is used to place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. CONFIG_ADDRESS[31] must be a ‘1’ to enable a configuration cycle. CONFIG_DATA then becomes a window into the four bytes of configuration space specified by the contents of CONFIG_ADDRESS. Any read or write to CONFIG_DATA will result in the IMCH translating the CONFIG_ADDRESS into the appropriate configuration cycle. The IMCH is responsible for translating and routing the IA-32 core I/O accesses to the CONFIG_ADDRESS and CONFIG_DATA registers to internal IMCH configuration registers, for NSI, and PCI Express ports PEA(0:1). Note: It is only possible to generate 1-4 byte configuration accesses via this mechanism, which is in line with IMCH capabilities. The IMCH ONLY supports accesses up to 1 Dword (32 bits) in size into the configuration register space (internal or external).

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13.3.2 PCI Bus #0 Configura tion Mechanism

The IMCH decodes the Bus Number (bits 23:16) and the Device Number fields of the CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, the configuration cycle is targeting a PCI Bus #0 device. The Host-NSI Bridge entity within the IMCH is hardwired as Device #0 on PCI Bus #0. The EDMA Controller within the IMCH is hardwired as Device #1 on PCI Bus #0. The Host-PEA0 bridge entity within the IMCH is hardwired as Device #2 on PCI Bus #0. The Host-PEA1 bridge entity within the IMCH is hardwired as Device #3 on PCI Bus #0. The PCI-to-PCI Bridge entity within the IMCH is hardwired as Device #4 on PCI Bus #0 Configuration cycles to any of the IMCH’s enabled internal devices are confined to the IMCH and not sent over NSI. Accesses to disabled IMCH internal devices, or devices #10 to #31 is forwarded over NSI as Type 0 Configuration Cycles. A[1:0] of the NSI Request Packet for the Type 0 configuration cycle is “00”. Bits 31:2 of the CONFIG_ADDRESS register is translated to the A[31:2] field of the NSI Request Packet of the configuration cycle as shown in Figure 13-2. The IICH decodes the Type 0 access and generates a configuration access to the selected internal device.

13.3.3 Primary PCI and Downstre am Configuration Mechanism

If the Bus Number in the CONFIG_ADDRESS is non-zero, and does not lie between the SECONDARY BUS NUMBER register and the SUBORDINATE BUS NUMBER register for one of the PCI Express ports, the IMCH will generate a Type 1 NSI Configuration Cycle. A[1:0] of the NSI request packet for the Type 1 configuration cycle is “01”. Bits 31:2 of the CONFIG_ADDRESS register is translated to the A[31:2] field of the NSI request packet of the configuration cycle as shown in Figure 13-3. This NSI configuration cycle is sent over NSI. If the cycle is forwarded to the IICH via NSI, the IICH compares the non-zero Bus Number with the SECONDARY BUS NUMBER and SUBORDINATE BUS NUMBER registers of its P2P bridges to determine if the configuration cycle is meant for the Primary PCI or one of the IICH’s PCI Express ports. Figure 13-2. NSI Type 0 Configuration Address Translation CONFIG_ADDRESS 31 2 4 23 1 6 15 1 1 10 8 7 2 1 0

1 Reserved 0 Device Number Function Register Number x x

NSI Type 0 Configuration Address Extension 31 28 27 24 23 1 6 15 1 1 10 8 7 2 1 0 Reserved Device Number Function Register Number 0 0

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13.3.4 IMCH PCI Express Bus Configuration Mechanism

From the configuration perspective, the PCI Express ports are seen as PCI bus interfaces residing on a Secondary Bus side of the “virtual” PCI-to-PCI bridges referred to as the IMCH Host-PCI Express bridge. On the Primary bus side, the “virtual” PCI-to- PCI bridge is attached to PCI Bus #0. Therefore the PRIMARY BUS NUMBER register is hardwired to “0”. The “virtual” PCI-PCI bridge entity converts Type #1 PCI Bus Configuration cycles on PCI Bus #0 into Type 0 or Type 1 configuration cycles on the PCI Express interfaces. Type 1 configuration cycles on PCI Bus #0 that have a BUS NUMBER that matches the SECONDARY BUS NUMBER of one of the IMCH’s “virtual” P2P bridges are translated into Type 0 configuration cycles on the appropriate PCI Express interface. The address bits are mapped as described in Figure 13-3. If the Bus Number is non-zero, greater than the value programmed into the SECONDARY BUS NUMBER register, and less than or equal to the value programmed into the corresponding SUBORDINATE BUS NUMBER register the configuration cycle is targeting a PCI bus downstream of the targeted PCI Express interface. The IMCH will generate a Type 1 configuration cycle on the appropriate PCI Express interface. The address bits are mapped as described in Figure 13-4. To prepare for mapping of the configuration cycles on PCI Express the initialization software will go through the following sequence: Scan all devices residing on the PCI Bus #0 using Type 0 configuration accesses. For every device residing at bus #0 which implements PCI-to-PCI bridge functionality, it will configure the secondary bus of the bridge with the appropriate number and scan further down the hierarchy. This process will include the configuration of the “virtual” PCI-to-PCI bridges within the IMCH used to map the PCI Express device’s address spaces in a software specific manner. Figure 13-3. NSI Type 1 Configuration Address Translation CONFIG_ADDRESS 31 2 4 23 1 6 15 11 10 8 7 2 1 0

1 Reserved Bus Number Device Number Function Register Number x x

NSI Type 1 Configuration Address Extension 31 28 27 24 23 1 6 15 11 10 8 7 2 1 0 Reserved Bus Number Device Number Function Register Number 0 1 Figure 13-4. Mechanism #1 Type 1 Configuration Address to PCI Address Mapping

1 Reserved Bus Number Device Number Function Number

Reg. Index X X 201 CONFIG_ADDRESS 1 0 Bus Number Device Number Function Number 3130 24 10 11151623 8 7 Reg. Index 0 1 201 PCI Address AD(31:0)

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13.3.5 IMCH Configuration Cycle Flow Chart

Figure 13-5. IMCH Configuration Flow Chart DW I/O Write to Config_Addr SS with Bit 31=1 I/O Read/Write to CONFIG_DATA BUS#=0 DEVICE#=0BUS#= Secondary Bus in IMCH Dev#2 BUS#= Secondary Bus in IMCH Dev#3 Yes Yes IMCH generates Type 0 Access to PEA0 No No No No Yes IMCH generates Type 0 Access to PEA1 Yes Yes No Yes No IMCH claims if Function=0 and device 1 is enabled IMCH claims if Function=0 and device 2 is enabled IMCH claims if Function=0 and device 3 is enabled IMCH generates NSI Type 0 Configuration Cycle No Access through memory aperture BUS# >Sec Bus BUS# <=Sub Bus in IMCH Dev#2 Yes IMCH generates Type 1 Access to PEA0 No Yes IMCH generates Type 1 Access to PEA1 BUS# >Sec Bus BUS# <=Sub Bus in IMCH Dev#3 IMCH generates NSI Type 1 Configuration Cycle No DEVICE#=1 DEVICE#=2 DEVICE#=3 DEVICE#=4 IMCH claims if Function=0, or 1 and that function is enabled BUS#= Secondary Bus in IMCH Dev#4 No IMCH generates Type 0 Access to PCI-to-PCI Bridge Yes Note: This path will never be taken since no bridge will ever be beneath the PCI-to-PCI Bridge. IMCH claims if Function=0 and device 4 is enabledYes No BUS# >Sec Bus BUS# <=Sub Bus in IMCH Dev#4 No IMCH generates Type 1 Access to PCI-to-PCI Bridge Yes

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13.4 IMCH Register Introduction

The IMCH contains two sets of software accessible registers, accessed via the IA-32 core I/O address space: control registers I/O mapped into the IA-32 core I/O space, which control access to PCI configuration space, and internal configuration registers residing within the IMCH, which are partitioned into multiple logical device register sets (“logical” since they reside within a single physical device). The IMCH internal registers (I/O Mapped and Configuration registers) are accessible by the IA-32 core. The registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities, with the exception of CONFIG_ADDRESS, which can only be accessed as a Dword. All multi-byte numeric fields use “little-endian” ordering (i.e., lower addresses contain the least significant parts of the field). Note: Irrespective of the access mechanism used (I/O register mechanism, or memory- mapped mechanism), the IMCH ONLY supports 1-4 byte accesses into configuration space. Software must (if necessary) take steps to prevent use of opcodes that would treat configuration space destinations as objects greater than a single Dword (32 bits) in size. Such attempted usage will result in spurious behavior up to and including hanging the platform. Some of the IMCH registers described in this section contain reserved bits which are labeled “Reserved”. Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note the software does not need to perform read, merge, write operation for the configuration address register. In addition to reserved bits within a register, the IMCH contains address locations in the configuration space of the Host-NSI Bridge entity that are marked either “Reserved” or “Intel Reserved”. The IMCH responds to accesses to “Reserved” address locations by completing the host cycle. When a “Reserved” register location is read, a zero value is returned. (“Reserved” registers can be 8-, 16-, or 32-bit in size). Write operations to “Reserved” registers have no effect on the IMCH. Registers that are marked as “Intel Reserved” must not be modified by system software. Writes to “Intel Reserved” registers may cause system failure. Reads to “Intel Reserved” registers may return a non-zero value. Upon a Reset, CMI sets its entire internal configuration registers to predetermined default states. At reset, some register values are determined by external strapping options. A register’s default value represents the minimum functionality feature set required to successfully bring up the system. It is the responsibility of the system initialization software (usually the BIOS) to properly determine the DRAM configurations, operating parameters and optional system features that are applicable, and to program CMI registers accordingly.

13.5 IMCH Sticky Registers

Certain registers in the IMCH are sticky through a hard-reset. They will only be reset on a Power-good reset. In general, these registers are the error logging registers and a few special cases. The error command registers are not sticky, so that on reset bogus errors are not reported and that errors are not reported through a mechanism that hasn’t been set up in code yet. Only those registers that are explicitly marked as “Sticky: YES” are sticky. Those not marked or those marked as NO are not sticky. The following registers are sticky:

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Device 0, Function 0: Critical DRAM control registers, a portion of DRC, DRT clock gearing and clock disable registers
Device 0, Function 0: ECO sticky register
Device 0, Function 0, Bar 14: BIOS notepad sticky register
Device 0, Function 1: error information registers (Not the command registers)
Device 2, Function 0: error information registers (Not the command registers)
Device 3, Function 0: error information registers (Not the command registers)
Device 8, Function 0: PILOT control registers
Device 8 Function 0: Power On Configuration bits

13.6 IMCH I/O Mapped Registers

The IMCH contains two registers that reside in the IA-32 core I/O address space − the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window.

13.6.0.1 Offset 0CF8h: CONFIG_ADDRESS - Configuration Address Register

CONFIG_ADDRESS is a 32-bit register that can be accessed only as a Dword. A Byte or Word reference will “pass through” the Configuration Address Register and NSI onto the IICH as an I/O cycle. The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended. Table 13-2. Summary of IMCH PCI Configuration Registers Mapped in I/O Space Offset Start Offset End Register ID - Description Default Value 0CF8h 0CF8h “Offset 0CF8h: CONFIG_ADDRESS: Configuration Address Register” on page 354 00000000h 0CFCh 0CFCh “Offset 0CFCh: CONFIG_DATA: Configuration Data Register” on page 355 00000000h Table 13-3. Offset 0CF8h: CONFIG_ADDRESS: Configuration Address Register (Sheet 1 of Description: View: IA F Base Address: 0000h (IO) Offset Start: Offset End: 0CF8h 0CF8h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

31 CFGE

Configuration Enable. 0 = Accesses to PCI configuration space are disabled. 1 = Accesses to PCI configuration space are enabled. 0h RW 30 :24 Reserved Reserved. These bits are read only and have a value of 0. 0h RO 23 :16 Bus_Number Contains the bus number being targeted by the configuration cycle. 0h RW

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13.6.0.2 Offset 0CFCh: CONFIG_DATA - Configuration Data Register

CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of configuration space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS.

13.7 IMCH Memory Mapped Registers

Certain DRAM compensation control, EDMA control/status registers, NSI control/status and PCI Express will reside in memory mapped space instead of configuration space. These memory mapped address regions are setup through base address registers and capability pointers, which will reside in configuration address space. These registers are documented in the configuration register chapter. These base address registers follow the standard definition as found in the PCI Express Specification. These memory mapped register regions must not be marked as WC (Write-Combining), as all accesses to the registers within these regions are limited to Dword access, and write-combining is not allowed. Further, these registers must not be accessed utilizing IA-32 core operations with a data operand size greater than 32-bits, as such access is strictly unsupported by the IMCH. 15 :11 Device_Number Selects one of the 32 possible devices per bus. 0h RW 10 :08 Function_Numb er Selects one of eight possible functions within a device. 0h RW 07 :02 Register_Numb er This field selects one register within the particular Bus, Device, and Function as specified by the other fields in the Configuration Address Register. This field is mapped to A[07:02] during NSI or PCI Express Configuration cycles. 0h RW 01 :00 Reserved Reserved 0h Table 13-3. Offset 0CF8h: CONFIG_ADDRESS: Configuration Address Register (Sheet 2 of Description: View: IA F Base Address: 0000h (IO) Offset Start: Offset End: 0CF8h 0CF8h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Table 13-4. Offset 0CFCh: CONFIG_D ATA: Configuration Data Register Description: View: IA F Base Address: 0000h (IO) Offset Start: Offset End: 0CFCh 0CFCh Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 :00 CDW Configuration Data Window. If bit 31 of CONFIG_ADDRESS is one any I/O access to the CONFIG_DATA register is mapped to configuration space using the contents of CONFIG_ADDRESS. 0h RW

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13.8 PCI Express Enhanced Configuration Mechanisms

PCI Express extends the configuration space to 4096 bytes per device/function as compared to 256 bytes allowed by PCI 2.2 configuration space. PCI Express configuration space is divided into a PCI 2.2 compatible region, which consists of the first 256 B of a logical device’s configuration space and an extended PCI Express region which consists of the remaining configuration space. The PCI 2.2 compatible region can be accessed using either the mechanisms defined in the PCI 2.2 or using the enhanced PCI Express configuration access mechanism. All changes made using either access mechanism are equivalent; however, software is not allowed to interleave PCI Express and PCI access mechanisms to access the configuration registers of devices. The extended PCI Express region can only be accessed using the enhanced PCI Express configuration access mechanism.

13.8.1 PCI Express Configuration Transaction Header

The PCI Express Configuration Transaction Header includes an additional four bits for the Register Number field (ExtendedRegisterAddress[3:0]) to provide additional configuration space. The PCI 2.2 compatible configuration access mechanism uses the same Request format as the enhanced PCI Express mechanism. For PCI compatible Configuration Requests, the Extended Register Address field must be all zeros. To maintain compatibility with PCI configuration addressing mechanisms, system software must access the enhanced configuration space using Dword operations (Dword-aligned) only

13.8.2 Enhanced Configuratio n Hardware Implications

The IMCH must translate the memory-mapped extended enhanced PCI Express configuration access cycles from the host processor to PCI Express configuration cycles. Devices are required to respond to an additional four bits for decoding configuration register access. Devices must decode the ExtendedRegisterAddress[3:0] field of the Configuration Request Header. This field is used in conjunction with the Register Number to specify the Dword address of the register being accessed. A PCI Express device must be able to operate with basic required functionality in a legacy environment without requiring access to any extended PCI Express configuration. Figure 13-6. PCI Express Configuration Transaction Header B4494-01 Fmt X 0 Type 765 21043 765 21043 TC 0 0 0 765 21043 Reserved 65 21043 Length 0 0 0 0 0 0 0 0 0 0 1 1st DW BE +1 +2 +3 Reserved Ext. Reg. AddressBus Number Device Number Function Number Requester ID Tag Register Number R R T D E P Attr 0 0 R Last DW BE 0 0 0 0 R

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13.8.3 Enhanced Configuration Memory Address Map

The Enhanced Configuration Memory Address Map is positioned into CMI memory space by use of the PCI Express Enhanced Configuration Base register known as HECBASE. This register contains the address that corresponds to bits 31 to 28 of the base address for PCI Express enhanced configuration space below 4 GB. Configuration software will read this register to determine where the 256 Mbyte range of memory addresses resides for enhanced configuration. This register defaults to a value of E, which corresponds to E000 0000 for the IMCH. It is not intended that this value is ever changed by BIOS.

13.8.4 Enhanced Configuration FSB Address Format

Table 13-5 presents the enhanced configuration address format for the front side bus. Note that bits 31:28 of Table 13-5 correspond to the default value of HECBASE. § § Figure 13-7. Enhanced Configuration Memory Address Map B4495-01 Bus 255 0xFFFFFFFF Bus 1 Bus 0 0x1FFFFF 0xFFFFF 0xFFFFF 0x7FFF 0x1FFF Device 0 Function 0 Device 0 Function 0 Device 0 Function 10xFFFFF Device 0 Function 0 Located by PCI Express base address (HECBASE) Table 13-5. Enhanced Configuration FSB Address Format Bits Description 35:32 0h 31:28 Eh 27:20 Bus Number 19:15 Device Number 14:12 Function Number 11:00 Register Offset

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14.0 RAS Features and Exception Handling

CMI is designed to bring enterprise level reliability, availability, serviceability, usability, and manageability (RASUM) to the embedded platform.

14.1 RAS Features

14.1.1 Data Protection

Due to the nature of having various data protection schemes on the different interfaces (ECC, parity, and CRC) it is necessary to be able to convert between them when transferring data internally. To accomplish this, protection of internal data is done with parity.

14.1.1.1 DRAM ECC

The DRAM interface uses a standard SEC/DED ECC across a 64-bit data quantity.

14.1.1.2 PCI Express Interface

These high-speed serial interfaces have traditional CRC protection. The data packets utilize a 32-bit CRC protection scheme, specifically the same CRC-32 used by Ethernet - 0x04C11DB7. The smaller and less error-prone link packets utilize a 16-bit CRC scheme. Since packets utilize 8B/10B encoding and not all encodings are used, this provides further data protection because illegal codes can be detected. Also, if errors are detected on the reception of data packets due to various transients, these data packets can be retransmitted. Hardware logic supports this link-level retry without software intervention.

14.1.1.3 Data Error Propagation Between Interfaces/Units

Due to the nature of having various data protection schemes; ECC, parity, and CRC - it is necessary to be able to convert between the separate schemes. Beyond this requirement, it is necessary to indicate whether or not incoming data is corrupted. Also, it is useful to know when internal data has been corrupted during transit. To accomplish this, the IMCH uses parity to protect internal data. This requires units to add two parity bits for each 64 bits of data path width. Data received by a unit from outside the chip creates two parity bits to travel with the data, one provides parity on the upper 32 bits, and the other provides parity on the lower 32 bits. If either of the 32-bit halves is required to be poisoned, both halves are poisoned. This provides the user of the data a mechanism to recognize when a bit was flipped in transit by detecting when only one of the parity bits is bad. The user will flag this error condition as well as mark both halves bad. This covers both cases of the data starting out as either good or bad. If it started out as good, but a bit was flipped, it is indeed corrupted and must be marked as such. In the case where it started out as bad, and a bit was flipped, it is still corrupted, although probably a different data value than its starting value. This scheme works when all quantities being passed are 64 bits or greater. If a data path must be padded, it must be padded with zeroes. Even parity will be used for

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this scheme; meaning that the total number of asserted bits including the parity bits is an even number of bits. This parity protection scheme applies to different interfaces on the chip hence the name: “Chip Two Bit Parity” or CTB parity. Note: Due to EDMA byte realignment and parity manipulation, a single CTB parity bit error observed by the EDMA unit may poison either 2 or 4 DWords depending on the resultant alignment. Refer to the EDMA chapter for more details.

14.1.2 DRAM Data Integrity

14.1.2.1 Periodic Memory Scrubbing

When enabled a special DRAM memory scrubbing unit will walk through all DRAM, on a periodic basis, doing reads. Correctable errors found by the read are corrected and then the good data written back to DRAM. A write is only performed when a single bit error has been detected and is correctable, except when an incoming write to the same memory address is detected. In this case the scrub write is dropped and the scrub counter is advanced since this location is already being written. These transactions are treated as non-coherent, since these addresses are not placed on the FSB. The scrub unit starts at an address than can be programmed and counts to 0. The scrub rate is also programmable so using this method, a 4 GB system can be completely scrubbed in less than a day. The cumulative effect of these scrub writes do not cause any noticeable degradation to memory bandwidth, although they will cause a greater latency for that one very infrequent read that is delayed due to the scrub write cycle.

14.1.2.2 DRAM Hardware Initialization

Hardware will be used to initialize main memory under the direction of BIOS. Once BIOS has programmed the IMCH with the DIMM profile, and has configured and calibrated the IMCH and populated DIMMs, it can utilize the MBIST CSRs to initialize and/or test populated memory. The initialization of MBISTCSR will traverse the target range of memory addresses as rapidly as possible, providing an order of magnitude performance improvement over IA-32 core-generated initialization or test. The MBIST engine can be configured to choose values other than zero. The eight fixed hex data values selectable are alternating pairs of 0/F, A/5, 3/C, or 6/9. Alternate modes are provided in which LFSR random data may be used, or software explicitly specifies the full pattern of bits to be written in a collection of MBIST DATA registers with or without a shift after every write. In all cases of pattern based initialization and test, the MBIST function does NOT calculate ECC on the fixed pattern or programmed value to be written across the target address range. Rather, the fixed pattern is extended to cover the data devices as well as the ECC devices in the target DIMM, and a strict bit-wise comparison is utilized to determine whether read-back verification passes or fails. Once all desired testing has been completed, WHQL requirements dictate that memory be completely initialized to “0” prior to transferring control to the operating system. To accomplish this, BIOS must clear all the MBISTDATA registers and utilize the explicit pattern mode of MBIST. It is possible to initialize memory a rank at a time, or en- masse, at the discretion of BIOS.

14.1.2.3 Uncorrectable Retries

The memory controller will not support uncorrectable retries.

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14.1.2.4 DRAM Refresh

As with any DRAM device, the storage element is inherently leaky, and must be recharged periodically to avoid loss of data integrity. Circuitry in the memory subsystem will ensure that refresh cycles occur in a periodic fashion across all active DIMMS to meet the specific DRAM requirements.

14.1.2.5 DDR I/O Hardware Assisted Calibration

To determine read capture timing, hardware assisted calibration logic writes a pattern into memory and then reads the data back with different hardware settings until the optimum timing is found. Such calibration is described in the initialization walk-through provided in the clocking and reset chapter of this document. Hardware provides the capability to tune receive-enable timing, DQS centering within the received data eye (both vertical and horizontal), output drive strength, and receive termination.

14.1.3 PCI Express Data Integrity

The PCI Express interfaces will incorporate several features to make this interface as robust as possible without software intervention.

14.1.3.1 PCI Express Training

To establish a connection between PCI Express endpoints, they both participate in a sequence of steps known as training. This sequence will establish the operational width of the link as well as adjust skews of the various lanes within a link so that the data sample points can correctly take a data sample off of the link. The x4 link pairs capable of collapsing to x8 will first attempt to train independently, and will collapse to a single link at the x8 width upon detection of a single device returning link ID information upstream. Once the number of links has been established, they will negotiate to train at the highest common width, and will step down in its supported link widths in order to succeed in training. The ultimate result may be that the link has trained as a X1 link. Although the bandwidth of this link size is substantially lower than a X8 link or even a X4 link, it will allow communication between the two devices. Software will then be able to interrogate the device at the other end of the link to determine why it failed to train at a higher width, something that would not be possible without support for the X1 link width. It should be noted that width negotiation is only done during training or retraining, but not recovery.

14.1.3.2 PCI Express Retry

The PCI Express interface incorporates a link level retry mechanism. The hardware detects when a transmission packet is corrupted and a retry of that particular packet and all following packets will be performed. Although this will cause a temporary interruption in the delivery of packets, it does so in order to maintain the link integrity.

14.1.3.3 PCI Express Recovery

When numerous errors occur, the hardware may determine that the quality of the connection is in question, and the end points can enter a quick training sequence known as recovery. The width of the connection will not be renegotiated, but the adjustment of skew between lanes of the link may occur. This occurs without any software intervention, but the software may be notified.

14.1.3.4 PCI Express Retrain

If the hardware is unable to perform a successful recovery then the link will automatically revert to the polling state, and initiate a full retraining sequence. This is a drastic event with an implicit reset to the downstream device and all subordinate

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devices, and is logged by the IMCH as a “Link Down” error. If escalation of this event is enabled, software is notified of the link DL_DOWN condition. Once software has to be involved, then data will likely be lost, and processes need to be restarted, but this is still preferred to having to shut the system down, or go offline for an extended period of time.

14.1.4 Test/Support Major Buses

14.1.4.1 IICH XOR

The IICH supports XOR chain test mode. This non-functional test mode is a dedicated test mode when the chip is not operating in its normal manner.

14.1.4.2 SMB (IMCH)

Full access to internal configuration registers via the System Management Bus is supported. This will allow a server management card to control system configuration and to read various error/status information. Accesses to devices marked as not present will still be possible through SMB.

14.1.4.3 SMB (IICH)

The IICH SMB is SMBus 2.0 compliant and it is compatible with most 2-wire components that are also I2C compatible. The host interface allows IA-32 core to communicate via SMBus, the slave interface allows external microcontroller to access system resource in IICH. This IICH SMB does not support access to internal configuration registers.

14.1.4.4 I 2C

Access to the external DIMMs will be through the IICH, via I2C. This will be used to determine the nature of the DIMMs present in order to configure the memory subsystem correctly.

14.2 Exception Handling

There are a variety of exception conditions. Some are internally detected; some are detected on input pins; some are passed on behalf of other devices. All recognized exceptions eventually cause the IMCH to do one of the following: Send a SERR message, send a SCI message to the IICH, send a SMI message to the IICH, assert MCERR# on the front side bus, or do nothing. There is no determination of which errors go to which of the three error message schemes; it merely provides the capability for all combinations. It is the responsibility of the BIOS to determine the ultimate error reporting scheme. There will be an attempt to classify errors to whether they are fatal or non-fatal to more closely match the enterprise error presentation.

14.2.1 FERR/NERR Global Register Scheme

The Global FERR register consists of three fields. The first or fatal field has 14b indicates the first signaled fatal global error from 14 different units. The second or non- fatal field indicates the first non-fatal global error that occurs from the same 14 different units. A non-fatal error may be either correctable or uncorrectable, but not Figure 14-1. Global FERR/NERR Register Representation Fatal (14b) Non-Fatal (14b) Reserved (4b)

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 363 Intel® EP80579 Integrated Processor fatal. These two fields usually have at most one bit asserted in each field. In the event of simultaneous errors occurring in the same core clock, more than one bit in a field may be set. The third 4-bit field is reserved for future enhancements. The Global NERR register consists of these same three fields with slightly different functionality. Instead of just the first fatal or non-fatal global errors recorded, this register indicates the second, third, fourth, etc. global errors that are reported by the IMCH. These two registers do not indicate what the error was, they just indicate the severity of the error and what unit has more specific error information.

14.2.1.1 FERR/NERR Unit Registers

Each major unit will have a minimum of a pair of registers, known as the first error (FERR) and next error (NERR). Each unit has different and specific error bit definitions, and provides the specific type of error; information that is not found in the global registers. It is important to note that the unit FERR/NERR registers are simpler than the global for purposes of reuse and ease of implementation. While the global FERR register has a fatal and a non-fatal field, which lock down separately, the unit FERR register only has one field. The unit is however still required to send out separate fatal and non-fatal indications to the global FERR register if they detect both classifications of errors. Some units will support only one type. A unit that doesn’t detect errors would not support either type.

14.2.1.2 Clearing FERR/NERR Registers

The following write-up is the recommended guideline to minimize the loss of errors information. For a given FERR/NERR register pair, the FERR is read and then cleared first, and followed by the NERR. This sequence is true for either the global FERR/NERR register pair or any given unit. Any errors occurring after the FERR is cleared will then cause the FERR to have a non-zero value. After the global FERR/NERR register pair is cleared, the unit FERR/NERR register pairs are interrogated, but only those indicated by the global FERR/NERR registers. Once the unit pair has been cleared, the unit FERR can be read again to ensure that no errors occurred during this local unit sequence. After the first unit FERR/NERR register pair has been serviced, this same sequence is performed for all other unit FERR/NERR register pairs that indicated errors in the global FERR/NERR registers. Once all unit error registers have been serviced, the final step is to read the global FERR register to determine if all system errors have been serviced. It is possible that errors could have occurred for a particular unit after that unit was serviced during the error routine, or that a unit had errors after the reading of the global FERR/NERR registers. When clearing errors, software must clear all the FERR/NERR bits in the local interface registers before clearing the global FERR/NERR registers. If the local registers are not cleared first, then the global FERR/NERR registers will latch the same error again as soon as they are cleared. This implementation allows software to clear the local FERR/ NERR registers, and then go clear the global FERR/NERR. S/W then reads back the global FERR/NERR and if it is non-zero, then a new error has occurred. If the global FERR/NERR has no bits set, then there are no more system errors.

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14.2.1.3 FERR/NERR Unit Specific

Each unit has different and specific error bit definitions.

14.2.1.4 SERR/SMI/SCI Enabling Registers

Each error reported has a full matrix of direction as to what error message it generates. For each unit FERR/NERR pair there are three more registers that enable each error for one of the three specific error messages. The logic does not appear to preclude the generation of all three messages for a single error, but this would not be a recommended configuration, and this needs to be looked into further. SERR stands for system error and is for reporting address and data parity errors, or any other catastrophic system error. SCI stands for system control interrupt and is a shareable interrupt used to notify the OS of ACPI events. SMI stands for System Management Interrupt and is an OS-transparent interrupt generated by events on legacy systems. Figure 14-2. FERR/NERR Service Routine Read Global FERR & snapshot Error Irpt/Msg Clear Global FERR always always Read Global NERR & snapshot always Read Local FERR always Clear Local FERR elseif error type has support registers Clear Global NERR always Read Local NERR Clear Local NERR always Read Support Registers always elseRead Support Registers else if error type has support registers Read Global FERR always If no local errors indicated NOTE: The local reads must be performed for the next unit, if any, indicated in the FERR/NERR snapshot taken EXIT If no errors Service Routine [Unit] Service Routine [Global] else

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14.2.1.5 MCERR Enabling Registers

An additional entry to the matrix of error signaling paths is the MCERR (machine check error) enabling register. In addition to the SERR, SMI, and SCI enabling registers, the MCERR enabling register allows the occurrence of an error to result in the MCERR# signal to be asserted on the front side bus. Machine check error is asserted to indicate an unrecoverable error, which is not a bus protocol violation.

14.2.1.6 Error Escalation Register

Since all error bits in the error registers are fully configurable, meaning that a given error can be configured to go to any of the four messaging methods, no global error escalation mechanism is required. Although, the errors occurrence is accumulated in the global FERR/NERR registers, all error messaging is initiated from the units themselves, and not from a central location.

14.2.1.7 Error Masking

A new feature being added for CMI is the concept of an error masking register. Each unit has a mask register, which blocks the recognition/logging/reporting of each specific error type. Since the error will not be recognized when the corresponding mask bit is set, no error messages can be generated. This feature allows intelligent software to ignore specific error types during critical areas of code, where it does not want to be informed of errors that it will create, without ignoring other error types that it doesn’t expect to happen. These mask bits will default to unmasked, and must be set by software or BIOS to take effect.

14.2.1.7.1 Locking DRAM Address and Syndrome on Errors

The first pair of error logging registers for CE (correctable errors) DRAM_SECF_ADD and DRAM_SECF_SYNDROME are locked when bit 0 of the DRAM_FERR is set. The second pair of error logging registers for CE (correctable errors) DRAM_SECN_ADD and DRAM_SECN_SYNDROME are locked when bit 0 of the DRAM_NERR is set. These pairs of two registers will retain their value even if new CE’s are found. This allows the first (and possibly next) error to be captured and held instead of retaining the last. Corrected data errors as a result of either demand reads or scrubber-initiated traffic will be reflected in these error registers. The logging register for UE (uncorrectable errors), DRAM_DED_ADD is locked when bit 1 of the DRAM_FERR or DRAM_NERR is set. This register holds the address of uncorrectable errors on data reads not initiated by the scrubber for either periodic or demand scrubbing. The logging register for Scrub detected errors, DRAM_SCRUB_ADD should be locked when bit 2 of the DRAM_FERR or DRAM_NERR is set. This register holds the address for scrubber-initiated transactions for either demand or periodic memory scrubbing. When the FERR/NERR registers are cleared the logging registers are free to update their contents until such time that either of these FERR/NERR registers again lock.

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14.2.1.8 PCI Express Errors and Errors on Behalf of PCI Express

IMCH-specific error detection, masking, and escalation mechanisms operate on a parallel path to their standardized counterparts included in the PCI Express* Interface Specification, Rev 1.0a. PCI Express errors are classified as either correctable or uncorrectable. Uncorrectable errors are further broken down as fatal or non-fatal. PCI Express specified correctable errors are logged in the Correctable Error Status Register (Device 2-3, Function 0, Offset 110 - 113h), unless they are masked by a corresponding bit in the Correctable Error Detect Mask Register (Device 2-3, Function 0, Offset 150-153h). PCI Express specified uncorrectable errors are logged in the Uncorrectable Error Status Register (Device 2-3, Function 0, Offset 104-107h), unless they are masked by a corresponding bit in the Uncorrectable Error Detect Mask Register (Device 2-3, Function 0, Offset 14C-14Fh). The Uncorrectable Error Severity Register (Device 2-3, Function 0, Offset 10C - 10Fh) determines if bits in the Uncorrectable Status register are treated as uncorrectable fatal or uncorrectable non-fatal errors. The Device Status register (6Eh) bits are set when the corresponding category of bit is set in the uncorrectable and correctable status registers. Reporting of non-masked error bits to the root complex hierarchy of PCI Express error registers is controlled on three different levels. Individual errors are masked for reporting by the Uncorrectable Error Mask (Device 2-3, Function 0, Offset 108-10Bh) and the Correctable Error Mask (Device 2-3, Function 0, Offset 114-117h) registers. Individual error category (fatal, non-fatal, correctable, or unsupported) reporting is enabled in the Device Control Register (Device 2-3, Function 0, Offset 6Ch) bits 3:0. Finally, uncorrectable error reporting (fatal or non-fatal) reporting may also be enabled by setting the SERR Enable bit in the PCI Command Register (Device 2-3, Function 0, Offset 04-05h). There is an error pointer, in the Advanced Error Capability and Control Register (Device 2-3, Function 0, Offset 118-11Bh) which will log the first uncorrectable error that is enabled for reporting. Also some uncorrectable errors, when they are the first uncorrectable error, will log their corresponding header log in the Header Log Registers (Device 2-3, Function 0, Offset 11C-12Bh). An error pointer for unmasked correctable errors has been added in the Error Do Command Register (Device 2-3, Function 0, Offset 148-14Bh). These internally detected errors when they are reported are referred to as virtual error messages. These are different from errors which are detected by the downstream device which then sends an error message to the root complex, which are referred to as externally detected or “received’ error messages. The received system error bit in the Secondary Status Register (Device 2-3, Function 0, Offset 1E-1F) is set when either fatal or non-fatal messages are received at the root complex. At this point in the PCI Express error hierarchy, these virtual error messages are logically ORed with the received error messages, and will just be referred to as fatal, non-fatal, or correctable error messages, no reference to either virtual or received. When enabled by the enable system error bit in the PCI Command Register, any fatal or non-fatal messages will set the signaled system error bit in the PCI Status register (Device 2-3, Function 0, Offset 06-07h). The Root Port Error Message Status Register (Device 2-3, Function 0, Offset 130-133h) will indicate first and multiple errors of each error message category, and the corresponding error source IDs of the first correctable and uncorrectable error messages will be the logged in the Error Source ID register (134h). These errors that have been reported to the root complex can now be reported to the system, via the category enables in the Root Port Error Command Register (Device 2-3, Function 0, Offset 12C-12Fh) for interrupts. These interrupts can be in the form of

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 367 Intel® EP80579 Integrated Processor legacy type interrupts if so enabled in the PCI command register and MSI is not enabled, or message signaled interrupts if so enabled in the MSI Capabilities register (Device 2-3, Function 0, Offset 5A-5Bh). The Root Port Control register (Device 2-3, Function 0, Offset 80-83h) enables errors to be reported to the system via other IMCH specific methods, again on a category basis. The Error Do Command register, selects between the four methods of system signaling, SERR, SCI, SMI, and MCERR. The error model outside of PCI Express includes a local FERR/NERR pair of registers in each unit and a global FERR/NERR pair of registers that indicates which unit had problems. The Local FERR/NERR register pair (Device 2-3, Function 0, Offset 160-163h & 164-167h) includes PCI Express defined errors and additional detected errors within the PCI Express unit. This register pair has three sets of error bits for the three categories of errors: the first set for received messages, the second set for internally detected errors (virtual messages need not have been generated), and unit specific errors outside of the PCI Express spec, and the third set for device errors. This error scheme sets FERR/NERR error bits regardless whether or not they were reported via interrupt or other signaling method. The signaling due to unit specific errors has its logic dependent on the PCI Express Unit Error Register (Device 2-3, Function 0, Offset 140-143h). The errors flagged in this register must be cleared before exiting the error service routine. The signaling due to received messages has its logic dependent on the Root Error Message Status register (Device 2-3, Function 0, Offset 130-133h). The Root Error Status register must be cleared before exiting the error service routine. The signaling due to internally detected PCI Express errors has its logic dependent on the Device Status register (Device 2-3, Function 0, Offset 6E-6Fh). The Device Status register must be cleared before exiting the error service routine. Software must clear the global FERR first, and then the global NERR. Software then clears the local FERR register and the local NERR register of each unit in that order. After clearing FERR and then clearing NERR, the local FERR must be read to make sure that remains ‘0’ indicating no more errors have occurred during the clearing of these registers. After all units’ FERR & NERR registers have been cleared, the global FERR is again read to ensure that no additional errors occurred during the clearing sequence. Since the PCI Express units have more hierarchy than other units, more registers must be cleared other than just the local FERR and NERR registers. After clearing the local FERR & NERR, one must also clear the Root Error Status, Unit Error Status, Device Status, Uncorrectable Error Status, and Correctable Error Status registers. One only needs to clear the PCI Status and Secondary Status registers if these are being utilized in a given particular error model. No logic depends on the state of any of these status bits. If not utilized, they can be ignored. If a PCI Express error handler is used, with no knowledge of the FERR/NERR registers, then clear the PCI Express specific registers: Device Status, Uncorrectable Error Status, Correctable Error Status, and Root Error Status. The IMCH specific unit errors would not be enabled for reporting errors. Figure 14-3 helps to illustrate the relationship of the error registers from the PCI Express* Specification.

14.2.1.9 Configurable Error Containment at the Legacy Interface

Depending on the I/O devices in use, data errors could have catastrophic effects when allowed to propagate. The Legacy interface has the configurability of allowing the poisoning and propagation of data errors or to stop the data from transferring at all and escalate the data errors to the system. This is extreme behavior, which can be enabled or disabled, in order to prevent data corruption on a critical device, and is referred to as “stop and scream”. Refer to the Error Injection section for more details.

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14.3 Error Conditions Signaled

The IICH-notification action taken by the IMCH upon detection of an error is controlled through three registers. The SERRCMD register enables the generation of the SERR message, the SCICMD register enables the generation of the SCI message, and the SMICMD register enables the generation of SMI messages. Special cycle types of DO_SERR, DO_SCI, or DO_SMI may be transmitted to the IICH. The IICH receives the exception notification from the IMCH and may be configured to notify the processor of the condition. Once the processor has been interrupted, it polls the system to determine the cause of the exception. If the IMCH initiated the exception condition by sending a message over NSI, then the processor is so informed by the IICH. At this point, the processor may read the IMCH’s error status registers to determine the exact cause of the condition. The processor explicitly clears the status bit that points to the exception condition. The IMCH in addition to signaling errors to the IICH for further handling, has added the capability of signaling the processor directly by use of the front side bus error signal MCERR#. The processor, upon observing this signal active, enters into special error handling code known as machine check code. Figure 14-3. PCI Express Error Handling Uncorrectable Error Mask EXP_UNCERRMSK Correctable Error Status EXP_CORERRSTS Correctable Error Mask EXP_CORERRMSK Uncorrectable Severity EXP_UNCERRSEV Enable SysERR Mask on a per bit basis NF Fatal Message Uncorrectable Errors Correctable Errors Correctable Message Non-fatal Message Virtual Fatal Message C F Device Status EXP_ DEVSTS Device Control EXP_ DEVCTL PCICMD[8] Mask on a per bit basis Virtual Correctable Message Virtual Non-fatal Message Adv. Error Capability & Control EXP_AERCACR Header Log Register EXP_HDRLOG[3:0] Uncorrectable Error Status EXP_UNCERRSTS Uncorrectable Error Detect Mask EXP_UNCERRDMSK Correctable Error Detect Mask EXP_CORERRDMSK Uncorrectable Severity EXP_UNCERRSEV All UNCs F NF C C NF F Root Error Status EXP_RPERRMSTS Error Source ID EXP_ERRSID REPORT SELECT EXP_ERRDOCMD MCERR SCI SMI MSI INTx 1st Error Indicators 1st Error Source IDs IMCH specific registers in dark grey SERR Correctable Error Ptr EXP_ERRDOCMD NFM FM UR BCTRL[1]SERRE Virtual & Recieved Message Logic SEC_STS[14]RSE All UNCs Unsupport Request UR [3] PCISTS[14]SSE FN F C UNCs w/o UR MSICAPA [0] MSI enable Root Error Cmd EXP_RPERRCMD Irpt Enable per type Root Control EXP_RPCTL report enable Root Error Cmd EXP_RPERRCMD Irpt Enable per type

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 369 Intel® EP80579 Integrated Processor For each type of error detected in a given unit, there is a bit that corresponds to that error in the unit_FERR, unit_NERR, SERRCMD_unit, SMICMD_unit, SCICMD_unit, and MCERRCMD_unit registers. (Note that one and only one xCMD bit can be enabled per error type.) The first occurrence of an error type will be indicated by the bit assertion in the unit_FERR. If that error occurs again than the corresponding bit will be set in the unit_NERR register. When a bit is asserted in either the unit_FERR or unit_NERR, and if the corresponding enable bit is set in one of the named CMD registers, then an error signal will be asserted, corresponding to the name of the CMD register: DO_SERR, DO_SCI, DO_SMI, or DO_MCERR. The assertion of the DO_SERR signal also requires that the SERR enable in the PCICMD register is set. The assertion of the DO_SERR signal also causes the appropriate SERR signaled status bit to be set in the PCISTS register. Table 14-1. Pseudocode for EDMA Errors (Sheet 1 of 2) Condition Source Action Status The descriptor pointer in next descriptor address register is of incorrect type or range for EDMA channel 3. Internal DO_SERR and set PCISTS10[SSE] if (PCICMD10[SERRE]=1 AND EDMA_EMASK[7]=0 AND SERRCMD_EDMA[7]=1 AND R_EDGE{EDMA_FERR[31] OR EDMA_NERR[31]}); DO_SMI if EDMA_EMASK[7]=0 AND SMICMD_EDMA[7]=1 AND R_EDGE{EDMA_FERR[31] OR EDMA_NERR[31]}; DO_SCI if EDMA_EMASK[7]=0 AND SCICMD_EDMA[7]=1 AND R_EDGE{EDMA_FERR[31] OR EDMA_NERR[31]}; DO_MCERR if EDMA_EMASK[7]=0 AND MCERRCMD_EDMA[7]=1 AND R_EDGE{EDMA_FERR[31] OR EDMA_NERR[31]}; EDMA_FERR[31] The descriptor pointer in next descriptor address register is not aligned to eight double-word boundary for EDMA channel 3. Internal DO_SERR and set PCISTS10[SSE] if (PCICMD10[SERRE]=1 AND EDMA_EMASK[6]=0 AND SERRCMD_EDMA[6]=1 AND R_EDGE{EDMA_FERR[30] OR EDMA_NERR[30]}); DO_SMI if EDMA_EMASK[6]=0 AND SMICMD_EDMA[6]=1 AND R_EDGE{EDMA_FERR[30] OR EDMA_NERR[30]}; DO_SCI if EDMA_EMASK[6]=0 AND SCICMD_EDMA[6]=1 AND R_EDGE{EDMA_FERR[30] OR EDMA_NERR[30]}; DO_MCERR if EDMA_EMASK[6]=0 AND MCERRCMD_EDMA[6]=1 AND R_EDGE{EDMA_FERR[30] OR EDMA_NERR[30]}; EDMA_FERR[30] The source address does not comply with the source type or range for EDMA channel 3. Internal DO_SERR and set PCISTS10[SSE] if (PCICMD10[SERRE]=1 AND EDMA_EMASK[5]=0 AND SERRCMD_EDMA[5]=1 AND R_EDGE{EDMA_FERR[29] OR EDMA_NERR[29]}); DO_SMI if EDMA_EMASK[5]=0 AND SMICMD_EDMA[5]=1 AND R_EDGE{EDMA_FERR[29] OR EDMA_NERR[29]}; DO_SCI if EDMA_EMASK[5]=0 AND SCICMD_EDMA[5]=1 AND R_EDGE{EDMA_FERR[29] OR EDMA_NERR[29]}; DO_MCERR if EDMA_EMASK[5]=0 AND MCERRCMD_EDMA[5]=1 AND R_EDGE{EDMA_FERR[29] OR EDMA_NERR[29]}; EDMA_NERR[29] The source address is not aligned as specified by the source address bit for EDMA channel Internal DO_SERR and set PCISTS10[SSE] if (PCICMD10[SERRE]=1 AND EDMA_EMASK[4]=0 AND SERRCMD_EDMA[4]=1 AND R_EDGE{EDMA_FERR[28] OR EDMA_NERR[28]}); DO_SMI if EDMA_EMASK[4]=0 AND SMICMD_EDMA[4]=1 AND R_EDGE{EDMA_FERR[28] OR EDMA_NERR[28]}; DO_SCI if EDMA_EMASK[4]=0 AND SCICMD_EDMA[4]=1 AND R_EDGE{EDMA_FERR[28] OR EDMA_NERR[28]}; DO_MCERR if EDMA_EMASK[4]=0 AND MCERRCMD_EDMA[4]=1 AND R_EDGE{EDMA_FERR[28] OR EDMA_NERR[28]}; EDMA_FERR[28] The destination address does not comply with the destination type or range for EDMA channel 3. Internal DO_SERR and set PCISTS10[SSE] if (PCICMD10[SERRE]=1 AND EDMA_EMASK[3]=0 AND SERRCMD_EDMA[3]=1 AND R_EDGE{EDMA_FERR[27] OR EDMA_NERR[27]}); DO_SMI if EDMA_EMASK[3]=0 AND SMICMD_EDMA[3]=1 AND R_EDGE{EDMA_FERR[27] OR EDMA_NERR[27]}; DO_SCI if EDMA_EMASK[3]=0 AND SCICMD_EDMA[3]=1 AND R_EDGE{EDMA_FERR[27] OR EDMA_NERR[27]}; DO_MCERR if EDMA_EMASK[3]=0 AND MCERRCMD_EDMA[3]=1 AND R_EDGE{EDMA_FERR[27] OR EDMA_NERR[27]}; EDMA_FERR[27]

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§ § The destination address is not aligned as specified by the destination address bit for EDMA channel 3. Internal DO_SERR and set PCISTS10[SSE] if (PCICMD10[SERRE]=1 AND EDMA_EMASK[2]=0 AND SERRCMD_EDMA[2]=1 AND R_EDGE{EDMA_FERR[26] OR EDMA_NERR[26]}); DO_SMI if EDMA_EMASK[2]=0 AND SMICMD_EDMA[2]=1 AND R_EDGE{EDMA_FERR[26] OR EDMA_NERR[26]}; DO_SCI if EDMA_EMASK[2]=0 AND SCICMD_EDMA[2]=1 AND R_EDGE{EDMA_FERR[26] OR EDMA_NERR[26]}; DO_MCERR if EDMA_EMASK[2]=0 AND MCERRCMD_EDMA[2]=1 AND R_EDGE{EDMA_FERR[26] OR EDMA_NERR[26]}; EDMA_FERR[26] Data parity Error in reading source data from system memory for EDMA channel 3. Internal DO_SERR and set PCISTS10[SSE] if (PCICMD10[SERRE]=1 AND EDMA_EMASK[1]=0 AND SERRCMD_EDMA[1]=1 AND R_EDGE{EDMA_FERR[25] OR EDMA_NERR[25]}); DO_SMI if EDMA_EMASK[1]=0 AND SMICMD_EDMA[1]=1 AND R_EDGE{EDMA_FERR[25] OR EDMA_NERR[25]}; DO_SCI if EDMA_EMASK[1]=0 AND SCICMD_EDMA[1]=1 AND R_EDGE{EDMA_FERR[25] OR EDMA_NERR[25]}; DO_MCERR if EDMA_EMASK1]=0 AND MCERRCMD_EDMA1]=1 AND R_EDGE{EDMA_FERR[25] OR EDMA_NERR[25]}; EDMA_FERR[25] Received configuration write command when EDMA is in Normal Mode for EDMA channel 3. Internal DO_SERR and set PCISTS10[SSE] if (PCICMD10[SERRE]=1 AND EDMA_EMASK[0]=0 AND SERRCMD_EDMA[0]=1 AND R_EDGE{EDMA_FERR[24] OR EDMA_NERR[24]}); DO_SMI if EDMA_EMASK[0]=0 AND SMICMD_EDMA[0]=1 AND R_EDGE{EDMA_FERR[24] OR EDMA_NERR[24]}; DO_SCI if EDMA_EMASK[0]=0 AND SCICMD_EDMA[0]=1 AND R_EDGE{EDMA_FERR[24] OR EDMA_NERR[24]}; DO_MCERR if EDMA_EMASK[0]=0 AND MCERRCMD_EDMA[0]=1 AND R_EDGE{EDMA_FERR[24] OR EDMA_NERR[24]}; EDMA_FERR[24] EDMA channel 2 errors Internal Same bit functionality as bits 31:24 except these are for EDMA channel 2. (Use bits 23:16) EDMA channel 1 errors Internal Same bit functionality as bits 31:24 except these are for EDMA channel 1. (Use bits 15:8) EDMA channel 0 errors Internal Same bit functionality as bits 31:24 except these are for EDMA channel 0. (Use bits 7:0) Table 14-1. Pseudocode for EDMA Errors (Sheet 2 of 2) Condition Source Action Status

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15.0 Platform Management (IMCH)

This chapter provides an overview of the system management support provided by the IMCH. There are two primary management support features in the IMCH:

Integrated system management bus (SMBus) interface
Architectural support for platform power management Note: Material in this chapter is specific to the IMCH and does not apply to the IICH.

15.1 Integrated SMBus Interface

The IMCH provides a fully functional System Management Bus (SMBus) target interface, which provides direct access to all internal IMCH configuration register space. SMBus access is available to all internal configuration registers, regardless of whether or not the register in question is normally accessed via the memory-mapped mechanism or the standard configuration mechanism. This provides for highly flexible platform management architectures, particularly given a baseboard management controller (BMC) with an integrated network interface controller (NIC) function.

15.2 SMBus Target Architecture

The SMBus target integrated into the IMCH is compatible with the System Management Bus (SMBus) Specification, Version 2. A brief overview of the SMBus architecture is provided below for reference.

15.2.1 High Level Operation

The SMBus interface consists of two interface pins: a clock and serial data. Multiple initiator and target devices may be electrically present on the same pair of signals. Each target recognizes a start signaling semantic and recognizes its own seven-bit address to identify pertinent bus traffic. The IMCH address is hard-coded to 011_0000. The protocol allows for traffic to stop in “midsentence,” requiring all targets to tolerate and properly “clean up” in the event of an access sequence that is abandoned by the initiator prior to normal completion. The IMCH is compliant with this requirement. The protocol comprehends “wait states” on read and write operations, which the IMCH takes advantage of to keep the bus busy during internal configuration space accesses.

15.2.1.1 SMBus Register Summary

Table 15-1 provides a quick-reference summary of the SMBus target register space. These registers are part of the target itself and therefore not accessible by any other means other than the direct SMBus connection.

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Table 15-1 and Table 15-2 indicate the sequence of data as it is presented on the SMBus following the byte address of the IMCH itself. This is not necessarily to indicate any specific register stack or array implemented in the IMCH. The registers can take on different meanings depending on whether it is a configuration or memory-mapped access type. The command indicates how to interpret the registers. Refer to the System Management Bus (SMBus) Specification, Version 2 for interface protocol details. Table 15-1. SMBus Register Summary Symbol Full Name/Function CMD Command BYTCNT Byte Count ADDR3 Bus Number (Only lower five bits are utilized) ADDR2 Device/Function Number ADDR1 Extended Reg Number (Bits 03:00 - 4 k page extension) ADDR0 Register Number (offset into function space) DATA3 Data, fourth byte (31:24) DATA2 Data, third byte (23:16) DATA1 Data, second byte (15:08) DATA0 Data, first byte (07:00) STS Status, only for reads Table 15-2. SMBus Memory-Mapped Register Summary Symbol Full Name/Function CMD Command BYTCNT Byte Count ADDR3 Destination Memory (BAR Selection) ADDR2 Address Offset 23:16 (Filler-used to zero out register) ADDR1 Address Offset 15:08 (15:12 not used) ADDR0 Address Offset 07:00 (11:00 used for 4 K page) DATA3 Data, fourth byte (31:24) DATA2 Data, third byte (23:16) DATA1 Data, second byte (15:08) DATA0 Data, first byte (07:00) STS Status, only for reads Table 15-3. ADDR3 Memory Assignments ADDR3 Destination Memory Assignments 00_000000 NSI 00_000001 EDMA 00_001000 DDR2 All others Reserved

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15.2.1.2 Internal Register Access Mechanism

All SMBus accesses to the internal register space are initiated via a write to the CMD register. Any register writes received by the IMCH while a command is already in progress receive a NAK to prevent spurious operation. The master is no longer expected to poll the CMD register to prevent clobbering a command in progress prior to issuing further writes. The SMBus access is delayed by stretching the clock until such time that the data is delivered. Note that per the System Management Bus (SMBus) Specification, Version 2, this interval can not be longer than 25 ms. To set up an internal access, the four ADDR bytes are programmed, followed by a command indicator to execute a read or write. Depending on the type of access, these four bytes indicate either the Bus number, Device, Function, Extended Register Offset, and Register Offset; or the Memory-mapped region selected and the address within the region. The configuration type access utilizes the traditional bus number, device, function, and register offset; but also uses an extended register offset, which expands the addressable register space from 256B to 4 KB. The memory-mapped type access redefines these bytes to be a memory-mapped region selection byte and the memory address within the region. Table 15-2 and Table 15-3 show this information. FSB-initiated accesses to registers are serviced through the configuration ring. For these registers, it is perfectly legal for an SMBus access to be requested while an FSB- initiated access is already in progress. The IMCH supports “wait your turn” arbitration to resolve all collisions and overlaps, such that the access that reaches the configuration ring arbiter first is serviced first while the conflicting access is held off. An absolute tie at the arbiter is resolved in favor of the FSB. Note that SMBus accesses must be allowed to proceed even if the internal transaction handling hardware and one or more of the other external interfaces are hung or otherwise unresponsive.

15.2.1.3 SMBus Register Definitions

15.2.1.3.1 CMD – Command Register

When written, this Command Register indicates the type and size of transfer. All configuration accesses from the SMBus port are initiated by writing to this register. While a command is in progress, all future writes or reads are NACK’ed by the IMCH to avoid overwriting registers while in use. The two command size fields allow for more flexibility on how the data payload is transferred, both internally and externally. The begin and end bits support the breaking of the transaction up into smaller transfers, by defining the start and finish of an overall transfer. Table 15-4. Command (CMD) Register (Sheet 1 of 2) Bit Description Begin Transaction Indicator 0 = Current transaction is NOT the first of a read or write sequence. 1 = Current transaction is the first of a read or write sequence. On a single transaction sequence this bit is set along with the End Transaction Indicator. End Transition Indicator 0 = Current transaction is NOT the last of a read or write sequence. 1 = Current transaction is the last of a read or write sequence. On a single transaction sequence this bit is set along with the Begin Transaction Indicator. Address Mode: Indicates whether memory or configuration space is being accessed in this SMBus sequence. 0 = Memory Mapped Mode 1 = Configuration Register Mode

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15.2.1.3.2 BYTCNT – Byte Count Register

The byte count register indicates the number of bytes following the byte count register when performing a write or when setting up for a read. The byte count is also used when returning data to indicate the following number of bytes (including the status byte), which are returned prior to the data. Note that the byte count is only transmitted for block type accesses on SMBus. SMBus word or byte accesses do not use the byte count.

15.2.1.3.3 ADDR3 – Address Byte 3 Register

This register must be programmed with the Bus Number of the desired configuration register in the lower five bits for a configuration access. For a memory-mapped access this field selects which memory-map region is being accessed. There is no status bit to poll to see if a transfer is currently in progress, because by definition, if the transfer completed, the task is done. The clock stretch is used to guarantee the transfer is truly complete. The EP80579 does not support access to other logical bus numbers via the SMBus port. All registers “attached” to the configuration mechanism that the SMBus has access to, reside on logical bus#0. 04 Reserved - Set to 0. 03: 02 Internal Command Size: All accesses are naturally aligned to the access width. This field specifies the internal command to be issued by the SMBus slave logic to the IMCH core. 00 = Read Dword 01 = Write Byte 10 = Write Word 11 = Write Dword 01: 00 SMBus Command Size: This field specifies the SMBus command to be issued on the SMBus. This field is used as an indication of the length of the transfer so that the slave knows when to expect the PEC packet (if enabled). 00 = Byte 01 = Word 10 = Dword 11 = Reserved Table 15-4. Command (CMD) Register (Sheet 2 of 2) Bit Description Table 15-5. Byte Count Register Position Description 07:00 Byte Count: Number of bytes following the byte count for a transaction. Table 15-6. Address Byte 3 Register Position Configuration Register Mode De scription Memory Mapped Mode Description 07:05 Ignored. Memory map region to access. 00h = NSI 01h = EDMA 08h = DDR2 Others = Reserved 04:00 Bus Number: Must be zero: the SMBus port can only access devices on the IMCH and all devices are bus zero.

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15.2.1.3.4 ADDR2 – Address Byte 2 Register

This register must be programmed with the Device Number and Function Number of the desired configuration register if for a configuration type access, otherwise it must be set to zero.

15.2.1.3.5 ADDR1 – Address Byte 1 Register

This register must be programmed with the upper address bits for the register with the 4K region. Whether it is a configuration or memory-map type of access, only the lower bits are utilized, the upper four bits are ignored.

15.2.1.3.6 ADDR0 – Address Byte 0 Register

This register indicates the lower eight address bits for the register within the 4 K region, regardless of whether it is a configuration or memory-map type of access.

15.2.1.3.7 DATA – Data Register

This field is used to receive the read data or to provide the write data associated with the desired register. At the completion of a read command, this field contains the data retrieved from the selected register. All reads return an entire aligned Dword (32 bits) of data. The appropriate number of byte(s) of this 32-bit logical register must be written with the desired write data prior to issuing a write command. For a byte write only, bits 7:0 are used, for a Word write, only bits 15:0 are used, and for a Dword write, all 32 bits are used. Table 15-7. ADDR2 – Address Byte 2 Register Position Configuration Register Mode Description Memory Mapped Mode Description 07:03 Device Number. Can only be devices on the IMCH. Zeros used for padding. 02:00 Function Number. Table 15-8. ADDR1 – Address Byte 1 Register Position Description 07:04 Ignored. 03:00 Extended Register Number. Upper address bi ts for the 4 K region of register offset. Table 15-9. ADDR0 – Address Byte 0 Register Position Description 07:00 Register Offset.

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15.2.1.3.8 STS – Status Register

For a read cycle, the data is preceded by a byte of status. Table 15-11 shows how these bits are defined.

15.2.1.4 Unsupported Access Addresses

It is possible for an SMBus master to program an unsupported bit combination into the ADDR registers. The IMCH does not support such usage, and may not gracefully terminate such accesses.

15.2.1.5 SMBus Transaction Pictograms

Since the new SMBus target interface is of enterprise origin, it is more complex than the original SMBus target interface of desktop origin. The following drawings are included to demonstrate the different types of transactions, especially how they can be broken up into multiple smaller transfers. Table 15-10. Offset 04-07: DATA - Data Register Bits Type Reset Description 31:24 RW 00h Byte 3 (DATA3): Data bits [31:24] 23:16 RW 00h Byte 2 (DATA2): Data bits [23:16] 15:08 RW 00h Byte 1 (DATA1): Data bits [15:8] 07:00 RW 00h Byte 0 (DATA0): Data bits [7:0] Table 15-11. Status Register Position Description Internal Timeout 0 = SMBus request is completed within 2 ms internally 1 = SMBus request is not completed in 2 ms internally

06 Ignored

0 = No Internal Master Abort Detected 1 = Detected an Internal Master Abort Internal Target Abort 0 = No Internal Target Abort Detected 1 = Detected an Internal Target Abort 03:01 Ignored Successful 0 = The last SMBus transaction was not completed successfully 1 = The last SMBus transaction was completed successfully

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Figure 15-5. Dword Configuration Read Protocol Figure 15-6. Dword Configuration Write Protocol B4534-01 DWORD Configuration Read Protocol (SMBus Word Write/Word Read, PEC Disabled) 0110_000 W A Cmd = 10000001 A Bus Number A Device/Function A P 0110_000 W A Cmd = 01000001 A Register Num [15:8] A Register Num [7:0] A PCLOCK STRETCH 0110_000 W A Cmd = 10000001 A 0110_000 R A Status A Data[31:24] N P 0110_000 W A Cmd = 00000001 A 0110_000 R A Data[23:16] A Data[15:8] N P 0110_000 W A Cmd = 01000000 A 0110_000 R A Data[7:0] N P Sr S S S S Sr S Sr B4535-01 DWORD Configuration Write Protocol (SMBus Word Write, PEC Disabled) 0110_000 W A Cmd = 10001101 A Bus Number A Device/Function AS P 0110_000 W A Cmd = 00001101 A Register Num [15:8] A Register Num [7:0] AS P 0110_000 W A Cmd

00001101 A Data[31:24] A Data[23:16] AS P

0110_000 W A Cmd = 01001101 A Data[15:8] A Data[7:0] AS PCLOCK STRETCH 0110_000 W A Cmd = 10101101 A Destination Memory A Add Offset [23:16] AS P 0110_000 W A Cmd = 00101101 A Add Offset [15:8] A Add Offset [7:0] AS P 0110_000 W A Cmd

00101101 A Data[31:24] A Data[23:16] AS P

0110_000 W A Cmd = 01101101 A Data[15:8] A Data[7:0] AS PCLOCK STRETCH

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15.2.2 Suggested SMBus Usage Models

15.2.2.1 Remote Error Handling

The EP80579 supports error escalation via both SMI and MCERR FSB signaling, thus error handling may be implemented in system management mode (SMM) software, machine check architecture (MCA) software, or a combination of the two. Such software could direct a BMC with an integrated NIC to “call home” when errors are reported by the IMCH. The BMC could then interrogate internal IMCH error logging registers under remote control across the network interface, providing full identification and isolation of reported errors as described elsewhere in this document. The possibility also exists for remotely managed reconfiguration via the SMBus target port, as well as remotely managed system reboot via the BMC (if necessary).

15.2.2.2 Remote Platform Monitoring

The SMBus target also provides a sophisticated BMC with the capability to monitor the health of an EP80579-based platform, such that statistics on correctable error location and frequency may be tracked remotely in an effort to anticipate and prevent more serious failures. The IMCH includes significant RASUM functionality on both its memory subsystem and its PCI Express interfaces. Some types of errors are expected at a modest frequency within a platform of this complexity, and the IMCH provides internal hardware to track the frequency of such errors. These include correctable ECC errors on the memory interface, as well as transient communication errors on the high-speed serial PCI Express interfaces – refer to Chapter 14.0, “RAS Features and Exception Handling” for further details. The BMC could be remotely directed to periodically poll the internal error logging registers of the IMCH, permitting a remote management software package to maintain a running profile of error types and frequencies experienced by an EP80579-based platform. Changes in error frequency or type could be flagged by the remote monitoring software to prompt follow-up preventative maintenance on the platform.

15.3 Platform Power Management Support

The IMCH is compatible with the PCI Bus Power Management Interface Specification, Revision 1.1 (referred to here as PCI-to-PMI). The IMCH is also compatible with the Advanced Configuration and Power Interface Specification, Rev. 2.0 (ACPI). The EP80579 is designed to operate seamlessly with operating systems employing these specifications. The anticipated implementation for platform power management control is an add-on component connected to the IICH component of the core logic via its LPC and/or SMBus interfaces.

15.3.1 Supported System Power States

The IMCH and the system power states are analogous, thus no “device” power states are defined for the IMCH. As a result, the IMCH power state may be directly inferred from the system power state. Like all systems, EP80579-based platforms must support the S0 (fully active) state at a minimum. The IMCH also supports S1 (Idle), S3 cold (suspend to RAM), S4 (suspend to disk), and S5 (soft off). S2 (power-on suspend) and S3 hot are not supported.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 381 Intel® EP80579 Integrated Processor S3 support requires specialized internal hardware. A request to enter the S3 power state is communicated to the IMCH by the IICH. In response, the IMCH flushes all data from the internal coherent write buffer, sequences all active DIMM rows into their “self- refresh” state, and then returns an Ack_Sx special cycle to the IICH. Upon completion of this sequence, the IMCH tolerates the removal of all clock references and power sources, save the DDR2 interface power. DDR2 interface power must be supplied so that the IMCH may hold the DIMMs in self-refresh. A full system initialization and configuration sequence is required upon system exit from the S3 state, as all (non- AUX) internal configuration information has been throughout the platform, but exit latency is much lower than it would be from S5, as the memory image has been maintained. Note: The Go_S3 message indicates that the IICH is getting ready to put the system into S3, S4 or S5 state. The extra internal logic support for S3 and S4 is not required for the S5 (soft off) system power state because all data in the memory array is lost regardless, and the coherent write buffer is architecturally part of the data stored in main memory.

15.3.1.1 Supported CPU Power States

EP80579-based platforms support the C0, C1, C2 and C3 states as defined by the Advanced Configuration and Power Interface Specification (ACPI). This implies that the core logic anchored by the IMCH properly understands and handles messaging between the IMCH and the FSB to facilitate transitions into and out of these states.

15.3.1.2 Supported Device Power States

The IMCH supports all PCI-to-PMI and PCI Express messaging required to place any subordinate device on any of its PCI Express ports into any of the defined device low power states. Peripherals attached to the PCI segments provided via a PXH component may be placed in any of their supported low power states via messaging directed from the IMCH through the intervening PCI Express hierarchy. Directly attached native PCI Express devices are not limited in their available low power states, although not all available states support the downstream device “wake-up” semantic. Further details about PCI Express power management support and accompanying PCI Express and subordinate device power management support are provided in Section 15.3.3, “PCI Express Interface Power Management” on page 382.

15.3.1.3 Supported Bus Power States

No low power bus states are supported by the EP80579 on its internal NSI interface between the IMCH and the IICH. Also, IMCH does not support placement of the IICH only into any low-power state below D0, other than as a side-effect of placing the entire system into one of the S3 cold, S4, or S5 states. Significant low power mode support is provided for the several IMCH PCI Express ports, as detailed in Section 15.3.3, “PCI Express Interface Power Management” on page 382.

15.3.2 DDR2 Interface Power Management

DDR2 self-refresh is supported as an integral piece of the S3 support.

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15.3.3 PCI Express Interface Power Management

In PCI Express, the traditional bus (B*) power states assigned to system buses are replaced by link (L*) power states, which are largely managed by hardware without software intervention. Entry into and out of these states may be initiated by two distinct mechanisms:

traditional PCI-PMI type software managed state changes
non-traditional PCI Express autonomous hardware state changes The latter transition type is designated “Active State Power Management,” (ASPM) and included with the PCI Express Interface Specification, Rev. 1.0a.

15.3.3.1 PCI Express Link Power State Definitions

Support for all of the following PCI Express link power states is required for PCI Express Specification compatibility: Note: The IMCH does not support all PCI Express link power states.

L0 – Active state with all operations enabled (default state after platform initialization).
L0s –Low latency, energy saving standby state, disabling exchange of both transaction layer packets and device link layer messages. This state is used exclusively by the ASPM PCI Express function, with entry and exit managed autonomously by PCI Express interface hardware.
L1 – (Only supported in software managed state changes) Moderate to high latency, very low power, standby state, disabling exchange of both transaction layer packets and device link layer messages. Entered when the downstream device is programmed to a device power state below the D0 active state, or optionally under hardware control during ASPM. The clock remains active in L1, and exit from this state may be initiated by either the upstream or the downstream device.
L2/L3 Ready – Staging point for removal of main power and clocking. New intermediate state not directly related to PCI PM D-state transitions, nor to ASPM. Hand-shaking lands the link in this state in anticipation of power removal, at which point the link moves to either L2 or L3 depending upon the presence of Vaux.
L2 – High latency, very low deep sleep state, disabling exchange of transaction layer packets and device link layer messages. L2 is characterized by removal of clocking and main power, but presence of Vaux power. Exit is initiated by restoring clocking and power, and full initialization.
L3 – High latency, link off state with power, Vaux, and clock reference removed. Exit is initiated by restoring clocking and power, and full initialization. The IMCH is fully compliant with the PCI Express Specification, but does not support the optional L1 state via the ASPM mechanism. Refer to the PCI Express* Interface Specification, Rev. 1.0a for further detail on the link states and specific information on entry and exit mechanisms.

15.3.3.2 Software Controlled PCI Express Link States

Software managed device power state changes do not explicitly control the power L- state of PCI Express links. Instead the L-state is inferred by hardware from the PCI-PMI power state of the devices attached to that link. When PM software transitions a PCI Express device to a low power state, that device automatically negotiates with hardware to bring its upstream link into the appropriate link power state. No link is allowed to be in a link power state “below” that which is dictated by its attached components.

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 383 Intel® EP80579 Integrated Processor Table 15-12 defines the legal relationships between link and attached device power states. Several new semantics are introduced with PCI Express to support PCI-PMI compatible software managed device and link power state transitions. The majority of the new functionality is to accommodate an essentially edge-triggered, in-band message scheme supporting multi chassis cabled system topologies, which must replace the function of traditional level-sensitive board traces for PM event and wake signaling. Further details about PME signaling appears in Section 15.3.5, “PME Support” on page 385. The IMCH supports messaging to facilitate transition of attached PCI Express devices to power states D0, D1, D2, and D3 (both D3HOT and D3COLD). All attached devices are required by the PCI Express Specification to support the D0 and both D3 states, while D1 and D2 support are optional. Software should confirm device support of the optional D1 and D2 states prior to attempting their use on any attached PCI Express device. In the D1, D2, and D3HOT states, the attached device is required to suppress initiation of any link traffic other than PME initiation (if enabled) as a master, and must only accept configuration transactions as a target. Functional context is maintained in the D1 and D2 states, such that full initialization of the attached device is not required upon the wake-up transition back to the D0 state. In both D3 states, functional context is not maintained, and full initialization is required after a transition back to D0. Placing an attached device into a low power state results in automatic transition of the associated PCI Express port to its L1, L2 or L3 link state (depending upon the device power state). To save additional power in the L2 state, the platform power manager must remove the reference clock from the link. The IMCH does not provide the necessary internal clock generation and distribution control to allow clock removal from one PCI Express port interface without impacting the operation of its peer ports on the IMCH. CMI does not provide support on its PCI Express link interfaces for the in-band “tone” required to wake from such a state.

15.3.3.3 Hardware Controlled PCI Express Link States

Active-state power management (ASPM) support is a required component of PCI Express Specification compliance and is intended to provide granularity and flexibility for PCI Express components to dynamically manage their own power consumption without software supervision and support. All native PCI Express components, regardless of device class, must support active transitions to and from the L0s low power link state as a minimum and may optionally support active transitions to and from the L1 low power link state. The IMCH does not support ASPM entry into the L1 state under hardware control. CMI negatively acknowledges (NAK) ASPM requests for L1 state transitions. IMCH configuration registers reflect this level of support for ASPM. Table 15-12.Relationship Between Link and Device PM States Downstream Component D-State Permissible Upstream Component D-State Permissible Interconnect L-State D0 D0 L0, L0s, L1 † D1 D0, D1 L1 D2 D0, D1, D2 L1 D3hot D0, D1, D2, D3 hot L1, L2/L3 Ready D3cold D0, D1, D2, D3 hot, D3 cold L2, L3 † Entry into L0s or L1 while attached devices remain in D0 only occurs as a part of ASPM. Per the PCI Express spec, L0s support is mandatory, while L1 is optional. L1 is not supported by ASPM.

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All ASPM functionality is disabled by default upon system power-up. It is the responsibility of software to verify a viable platform clocking configuration prior to enabling ASPM functionality within the IMCH or in any attached PCI Express devices. In topologies where independent clock references are used at any point within the PCI Express subsystem hierarchy, the “fast training” sequence associated with ASPM is not guaranteed to successfully revive the associated link, and ASPM must remain disabled in the devices at both ends of that link.

15.3.3.4 System Clocking Solution Dependencies

The topology of the platform clocking solution dictates the viability of ASPM on each of the PCI Express links. This is because the nature of the clocks directly impacts the amount of time required to re-acquire bit and symbol lock in the receiver after an arbitrarily long non-communicative period. When both ends of a link share a clock source, they “wander” together over the period they are out of communication with each other, and accordingly require a relatively brief period of training to re-acquire lock. When the two ends of a link utilize completely independent clock references, they may become arbitrarily out of phase with each other while they are in low power states, and therefore require a significantly longer amount of time to re-acquire lock upon waking. For this reason, the PCI Express Interface Specification provides for software discovery and communication of the actual clocking topology within the system prior to enabling the ASPM feature on any link within the system. There are two primary components to the clocking discovery mechanism. First, all downstream ports, such as those on the IMCH root device, must report whether they use the same clock source as that provided to the slot (or down-device) connected to that port in the platform. This information is recorded in the Slot Clock Configuration bit of the Link Status Register for each port and system BIOS is required to initialize these bits accordingly. Second, all add-in devices must report whether they utilize the clock reference provided on the add-in slot via the same bit in the same register of their capability structure. System software may examine the settings of the Slot Clock Configuration bits of both the upstream and downstream devices for each port in the system, and determine whether a common clock reference is in use. This information is then communicated to both the upstream and the downstream devices via programming of the Common Clock Configuration bit of the Link Status Register. The setting of this bit determines the reported exit latency requirements for the L1 state. System software may then compare the exit latency requirements with the tolerated exit latencies of the attached device and determine whether or not to enable ASPM for each link the system. All ASPM functionality defaults to disabled at power-on and remain so unless system software determines it may be enabled. The “N_FTS” parameters exchanged during initial training corresponds to the “long” exit latencies associated with independent clocks. If software later sets the Common Clock Configuration bits, it is also necessary to force link retraining in order to update the exchanged N_FTS information.

15.3.3.5 Device and Link PM Initialization

All PCI Express devices power-on into the D0uninitialized state and remain in that non- communicative state until they have been configured and at least one of the Memory Space Enable, I/O Space Enable, or Bus Master Enable bits has been set by system software, at which point the device automatically transitions to the D0 ACTIVE state indicative of normal operation.

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15.3.4 Device and Slot Power Limits

All add-in devices must power-on to a state in which they limit their total power dissipation to a default maximum according to their form-factor (10 W for add-in edge- connected cards). When BIOS updates the slot power limit register of the root ports within the IMCH, the IMCH automatically transmits a Set_Slot_Power_Limit message with corresponding information to the attached device.The platform BIOS is responsible for properly configuring the slot power limit registers in the IMCH. Failure to do so may result in attached endpoints remaining completely disabled in order to comply with the default power limitations associated with their form-factors.

15.3.5 PME Support

All information in this section refers to the IMCH PME support. See Chapter 27.0, “Power Management” for PME support in IICH. In CMI systems, only the system power manager or a device within the PCI Express hierarchy may initiate a power state change. Thus the only Power Management Event (PME) signaling support required in the IMCH is that associated with PCI Express. Note that a device bridging to another technology, such as a PXH bridging to PCI-X, may convert traditional PME signaling into PCI Express in-band PME messaging and thereby meet this requirement of the IMCH. PME signaling in PCI Express is crafted to accomplish two distinct functions. First, it provides a signaling mechanism for devices requiring service to propagate a wake-up request to the power management controller. Second, it provides a messaging mechanism for devices requesting a power state change to pass their unique location within the PCI Express hierarchy to the power management controller. The combination of these two functions provides great flexibility and controllability for the power manager.

15.3.5.1 PME Wake Signaling

Wake signaling is only required to provide for device-initiated transition out of low power states where clock and/or power have been removed from the sleeping device. The PME mechanism does not require a wake-up function for attached devices still powered and receiving an interface reference clock, as devices in this state may simply initiate PME messaging directly. Wake is only required if the device wishing to initiate a PME message cannot do so without first requesting a change to the system clocking and power profile from the power management controller. The wake signaling aspect of the system power management solution may vary in elegance and granularity. Depending upon the support level provided by the power management controller, a wake-up request from any given device may cause power and clocking to be restored to the entire system, to just the affected branch of the PCI Express hierarchy, or only to the requesting device. While the PCI Express Interface Specification provides for two distinct wake signaling mechanisms, CMI supports only the legacy mechanism described below.

15.3.5.1.1 Legacy Wake Mechanism

The legacy wake signaling mechanism is analogous to that used in historical PCI-based system designs. In this case, the platform architect is responsible for crafting paths routing collected wake signals between wake-capable devices and the management controller without participation from the IMCH and IICH equivalent devices. The collection of wake logic must run on auxiliary power, and must comprehend the potential for devices both with and without supplied auxiliary power co-existing on the same branch of the PCI Express hierarchy. Refer to the PCI Express Interface Specification for further details on legacy wake signaling.

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While familiar and well understood, this mechanism does not provide for device- initiated wake-up in the fully A/C coupled implementation of a multi-chassis PCI Express-based system solution. The limitation imposed upon CMI-based system is that remote-chassis devices must not be placed in a low-power state with the PCI Express link clocking and/or power disabled if legacy style wake signaling is desired for any peripheral in that remote chassis. It is still possible for software to place peripheral devices in low power sleep states and to manage the device state of the PCI Express device attached to the inter-chassis cable. Devices in the remote chassis may still initiate power state changes via PME messaging provided the inter-chassis link has not been placed into an uncommunicative state. An alternative for the platform architect would be to place a compatible switch device between the IMCH and the remote chassis that supports the in-band wake mechanism described below and rely on the switch to forward wake events to the management controller. The platform architect should ensure that the power management controller can adequately isolate the source of a PME wake request as required to take appropriate power management wake-up action.

15.3.5.2 PME Messaging

Once the link requesting a power state change has a communicative upstream link, it sends the PM_PME packet upstream toward the root device (IMCH), which in turn is responsible for notifying the management controller. This constitutes an in-band “virtual wire” signaling mechanism to replace the historical solution that involved multiple independent board traces routing PME requests to the power manager. Because the PM_PME propagates “in-band” on the PCI Express interface without any side-band signaling support, PME functionality is made available to multi-chassis system solutions. The IMCH collects and “OR” PME requests from all logical PCI Express ports and propagates it to IICH over the NSI link as an Assert_PMEGPE message. The IICH then generates a specified interrupt to wake the power manager and invokes power management software. The interrupt service routine may then interrogate the various PM status registers to determine the source(s) of PME. The IMCH would send a Deassert_PMEGPE message over NSI link after the power state change request has been serviced.

15.3.6 BIOS Support for PCI Express PM Messaging

The PCI Express Specification stipulates hierarchical messaging semantics enforced by the root device (IMCH) to guarantee proper entry into and exit from unpowered device states. CMI ACPI BIOS must make special allowances for support of these semantics. There are two sets of messages that must be software-assisted in CMI based platforms to support power-off device states within the PCI Express hierarchy.

15.3.6.1 PCI Express PME_TURN_OFF Semantic

Prior to removing power from any attached PCI Express links anywhere in the hierarchy, the root device must broadcast a PCI Express “PME_TURN_OFF” message to all downstream devices on the affected PCI Express port. The receiving devices propagate this message to all subordinate PCI Express ports (if any), collect “PME_TO_ACK” acknowledgement packets, and finally return a “PME_TO_ACK” transaction layer packet back to the root device. Once all active ports have acknowledged, the power management device may be notified that it is cleared to modify the collective power state of the PCI Express hierarchy. These message packets have posted semantics on the interface, thus the turn-off “pushes” all prior packets to

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 387 Intel® EP80579 Integrated Processor their endpoints, and the acknowledge “pushes” any pending inbound traffic all the way to the root. This prevents “trapping” transactions or PME messages somewhere in the hierarchy at the time power is dropped, ultimately causing them to be lost. In a pure PCI Express design, the PME_TURN_OFF packet would originate directly at the power manager, or perhaps at the IICH providing connection between the power manager and the remainder of the core logic. Neither the power manager nor the IICH is aware of the PCI Express messaging mechanism, thus the IMCH provides device- specific control and status bits for use by its ACPI BIOS. The sequence of events to place a PCI Express device in an unpowered state is as follows: 1. PCI-PM or ACPI-compliant O/S software is called to place the system into a low- power sleep state (S3, S4 or S5), prepares for suspension, and calls ACPI BIOS to carry out the platform power transition. 2. The BIOS then communicates to the root complex that all PCI Express devices must prepare for power-off. This is accomplished through the device-specific configuration space of the internal virtual PCI-to-PCI bridges with subordinate PCI Express hierarchies. The BIOS must configure each active root port to power-down. When the configuration write is received to set the “PM Turn Off” bit, the associated root port transmits a PM_Turn_Off message downstream. At this point, any traffic in-flight continues to be handled normally by the IMCH – routed outbound, and completed inbound. 3. The target PCI Express device ceases generation of new transactions inbound, waits for all pending transactions to complete and prepares to lose power and clocking. If the target device has a subordinate hierarchy of its own, it propagates the PM_Turn_Off message downstream and waits for acknowledges from all subordinate ports. Once ready to be brought off-line, the target device issues a PM_TO_Ack TLP cycle in acknowledgement back to the root. Note that the link is still communicative at this point, with both power and clock available. 4. After issuing the PM_TO_Ack cycle, the downstream device then issues a PM_Enter_L23 DLLP continuously upstream until it receives an acknowledge. In response to the PM_TO_Ack, the root port will commence the PCI Express handshake sequence necessary to sets its “Turn Off Ack” status bit. In response to the PM_Enter_L23 DLLP, the root transitions its downstream link to the electrical idle state. (This protocol sequence directly mirrors the L1 entry sequence.) 5. ACPI BIOS, which has been waiting for all of the “Turn Off Ack” status bits to assert, now clears all the command and status bits associated with the PME_TURN_OFF. The routine then informs the power manager to go ahead with the change to the system power state. Note that software is required (by the PCI Express specification) to implement a “dead-man” timer such that a failure to receive a full complement of “Turn Off Ack” status bits does not result in an indefinite hang. This timeout is nominally 1 second, after which the power state change proceeds regardless. 6. The power manager drops power and clocking to the target device(s), and all associated links automatically transition to either the L2 or L3 uncommunicative power states. The links enter L2 if Vaux is supplied by the platform, otherwise they enter L3. (Note that the IMCH does not support Vaux, so all downstream lanes will necessarily go to the L3 state.) The platform remains in the low-power state until a wake event is signaled. In a fully PCI Express aware core logic implementation, the ACPI BIOS would not need to act as the interlock between the IMCH and the power manager, as all that functionality would be handled in hardware via direct messaging. § §

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16.0 IMCH Registers

16.1 IMCH Registers: Bus 0, Device 0, Function 0

The Integrated Memory Controller Hub (IMCH) registers are in Bus 0, Device 0, Function 0. Table 16-1 provides the register address map for this device and function. Warning: Address locations that are not listed are considered reserved register locations. Reads to reserved registers may return non-zero values. Writes to reserved locations may cause system failure. Table 16-1. Bus 0, Device 0, Function 0: Summary of IMCH PCI Configuration Registers (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID – Vendor Identification Register” on page 391 8086h 02h 03h “Offset 02h: DID – Device Identification Register” on page 391 5020h 04h 05h “Offset 04h: PCICMD: PCI Command Register” on page 392 0006h 06h 07h “Offset 06h: PCISTS: PCI Status Register” on page 393 0010h 08h 08h “Offset 8h: RID - Revision Identification Register” on page 394 Variable 0Ah 0Ah “Offset 0Ah: SUBC - Sub-Class Code Register” on page 394 00h 0Bh 0Bh “Offset 0Bh: BCC – Base Class Code Register” on page 394 06h 0Eh 0Eh “Offset 0Eh: HDR - Header Type Register” on page 395 80h 14h 17h “Offset 14h: SMRBASE - System Memory RCOMP Base Address Register” on page 396 00000000h 2Ch 2Dh “Offset 2Ch: SVID - Subsystem Vendor Identification Register” on page 396 0000h 2Eh 2Fh “Offset 2Eh: SID - Subsystem Identification Register” on page 397 0000h 4Ch 4Fh “Offset 4Ch: NSIBAR - Root Complex Block Address Register” on page 397 00000000h 50h 50h “Offset 50h: CFG0- IMCH Configuration 0 Register” on page 398 0Ch 51h 51h “Offset 51h: IMCH_CFG1 – IMCH Configuration 1 Register” on page 399 00000h 53h 53h “Offset 53h: CFGNS1 - Configuration 1 (Non-Sticky) Register” on page 399 00h 58h 58h “Offset 58h: FDHC - Fixed DRAM Hole Control Register” on page 400 00h 59h 59h “Offset 59h: PAM0 - Programmable Attribute Map 0 Register” on page 401 00h 5Ah 5Ah “Offset 5Ah: PAM1: Programmable Attribute Map 1 Register” on page 402 00h 5Bh 5Bh “Offset 5Bh: PAM2 - Programmable Attribute Map 2 Register” on page 403 00h 5Ch 5Ch “Offset 5Ch: PAM3 - Programmable Attribute Map 3 Register” on page 404 00h 5Dh 5Dh “Offset 5Dh: PAM4 - Programmable Attribute Map 4 Register” on page 405 00h 5Eh 5Eh “Offset 5Eh: PAM5 - Programmable Attribute Map 5 Register” on page 406 00h 5Fh 5Fh “Offset 5FH: PAM6 - Programmable Attribute Map 6 Register” on page 407 00h

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9Ch 9Ch “Offset 9Ch: DEVPRES - Device Present Register” on page 408 33h 9Dh 9Dh “Offset 9Dh: EXSMRC - Extended System Management RAM Control Register” on page 409 00h 9Eh 9Eh “Offset 9Eh: SMRAM - System Management RAM Control Register” on page 411 02h 9Fh 9Fh “Offset 9Fh: EXSMRAMC - Expansion System Management RAM Control Register” on page 413 07h B8h BBh “Offset B8h: IMCH_MENCBASE: IA/ASU Shared Non-Coherent (AIOC-Direct) Memory Base Address Register” on page 413 000FFFFFh BCh BFh “Offset BCh: IMCH_MENCLIMIT - IA/ASU Shared Non-Coherent (AIOC-Direct) Memory Limit Address Register” on page 414 00000000h C4h C5h “Offset C4h: TOLM - Top of Low Memory Register” on page 415 0800h C6h C7h “Offset C6h: REMAPBASE - Remap Base Address Register” on page 416 03FFh C8h C9h “Offset C8h: REMAPLIMIT – Remap Limit Address Register” on page 416 0000h CAh CBh “Offset CAh: REMAPOFFSET - Remap Offset Register” on page 417 0000h CCh CDh “Offset CCh: TOM - Top Of Memory Register” on page 417 0000h CEh CFh “Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced Configuration Base Address Register” on page 418 E000h D8h D8h “Offset D8h: CACHECTL0 - Write Cache Control 0 Register” on page 418 00h DEh DFh “Offset DEh: SKPD - Scratchpad Data Register” on page 419 0000h F6h F6h “Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register” on page 419 00h 60h at 1h 60h at 1h “Offset 60h: DRB[0-3] - DRAM Row [3:0] Boundary Register” on page 421 ffh 70h at 4h 73h at 4h “Offset 70h: DRA[0-1] - DRAM Row [0:1] Attribute Register” on page 422 00000515h 78h 7Bh “Offset 78h: DRT0 - DRAM Timing Register 0” on page 424 242AD280h 64h 67h “Offset 64h: DRT1 - DRAM timing Register 1” on page 431 12110000h 7Ch 7Fh “Offset 7Ch: DRC - DRAM Controller Mode Register” on page 435 00000002h 84h 87h “Offset 84h: ECCDIAG - ECC Detection/Correction Diagnostic Register” on page 437 00000000h 88h 8Bh “Offset 88h: SDRC - DDR SDRAM Secondary Control Register” on page 439 00000002h 8Ch 8Ch “Offset 8Ch: CKDIS - CK/CK# Clock Disable Register” on page 441 00h 8Dh 8Dh “Offset 8Dh: CKEDIS - CKE Clock Enable Register” on page 442 00h 90h 93h “Offset 90h: SPARECTL - SPARE Control Register” on page 443 00000000h B0h B3h “Offset B0h: DDR2ODTC - DDR2 ODT Control Register” on page 444 00000000h Table 16-1. Bus 0, Device 0, Function 0: Summary of IMCH PCI Configuration Registers (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value

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16.1.1 Register Details

16.1.1.1 Offset 00h: VID – Vendor Identification Register

The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect.

16.1.1.2 Offset 02h: DID – Device Identification Register

This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to this register have no effect. Table 16-2. Offset 00h: VID – Vendor Identification Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 00h 01h Size: 16 bit Default: 8086h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 00 VID Vendor Identification: This register field contains the PCI standard identification for Intel 8086h. 8086h RO Table 16-3. Offset 02h: DID – Device Identification Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 02h 03h Size: 16 bit Default: 5020h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 00 DID Device Identification Number: This is a 16-bit value assigned to the IMCH Host-NSI Bridge Function 0. 5020h RO

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16.1.1.3 Offset 04h: PCICMD: PCI Command Register

Since IMCH Device 0 does not physically reside on a PCI bus, many of the bits are not supported. Table 16-4. Offset 04h: PCICMD: PCI Command Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 04h 05h Size: 16 bit Default: 0006h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 10 Reserved Reserved 00h 09 FB2B Fast Back-to-Back Enable: This bit is hardwired to 0. 0b RO

08 SERRE

SERR Enable: This bit is a global enable bit for Device 0 SERR messaging. The IMCH does not have a SERR signal. The IMCH communicates the SERR condition by sending a SERR message over NSI to the IICH. 0 = Disable. The SERR message is not generated by the IMCH for Device 0. 1 = Enable. The IMCH enables generation of SERR messages over NSI for specific Device 0, Function 0 error conditions that are enabled via the PCICMD register. The error status is reported in the PCISTS registers. The only error event enabled through Device 0, Function 0 is Detected Parity Error which is essentially a NSI poisoned TLP, and is enabled by the parity error enable bit (PERRE). Note: This bit only controls SERR messaging for Device 0, Function 0. Device 0, Function 1, and Devices 1-7 have their own SERR bits to control error reporting for error conditions occurring on their respective devices. The control bits are used in a logical OR manner to enable the SERR NSI message mechanism. 0b RW

07 Reserved Reserved 0b

06 PERRE

Parity Error Enable: 0 = Disable. The IMCH does not take any action when it detects data corruption on NSI. 1 = Enable. The IMCH generates an SERR message over the NSI to the IICH when a poisoned TLP is detected by the IMCH on NSI (DPE set in PCISTS) and SERRE is set to 1. 0b RW 05 : 03 Reserved Reserved 0h

02 BME

Bus Master Enable: The IMCH is always enabled as a master on NSI. This bit is hardwired to 1. Writes to this bit position have no effect. 1b RO 01 MAE Memory Access Enable: This bit is hardwired to 1. 1b RO

00 Reserved Reserved 0b

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16.1.1.4 Offset 06h: PCISTS: PCI Status Register

PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0’s PCI interface. Since IMCH Device 0 does not physically reside on a PCI bus many of the bits are not supported. Table 16-5. Offset 06h: PCISTS: PCI Status Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 06h 07h Size: 16 bit Default: 0010h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

15 DPE

Detected Parity Error: This bit is set to 1 whenever it receives a poisoned TLP regardless of the state of the parity error response bit. Software may clear this by writing a 1 to this bit. 0b RWC

14 SSE

Signaled System Error: 0 = Software clears this bit by writing a 1 to the bit location. 1 = IMCH Device 0, Function 0 generates a SERR message over NSI for any enabled Device 0, Function 0 error condition. Device 0 error conditions are enabled in the PCICMD register. Device 0 error flags are read/reset from the PCISTS register. The only error that can be enabled to signal system error through Device 0, Function 0 is the detected parity error which is essentially a NSI poisoned TLP. Software may clear this by writing a 1 to this bit. 0b RWC

13 RMAS

Received Master Abort Status: This bit is set if the IMCH generates a NSI request that receives a completion with unsupported request completion status. Software may clear this by writing a 1 to this bit. 0b RWC

12 RTAS

Received Target Abort Status: Set to 1 by hardware if the IMCH generated a request that received a completion with Completer Abort status. Software clears this bit by writing a 1 to this bit location. 0b RWC

11 STAS

Signaled Target Abort Status: The IMCH does not generate a Completer Abort on the NSI completion packet. This bit is hardwired to w10. Writes to this bit position have no effect. 0b RO 10 : 09 Reserved Reserved 00b

08 DPD Master Data Parity Error Detected: This bit is hardwired

to 0. 0b RWC 07 FB2B Fast Back-to-Back: Reserved. 0b 06 : 05 Reserved Reserved 00b

04 CLIST

Capability List: This bit is hardwired to 1 to indicate to the configuration software that this device/function implements a list of new capabilities. A list of new capabilities is accessed via register CAPPTR at configuration address offset 34h. 1b RO 03 : 00 Reserved Reserved 0h

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16.1.1.5 Offset 08h: RID - Revision Identification Register

This register contains the revision number of the IMCH Device 0. These bits are read- only and writes to this register have no effect.

16.1.1.6 Offset 0Ah: SUBC - Sub-Class Code Register

16.1.1.7 Offset 0Bh: BCC – Base Class Code Register

Table 16-6. Offset 8h: RID - Revision Identification Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 08h 08h Size: 8 bit Default: Variable Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 00 RID Revision Identification Number: This value indicates the revision identification number for the IMCH Device 0. Variable RO Table 16-7. Offset 0Ah: SUBC - Sub-Class Code Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 0Ah 0Ah Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 00 SUBC Sub-Class Code: This value indicates the Sub Class Code into which the IMCH Device 0 falls. 00h = Host Bridge 00h RO Table 16-8. Offset 0Bh: BCC – Base Class Code Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 0Bh 0Bh Size: 8 bit Default: 06h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 00 BASEC Base Class Code: This value indicates the Base Class Code for the IMCH Device 0. 06h = Bridge device 06h RO

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16.1.1.8 Offset 0Eh: HDR - Header Type Register

16.1.1.9 Offset 14h: SMRBASE - System Memory RCOMP Base Address Register

The SMRBASE is a standard PCI Base Address register that is used to set the base of the Memory Mapped Registers used to control the System Memory I/O Buffer RCOMP. In addition to calibration, the DCAL engine which resides within this memory mapped region also performs RAS functions. In addition, there are some BIOS scratch registers within this region. The actual behavior of this register depends on the SMRCOMP MMR Enable bit in the IMCH TST2 register (Device 0, Function 0, Offset F6, Bit 6). When IMCH TST2[6] is set, this register behaves like a standard PCI BAR requesting 4 Kbyte of address space. When IMCH TST2[6] is clear, this register is hardwired to all zeros, effectively disabling the BAR and the corresponding SM MMR region. Because of the more extensive functionality supported by DCAL, it is expected that once this address space has been enabled by System BIOS, it remains enabled to support various RAS features. Note: All accesses to these Memory Mapped Registers must be made as a single Dword (4 bytes) or less. Access must be aligned on a natural boundary. Table 16-9. Offset 0Eh: HDR - Header Type Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 0Eh 0Eh Size: 8 bit Default: 80h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 00 HDR Note: PCI Header: The header type of the IMCH Device 80h = multi-function device with standard header layout. This register should return a 00h indicating a single function device, when both functions 1 and 2 are disabled. 80h RO

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16.1.1.10 Offset 2Ch: SVID - Subsystem Vendor Identification Register

This value is used to identify the vendor of the subsystem. Table 16-10. Offset 14h: SMRBASE - System Memory RCOMP Base Address Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 14h 17h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 12 UPBITS Upper Programmable Base Address: These bits are part of the SM MMR region, normally set by configuration software to locate the base address of the region. The actual behavior of this field depends on the SM MMR Enable bit in the IMCH TST2 register (bit 6) as defined above. When IMCH TST2[6] = 1 these bits are Read/Write. When IMCH TST2[6] = 0 these bits are Read-Only as zeros. 00000h RW or RO 11 : 04 LOWBITS Lower Bits: These bits are hardwired to 0. This forces the size of the memory region to be 4 Kbyte. 00h RO

03 PF Prefetchable: This bit is hardwired to 0 to indicate that

the System Memory MMR region is NON-Prefetchable. 0b RO 02 : 01 TYPE Addressing Type: These bits determine addressing type and they are hardwired to 00 to indicate that address range defined by the upper bits of this register can be located anywhere in the 32-bit address space in order to comply with the PCI specification for base address registers. 00b RO

00 MSPACE

Memory Space Indicator: Hardwired to 0 to identify the MMR range as a memory range as per the specification for PCI base address registers. 0b ROTable 16-11.Offset 2Ch: SVID - Subsystem Vendor Identification Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 2Ch 2Dh Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 00 SUBVID Subsystem Vendor ID: This field must be programmed during boot-up to indicate the vendor of the system board. 0000h RWO

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16.1.1.11 Offset 2Eh: SID - Subsystem Identification Register

This value is used to identify a particular subsystem.

16.1.1.12 Offset 4Ch: NSIBAR - Root Complex Block Address Register

This is the base address for the Root Complex memory-mapped configuration space. This window of addresses contains the Root Complex Register Block for the NSI hierarchy associated with the IMCH. There is no physical memory within this 4 Kbyte window that can be addressed. The 4 Kbyte reserved by this register does not alias to any PCI 2.3 compliant memory mapped space. All accesses to these Memory Mapped Registers must be made as a single Dword (4 bytes) or less. Access must be aligned on a natural boundary. Table 16-12.Offset 2Eh: SID - Subsystem Identification Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 2Eh 2Fh Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 00 SUBID Subsystem ID: This field must be programmed during BIOS initialization. After it has been written once it becomes Read-Only. When any byte or combination of bytes of this register is written, the register value locks and cannot be further updated. 0000h RWO Table 16-14.Offset 4Ch: NSIBAR - Root Complex Block Address Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 4Ch 4Fh Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 12 NSI_BA NSI Base Address: The BIOS programs this register resulting in a base address for a 4 Kbyte block of contiguous memory address space. This register ensures that a naturally aligned 4 Kbyte space is allocated within total addressable memory space of 4 Gbyte. System Software uses this base address to program the NSI register set. When IMCH TST2[5] = 1, the NSI Memory Mapped Register space is visible and memory mapped accesses are claimed and decoded appropriately. When IMCH TST2[5] = 0, the NSI Memory Mapped Register space is disabled and does not claim any memory. (THE NSIBAR register is still read/write accessible.) 00000h RW or RO 11 : 00 Reserved Hardwired to 0 000h

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16.1.1.13 Offset 50h: CFG0 - IMCH Configuration 0 Register

MCHCFG consists of IMCH CFG1 in the upper 8 bits and IMCH CFG0 in the lower 8 bits. Table 16-15. Offset 50h: CFG0- IMCH Configuration 0 Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 50h 50h Size: 8 bit Default: 0Ch Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 03 Reserved Reserved 0h

02 IOQD

In-Order Queue Depth: This bit reflects the value sampled on HA[7]# on the de-assertion of the CPURST#. It indicates the depth of the CPU bus in-order queue. 0 = HA[7]# has been sampled asserted (e.g., logic one, or electrical low). The depth of the IOQ is set to one (e.g., no pipelining on the processor bus). HA[7]# may be driven low during CPURST# by an external source. 1 = HA[7]# was sampled as deasserted (e.g. logic zero or electrical high). The depth of the processor bus in- order queue is configured to the maximum (e.g., 12). 1b RO

01 DRFD

Deferred Resource Fairness Disable: 0 = Clearing the bit allows the fairness logic to start working again. 1 = Setting this bit clears the fairness logic for deferred resources and hold it in reset. Note: This bit should only be changed in the event that there is some issue with the fairness logic. 0b RW

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16.1.1.14 Offset 51h: IMCH _CFG1 – IMCH Configuration 1 Register

16.1.1.15 Offset 53h: CFGNS1 - Configuration 1 Register

This register contains IMCH control bits that are not sticky. Table 16-16.Offset 51h: IMCH_CFG1 – IMCH Configuration 1 Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 51h 51h Size: 8 bit Default: 00000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 05 NSG Number of Stop Grant Cycles: Number of Stop Grant transactions expected on the FSB bus before a Req_C2 packet is sent to the IICH. This field is programmed by the BIOS after it has enumerated the processors and before it has enabled Stop Clock generation in the IICH. Once this field has been set, it must not be modified. Note that each enabled thread within each CPU generates Stop Grant Acknowledge transactions. Note: This register is read/write and not write-once as in some implementations. Encoding Description 0 0 0 NSI Stop Grant generated after 1 FSB Stop Grant 0 0 1 NSI Stop Grant generated after 2 FSB Stop Grant 0 1 0 NSI Stop Grant generated after 3 FSB Stop Grant 0 1 1 NSI Stop Grant generated after 4 FSB Stop Grant 1 0 0 NSI Stop Grant generated after 5 FSB Stop Grant 1 0 1 NSI Stop Grant generated after 6 FSB Stop Grant 1 1 0 NSI Stop Grant generated after 7 FSB Stop Grant 1 1 1 NSI Stop Grant generated after 8 FSB Stop Grant 000b RW 04 : 00 Reserved Reserved 00000b Table 16-17.Offset 53h: CFGNS1 - Configuration 1 (Non-Sticky) Register (Sheet 1 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 53h 53h Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 02 Reserved Reserved 000b

01 THWO

Throttled-Write Occurred: 0 = Writing a zero clears this bit. 1 = This bit is set by hardware when a write is throttled. This happens when the maximum allowed number of writes has been reached during a time-slice and there is at least one more write to be completed. 0b RW0C

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16.1.1.16 Offset 58h: FDHC - Fixed DRAM Hole Control Register

This 8-bit register controls a fixed DRAM hole from 15–16 Mbytes.

00 THRO

Throttled-Read Occurred: 0 = Writing a zero clears this bit. 1 = This bit is set by hardware when a read is throttled. This happens when the maximum allowed number of reads has been reached during a time-slice and there is at least one more read to be done. 0b RW0C Table 16-17. Offset 53h: CFGNS1 - Configuration 1 (Non-Sticky) Register (Sheet 2 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 53h 53h Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Table 16-18. Offset 58h: FDHC - Fixed DRAM Hole Control Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 58h 58h Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

07 HEN

Hole Enable: This field enables a memory hole in DRAM space. The DRAM that lies “behind” this space is not remapped. 0 = No memory hole 1 = Memory hole from 15–16 Mbytes. Accesses in this range are sent to NSI. 0b RW 06 : 00 Reserved Reserved 00h

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16.1.1.17 Offset 59h: PAM0 - Programmable Attribute Map 0 Register

This register controls the read, write, and shadowing attributes of the BIOS area from 0F0000h-0FFFFFh. See Section 19.0.3, “PAM Memory Spaces” for more information on PAM memory spaces. Table 16-19.Offset 59h: PAM0 - Programmable Attribute Map 0 Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 59h 59h Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 06 Reserved Reserved 00b 05 : 04 HIENABLE Attribute Register: This field controls the steering of read and write cycles that address the BIOS area from 0F0000 to 0FFFFF. Encoding Description: 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write-Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. 00b RW 03 : 00 Reserved Reserved 0h

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16.1.1.18 Offset 5Ah: PAM1 - Programmable Attribute Map 1 Register

This register controls the read, write, and shadowing attributes of the BIOS areas from 0C0000h-0C7FFFh. Table 16-20.Offset 5Ah: PAM1: Programmable Attribute Map 1 Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 5Ah 5Ah Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 06 Reserved Reserved 00b 05 : 04 HIENABLE Attribute Register 0C4000-0C7FFF: This field controls the steering of read and write cycles that address the BIOS area from 0C4000 to 0C7FFF Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write-Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. 00b RW 03 : 02 Reserved Reserved 00b 01 : 00 LOENABLE Attribute Register 0C0000-0C3FFF: This field controls the steering of read and write cycles that address the BIOS area from 0C0000 to 0C3FFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write-Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. 00b RW

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16.1.1.19 Offset 5Bh: PAM2 - Programmable Attribute Map 2 Register

This register controls the read, write, and shadowing attributes of the BIOS areas from 0C8000h-0CFFFFh. Table 16-21.Offset 5Bh: PAM2 - Programmable Attribute Map 2 Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 5Bh 5Bh Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 06 Reserved Reserved 00b 05 : 04 HIENABLE Attribute Register 0CC000-0CFFFF: Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write-Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. 00b RW 03 : 02 Reserved Reserved 00b 01 : 00 LOENABLE Attribute Register 0C8000-0CBFFF: This field controls the steering of read and write cycles that address the BIOS area from 0C8000 to 0CBFFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. A writes are forwarded to NSI. 1 0 Write-Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. 00b RW

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16.1.1.20 Offset 5Ch: PAM3 - Programmable Attribute Map 3 Register

This register controls the read, write, and shadowing attributes of the BIOS areas from 0D0000h-0D7FFFh. Table 16-22. Offset 5Ch: PAM3 - Programmable Attribute Map 3 Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 5Ch 5Ch Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 06 Reserved Reserved 00b 05 : 04 HIENABLE Attribute Register 0D4000-0D7FFF: This field controls the steering of read and write cycles that address the BIOS area from 0D4000 to 0D7FFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. 00b RW 03 : 02 Reserved Reserved 00b 01 : 00 LOENABLE Attribute Register 0D0000-0D3FFF: This field controls the steering of read and write cycles that address the BIOS area from 0D0000 to 0D3FFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. 00b RW

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16.1.1.21 Offset 5Dh: PAM4 - Programmable Attribute Map 4 Register

This register controls the read, write, and shadowing attributes of the BIOS areas from 0D8000h-0DFFFFh. Table 16-23.Offset 5Dh: PAM4 - Programmable Attribute Map 4 Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 5Dh 5Dh Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 06 Reserved Reserved 00b 05 : 04 HIENABLE Attribute Register 0DC000-0DFFFF: This field controls the steering of read and write cycles that address the BIOS area from 0DC000 to 0DFFFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. 00b RW 03 : 02 Reserved Reserved 00b 01 : 00 LOENABLE Attribute Register 0D8000-0DBFFF: This field controls the steering of read and write cycles that address the BIOS area from 0D8000 to 0DBFFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. 00b RW

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16.1.1.22 Offset 5Eh: PAM5 - Programmable Attribute Map 5 Register

This register controls the read, write, and shadowing attributes of the BIOS areas from 0E0000h-0E7FFFh. Table 16-24.Offset 5Eh: PAM5 - Programmable Attribute Map 5 Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 5Eh 5Eh Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 06 Reserved Reserved 00b 05 : 04 HIENABLE Attribute Register 0E4000-0E7FFF: This field controls the steering of read and write cycles that address the BIOS area from 0E4000 to 0E7FFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. 00b RW 03 : 02 Reserved Reserved 00b 01 : 00 LOENABLE Attribute Register 0E0000-0E3FFF: This field controls the steering of read and write cycles that address the BIOS area from 0E0000 to 0E3FFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI. 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI. 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI. 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM. 00b RW

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16.1.1.23 Offset 5Fh: PAM6 - Programmable Attribute Map 6 Register

This register controls the read, write, and shadowing attributes of the BIOS areas from 0E8000h-0EFFFFh.

16.1.1.24 Offset 9Ch: DEVPRES - Device Present Register

The Device Present bits can be used to enable/disable devices within the IMCH and make their PCI configuration space respectively visible/invisible to software. The Device Present bits convey when cleared that the corresponding device is never available. When a bit is 0, the configuration space associated with that device is hidden, returning all 1’s for all configuration register reads just as if the cycle terminated with a master abort on PCI. For the two PCIe* devices listed the I/O buffers and compensation associated with those devices are disabled and tri-stated. When a bit is 1, the configuration space associated with that device is accessible. For the two PCIe* devices the I/O buffers and compensation are enabled. Note: BIOS should write this register as part of its power on configuration sequence. Bits within this register are broken into two categories “RWO or RO” and “RW” and are functionally defined below. Table 16-25.Offset 5FH: PAM6 - Programmable Attribute Map 6 Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 5Fh 5Fh Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 06 Reserved Reserved 00b 05 : 04 HIENABLE Attribute Register 0EC000-0EFFFF: This field controls the steering of read and write cycles that address the BIOS area from 0EC000 to 0EFFFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM 00b RW 03 : 02 Reserved Reserved 00b 01 : 00 LOENABLE Attribute Register 0E8000-0EBFFF: This field controls the steering of read and write cycles that address the BIOS area from 0E8000 to 0EBFFF. Encoding Description 0 0 DRAM Disabled - All accesses are directed to NSI 0 1 Read-Only - All reads are serviced by DRAM. All writes are forwarded to NSI 1 0 Write Only - All writes are sent to DRAM. Reads are serviced by NSI 1 1 Normal DRAM Operation - All reads and writes are serviced by DRAM 00b RW

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“RWO or RO” bits: All of the “RWO or RO” bits in this register are gated with a SKU value. The SKU value has priority over values written by software. This means that if the SKU value of this bit is set to a 0, neither a configuration write or a reset sets this bit. If a SKU value is not present then the register will have RO access. When a SKU value is not present, the device is invisible to software. Writes to this register when the SKU value is not present, will have no effect, always returning ‘0’ when read. If a SKU value is present the register will have RWO access. Note: BIOS must write a bit to a 0 to disable a device, or a 1 to enable a device. This register can only be written once. After the first write, the register is locked. Note: RWO Devices that are disabled via software can only be re-enabled via a reset. This register should only be written to at boot time when there is no traffic to or from the PEA. Once software or BIOS has written these RWO register bits for the first time after power-up, the register value locks, and cannot be further updated. In other words, once software has disabled RWO devices, they can only be re-enabled via a reset. For RWO access bits the IMCH does not support turning off a device, and then turning it back on. (The reverse is also true: once software has enabled RWO devices, they can only be re-disabled via a reset.) RW bits: Two devices have RW bit access. These devices need to be enabled/disabled for power management during normal operation Table 16-26.Offset 9Ch: DEVPRES - Device Present Register (Sheet 1 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 9Ch 9Ch Size: 8 bit Default: 33h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 06 Reserved Reserved 0b

05 Reserved Reserved 1b RW

04 Device_4_Prese

0 = PCI-to-PCI Bridge is disabled. 1 = PCI-to-PCI Bridge is enabled. 1b RW

03 Device_3_Prese

0 = PCI Express* port A1 (x4) is disabled. In this state, port A (Device 2) can operate with a maximum x8 link width. 1 = PCI Express port A1 is enabled. In this state, port A can operate with a maximum x4 link width.When the SKU value is cleared, this field is read/write. When the SKU value is set, this field becomes a read-only ‘0’ 0b RWO or RO

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16.1.1.25 Offset 9Dh: EXSMRC - Extended System Management RAM Control

The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 MByte.

02 Device_2_Prese

0 = PCI Express port A is disabled. 1 = PCI Express port A is enabled.When the SKU value is cleared, this field is read/write. When the SKU value is set, this field becomes a read-only ‘0’ 0b RWO or RO

01 Device_1_Prese

0 = EDMA Controller is disabled. 1 = EDMA Controller is enabled. 1b RWO

00 Reserved Reserved 1b

Table 16-26.Offset 9Ch: DEVPRES - Device Present Register (Sheet 2 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 9Ch 9Ch Size: 8 bit Default: 33h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Table 16-27.Offset 9Dh: EXSMRC - Extended System Management RAM Control Register (Sheet 1 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 9Dh 9Dh Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

07 H_SMRAME

Enable High SMRAM: Controls the SMM memory space location (above 1 MByte or below 1 MByte) 0 = High SMRAM memory space is disabled. 1 = And G_SMRAME is 1, the high SMRAM memory space is enabled. SMRAM accesses within the range 0FEDA_0000h to 0FEDB_FFFFh are remapped to DRAM addresses within the range 000A0000h to 000BFFFFh. Once D_LCK (See Table 35) has been set, this bit becomes Read-Only. 0b RWL

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06 MDAP

MDA Present: This bit works with the VGA Enable bits in the BCTRL registers of Devices 2–3 to control the routing of CPU initiated transactions targeting MDA compatible I/O and memory address ranges. This bit should not be set if none of the VGA Enable bits are set. If none of the VGA enable bits are set, then accesses to IO address range x3BCh-x3BFh are forwarded to NSI. If the VGA enable bit is not set then accesses to IO address range x3BCh-x3BFh are treated just like any other IO accesses. For example, the cycles are forwarded to PEA[0:1] if the address is within the corresponding IOBASE and IOLIMIT and ISA enable bit is not set, otherwise they are forwarded to NSI. Note: Since the logic performs the address decoding on a DW boundary, the DW that includes the address 3BF also includes addresses 3BC, 3BD, and 3BE, and accesses to any of these byte addresses are handled as MDA references. MDA resources are defined as the following: Memory: 0B0000h - 0B7FFFh I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh, (Including ISA address aliases, A[15:10] are not used in decode) Note: The VGA region includes I/O space ranges 3B0- 3BBh, and 3C0-3DFh, so there is an overlap between these two I/O regions. Any I/O reference that includes the I/O locations listed above, or their aliases, are forwarded to NSI even if the reference includes I/O locations not listed above. The following table shows the behavior for all combinations of MDA and VGA: VGA MDA Behavior 0 0 All References to MDA and VGA go to NSI 0 1 Illegal Combination (DO NOT USE) 1 0 All References to VGA go to device with VGA enable set. MDA- only references (I/O address 3BF and aliases) go to NSI. 1 1 VGA-only references go to the PCI Express port which has its VGA Enable bit set. MDA references go to the NSI. 0b RW

05 APICDIS

APIC Memory Range Disable: 0 = The IMCH send cycles between 0_FEC0_0000 and 0_FEC7_FFFF to NSI, accesses between 0_FEC8_0000 and 0_FEC8_0FFF are sent to PEA0, between 0_FEC8_1000 and 0_FEC8_1FFF are sent to PEA1B. 1 = The IMCH forwards all accesses to the IOAPIC regions to NSI. 0b RW

04 Reserved Reserved 0b

03 G_SMRAME

Global SMRAM Enable: 0 = The Compatible SMRAM functions are disabled. 1 = The Compatible SMRAM functions are enabled, providing 128 Kbyte of DRAM accessible at the A0000h address while in SMM (ADS# with SMM decode). To enable Extended SMRAM function this bit has be set to 1. Refer to Section 16.1.1.26, “Offset 9Eh: SMRAM - System Management RAM Control Register” for more details. Once D_LCK (See Table 16-28) is set, this bit becomes read-only. 0b RWL Table 16-27.Offset 9Dh: EXSMRC - Extended System Management RAM Control Register (Sheet 2 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 9Dh 9Dh Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

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16.1.1.26 Offset 9Eh: SMRAM - System Management RAM Control Register

The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set. 02 : 01 TSEG_SZ TSEG Size: Selects the size of the TSEG memory block if enabled. Memory from the top of DRAM space (TOLM - TSEG_SZ) to TOLM is partitioned away so that it may only be accessed by the processor interface and only then when the SMM bit is set in the request packet. Non-SMM accesses to this memory region are specially terminated when the TSEG memory block is enabled. Note that once D_LCK (See Table 16-28) is set, these bits become Read- Only. 0 0 (TOLM – 128 k) to TOLM 0 1 (TOLM – 256 k) to TOLM 1 0 (TOLM – 512 k) to TOLM 1 1 (TOLM – 1 M) to TOLM 00b RWL

00 T_EN

TSEG Enable: Enabling of SMRAM memory for Extended SMRAM space only. 0 = SMRAM memory for Extended SMRAM space disabled. 1 = And G_SMRAME =1 and T_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Once D_LCK (See Table 16-28) is set, this bit becomes Read-Only. 0b RWL Table 16-27.Offset 9Dh: EXSMRC - Extended System Management RAM Control Register (Sheet 3 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 9Dh 9Dh Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Table 16-28.Offset 9Eh: SMRAM - System Management RAM Control Register (Sheet 1 of Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 9Eh 9Eh Size: 8 bit Default: 02h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

06 D_OPEN

SMM Space Open: 0 = The SMM space DRAM is not visible 1 = And D_LCK=0, the SMM space DRAM is made visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space. Software must ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. This bit becomes RO when D_LCK is set to 1. 0b RWL

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05 D_CLS

SMM Space Closed: 0 = SMM space DRAM is accessible to data references 1 = SMM space DRAM is not accessible to data references, even if SMM decode is active. Code references may still access SMM space DRAM. This allows SMM software to reference through SMM space to update the display even when SMM is mapped over the VGA range. Software must ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. Note: The D_CLS bit only applies to Compatible SMM space. 0b RW

04 D_LCK

SMM Space Locked: 0 = SMM space unlocked 1 = And then D_OPEN is reset to 0 and D_LCK, D_OPEN, H_SMRAME, TSEG_SZ and T_EN become Read-Only. D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a Full Reset. The combination of D_LCK and D_OPEN provide convenience with security. The BIOS can use the D_OPEN function to initialize SMM space and then use D_LCK to lock SMM space in the future so that no application software (or BIOS itself) can violate the integrity of SMM space, even if the program has knowledge of the D_OPEN function. 0b RWS 03 Reserved Reserved. 0b 02 : 00 C_BASE_SEG Compatible SMM Space Base Segment: This field indicates the location of SMM space. SMM DRAM is not remapped. It is simply made visible if the conditions are right to access SMM space, otherwise the access is treated as a VGA access. Since the IMCH supports only the SMM space between A0000 and BFFFF, this field is hardwired to 010. 010b RO Table 16-28. Offset 9Eh: SMRAM - System Management RAM Control Register (Sheet 2 of Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 9Eh 9Eh Size: 8 bit Default: 02h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

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16.1.1.27 Offset 9Fh: EXSMRAMC - Expansion System Management RAM Control

The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 MByte.

16.1.1.28 Offset B8h: IMCH_MENCBASE - IA/ASU Shared Non-Coherent (AIOC-

Direct) Memory Base Address Register Table 16-29.Offset 9Fh: EXSMRAMC - Expansion System Management RAM Control Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 9Fh 9Fh Size: 8 bit Default: 07h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

07 E_SMERR

Invalid SMRAM Access: 0 = CPU has not accessed the defined memory ranges in Extended SMRAM. 1 = This bit is set when CPU has accessed the defined memory ranges in Extended SMRAM (High Memory and T-segment) while not in SMM space and with the D-OPEN bit = 0. It is software’s responsibility to clear this bit. This bit is cleared by software writing a 1 to the bit location. 0b RWC 06 : 03 Reserved Reserved 0h 02 SM_CACHE SMRAM Cacheable: This bit is forced to 1 by IMCH. (Moved from ESMRAMC bit 5) 1b RO

01 SM_L1 L1 Cache Enable for SMRAM: This bit is forced to 1 by

IMCH. (Moved from ESMRAMC bit 4) 1b RO

00 SM_L2 L2 Cache Enable for SMRAM: This bit is forced to 1 by

IMCH. (Moved from ESMRAMC bit 3) 1b ROTable 16-30.Offset B8h: IMCH_MENCBASE: IA/ASU Shared Non-Coherent (AIOC-Direct) Memory Base Address Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: B8h BBh Size: 32 bit Default: 000FFFFFh Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 20 Reserved Reserved 000h 19 : 00 MENCBASE IA/ASU Shared Non-Coherent Memory Base Address Bits[31:12]: Specifies the address of the lower boundary of the IA/ASU shared non-coherent window in 32-bit system address space. The window is 4KB-aligned and inclusive of this address. This register field specifies bits[31:12] of the address; bits[11:0] are assumed zeros given 4KB alignment. FFFFFh RW

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16.1.1.29 Offset BCh: IMCH_MENCLIMIT - IA/ASU Shared Non-Coherent (AIOC-

Direct) Memory Limit Address Register

16.1.1.30 Offset C4h: TOLM - Top of Low Memory Register

This register contains the maximum address below 4 Gbyte that must be treated as a memory access and is defined on a 128 Mbyte boundary. Usually it is below the areas configured for PCI Express, NSI, and PCI memory. The memory address found in DRB3 reflects the amount of total memory populated. Table 16-31.Offset BCh: IMCH_MENCLIMIT - IA/ASU Shared Non-Coherent (AIOC-Direct) Memory Limit Address Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: BCh BFh Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 20 Reserved Reserved 00h 19 : 00 MENCLIMIT IA/ASU Shared Non-Coherent Memory Limit Address Bits[31:12]: Specifies the address of the upper boundary of the IA/ASU shared non-coherent window in 32-bit system address space. The window is 4KB-aligned and inclusive of this address. This register field specifies bits[31:12] of the address; bits[11:0] are assumed ones. Setting IMCH_MENCLIMIT less than IMCH_MENCBASE indicates a zero-sized window and thus that all memory is coherent. 00000h RW

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 415 Intel® EP80579 Integrated Processor Table 16-32.Offset C4h: TOLM - Top of Low Memory Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: C4h C5h Size: 16 bit Default: 0800h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 11 TOLM Top of Low Memory: This register corresponds to bits 31 to 27 of the system address which is 1 greater than the maximum DRAM location below 4 Gbyte. Configuration software must set this value to either the maximum amount of memory in the system or to the minimum address allocated for PCI memory or the graphics aperture, whichever is smaller. Address bits 26:00 are assumed to be 0 for the purposes of address comparison. Addresses equal to or greater than the TOLM, and less than 4 G, are treated as non-memory accesses. All accesses less than the TOLM are treated as DRAM accesses (except for the 15–16 Mbyte or PAM gaps). This register must be set to at least 0800h, for a minimum of 128 Mbyte of DRAM. There is also a minimum of 128 Mbyte of PCI space, since this register is on a 128 Mbyte boundary. Configuration software must set this value to either the maximum amount of memory in the system (same as DRB3), or to the lower 128 Mbyte boundary of the Memory Mapped IO range, whichever is smaller. Programming example: 1100_0b = 3 Gbyte (assuming that DBR7 is set > 4 Gbyte): An access to 0_C000_0000h or above (but <4 Gbyte) is considered above the TOLM and therefore not to DRAM. It may go to one of the PEA ports or NSI or be subtracted and decoded to NSI. An access to 0_BFFF_FFFFh and below is considered below the TOLM and go to DRAM. 00001b RW 10 : 00 Reserved Reserved 000h

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16.1.1.31 Offset C6h: REMAPBASE - Remap Base Address Register

Note: This register should not be enabled since the IA-32 core only supports 32-bit addressing.

16.1.1.32 Offset C8h: REMAPLIMIT – Remap Limit Address Register

Note: This register should not be enabled since the IA-32 core only supports 32-bit addressing. Table 16-33. Offset C6h: REMAPBASE - Remap Base Address Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: C6h C7h Size: 16 bit Default: 03FFh Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 10 Reserved Reserved 00h 09 : 00 REMAPBASE Remap Base Address Bits [35:26]: The value in this register defines the lower boundary of the Remap window. The Remap window is inclusive of this address. In the decoder A[25:0] of the Remap Base Address are assumed to be 0s. Thus the bottom of the defined memory range is aligned to a 64 Mbyte boundary. When the value in this register is greater than the value programmed into the Remap Limit register, the Remap window is disabled. This field defaults to 3FF. 3FFh RW Table 16-34. Offset C8h: REMAPLIMIT – Remap Limit Address Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: C8h C9h Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 10 Reserved Reserved 00h 09 : 00 REMAPLIMIT Remap Limit Address Bits [35:26]: The value in this register defines the upper boundary of the Remap window. The Remap window is inclusive of this address. In the decoder A[25:00] of the Remap Limit Address are assumed to be Fs. Thus the top of the defined range is one less than a 64 Mbyte boundary. When the value in this register is less than the value programmed into the Remap Base register, the Remap window is disabled. 00h RW

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16.1.1.33 Offset CAh: REMAPOFFSET - Remap Offset Register

This register contains the difference between the REMAPBASE and TOLM.Note: This register should not be enabled since the IA-32 core only supports 32-bit addressing.

16.1.1.34 Offset CCh: TOM - Top Of Memory Register

This register contains the effective size of memory. The value in this register hides any DIMMs that can’t be directly addressed. BIOS determines the memory size reported to the OS using this register. Table 16-35.Offset CAh: REMAPOFFSET - Remap Offset Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: CAh CBh Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 10 Reserved Reserved 00h 09 : 00 REMAPOFFST Remap Offset: This register contains the difference between the REMAPBASE and TOLM. This register value corresponds to address bits 35:26. It is used to translate the physical FSB address to the system memory address for accesses to the remap region. 000h RW Table 16-36.Offset CCh: TOM - Top Of Memory Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: CCh CDh Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 9 Reserved Reserved 00h 08 : 00 TOM Top of Memory: This register reflects the effective size of memory. These bits correspond to address bits 35:27. (128 Mbyte granularity) Bits 26:00 are assumed to be 0. 000h RW

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16.1.1.35 Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced

Configuration Base Address Register Configuration software reads this register to determine where the 256 Mbyte range of addresses resides for this particular host bridge. This register contains the base address of enhanced configuration memory.

16.1.1.36 Offset D8h: CACHECTL0 - Write Cache Control 0 Register

Table 16-37.Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced Configuration Base Address Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: CEh CFh Size: 16 bit Default: E000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 12 HECBASE PEA Enhanced Configuration Base: This register contains the address that corresponds to bits 31 to 28 of the base address for PEA enhanced configuration space below 4 Gbyte. Configuration software reads this register to determine where the 256 Mbyte range of addresses resides for this particular host bridge. BIOS needs to write this register at boot time. Settings 0 and F are not valid. When any byte or combination of bytes of this register is written, the register value locks down and cannot be further updated. 1110b RWO 11 : 00 Reserved Reserved. 000h Table 16-38.Offset D8h: CACHECTL0 - Write Cache Control 0 Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: D8h D8h Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 01 Reserved Reserved for other customer visible features. 00h RO

00 WCFLUSH

Write Cache Flush: 0 = Cleared by hardware when flush is complete. 1 = All entries in the write cache are flushed to DRAM with high priority. The arbiter no longer accepts requests until the write cache has been flushed. Software can poll this bit to determine when the flush is complete. 0b RWS

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16.1.1.37 Offset DEh: SKPD - Scratchpad Data Register

16.1.1.38 Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register

Table 16-39.Offset DEh: SKPD - Scratchpad Data Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: DEh DFh Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 00 SCRTCH Scratchpad: These bits are simply Read/Write storage bits that have no effect on the IMCH functionality. BIOS typically programs this register to the revision ID of the Memory Reference Code. 0000h RW Table 16-40.Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: F6h F6h Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

06 SYSMMREN

System Memory MMR Enable: 0 = This BAR is hardwired to all zeros (effectively disabling this memory space). 1 = The SM Memory Mapped Register space and corresponding Base Address Register (B:D:F:R 0,0,0,14H) is visible. Section 16.1.1.9, “Offset 14h: SMRBASE - System Memory RCOMP Base Address Register” 0b RW

05 NSIMMREN

NSI MMR Enable: 0 = The NSI Memory Mapped Register space is disabled, and does not claim any memory. (THE NSIBAR register is still read/write accessible.) 1 = The NSI Memory Mapped Register space is visible, and memory mapped accesses are claimed and decoded appropriately. (B:D:F:R 0,0,0,4CH) Section 16.1.1.12, “Offset 4Ch: NSIBAR - Root Complex Block Address Register” 0b RW 04 Reserved Reserved. 0b

03 Reserved Reserved 0b

02 Reserved Reserved 0b

01 Reserved Reserved 0b

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16.1.1.39 Offset 60h: DRB[0-3] – DRAM Row [3:0] Boundary Register

DRAM row boundary register defines the upper boundary address for each DRAM row with a granularity of 64MB. Each row has its own single byte DRB register. The value in a given DRB corresponds to the cumulative memory size including that row. For example, a value of 1 (0000 0001) in DRB0 (address lines 33 to 26) indicates that 64 Mbytes of DRAM has been populated in the first row. DRB0 = Total memory in row0 (64 Mbyte increments) DRB1 = Total memory in row0 + row1 (64 Mbyte increments) DRB2 = Total memory in row0 + row1 + row2 (64 Mbyte increments) DRB3 = Total memory in row0 + row1+ row2 + row3 (64 Mbyte increments) The functionality of DRB3 is somewhat different than DRB[2:0]. In order to avoid a 64MByte “hole” at the top of memory, a value of 0x00 in DRB3, is interpreted as 0x100. In practice, this 0x00 value should not be set, since it implies addressing more memory than the EP80579 supported. Note: The memory controller does not implement any hardware checks to prevent accesses to DRAM locations beyond what is populated in the DRB3 register. Such accesses are software programming errors and will result in unreliable operation. Table 16-41 shows the DRBx to DIMM mapping. Please note that before populating the DIMM’s, all limitation described in Section 11.3.1, “Rules for Populating DIMM Slots” need to be followed. Rules for programming the DRBx registers:

DRB1 and DRB3 are unused and reserved. — DRB1 and DRB3 should be programmed to be the same value as what was programmed in the even row. (DRB1 = DRB0, DRB3 = DRB2).
Unpopulated rows must be programmed with a value of the last populated slot. This guarantees the unpopulated row will not be selected.
Depending upon the configuration and amount of memory populated in each row, DRB0 and DRB2 should be programmed. This will correspond to on the EP80579, CS0# and CS1#. — Single rank, 1 DIMM system programs DRB0 with the encoding for memory capacity in row 0. Further, DRB1 = DRB2 = DRB3 = DRB0. — Single ranks in a 2 DIMM system programs DRB0 with the encoding for memory capacity in row 0 and DRB2 with the encoding for memory capacity in row 0 + row 1 + row 2. Further, DRB1 = DRB0 and DRB3 = DRB2. Table 16-41. DRB to DIMM designation Even Row Odd Row Row/DRB Number Address or DRB Row/DRB Number Address or DRB DIMM0 DRB0 60h DRB2 62h DIMM1 DRB2 62h NA NA

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 421 Intel® EP80579 Integrated Processor — Single DIMM with dual ranks should program DRB0 with the encoding for memory capacity in row 0 and DRB2 with the encoding for memory capacity in row 0 + row 1 + row 2. Further, DRB1 = DRB0 and DRB3 = DRB2.

It must always be the case with the EP80579 memory controller that for single rank, 1 DIMM systems, DRB0 = DRB1 = DRB2 = DRB3 and for all other configurations, DRB0 = DRB1 < DRB2 = DRB3. Table 11-7, “Supported Rank Configurations in Single and Dual DIMM mode” on page 293 shows the mapping of the chip selects in the different legal rank populations on the EP80579. Note: DRB0=DRAM Row 0, DRB1=DRAM Row 1, etc.

16.1.1.40 Offset 70h: DRA[0-1] – DRAM Row [0:1] Attribute Register

The DRAM Row Attribute register defines the DRAM technology. DRA is used to calculate the address mapping for column and row addresses as a function of DRAM technology specified in the DTYPE, DW and DIMMTECH fields.

DRA0 describes characteristics of rows 0 (even) and 1 (odd).
DRA1 describes characteristics of rows 2 (even) and 3 (odd).
Due to the rules of the EP80579 DDR configuration, many fields of DRA0 and DRA1 are not meaningful (they exist only for backward compatibility). For most configurations, the values in DRA0[DW_EVEN] and DRA0[DIMMTECH_EVEN] are used. An exception is DRA1[DIMMTECH_EVEN] which is used to select the size of the devices on the second DIMM of a two DIMM system. See Table 16-43 for details.
Bit fields that are not valid because the rank (or row) is not populated should not be changed. For such fields the reset value should be the benign state.
The controller determines which of rows are populated after decoding the DRB registers. Please see Section 16.1.1.39, “Offset 60h: DRB[0-3] – DRAM Row [3:0] Boundary Register” for more details. Note: All fields of the DRA[1:0] register need to be consistent or else unreliable operation will occur. For example the value programmed in NC_ODD should be consistent with the DIMMTECH_ODD field. The number of columns depends on the device technology. Table 16-42.Offset 60h: DRB[0-3] - DRAM Row [3:0] Boundary Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 60h at 1h 60h at 1h Size: 8 bit Default: ffh Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 :00 DRAM_RBA DRAM Row Boundary Address: This 8 bit value defines the upper address for each row of DRAM rows. This 8 bit value is compared against a set of address lines to determine the upper address limit of a particular row. This field corresponds to bits 33:26of the system address. Nf f h R W

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Table 16-43.DRA[1:0] Field Selection Case DRA0 [DTYPE_ MSB] Address Value used for DIMMTECH Value used for num_column /num_row Value used for DW Value used for DTYPE

1 DIMM, single

rank 0 (single rank) any address up to DRB0 limit DRA0 [DIMMTECH_EV EN] DRA0 [NC_EVEN/ NR_EVEN] DRA0 [DW_EVEN] DRA0 [DTYPE]

1 DIMM, dual

1 (dual rank) any address up to DRB0 limit DRA0 [DIMMTECH_EV EN] DRA0 [NC_EVEN/ NR_EVEN] DRA0 [DW_EVEN] DRA0 [DTYPE] 1 (dual rank) any address between DRB0 and DRB2 limit DRA0 [DIMMTECH_EV EN] DRA0 [NC_EVEN/ NR_EVEN] DRA0 [DW_EVEN] DRA0 [DTYPE]

2 DIMMs, (one

rank each) 0 (single rank per DIMM) any address up to DRB0 limit DRA0 [DIMMTECH_EV EN] DRA0 [NC_EVEN/ NR_EVEN] DRA0 [DW_EVEN] DRA0 [DTYPE] 0 (single rank per DIMM) any address between DRB0 and DRB2 limit DRA1 [DIMMTECH_EV EN] DRA1 [NC_EVEN/ NR_EVEN] DRA0 [DW_EVEN] DRA0 [DTYPE] Table 16-44. Offset 70h: DRA[0-1] - DRAM Row [0:1] Attribute Register (Sheet 1 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 70h at 4h 73h at 4h Size: 32 bit Default: 00000515h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 :29 NR_ODD Number of Rows for odd numbered row. Functionality and encoding is exactly the same as NR_EVEN N 000b RW 28 :26 NC_ODD Number of Columns for odd numbered row. Functionality and encoding is exactly the same as NC_EVEN N 000b RW 25 :23 NR_EVEN Number of Rows for even numbered row: This information is used by the Mbist engine. Note that this field should be programmed to be consistent with the DIMMTECH fields of the DRA register. N 000b RW 000 8192 001 16,384 010 32,768 011 65,536 Others Reserved

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 423 Intel® EP80579 Integrated Processor 22 :20 NC_EVEN Number of Columns for even numbered row. This information is used by the Mbist engine. Note that this field should be programmed to be consistent with the DIMMTECH fields of the DRA register. N 000b RW 19 :18 Reserved Reserved N 00b RO 17 :14 DTYPE Device Type: Bios sets these bits according to information read pertaining to the DIMMs installed bit 17: single or dual rank DIMM (0=single rank per DIMM) bit 16: DDR2 (0=DDR2) bit 15: 32 or 64 bit DDR populated (0=64bits) bit 14: unbuffered or registered DIMM (0=unbuffered) N 0000b RW 13 :12 Reserved Reserved N 00b RO 11 :10 DWODD Device Width for odd-numbered row: Functionality and encoding is exactly the same as DWEVEN. This value should be set to exactly the same as DWEVEN. N 01b RW 09 :06 DIMMTECH_OD D DIMM technology for odd-numbered row. Functionality and encoding is exactly the same as DIMMTECH_EVEN (bits 3:0) N 0100b RW 05 :04 DWEVEN Device Width for even-numbered row: BIOS sets this bit according to the width of the DDR2 SDRAM devices populated in this row. This is used to determine the page size and the DQS to DQ signal mapping. 00 = Reserved 01 = x8 DDR2 (1 strobe pair per byte) 10 = Reserved 11 = Reserved N 01b RW 03 :00 DIMMTECH_EV EN DIMM technology for even-numbered row: BIOS sets this bit according to the density of the DDR devices populated in this row. This is used along with the device width and the DTYPE to determine the page size and the DQS to DQ signal mapping. 0000 = reserved 0011 = 2Gb DIMM 0100 = 1Gb DIMM 0101 = 512Mb DIMM 0110 = 256Mb DIMM others - reserved N 0101b RW Table 16-44.Offset 70h: DRA[0-1] - DRAM Row [0:1] Attribute Register (Sheet 2 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 70h at 4h 73h at 4h Size: 32 bit Default: 00000515h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 000 1024 001 2048 010 4096 011 8192 Others Reserved

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16.1.1.41 Offset 78h: DRT0 - DRAM Timing Register 0

The DRT register defines the DRAM timing parameter. For the EP80579, there are 2 DRT registers that need to be programmed based on the external capabilities of the memory devices, number of ranks/DIMM’s, supported EP80579 memory configurations etc. For details about the DRT1 register see “Offset 64h: DRT1 – DRAM Timing Register 1” on page 431. Table 16-45. Offset 78h: DRT0 - DRAM Timing Register 0 (Sheet 1 of 7) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 78h 7Bh Size: 32 bit Default: 242AD280h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 :29 BTBRWTA Back-To-Back Read-Write Turn Around: This field determines the minimum number of CMDCLK on the DQ bus between Read-Write commands. It applies to RD-WR pairs to any destinations (in same or different rows). The purpose of this bit is to control the turnaround time on the DQ bus. The encoding below will be translated by the hardware into a number of CMDCLK’s that will be inserted between read write commands. N 001b RW Encoding Command Clocks per Frequency 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 425 Intel® EP80579 Integrated Processor 28 :26 BTBRTA Back To Back Read Turn Around: This field determines the minimum number of CMDCLK on the DQ bus between two reads destined to different ranks. The purpose of these bits is to control the turnaround time on the DQ bus. The encoding below will be translated by the hardware into a number of CMDCLK’s that will be inserted between read write commands. N 001b RW 25 :23 BBWRTA Back to Back Write-Read turn around: This field determines the minimum number of CMDCLK on the DQ bus between Write-Read commands. The purpose of these 3 bits are to control the turnaround time on the DQ bus. The encoding below will be translated by the hardware into a number of CMDCLK’s that will be inserted between read write commands. Command clocks apart based on the following encoding: N 000b RW Table 16-45.Offset 78h: DRT0 - DRAM Timing Register 0 (Sheet 2 of 7) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 78h 7Bh Size: 32 bit Default: 242AD280h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Encoding Command Clocks per Frequency 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 Encoding Command Clocks per Frequency 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7

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22 :20 Trrd Row Delay: The required row delay period between two activate commands accessing the same cs of a DIMM in tCK cycles. JEDEC recommendation for this parameter is based on the device width. x8 devices = 7.5ns N 010b RW 19 :17 Twr Write Recovery Delay: The required write recovery delay before being able to issue a precharge to the same page accessing the same cs/bank of a DIMM in tCK cycles. JEDEC recommendation for this parameter is 15ns min. N 101b RW Table 16-45. Offset 78h: DRT0 - DRAM Timing Register 0 (Sheet 3 of 7) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 78h 7Bh Size: 32 bit Default: 242AD280h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Encoding Number of CMDCLK delays

000 No delay

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 427 Intel® EP80579 Integrated Processor 16 :12 Trc This bit controls the number of DRAM clocks to enforce as the RAS cycle time. N 01101b RW Table 16-45.Offset 78h: DRT0 - DRAM Timing Register 0 (Sheet 4 of 7) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 78h 7Bh Size: 32 bit Default: 242AD280h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Encoding Number of CMDCLK delays 00000 11 00001 12 00010 13 00011 14 00100 15 00101 16 00110 17 00111 18 01000 19 01001 20 01010 21 01011 22 01100 23 01101 24 01110 25 01111 26 10000 27 10001 28 10010 29 Others Reserved

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11 :09 Trcd DRAM RAS# to CAS# delay: This bits controls the number of clocks inserted between a row activate command and a read or write command to that row N 001b RW 8: 0 6 T r p DRAM RAS# Precharge: Time: the number of clock cycles needed to terminate access (precharge) to an open row of memory, and open access (activate) to the next row. N 010b RW Table 16-45. Offset 78h: DRT0 - DRAM Timing Register 0 (Sheet 5 of 7) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 78h 7Bh Size: 32 bit Default: 242AD280h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Encoding Number of CMDCLK delays 000 3 001 4 010 5 011 6 Others ReservedEncoding Number of CMDCLK delays 000 3 001 4 010 5 011 6 Others Reserved

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 429 Intel® EP80579 Integrated Processor 5: 0 3 C L CAS# Latency: The number of clocks between the rising edge used by DRAMS to sample the Read Command and the rising edge that is used by the DRAM to drive read data. DDR2 JEDEC Spec: Write latency (WL) is defined by a read latency (RL) minus one. Please refer to the DDR2 JEDEC Spec for more details. N 000b RW Table 16-45.Offset 78h: DRT0 - DRAM Timing Register 0 (Sheet 6 of 7) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 78h 7Bh Size: 32 bit Default: 242AD280h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Encoding Number of CMDCLK delays 000 3 001 4 010 5 011 6 Others Reserved

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2 :00 PRGRPD Programmable Read Pointer Delay: This bit field determines the read delay, which is based on both DIMM topology and technology. The round trip timing budget has been estimated to be about 11.5 ns. Since an encoding of “000” means less than one command clock, the encoding values in this table refer to additional delays beyond one command clock. Note that the PRGRPD encoding shown below is for 4 bits. The 4 bits are formed by concatenating DRT1[0] and DRT0[2:0]. Please refer to Section 16.1.1.42 for details on the DRT1 register. N 000b RW Table 16-45. Offset 78h: DRT0 - DRAM Timing Register 0 (Sheet 7 of 7) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 78h 7Bh Size: 32 bit Default: 242AD280h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access PRGRPD[3:0] Encoding Number of CMDCLK delaysDRT1[0], DRT0[2:0] 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 Others Reserved

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16.1.1.42 Offset 64h: DRT1 – DRAM Timing Register 1

This register controls the DRAM timing parameters. For details about the DRT1 register see “Offset 78h: DRT0 - DRAM Timing Register 0” on page 424. Table 16-46.Offset 64h: DRT1 - DRAM timing Register 1 (Sheet 1 of 4) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 64h 67h Size: 32 bit Default: 12110000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 :28 tRAS (Time for activation / RAS Active Strobe): time to activate a row of a bank (minimum time bank stays open before it can be closed/precharged again) SW needs to program this parameter based on the DDR speed as shown in the table below. Note however that the HW will use a different tRAS value when the DDR commands are generated by the Mbist Engine. During all other modes the controller will use the tRAS value programmed in this field. N 0001b RW 27 :25 tRTP RAS to Precharge (needed to calculate Read AutoPrecharge delay) N 001b RW DDR Speed Encoding # of CMD clks Tras value used by Mbist 400 0000 8 (40ns) 12 400 0001 9 (45ns) 12 533 0100 12 (45ns) 12 667 0111 15 (45ns) 15 800 1000 16 (40ns) 18 800 1010 18 (40ns) 18 Encoding Number of CMDCLK delays 000 2 001 3 010 4 011 5 Others Reserved

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24 :20 tFAW 8 bank device Sequential Bank Activation Restriction: No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW(ns) by tCK(ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command. This field is not valid for 4 banks device technologies like 256Mb x8 and 512 x8. JEDEC recommendations: 1KB Page size = 37.5ns 2KB Page size = 50ns N 00001b RW Table 16-46. Offset 64h: DRT1 - DRAM timing Register 1 (Sheet 2 of 4) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 64h 67h Size: 32 bit Default: 12110000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Encoding Number of CMDCLK delays

00000 No restriction

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 433 Intel® EP80579 Integrated Processor 19 :18 tCCD CAS to CAS Delay Note: set tCCD to 2 clock delay for Burst of 4 (64 bit wide data interface) or set tCCD to 4 clock delay for Burst of 8 (32 bit wide data interface). N 00b RW 17 :15 tWTR Internal Write to Read command delay, at least 2 x tCK and independent of operating frequency JEDEC recommendations for DDR2 400MTS = 10ns Others = 7.5ns N 010b RW 14 :13 BLEN Burst length N 00b RW Table 16-46.Offset 64h: DRT1 - DRAM timing Register 1 (Sheet 3 of 4) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 64h 67h Size: 32 bit Default: 12110000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Encoding Number of CMDCLK delays 00 2 10 4 Others Reserved Encoding Number of CMDCLK delays (DDR2 64 bit data width) (DDR2 32 bit data width)

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12 :12 2Tor1T 2T or 1T timing on the command bus to DRAM devices. N0 b R W 11 :04 NOPCNT Programmable NOP insertion: Number of NOPs will be inserted between read/write commands to slow down Membist activities in the same page. Up to 255 clocks NOPs can be programmed to insert delay between read/write commands. If NOPs delay is programmable less than the required DRAM timing, Overall NOP delay from command to command will not be seen. N0 0 h R W 03 :01 BTBWTA Back-To-Back Write Turn Around: This field determines the data bubble duration between write data bursts. It applies to WR-WR pairs to different ranks, and is only expected to be used in DDR2 mode with ODT enabled in the event that ODT selections must change between ranks. The purpose of this field is to control the data burst spacing on the DQ bus. The encoding below will be translated by the hardware into a number of CMDCLK’s that will be inserted between read write commands. N 000b RW 0 :0 PRGRPD_4 Bit[3] of the Programmable Read Pointer Delay field. Please refer to DRT0[2:0] for more details on this bit field (Section 16.1.1.41). N0 b R W Table 16-46. Offset 64h: DRT1 - DRAM timing Register 1 (Sheet 4 of 4) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 64h 67h Size: 32 bit Default: 12110000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Encoding Timing 01 T 12 T Encoding Number of CMDCLK delays 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7

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16.1.1.43 Offset 7Ch: DRC – DRAM Controller Mode Register

This register controls the mode of the DRAM controller. Table 16-47.Offset 7Ch: DRC - DRAM Controller Mode Register (Sheet 1 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 7Ch 7Fh Size: 32 bit Default: 00000002h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 :31 CKE1 This bit controls the value that will be driven on the CKE[1] pin. Note however that CKEPNM bit in this CSR can override and force low the state of both CKE[1:0] pins regardless of the state of this bit. BIOS can write to this CSR bit to directly control the state of the CKE pin. HW will update the state of this bit based on self-refresh exit command.

0 Drive CKE[1] low, de-activates DRAM devices

1 Drive CKE[1] asserted, activates DRAM devices

This bit controls the value that will be driven on the CKE[0] pin. Note however that CKEPNM bit in this CSR can override and force low the state of both CKE[1:0] pins regardless of the state of this bit. BIOS can write to this CSR bit to directly control the state of the CKE pin. HW will update the state of this bit based on self-refresh exit command.

0 Drive CKE[0] low, de-activates DRAM devices

1 Drive CKE[0] asserted, activates DRAM devices

0 = Initialization Complete: This bit is used for communication of software state between the memory controller and the BIOS. DRAM interface has not been initialized. 1 = DRAM interface has been initialized. N0 b R W 28 :22 Reserved Reserved N 0000000b RO 21 :20 DDIM DRAM Data Integrity Mode: These bits select DRAM data integrity modes. When in non-ECC mode no ECC correction is done and no ECC errors are logged in the FERR/NERR registers.

00 Non-ECC mode

01 ECC enabled

10 Reserved

11 Reserved

19 :14 Reserved Reserved N 0b RO

13 HLDDIS

Command/address hold disable Disabling hold will allow the address and bank address pins to revert to all zeros during idle cycles. When hlddis is clear, the addresses retain the value of the last non-idle command cycle in order to reduce switching on the bus. 0 = disabled, 1 enabled Y0 b R W

12 CADIS

DDR Command/address pin output disable: This bit controls Address, bank address, CAS, RAS, WE. 0 = Enabled 1 = Disabled Y0 b R W

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11 :10 CSDIS DDR Chip select output disable bit[11] = CS[1] bit[10] = CS[0] 0 = Enabled 1 = Disabled Y 00b RW 9 9 Reserved Reserved N 0b RO 7 8 Reserved_2 Reserved_RW_Sticky Y 00b RW 06 :05 ODTDIS DRAM ODT Disable: bit[5] = ODT[0] bit[6] = ODT[1] 0 = Enables the use of ODT when running 1 = Disables (tristates) the use of ODT when running Y 00b RW 04 04 CKEPNM CKE pin mode: 0 = Force low. Forces the state of CKE[1:0] low. When this bit is cleared it over-rides all functionality that drives the CKE pin and forces it low. SW needs to set this bit for normal operation 1 = Enable CKE[1:0]. BIOS will set this bit to a 1 for normal operating mode. Y0 b R W 3: 0 D S The PLL only supports one update of ratio (the lower nibble of this register). This register defaults to DDR2-400 This field reflects BIOS selection of DDR speed, which may have been “down-binned” due to fuse settings (see SDRC.FUSESPEED) Y 0010b RWO Table 16-47.Offset 7Ch: DRC - DRAM Controller Mode Register (Sheet 2 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 7Ch 7Fh Size: 32 bit Default: 00000002h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Encoding DDR Data Speed (MT/s) DDR CMD Freq (Mhz) 0x10 400 200 Default 0x00 533 266 0111 667 333 0101 800 400 Others Reserve d

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16.1.1.44 Offset 84h: ECCDIAG – ECC Detection/Correction Diagnostic Register

The MEMPEN bit of this register controls if the memory controller poisons write data to the DRAM when it detects a parity error on its interface. By default, this bit is clear and the memory controller will not poison the write data to DRAM when it detects a parity error on its interface. If MEMPEN is set, and a write transaction with bad parity is sent to memory controller from either IMCH or AIOC, the write to DDR will be poisoned as follows: each bit of ECC will be flipped from the value otherwise calculated for that data write, based on the “bad” data sent from either IMCH or AIOC. Table 16-48.Offset 84h: ECCDIAG - ECC Detection/Correction Diagnostic Register (Sheet 1 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 84h 87h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 :21 Reserved Reserved N 000b RO 20 20 FECCDT Flip ECC on all data transfers: Flip the designated ECC bits (bits 15:00) on all data transfers to DRAM. If a cacheline is in progress when this register is written, wait until the start of the next cacheline to flip parity bits. Note that if FECCDT and MEMPEN is set and a bad parity is detected, the M_unit will poison and flip the ECC bits. N0 b R W 19 19 Reserved Reserved N 0b RO

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Memory Poison Enable: Allows for propagation of data errors not initiated by this feature to DRAM. Error injection via bit 20 is possible regardless of this bit setting. The setting of this bit has no effect on the reporting or logging of data errors. 0 = Error poisoning is disabled, data errors are not propagated, meaning that only good ECC is generated ECC mode even when bad parity is detected on its interface. 1 = Error poisoning enabled when in ECC mode. The memory controller will poison the write data to DRAM when it detects a parity error on its interface. N0 b R W 17 :16 DPRSL Data pair selector: This two-bit field selects which pair of quad-words in a cache line the inversion vector is applied against. Regardless of what operational mode the memory subsystem is in, this field always applies to the same QW pair. QW0 corresponds to data bits 63:00, QW1 to [127:64] … and QW7 corresponds to [511:448]

00 QW0 and QW1

01 QW2 and QW3

10 QW4 and QW5

11 QW6 and QW7

15 : 00 ECCBIN ECC bit invert vector: This vector operates individually for every ECC bit in the selected High or Low ECC block, during writes to DRAM. For all k between 0 and 15, when bit (k) set to 1, the value of the k ECC bit (which corresponds with the k data byte lane) is inverted. Otherwise, the value the k ECC bit is not affected. In other words, bits 15:08 are applied to the ECC vector of the high Qword in the selected pair, and bits 07:00 are applied to the ECC vector of the low Qword in the selected pair. For Example: Data Pair Selector bits 17:16 = 00 ECC bit invert vector bits 15:08 are applied to the ECC vector for QW1 ECC bit invert vector bits 07:00 are applied to the ECC vector for QW0 N 0000h RW Table 16-48.Offset 84h: ECCDIAG - ECC Detection/Correction Diagnostic Register (Sheet 2 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 84h 87h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

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16.1.1.45 Offset 88h: SDRC – DDR SDRAM Secondary Control Register

This register is used or setting memory controller parameters such as queue depths, scheduler parameters, arbiter parameters, AIOC and IA-32 core stream enabling, IA-32 core parity checking, bank remapping, etc. Table 16-49.Offset 88h: SDRC - DDR SDRAM Secondary Control Register (Sheet 1 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 88h 8Bh Size: 32 bit Default: 00000002h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 :30 ODTZENA1 On Die Termination Enable: These bits enable the EP80579 on die termination. ODT control for the DQ[71:64]/DQS[8] (ECC byte) buffers on the inbound read path. Y 00b RW 29 :28 ODTZENA On Die Termination Enable: These bits enable the EP80579 on die termination. ODT for the DQ[63:0]/DQS[7:0] buffers on the inbound read path Y 00b RW 27 :26 Reserved Reserved Y 00b 25 22 Reserved Reserved N 0x0b RW 21 :20 FUSESPEED Fuse Speed - Read only copy of the DDR speed fuse setting 00b - DDR-800 MTS 01b - DDR-667 MTS 10b - DDR-533 MTS 11b - DDR-400 MTS Nf u s e R O Encoding ODT

00 Disabled

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19 :17 DRRIRR Demand Scrub Retry (DRR) Injection Rate Regulator: This field determines the minimum rate at which DRRs will be scheduled to the DRAM. If multiple DRR’s are pending in the MC, they will be issued to the DRAM spaced apart by at least DRRIRR by the hardware. 000b - 4 DDR controller clock cycles (Default) Others - Reserved The only supported/validated value is 000b. Note: This feature should not be confused with DED retry feature that is not support by the EP80579. N 000b RW 16 16 DDRDIS Demand Scrub Retry (DRR) Disable: This bit by default is set to 0 to enable the demand scrub retry feature. When enabled any demand scrub writes that do not get scheduled to DRAM will be retried. When this bit is set, demand scrubs that are dropped will not be retried. Note: This feature should not be confused with DED retry feature that is not support by the EP80579. N0 b R W 15 :12 SCH_WGT Controls for weighted round robin scheduling when both IA and AIOC requests are posted for accessing the same bank. Selects the number of IA transfers consecutively selected instead of AIOC transfers when requests are posted from both, and from the same bank. Works in conjunction with eight 2 bit counter, one for each bank, which indicates how many IA transfers, from each bank, have been selected since the last AIOC transfer was selected form that bank. xx00 = choose AIOC command if AIOC and IA are both present, and the last 1 command selected was IA. If no IA commands are present, choose AIOC and reset 2 bit bank count of IA transfers for the selected bank. xx01 = choose AIOC command if AIOC and IA are both present, and the last 2 commands selected were IA. If no IA commands are present, choose AIOC and reset 2 bit bank count of IA transfers for the selected bank xx11 = choose AIOC command if AIOC and IA are both present, and the last 3 commands selected were IA. If no IA commands are present, choose AIOC and reset 2 bit bank count of IA transfers for the selected bank Otherwise = reserved N 0000b RW 11 mu_enable_aio ccmd Enable scheduler to pass AIOC transfers to DDR N 0b RW 10 mu_enable_bc md Enable scheduler to pass IMCH transfers to DDR N 0b RW 09 mu_enable_ecc rrwcmd Enable scheduler to pass internally generated demand scrubs (upon detection of single bit ECC error) transfers to DDR. Please also refer SDRC.DDRDIS for the Demand Scrub Retry Feature. In order to ensure that no demand scrubs are dropped, the DRR feature should be enabled. N0 b R W 08 mu_enable_bsc rubcmd Enable scheduler to pass internally generated background scrub transfers to DDR N0 b R W Table 16-49. Offset 88h: SDRC - DDR SDRAM Secondary Control Register (Sheet 2 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 88h 8Bh Size: 32 bit Default: 00000002h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

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16.1.1.46 Offset 8Ch: CKDIS – CK/CK# Clock Disable Register

This register is used to enable or disable the CK/CK# pins to the DIMMS. This feature is intended to reduce EMI and power consumption due to clocks toggling to DIMMs that are not populated. 07 : 00 ASU_CMDQSIZ E Size of command queue available to ASU The Scheduler implements a shared Command Queue which is nominally 64 entries deep. This queue is shared between ASU and IA traffic. In order to reserve some queue entries for IA commands only, software is able to set an upper limit on the number of ASU commands that can occupy this queue. If the number of ASU commands exceeds this programmed value, subsequent AIOC commands may be backed off by the memory controller, until ASU commands drain to DDR, and the number in the command queue, once again, falls below the programmed value. Recommended value is 0x30. Do not set this field to 0. N 00000010b RW Table 16-49.Offset 88h: SDRC - DDR SDRAM Secondary Control Register (Sheet 3 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 88h 8Bh Size: 32 bit Default: 00000002h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Table 16-50.Offset 8Ch: CKDIS - CK/CK# Clock Disable Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 8Ch 8Ch Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 7 :06 Reserved Reserved N 00b RO 05 :00 CKDIS CK/CK# Disable (Sticky) Each bit corresponds to a pair of CK pins. Default is enabled. 0 = Enable CK signals 1 = Disable CK signals. When disabled, the CK/CK# signals are tristated. Bit 5: Enable/Disable CK[5]/CK#[5] Bit 4: Enable/Disable CK[4]/CK#[4] Bit 3: Enable/Disable CK[3]/CK#[3] Bit 2: Enable/Disable CK[2]/CK#[2] Bit 1: Enable/Disable CK[1]/CK#[1] Bit 0: Enable/Disable CK[0]/CK#[0] Y 000000b RW

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16.1.1.47 Offset 8Dh: CKEDIS - CKE Clock Disable Register

This register is used to enable or disable the CKE pins to the DIMMS. Also see Section 16.1.1.43, “Offset 7Ch: DRC – DRAM Controller Mode Register” CSR that describes the CKEPNM bit that can force the CKE[1:0] pins low. Table 16-51.Offset 8Dh: CKEDIS - CKE Clock Enable Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 8Dh 8Dh Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 7 :03 Reserved Reserved N 00000b RO 02 02 CKE1DIS CKE1 Disable (Sticky) Bit corresponds CKE[1] pin. Default is enabled. 1 = Disable CKE[1] signals 0 = Enable CKE[1] signals. When disabled, the CKE[1] pin is tristated. Y0 b R W 01 01 Reserved Reserved N 0b RO 00 00 CKE0DIS CKE0 Disable (Sticky) Bit controls CKE[0] pin. Default is enabled. 1 = Disable CKE[0] signals 0 = Enable CKE[0] signals. When disabled, the CKE[0] pin is tristated. Y0 b R W

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16.1.1.48 Offset 90h: SPARECTL - SPARE Control Register

This register is used to set the prescale values for the leaky bucket error counting mechanism.

16.1.1.49 Offset B0h: DDR2ODTC - DDR2 ODT Control Register

The DDR2ODTC controls the behavior of the ODT[1:0] output pins. The ODT pins control the on-die termination on the DDR DRAM devices. (To control the ODT behavior on the EP80579 please refer to Section 11.4.3, “On-Die Termination (ODTZ) on the EP80579”.) The DDR2ODTC control register provides separate fields to control the ODT pin behavior for each of the four possible active cases: read to rank0, read to rank1, write to rank0, and write to rank1. Each field is two bits wide as there are two ODT pins on the EP80579. Please refer the different ODT configurations that the EP80579 supports as shown in Figure 11-4, “ODT Timing on Back-to-Back Reads to Different Slots” on page 300 and Figure 11-5, “ODT Timing on Back-to-Back Writes to Different Slots” on page 301. Table 16-52.Offset 90h: SPARECTL - SPARE Control Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: 90h 93h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 :24 DEDEPV DED error prescale value: Prescale value ranges from 0- 255. Y 00h RW 23 :16 SECEPV SEC error prescale value: Prescale value ranges from 0- 255. Y 00h RW 15 :12 DEDEPU DED error prescale unit:

0000 Never

0001 1 µs 0010 1 ms 0011 1 s 0100 1 minute 0101 1 hour 0110 1 day 0111 1 week 1XXX Never Y 0000b RW 11 :08 SECEPU SEC error prescale unit: 0001 1 µs 0010 1 ms 0011 1 s 0100 1 minute 0101 1 hour 0110 1 day 0111 1 week 1XXX Never Y 0000b RW 07 :00 Reserved Reserved N 00h RO

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Table 16-53. Offset B0h: DDR2ODTC - DDR2 ODT Control Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:0 Offset Start: Offset End: B0h B3h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 :14 Reserved Reserved N 0000h RO 13 12 R1ODTWR R1ODTWR: Value for logical ODT[1:0] for the case of write access to logical rank 1. N 00b RW 11 10 Reserved Reserved N 00b RO

98 R 1 O D T R D R1ODTRD:Value for logical ODT[1:0] for the case of read

access to logical rank 1. N 00b RW 7 6 Reserved Reserved N 00b RO 54 R 0 O D T W R R0ODTWR. Value for logical ODT[1:0] for the case of write access to logical rank 0. N 00b RW

32 R e s e r v e d N 00b RO

10 R 0 O D T R D R0ODTRD. Value for logical ODT[1:0] for the case of read access to logical rank 0. N 00b RW

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16.2 DRAM Controller Error Reporting Registers: Bus 0, Device

0, Function 1 The DRAM Controller Error Reporting registers are in Bus 0, Device 0, Function 1. Table 16-54 provides the register address map for this device and function. Warning: Address locations that are not listed are considered reserved register locations. Reads to reserved registers may return non-zero values. Writes to reserved locations may cause system failure. Note: Reserved bits are Read Only. Table 16-54.Bus 0, Device 0, Function 1: Summary of IMCH Error Reporting PCI Configuration Registers (Sheet 1 of 2) Offset Start Offset End Register ID - Description Default Value 00h 01h “Offset 00h: VID - Vendor Identification Register” on page 447 8086h 02h 03h “Offset 02h: DID - Device Identification Register” on page 447 5021h 04h 05h “Offset 04h: PCICMD - PCI Command Register” on page 448 0000h 06h 07h “Offset 06h: PCISTS - PCI Status Register” on page 448 0000h 08h 08h “Offset 08h: RID - Revision Identification Register” on page 449 Variable 0Ah 0Ah “Offset 0Ah: SUBC - Sub-Class Code Register” on page 449 00h 0Bh 0Bh “Offset 0Bh: BCC - Base Class Code Register” on page 449 FFh 0Dh 0Dh “Offset 0Dh: MLT - Master Latency Timer Register” on page 450 00h 0Eh 0Eh “Offset 0Eh: HDR - Header Type Register” on page 450 00h 2Ch 2Dh “Offset 2Ch: SVID - Subsystem Vendor Identification Register” on page 450 0000h 2Eh 2Fh “Offset 2Eh: SID - Subsystem Identification Register” on page 451 0000h 40h 43h “Offset 40h: GLOBAL_FERR - Global First Error Register” on page 451 00000000h 44h 47h “Offset 44h: GLOBAL_NERR - Global Next Error Register” on page 453 00000000h 48h 4Bh “Offset 48h: NSI_FERR - NSI First Error Register” on page 454 00000000h 4Ch 4Fh “Offset 4Ch: NSI_NERR - NSI Next Error Register” on page 457 00000000h 50h 53h “Offset 50h: NSI_SCICMD - NSI SCI Command Register” on page 459 00000000h 54h 57h “Offset 54h: NSI_SMICMD: NSI SMI Command Register” on page 461 00000000h 58h 5Bh “Offset 58h: NSI_SERRCMD - NSI SERR Command Register” on page 464 00000000h 5Ch 5Fh “Offset 5Ch: NSI_MCERRCMD - NSI MCERR Command Register” on page 466 00000000h 60h 61h “Offset 60h: FSB_FERR - FSB First Error Register” on page 468 0000h 62h 63h “Offset 62h: FSB_NERR - FSB Next Error Register” on page 469 0000h 64h 65h “Offset 64h: FSB_EMASK - FSB Error Mask Register” on page 470 0009h 68h 69h “offset 68h: FSB_SCICMD - FSB SCI Command Register” on page 471 0000h 6Ah 6Bh “Offset 6Ah: FSB_SMICMD - FSB SMI Command Register” on page 472 0000h 6Ch 6Dh “Offset 6Ch: FSB_SERRCMD - FSB SERR Command Register” on page 473 0000h 6Eh 6Fh “Offset 6Eh: FSB_MCERRCMD - FSB MCERR Command Register” on page 474 0000h 70h 70h “Offset 70h: BUF_FERR - Memory Buffer First Error Register” on page 475 00h 72h 72h “Offset 72h: BUF_NERR - Memory Buffer Next Error Register” on page 475 00h 74h 74h “Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register” on page 476 00h

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78h 78h “Offset 78h: BUF_SCICMD - Memory Buffer SCI Command Register” on page 477 00h 7Ah 7Ah “Offset 7Ah: BUF_SMICMD - Memory Buffer SMI Command Register” on page 478 00h 7Ch 7Ch “Offset 7Ch: BUF_SERRCMD - Memory Buffer SERR Command Register” on page 479 00h 7Eh 7Eh “Offset 7Eh: BUF_MCERRCMD - Memory Buffer MCERR Command Register” on page 480 00h E4h E7h “Offset E4h: NSIERRINJCTL - NSI Error Injection Control Register” on page 481 00040000h E8h EBh “Offset E8h: BERRINJCTL - Buffer Error Injection Control Register” on page 482 00000000h 80h 81h “Offset 80h: DRAM_FERR - DRAM First Error Register” on page 483 0000h 82h 83h “Offset 82h: DRAM_NERR - DRAM Next Error Register” on page 484 0000h 84h 84h “Offset 84h: DRAM_EMASK - DRAM Error Mask Register” on page 486 00h 88h 88h “Offset 88h: DRAM_SCICMD - DRAM SCI Command Register” on page 487 00h 8Ah 8Ah “Offset 8Ah: DRAM_SMICMD - DRAM SMI Command Register” on page 488 00h 8Ch 8Ch “Offset 8Ch: DRAM_SERRCMD - DRAM SERR Command Register” on page 489 00h 8Eh 8Eh “Offset 8Eh: DRAM_MCERRCMD - DRAM MCERR Command Register” on page 490 00h 98h 99h “Offset 98h: THRESH_SEC0 - Rank 0 SEC Error Threshold Register” on page 491 0000h 9Ah 9Bh “Offset 9Ah: THRESH_SEC1 - Rank 1 SEC Error Threshold Register” on page 491 0000h A0h A3h “Offset A0h: DRAM_SECF_ADD - DRAM First Single Bit Error Correct Address Register” on page 492 00000000h A4h A7h “Offset A4h: DRAM_DED_ADD - DRAM Double Bit Error Address Register” on page 492 00000000h A8h ABh “Offset A8h: DRAM_SCRB_ADD - DRAM Scrub Error Address Register” on page 493 00000000h B0h B1h “Offset B0h: DRAM_SEC_R0 - DRAM Rank 0 SEC Error Counter Register” on page 494 0000h B2h B3h “Offset B2h: DRAM_DED_R0 - DRAM Rank 0 DED Error Counter Register” on page 494 0000h B4h B5h “Offset B4h: DRAM_SEC_R1 - DRAM Rank 1 SEC Error Counter Register” on page 494 0000h B6h B7h “Offset B6h: DRAM_DED_R1 - DRAM Rank 1 DED Error Counter Register” on page 495 0000h C2h C3h “Offset C2h: THRESH_DED - DED Error Threshold Register” on page 495 0000h C4h C5h “Offset C4h: DRAM_SECF_SYNDROME - DRAM First Single Error Correct Syndrome Register” on page 496 0000h C6h C7h “Offset C6h: DRAM_SECN_SYNDROME - DRAM Next Single Error Correct Syndrome Register” on page 496 0000h C8h CBh “Offset C8h: DRAM_SECN_ADD - DRAM Next Single Bit Error Correct Address Register” on page 497 00000000h DCh DDh “Offset DCh: RANKTHREX - Rank Error Threshold Exceeded Register” on page 498 0000h ECh EFh “Offset ECh: DERRINJCTL - DRAM Error Injection Control Register” on page 499 00000000h Table 16-54. Bus 0, Device 0, Function 1: Summary of IMCH Error Reporting PCI Configuration Registers (Sheet 2 of 2) Offset Start Offset End Register ID - Description Default Value

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16.2.1 Register Details

16.2.1.1 Offset 00h: VID - Vendor Identification Register

The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device.

16.2.1.2 Offset 02h: DID - Device Identification Register

This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Table 16-55.Offset 00h: VID - Vendor Identification Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 00h 01h Size: 16 bit Default: 8086h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 00 VID Vendor Identification: This register field contains the PCI standard identification for Intel 8086h. 8086h RO Table 16-56.Offset 02h: DID - Device Identification Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 02h 03h Size: 16 bit Default: 5021h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 00 DID Device Identification Number: This is a 16-bit value assigned to the IMCH Host-Bridge Function 1. 5021h RO

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16.2.1.3 Offset 04h: PCICMD - PCI Command Register

Since IMCH Device 0 does not physically reside on PCI_A (internal bus) many of the bits are not implemented.

16.2.1.4 Offset 06h: PCISTS - PCI Status Register

PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0’s PCI interface. Table 16-57. Offset 04h: PCICMD - PCI Command Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 04h 05h Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 09 Reserved Reserved 00h SERR Enable: This bit is a global enable bit for Device 0 SERR messaging. 0 = Disable, SERR message is not generated by the IMCH for Device 0, Function 1. 1 = The IMCH is enabled to generate SERR messages over the NSI for specific Device 0, Function 1 error conditions that are individually enabled in the ERRCMD registers. The IMCH communicates the SERR condition by sending a DO_SERR message over NSI to the IICH. If this bit is set to a 1, the IMCH is enabled to generate SERR messages over NSI for specific Device 0, Function 1 error conditions that are individually enabled in the NSI_SERRCMD, FSB_SERRCMD, BUF_SERRCMD, and DRAM_SERRCMD registers. The error status is reported in the PCISTS register as well as the corresponding FERR/NERR registers. Note: Reporting via SERR for detected parity error which is essentially NSI Poisoned TLP’s, can ALSO be reported through by the Device 0, Function 0. 0b RW 07 : 00 Reserved Reserved 0bTable 16-58.Offset 06h: PCISTS - PCI Status Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 06h 07h Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

15 Reserved Reserved 0b

Signaled System Error: 0 = SERR is not generated by IMCH Device 0, Function 1 1 = IMCH Device 0 Function 1 generated a SERR message over NSI for any enabled Device 0, Function 1 error condition. Software clears this bit by writing a 1 to the bit location. 0b RWC 13 : 00 Reserved Reserved 000h

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16.2.1.5 Offset 08h: RID - Revision Identification Register

This register contains the revision number of the IMCH Device 0.

16.2.1.6 Offset 0Ah: SUBC - Sub-Class Code Register

16.2.1.7 Offset 0Bh: BCC - Base Class Code Register

Table 16-59.Offset 08h: RID - Revision Identification Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 08h 08h Size: 8 bit Default: Variable Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 00 RID Revision Identification Number: This value indicates the revision identification number for the IMCH Device 0. Variable RO Table 16-60.Offset 0Ah: SUBC - Sub-Class Code Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 0Ah 0Ah Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 00 SUBC Sub-Class Code: This value indicates the Sub Class Code into which the IMCH falls. 00h = Bridge 00h RO Table 16-61.Offset 0Bh: BCC - Base Class Code Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 0Bh 0Bh Size: 8 bit Default: FFh Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 00 BASEC Base Class Code: This value indicates the Base Class Code for the IMCH Device 0, Function 1. FFh = A 'non-defined' device. Since this function is used for error conditions, it does not fall into any other class. FFh RO

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16.2.1.8 Offset 0Dh: MLT - Master Latency Timer Register

Device 0 in the IMCH is not a PCI master so this register is not implemented.

16.2.1.9 Offset 0Eh: HDR - Header Type Register

16.2.1.10 Offset 2Ch: SVID - Subsystem Vendor Identification Register

This value is used to identify the vendor of the subsystem. Table 16-62. Offset 0Dh: MLT - Master Latency Timer Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 0Dh 0Dh Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 00 Reserved Reserved 00h Table 16-63. Offset 0Eh: HDR - Header Type Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 0Eh 0Eh Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 00 HDR PCI Header: This value indicates the Header Type for the IMCH Device 0. 00h = IMCH is a multi-function device with a standard header layout. 00h RO Table 16-64.Offset 2Ch: SVID - Subsystem Vendor Identification Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 2Ch 2Dh Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 00 SUBVID Subsystem Vendor ID: This field must be programmed during boot-up to indicate the vendor of the system board. 0000h RWO

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16.2.1.11 Offset 2Eh: SID - Subsystem Identification Register

This value is used to identify a particular subsystem.

16.2.1.12 Offset 40h: GLOBAL_FERR - Global First Error Register

This register is used to log various error conditions at the “unit” level. These bits are “sticky” through reset, and are set regardless of whether or not any error messages (SCI, SMI, SERR#, MCERR#) are enabled and generated at the unit level. Specific error conditions within the various functional units are logged in the unit-specific error registers that follow. This register captures the FIRST global Fatal and the FIRST global Non-Fatal errors. For these global error registers, a non-fatal error can be either an uncorrectable error which is non-fatal, or a correctable error. Any future errors (NEXT errors) are captured in the Global_NERR register. No further error bits in this register are set until the existing error bit is cleared. Note: If multiple errors are reported in the same clock as the first error, all errors are latched. Table 16-65.Offset 2Eh: SID - Subsystem Identification Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 2Eh 2Fh Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 00 SUBID Subsystem ID: This field must be programmed during BIOS initialization. 0000h RWO Table 16-66.Offset 40h: GLOBAL_FERR - Global First Error Register (Sheet 1 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 40h 43h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 28 Reserved Reserved 0b

27 DRAM_FE

DRAM Controller Channel Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No fatal DRAM I/F error. 1 = The IMCH detected a fatal DRAM interface error. Y0 b R W C

26 FSB_FE

Host (FSB) Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No fatal FSB error. 1 = The IMCH detected a fatal FSB error. Y0 b R W C

25 NSI_FE

NSI Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No fatal NSI error. 1 = The IMCH detected a fatal NSI error. Y0 b R W C

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24 DMA_FE

DMA Controller Fatal Error Device 1 fatal error (EDMA): This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No fatal DMA Controller error. 1 = The IMCH detected a fatal DMA controller error. Y0 b

23 PA_FE

PCI Express* Port A(0) Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No fatal PCI Express Port A error. 1 = The IMCH detected a fatal PCI Express Port A(0) error. Y0 b R W C

22 PA1_FE

PCI Express Port A1 Fatal Error This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No fatal PCI Express Port A1 error. 1 = The IMCH detected a fatal PCI Express Port A1 error. Y0 b R W C 21 : 15 Reserved Reserved 0b

14 BUFF_NFE

Buffer unit detected non-fatal error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No non-fatal Buffer error. 1 = The IMCH detected a non-fatal Buffer error. Y0 b R W C

13 DRAM_NFE

DRAM Controller Non-Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No non-fatal DRAM Controller error. 1 = The IMCH detected a non-fatal DRAM Controller error. Y0 b R W C

12 FSB_NFE

FSB Non-Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No non-fatal FSB error. 1 = The IMCH detected a non-fatal FSB error. Y0 b R W C

11 NSI_NFE

NSI Non-Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No non-fatal NSI error. 1 = The IMCH detected a non-fatal NSI error. Y0 b R W C

10 DMA_NFE

DMA Controller Non-Fatal Error Device 1 non-fatal error (EDMA): This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No non-fatal DMA Controller error. 1 = The IMCH detected a non-fatal DMA Controller error. Y0 b

09 PA_NFE

PCI Express Port A(0) Non-Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No non-fatal PCI Express Port A error. 1 = The IMCH detected a non-fatal PCI Express Port A error. Y0 b R W C

08 PA1_NFE

PCI Express Port A1 Non-Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No non-fatal PCI Express Port A1 error. 1 = The IMCH detected a non-fatal PCI Express Port A1 error. Y0 b R W C 07 : 00 Reserved Reserved 00h Table 16-66. Offset 40h: GLOBAL_FERR - Global First Error Register (Sheet 2 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 40h 43h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

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16.2.1.13 Offset 44h: GLOBAL_NERR - Global Next Error Register

The bit definitions are defined for GLOBAL_FERR. Table 16-67.Offset 44h: GLOBAL_NERR - Global Next Error Register (Sheet 1 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 44h 47h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 28 Reserved Reserved 0b DRAM Controller Channel Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No fatal DRAM I/F error. 1 = The IMCH detected a fatal DRAM interface error. Y0 b R W C Host (FSB) Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No fatal FSB error. 1 = The IMCH detected a fatal FSB error. Y0 b R W C NSI Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No fatal NSI error. 1 = The IMCH detected a fatal NSI error. Y0 b R W C DMA Controller Fatal Error Device 1 fatal error (EDMA): This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No fatal DMA Controller error. 1 = The IMCH detected a fatal DMA controller error. Y0 b PCI Express* Port A(0) Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No fatal PCI Express Port A error. 1 = The IMCH detected a fatal PCI Express Port A(0) error. Y0 b R W C PCI Express Port A1 Fatal Error This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No fatal PCI Express Port A1 error. 1 = The IMCH detected a fatal PCI Express Port A1 error. Y0 b R W C 21 : 15 Reserved Reserved 0b Buffer unit detected non-fatal error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No non-fatal Buffer error. 1 = The IMCH detected a non-fatal Buffer error. Y0 b R W C DRAM Controller Non-Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No non-fatal DRAM Controller error. 1 = The IMCH detected a non-fatal DRAM Controller error. Y0 b R W C FSB Non-Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No non-fatal FSB error. 1 = The IMCH detected a non-fatal FSB error. Y0 b R W C

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16.2.1.14 Offset 48h: NSI_FERR - NSI First Error Register

NSI errors for NSI port to IICH. These errors include errors detected on the NSI link, errors from the NSI hierarchy, and errors internal to the NSI unit. NSI Non-Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No non-fatal NSI error. 1 = The IMCH detected a non-fatal NSI error. Y0 b R W C DMA Controller Non-Fatal Error Device 1 non-fatal error (EDMA): This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No non-fatal DMA Controller error. 1 = The IMCH detected a non-fatal DMA Controller error. Y0 b PCI Express Port A(0) Non-Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No non-fatal PCI Express Port A error. 1 = The IMCH detected a non-fatal PCI Express Port A error. Y0 b R W C PCI Express Port A1 Non-Fatal Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No non-fatal PCI Express Port A1 error. 1 = The IMCH detected a non-fatal PCI Express Port A1 error. Y0 b R W C 07 : 00 Reserved Reserved 0b Table 16-67. Offset 44h: GLOBAL_NERR - Global Next Error Register (Sheet 2 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 44h 47h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Table 16-68. Offset 48h: NSI_FERR - NSI First Error Register (Sheet 1 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 48h 4Bh Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 30 Reserved Reserved 0b 29 UR Unsupported Request: This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Unsupported Request detected. 0b RWC

28 Reserved Reserved 0b

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27 MTLP

Malformed TLP Status: Malformed TLP errors include: data payload length issues, byte enable rule violations, and various other illegal field settings. This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Malformed TLP detected. 0b RWC

26 ROVF

Receiver Overflow Status: IMCH checks for overflows on the following upstream queues: posted, non-posted, and completion. This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Receiver Overflow detected. 0b RWC

25 UEC

Unexpected Completion Status: This bit is set when the device receives a completion which does not correspond to any of the outstanding requests issued by that device. This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Unexpected Completion detected. 0b RWC 24 CA Completer Abort Status: If a request received violates the specific programming model of this device, but is otherwise legal, this bit is set. This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Completer Abort detected. 0b RWC 23 CT Completion Timeout Status: The Completion Timeout timer must expire if a Request is not completed in 50 ms, but must not expire earlier than 50 µs. When the timer expires, this bit is set. This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Completion timeout detected. Y0 b R W C

22 Reserved Reserved 0b

21 PTLP

Poisoned TLP Status: This bit when set indicates that some portion of the TLP data payload was corrupt. This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Poisoned TLP detected. 0b RWC

20 Reserved Reserved 0b

19 DLPE

Data Link Protocol Error Status: This bit is set when an ACK/NAK received does not specify the sequence number of an unacknowledged TLP, or of the most recently acknowledged TLP. This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Data Link Protocol Error detected. 0b RWC 18 : 16 Reserved Reserved 0b

15 RTTO

Replay Timer Timeout Status: The replay timer counts time since the last ACK or NAK DLLP was received. When the timer expires, this bit is set. This bit is sticky through system reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Replay Timer timeout detected. Y0 b R W C

14 Reserved Reserved 0b

Table 16-68.Offset 48h: NSI_FERR - NSI First Error Register (Sheet 2 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 48h 4Bh Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

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13 RNRO

REPLAY_NUM Rollover Status: A 2-bit counter counts the number of times the retry buffer has been retransmitted. When this counter rolls over, this bit is set. This bit is sticky through system reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = REPLAY_NUM rollover detected. Y0 b R W C

12 BDLLP

Bad DLLP Status: This bit is set when the calculated DLLP CRC is not equal to the received value. Also included are 8b/10b errors within the TLP including wrong disparity. An invalid sequence number also sets this bit. This bit is sticky through system reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Bad DLLP detected. Y0 b R W C

11 BTLP

Bad TLP Status: 0 = The calculated TLP CRC is equal to the received value. 1 = The calculated TLP CRC is not equal to the received value. Also included are 8b/10b errors within the TLP including wrong disparity, and invalid sequence numbers. Y0 b R W C

10 Reserved Reserved 0b

09 RCVRE

Receiver Error Status: Data is delivered over PCI Express via packets built out of 8b/10b symbols. This error is set for problems with the packet framing around these symbols or with symbols received outside of recognized packets. This bit is sticky through system reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Receiver Error detected. Y0 b R W C

08 Reserved Reserved 0b

07 FEMR

Fatal Error Message Received: 0 = No Fatal Error Message Received over the NSI link. 1 = Fatal Error Message Received over the NSI link. 0b RWC

06 NEMR

Non-Fatal Error Message Received: Non-Fatal Error Message Received over the NSI link. 0 = No Non-Fatal Error Message Received over the NSI link. 1 = Non-Fatal Error Message Received over the NSI link. 0b RWC

05 CEMR

Correctable Error Message Received: Correctable Error Message Received over the NSI link. 0 = No Correctable Error Message Received over the NSI link. 1 = Correctable Error Message Received over the NSI link. 0b RWC 04 : 03 Reserved Reserved 0b

02 PED

Parity Error Detected during parity conversion from CTB: Parity Error detected on data received from the core. 0 = No Parity Error detected on data received from the core. 1 = Parity Error detected on data received from the core. 0b RWC Link Down: 0 = Link has not transitioned from DL_UP to DL_DOWN. 1 = Link transitioned from DL_UP to DL_DOWN. 0b RWC Table 16-68. Offset 48h: NSI_FERR - NSI First Error Register (Sheet 3 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 48h 4Bh Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

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16.2.1.15 Offset 4Ch: NSI_NERR - NSI Next Error Register

Errors that are detected after the first error are captured by this register. Table 16-69.Offset 4Ch: NSI_NERR - NSI Next Error Register (Sheet 1 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 4Ch 4Fh Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 30 Reserved Reserved 0b 29 UR Unsupported Request: This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Unsupported Request detected. 0b RWC Malformed TLP Status: Malformed TLP errors include: data payload length issues, byte enable rule violations, and various other illegal field settings. This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Malformed TLP detected. 0b RWC Receiver Overflow Status: IMCH checks for overflows on the following upstream queues: posted, non-posted, and completion. This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Receiver Overflow detected. 0b RWC Unexpected Completion Status: This bit is set when the device receives a completion which does not correspond to any of the outstanding requests issued by that device. This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Unexpected Completion detected. 0b RWC 24 CA Completer Abort Status: If a request received violates the specific programming model of this device, but is otherwise legal, this bit is set. This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Completer Abort detected. 0b RWC 23 CT Completion Timeout Status: The Completion Timeout timer must expire if a Request is not completed in 50 ms, but must not expire earlier than 50 µs. When the timer expires, this bit is set. This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Completion timeout detected. 0b RWC Poisoned TLP Status: This bit when set indicates that some portion of the TLP data payload was corrupt. This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Poisoned TLP detected. 0b RWC Data Link Protocol Error Status: This bit is set when an ACK/NAK received does not specify the sequence number of an unacknowledged TLP, or of the most recently acknowledged TLP. This bit is sticky through reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Data Link Protocol Error detected. 0b RWC

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18 : 16 Reserved Reserved 0b Replay Timer Timeout Status: The replay timer counts time since the last ACK or NAK DLLP was received. When the timer expires, this bit is set. This bit is sticky through system reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Replay Timer timeout detected. Y0 b R W C REPLAY_NUM Rollover Status: A 2-bit counter counts the number of times the retry buffer has been retransmitted. When this counter rolls over, this bit is set. This bit is sticky through system reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = REPLAY_NUM rollover detected. Y0 b R W C Bad DLLP Status: This bit is set when the calculated DLLP CRC is not equal to the received value. Also included are 8b/10b errors within the TLP including wrong disparity. An invalid sequence number also sets this bit. This bit is sticky through system reset. 0 = Cleared by writing a ‘1’ to the bit location. 1= Bad DLLP detected. Y0 b R W C Bad TLP Status: 0 = The calculated TLP CRC is equal to the received value. 1 = The calculated TLP CRC is not equal to the received value. Also included are 8b/10b errors within the TLP including wrong disparity, and invalid sequence numbers. Y0 b R W C Receiver Error Status: Data is delivered over PCI Express via packets built out of 8b/10b symbols. This error is set for problems with the packet framing around these symbols or with symbols received outside of recognized packets. This bit is sticky through system reset. 0 = Cleared by writing a ‘1’ to the bit location. 1 = Receiver Error detected. Y0 b R W C Fatal Error Message Received: 0 = No Fatal Error Message Received over the NSI link. 1 = Fatal Error Message Received over the NSI link. 0b RWC Non-Fatal Error Message Received: Non-Fatal Error Message Received over the NSI link. 0 = No Non-Fatal Error Message Received over the NSI link. 1 = Non-Fatal Error Message Received over the NSI link. 0b RWC Correctable Error Message Received: Correctable Error Message Received over the NSI link. 0 = No Correctable Error Message Received over the NSI link. 1 = Correctable Error Message Received over the NSI link. 0b RWC 04 : 03 Reserved Reserved 0b Table 16-69. Offset 4Ch: NSI_NERR - NSI Next Error Register (Sheet 2 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 4Ch 4Fh Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

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16.2.1.16 Offset 50h: NSI_SCICMD - NSI SCI Command Register

This register enables various errors to generate an SCI special cycle. When an error flag is set in the FERR or NERR registers, it can generate an SCI special cycle when enabled in the SCICMD registers. Note that one and only one message type can be enabled. Parity Error Detected during parity conversion from CTB: Parity Error detected on data received from the core. 0 = No Parity Error detected on data received from the core. 1 = Parity Error detected on data received from the core. 0b RWC Link Down: 0 = Link has not transitioned from DL_UP to DL_DOWN. 1 = Link transitioned from DL_UP to DL_DOWN. 0b RWC Table 16-69.Offset 4Ch: NSI_NERR - NSI Next Error Register (Sheet 3 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 4Ch 4Fh Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Table 16-70.Offset 50h: NSI_SCICMD - NSI SCI Command Register (Sheet 1 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 50h 53h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 30 Reserved Reserved 0b

29 UR_SCI

Generate SCI for NSI Error 29: Generate SCI whenever bit 29 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

27 MTLP_SCI

Generate SCI for NSI Error 27: Generate SCI whenever bit 27 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

26 ROVF_SCI

Generate SCI for NSI Error 26: Generate SCI whenever bit 26 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

25 UEC_SCI

Generate SCI for NSI Error 25: Generate SCI whenever bit 25 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

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24 CA_SCI

Generate SCI for NSI Error 24: Generate SCI whenever bit 24 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

23 CT_SCI

Generate SCI for NSI Error 23: Generate SCI whenever bit 23 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

21 PTLP_SCI

Generate SCI for NSI Error 21: Generate SCI whenever bit 21 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

19 DLPE_SCI

Generate SCI for NSI Error 19: Generate SCI whenever bit 19 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW 18 : 16 Reserved Reserved 0b

15 RTTO_SCI

Generate SCI for NSI Error 15: Generate SCI whenever bit 15 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable Y0 b R W

13 RNRO_SCI

Generate SCI for NSI Error 13: Generate SCI whenever bit 13 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable Y0 b R W

12 BDLLP_SCI

Generate SCI for NSI Error 12: Generate SCI whenever bit 12 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable Y0 b R W

11 BTLP_SCI

Generate SCI for NSI Error 11: Generate SCI whenever bit 11 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable Y0 b R W

09 RCVRE_SCI

Generate SCI for NSI Error 9: Generate SCI whenever bit 9 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable Y0 b R W

07 FEMR_SCI

Generate SCI for NSI Error 7: Generate SCI whenever bit 7 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW Table 16-70. Offset 50h: NSI_SCICMD - NSI SCI Command Register (Sheet 2 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 50h 53h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

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16.2.1.17 Offset 54h: NSI_SMICMD - NSI SMI Command Register

This register enables various errors to generate an SMI NSI special cycle. When an error flag is set in the FERR or NERR registers it generates an SMI NSI special cycle when enabled in the SMICMD register. Note that one and only one message type can be enabled.

06 NEMR_SCI

Generate SCI for NSI Error 6: Generate SCI whenever bit 6 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

05 CEMR_SCI

Generate SCI for NSI Error 5: Generate SCI whenever bit 5 of NSI _FERR or NSI _NERR is set 0 = Disable 1 = Enable 0b RW 04 : 03 Reserved Reserved 0b

02 PED_SCI

Generate SCI for NSI Error 2: Generate SCI whenever bit 2 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

00 LD_SCI

Generate SCI for NSI Error 0: Generate SCI whenever bit 0 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW Table 16-70.Offset 50h: NSI_SCICMD - NSI SCI Command Register (Sheet 3 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 50h 53h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Table 16-71.Offset 54h: NSI_SMICMD: NSI SMI Command Register (Sheet 1 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 54h 57h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 30 Reserved Reserved 0b

29 UR_SMI

Generate SMI for NSI Error 29: Generate SMI whenever bit 29 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

27 MTLP_SMI

Generate SMI for NSI Error 27: Generate SMI whenever bit 27 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

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26 ROVF_SMI

Generate SMI for NSI Error 26: Generate SMI whenever bit 26 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

25 UEC_SMI

Generate SMI for NSI Error 25: Generate SMI whenever bit 25 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

24 CA_SMI

Generate SMI for NSI Error 24: Generate SMI whenever bit 24 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

23 CT_SMI

Generate SMI for NSI Error 23: Generate SMI whenever bit 23 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

21 PTLP_SMI

Generate SMI for NSI Error 21: Generate SMI whenever bit 21 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

19 DLPE_SMI

Generate SMI for NSI Error 19: Generate SMI whenever bit 19 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW 18 : 16 Reserved Reserved 0b

15 RTTO_SMI

Generate SMI for NSI Error 15: Generate SMI whenever bit 15 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

13 RNRO_SMI

Generate SMI for NSI Error 13: Generate SMI whenever bit 13 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

12 BDLLP_SMI

Generate SMI for NSI Error 12: Generate SMI whenever bit 12 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

11 BTLP_SMI

Generate SMI for NSI Error 11: Generate SMI whenever bit 11 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

09 RCVRE_SMI

Generate SMI for NSI Error 9: Generate SMI whenever bit 9 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW Table 16-71. Offset 54h: NSI_SMICMD: NSI SMI Command Register (Sheet 2 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 54h 57h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

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07 FEMR_SMI

Generate SMI for NSI Error 7: Generate SMI whenever bit 6 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

06 NEMR_SMI

Generate SMI for NSI Error 6: Generate SMI whenever bit 6 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

05 CEMR_SMI

Generate SMI for NSI Error 5: Generate SMI whenever bit 5 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW 04 : 03 Reserved Reserved 0b

02 PED_SMI

Generate SMI for NSI Error 2: Generate SMI whenever bit 2 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

00 LD_SMI

Generate SMI for NSI Error 0: Generate SMI whenever bit 0 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW Table 16-71.Offset 54h: NSI_SMICMD: NSI SMI Command Register (Sheet 3 of 3) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 54h 57h Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

464 Order Number: 320066-003US

16.2.1.18 Offset 58h: NSI_SERRCMD - NSI SERR Command Register

This register enables various errors to generate an SERR NSI special cycle. When an error flag is set in the FERR or NERR registers it generates an SERR NSI special cycle when enabled in the SERRCMD register. Note that one and only one message type can be enabled. Table 16-72. Offset 58h: NSI_SERRCMD - NSI SERR Command Register (Sheet 1 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 58h 5Bh Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 30 Reserved Reserved 0b

29 UR_SERR

Generate SERR for NSI Error 29: Generate SERR whenever bit 29 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

27 MTLP_SERR

Generate SERR for NSI Error 27: Generate SERR whenever bit 27 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

26 ROVF_SERR

Generate SERR for NSI Error 26: Generate SERR whenever bit 26 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

25 UEC_SERR

Generate SERR for NSI Error 25: Generate SERR whenever bit 25 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

24 CA_SERR

Generate SERR for NSI Error 24: Generate SERR whenever bit 24 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

23 CT_SERR

Generate SERR for NSI Error 23: Generate SERR whenever bit 23 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

21 PTLP_SERR

Generate SERR for NSI Error 21: Generate SERR whenever bit 21 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

19 DLPE_SERR

Generate SERR for NSI Error 19: Generate SERR whenever bit 19 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW 18 : 16 Reserved Reserved 0b

15 RTTO_SERR

Generate SERR for NSI Error 15: Generate SERR whenever bit 15 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 465 Intel® EP80579 Integrated Processor

13 RNRO_SERR

Generate SERR for NSI Error 13: Generate SERR whenever bit 13 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

12 BDLLP_SERR

Generate SERR for NSI Error 12: Generate SERR whenever bit 12 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

11 BTLP_SERR

Generate SERR for NSI Error 11: Generate SERR whenever bit 11 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

09 RCVRE_SERR

Generate SERR for NSI Error 9: Generate SERR whenever bit 9 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

07 FEMR_SERR

Generate SERR for NSI Error 7: Generate SERR whenever bit 7 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

06 NEMR_SERR

Generate SERR for NSI Error 6: Generate SERR whenever bit 6 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

05 CEMR_SERR

Generate SERR for NSI Error 5: Generate SERR whenever bit 5 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW 04 : 03 Reserved Reserved 0b

02 PED_SERR

Generate SERR for NSI Error 2: Generate SERR whenever bit 2 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

00 LD_SERR

Generate SERR for NSI Error 0: Generate SERR whenever bit 0 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW Table 16-72.Offset 58h: NSI_SERRCMD - NSI SERR Command Register (Sheet 2 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 58h 5Bh Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

466 Order Number: 320066-003US

16.2.1.19 Offset 5Ch: NSI_MCERRCMD - NSI MCERR Command Register

This register enables various errors to generate the MCERR signal on the FSB. When an error flag is set in the FERR or NERR registers it generates a MCERR when enabled in the MCERRCMD. Table 16-73. Offset 5Ch: NSI_MCERRCMD - NSI MCERR Command Register (Sheet 1 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 5Ch 5Fh Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 31 : 30 Reserved Reserved 0b

29 UR_MCERR

Generate MCERR for NSI Error 29: Generate MCERR whenever bit 29 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

27 MTLP_MCERR

Generate MCERR for NSI Error 27: Generate MCERR whenever bit 27 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

26 ROVF_MCERR

Generate MCERR for NSI Error 26: Generate MCERR whenever bit 26 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

25 UEC_MCERR

Generate MCERR for NSI Error 25: Generate MCERR whenever bit 25 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

24 CA_MCERR

Generate MCERR for NSI Error 24: Generate MCERR whenever bit 24 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

23 CT_MCERR

Generate MCERR for NSI Error 23: Generate MCERR whenever bit 23 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

21 PTLP_MCERR

Generate MCERR for NSI Error 21: Generate MCERR whenever bit 21 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

19 DLPE_MCERR

Generate MCERR for NSI Error 19: Generate MCERR whenever bit 19 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW 18 : 16 Reserved Reserved 0b

15 RTTO_MCERR

Generate MCERR for NSI Error 15: Generate MCERR whenever bit 15 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 467 Intel® EP80579 Integrated Processor

13 RNRO_MCERR

Generate MCERR for NSI Error 13: Generate MCERR whenever bit 13 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

12 BDLLP_MCERR

Generate MCERR for NSI Error 12: Generate MCERR whenever bit 12 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

11 BTLP_MCERR

Generate MCERR for NSI Error 11: Generate MCERR whenever bit 11 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

09 RCVRE_MCERR

Generate MCERR for NSI Error 9: Generate MCERR whenever bit 9 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

07 FEMR_MCERR

Generate MCERR for NSI Error 7: Generate MCERR whenever bit 7 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

06 NEMR_MCERR

Generate MCERR for NSI Error 6: Generate MCERR whenever bit 6 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

05 CEMR_MCERR

Generate MCERR for NSI Error 5: Generate MCERR whenever bit 5 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW 04 : 03 Reserved Reserved 0b

02 PED_MCERR

Generate MCERR for NSI Error 2: Generate MCERR whenever bit 2 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW

00 LD_MCERR

Generate MCERR for NSI Error 0: Generate MCERR whenever bit 0 of NSI _FERR or NSI _NERR is set. 0 = Disable 1 = Enable 0b RW Table 16-73.Offset 5Ch: NSI_MCERRCMD - NSI MCERR Command Register (Sheet 2 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 5Ch 5Fh Size: 32 bit Default: 00000000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

468 Order Number: 320066-003US

16.2.1.20 Offset 60h: FSB_FERR - FSB First Error Register

This register stores the first error related to the FSB. Only one error bit is set in this register. Any future errors (NEXT errors) are set in the FSB_NERR register. No further error bits in the FSB_FERR register are set until the existing error bit is cleared. These bits are sticky through reset. Software clears these bits by writing a 1 to the bit location. Note: If multiple errors are reported in the same clock as the first error, all errors are latched. Table 16-74. Offset 60h: FSB_FERR - FSB First Error Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 60h 61h Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 10 Reserved Reserved 00h 09 : 06 Reserved Reserved 0000b RWC

05 NDLOCK

Non-DRAM Lock Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No DRAM Lock Error detected 1 = IMCH detected a lock operation to memory space that did not map into DRAM. (NON-FATAL) Y0 b R W C

04 ATOM

FSB Address Above TOM/TOLM: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No FSB address above TOM/TOLM detected 1 = IMCH has detected an address above the Top of Memory and above 4 Gbyte.If the system has less than

4 Gbyte of DRAM, then unclaimed addresses between

TOLM and 4 Gbyte are sent to NSI. (NON-FATAL) Y0 b R W C

03 Reserved Reserved Y 0b RWC

02 FSBAGL

FSB Address Strobe Glitch Detected: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No FSB address strobe glitch detected. 1 = IMCH has detected a glitch one of the FSB address strobes. (FATAL) Y0 b R W C

01 FSBDGL

FSB Data Strobe Glitch Detected: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No FSB data strobe glitch detected. 1 = IMCH has detected a glitch one of the FSB data strobes. (FATAL) Y0 b R W C

00 Reserved Reserved Y 0b RWC

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 469 Intel® EP80579 Integrated Processor

16.2.1.21 Offset 62h: FSB_NERR - FSB Next Error Register

Table 16-75.Offset 62h: FSB_NERR - FSB Next Error Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 62h 63h Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 10 Reserved Reserved 00h 09 06 Reserved Reserved 0000b RWC Non-DRAM Lock Error: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No DRAM Lock Error detected 1 = IMCH detected a lock operation to memory space that did not map into DRAM. (NON-FATAL) Y0 b R W C FSB Address Above TOM/TOLM: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No FSB address above TOM/TOLM detected 1 = IMCH has detected an address above the Top of Memory and above 4 Gbyte.If the system has less than TOLM and 4 Gbyte are sent to NSI. (NON-FATAL) Y0 b R W C FSB Address Strobe Glitch Detected: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No FSB address strobe glitch detected. 1 = IMCH has detected a glitch one of the FSB address strobes. (FATAL) Y0 b R W C FSB Data Strobe Glitch Detected: This bit is sticky through reset. System software clears this bit by writing a 1 to the location. 0 = No FSB data strobe glitch detected. 1 = IMCH has detected a glitch one of the FSB data strobes. (FATAL) Y0 b R W C

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

470 Order Number: 320066-003US

16.2.1.22 Offset 64h: FSB_EMASK - FSB Error Mask Register

This register masks the FSB unit errors from being recognized, preventing them from being logged at the unit or global level, and no interrupt/messages are generated. These bits are sticky through reset. Table 16-76. Offset 64h: FSB_EMASK - FSB Error Mask Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 64h 65h Size: 16 bit Default: 0009h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 10 Reserved Reserved 00h 09 06 Reserved Reserved Y 0000b RW

05 NDLOCKM

Non-DRAM Lock Error Mask: This bit is sticky through reset. 0 = Enable Non-DRAM Lock Error detection and reporting 1 = Mask Non-DRAM Lock Error detection and reporting Y0 b R W

04 ATOMM

FSB Address Above TOM Mask: This bit is sticky through reset. 0 = Enable FSB address above TOM detection and reporting 1 = Mask address above TOM detection and reporting Y0 b R W

03 Reserved Reserved Y 1b RW

02 FSBAGLM

FSB Address Strobe Glitch Detected Mask: This bit is sticky through reset. 0 = Enable FSB address strobe glitch detection and reporting 1 = Mask address strobe glitch detection and reporting Y0 b R W

01 FSBDGLM

FSB Data Strobe Glitch Detected Mask: This bit is sticky through reset. 0 = Enable FSB data strobe glitch detection and reporting 1 = Mask data strobe glitch detection and reporting Y0 b R W

00 Reserved Reserved Y 1b RW

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 471 Intel® EP80579 Integrated Processor

16.2.1.23 Offset 68h: FSB_SCICMD - FSB SCI Command Register

This register enables various errors to generate an SCI NSI special cycle. When an error flag is set in the FERR or NERR registers, it generates an SCI NSI special cycle when enabled in the SCICMD register. Note that one and only one message type can be enabled. Table 16-77.offset 68h: FSB_SCICMD - FSB SCI Command Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 68h 69h Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 10 Reserved Reserved 00h 09 06 Reserved Reserved 0000b RW

05 NDLOCK_SCI

Non-DRAM Lock Error SCI Enable: Controls whether or not an SCI is generated when bit 5 of the FSB_FERR or FSB_NERR register is set. 0 = No SCI generated on Non-DRAM Lock Error detection 1 = Enable SCI generation on Non-DRAM Lock Error detection 0b RW

04 ATOM_SCI

FSB Address Above TOM SCI Enable: Controls whether or not an SCI is generated when bit 4 of the FSB_FERR or FSB_NERR register is set. 0 = No SCI generated on FSB address above TOM detection 1 = Enable SCI generation on FSB address above TOM detection 0b RW

03 Reserved Reserved 0b RW

02 FSBAGL_SCI

FSB Address Strobe Glitch Detected SCI Enable: Controls whether or not an SCI is generated when bit 2 of the FSB_FERR or FSB_NERR register is set. 0 = No SCI generated on FSB address strobe glitch detection 1 = Enable SCI generation on FSB address strobe glitch detection 0b RW

01 FSBDGL_SCI

FSB Data Strobe Glitch Detected SCI Enable: Controls whether or not an SCI is generated when bit 1 of the FSB_FERR or FSB_NERR register is set. 0 = No SCI generated on FSB data strobe glitch detection 1 = Enable SCI generation on FSB data strobe glitch detection 0b RW

00 Reserved Reserved 0b RW

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

472 Order Number: 320066-003US

16.2.1.24 Offset 6Ah: FSB_SMICMD - FSB SMI Command Register

This register enables various errors to generate an SMI NSI special cycle. When an error flag is set in the FSB_FERR or FSB_NERR register, it generates an SMI NSI special cycle when enabled in the SMICMD register. Note that one and only one message type can be enabled. Table 16-78. Offset 6Ah: FSB_SMICMD - FSB SMI Command Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 6Ah 6Bh Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 10 Reserved Reserved 00h 09 06 Reserved Reserved 0000b RW

05 NDLOCK_SMI

Non-DRAM Lock Error SMI Enable: Controls whether or not an SMI is generated when bit 5 of the FSB_FERR or FSB_NERR register is set. 0 = No SMI generated on Non-DRAM Lock Error detection 1 = Enable SMI generation on Non-DRAM Lock Error detection 0b RW

04 ATOM_SMI

FSB Address Above TOM SMI Enable: Controls whether or not an SMI is generated when bit 4 of the FSB_FERR or FSB_NERR register is set. 0 = No SMI generated on FSB address above TOM detection 1 = Enable SMI generation on FSB address above TOM detection 0b RW

02 FSBAGL_SMI

FSB Address Strobe Glitch Detected SMI Enable: Controls whether or not an SMI is generated when bit 2 of the FSB_FERR or FSB_NERR register is set. 0 = No SMI generated on FSB address strobe glitch detection 1 = Enable SMI generation on FSB address strobe glitch detection 0b RW

01 FSBDGL_SMI

FSB Data Strobe Glitch Detected SMI Enable: Controls whether or not an SMI is generated when bit 1 of the FSB_FERR or FSB_NERR register is set. 0 = No SMI generated on FSB data strobe glitch detection 1 = Enable SMI generation on FSB data strobe glitch detection 0b RW

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 473 Intel® EP80579 Integrated Processor

16.2.1.25 Offset 6Ch: FSB_SERRCMD - FSB SERR Command Register

This register enables various errors to generate an SERR NSI special cycle. When an error flag is set in the FSB_FERR or FSB_NERR register, it generates an SERR NSI special cycle when enabled in the SERRCMD register. Note that one and only one message type can be enabled. Table 16-79.Offset 6Ch: FSB_SERRCMD - FSB SERR Command Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 6Ch 6Dh Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 10 Reserved Reserved 00h 09 06 Reserved Reserved 0000b RW

05 NDLOCK_SERR

Non-DRAM Lock Error SERR Enable: Controls whether or not an SERR is generated when bit 5 of the FSB_FERR or FSB_NERR register is set. 0 = No SERR generated on Non-DRAM Lock Error detection 1 = Enable SERR generation on Non-DRAM Lock Error detection 0b RW

04 ATOM_SERR

FSB Address Above TOM SERR Enable: Controls whether or not an SERR is generated when bit 4 of the FSB_FERR or FSB_NERR register is set. 0 = No SERR generated on FSB address above TOM detection 1 = Enable SERR generation on FSB address above TOM detection 0b RW

02 FSBAGL_SERR

FSB Address Strobe Glitch Detected SERR Enable: Controls whether or not an SERR is generated when bit 2 of the FSB_FERR or FSB_NERR register is set. 0 = No SERR generated on FSB address strobe glitch detection 1 = Enable SERR generation on FSB address strobe glitch detection 0b RW

01 FSBDGL_SERR

FSB Data Strobe Glitch Detected SERR Enable: Controls whether or not an SERR is generated when bit 1 of the FSB_FERR or FSB_NERR register is set. 0 = No SERR generated on FSB data strobe glitch detection 1 = Enable SERR generation on FSB data strobe glitch detection 0b RW

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

474 Order Number: 320066-003US

16.2.1.26 Offset 6Eh: FSB_MCERRCMD - FSB MCERR Command Register

This register enables various errors to generate the MCERR signal on the FSB. When an error flag is set in the FSB_FERR or FSB_NERR register, it generates a MCERR# when enabled in the MCERRCMD. Table 16-80.Offset 6Eh: FSB_MCERRCMD - FSB MCERR Command Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 6Eh 6Fh Size: 16 bit Default: 0000h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 15 : 10 Reserved Reserved 00h 09 06 Reserved Reserved 0000b RW

05 NDLOCK_MCER

R_N Non-DRAM Lock Error MCERR# Enable: Controls whether or not an MCERR# is generated when bit 5 of the FSB_FERR or FSB_NERR register is set. 0 = No MCERR# generated on Non-DRAM Lock Error detection 1 = Enable MCERR# generation on Non-DRAM Lock Error detection 0b RW

04 ATOM_MCERR_

N FSB Address Above TOM MCERR# Enable: Controls whether or not an MCERR# is generated when bit 4 of the FSB_FERR or FSB_NERR register is set. 0 = No MCERR# generated on FSB address above TOM detection 1 = Enable MCERR# generation on FSB address above TOM detection 0b RW

02 FSBAGL_MCER

R_N FSB Address Strobe Glitch Detected MCERR# Enable: Controls whether or not an MCERR# is generated when bit 2 of the FSB_FERR or FSB_NERR register is set. 0 = No MCERR# generated on FSB address strobe glitch detection 1 = Enable MCERR# generation on FSB address strobe glitch detection 0b RW

01 FSBDGL_MCER

R_N FSB Data Strobe Glitch Detected MCERR# Enable: Controls whether or not an MCERR# is generated when bit 1 of the FSB_FERR or FSB_NERR register is set. 0 = No MCERR# generated on FSB data strobe glitch detection 1 = Enable MCERR# generation on FSB data strobe glitch detection 0b RW

0 Reserved Reserved 0b RW

August 2009 Intel® EP80579 Integrated Processor Product Line Datasheet Order Number: 320066-003US 475 Intel® EP80579 Integrated Processor

16.2.1.27 Offset 70h: BUF_FERR - Memory Buffer First Error Register

Signals errors occurring in the memory system coherent Posted Memory Write Buffer (PMWB).

16.2.1.28 Offset 72h: BUF_NERR - Memory Buffer Next Error Register

Table 16-81.Offset 70h: BUF_FERR - Memory Buffer First Error Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 70h 70h Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 04 Reserved Reserved 0h

03 DPMWB

Internal DRAM to PMWB Parity Error Detected: 0 = Parity error not detected. 1= Parity error detected when a cacheline read from DRAM was written to the PMWB as part of a Read/Modify/Write operation (partial write). (NON-FATAL) 0b RWC

02 IOPMWB

Internal System Bus or I/O to PMWB Parity Error Detected: 0 = Parity error not detected. 1 = Parity error detected on a line write to PMWB. (NON- FATAL) 0b RWC

01 PMWBSYS

Internal PMWB to System Bus Parity Error Detected: 0 = Parity error not detected. 1 = Parity error detected on data to the System Bus. (NON-FATAL) 0b RWC

00 PMWBD

Internal PMWB to DRAM Parity Error Detected: 0 = Parity error not detected. 1 = Parity error detected when PMWB is flushed to DRAM. (NON-FATAL) 0b RWC Table 16-82.Offset 72h: BUF_NERR - Memory Buffer Next Error Register (Sheet 1 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 72h 72h Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 04 Reserved Reserved 0h Internal DRAM to PMWB Parity Error Detected: 0 = Parity error not detected. 1 = Parity error detected when a cacheline read from DRAM was written to the PMWB as part of a Read/Modify/ Write operation (partial write). (NON-FATAL) 0b RWC

Intel® EP80579 Integrated Processor Intel® EP80579 Integrated Processor Product Line Datasheet August 2009

476 Order Number: 320066-003US

16.2.1.29 Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register

This register masks the unit errors from being recognized. Because they are not recognized, they are not logged at the unit or global level and no interrupt/messages are generated. Internal System Bus or I/O to PMWB Parity Error Detected: 0 = Parity error not detected. 1 = Parity error detected on a line write to PMWB. (NON- FATAL) 0b RWC Internal PMWB to System Bus Parity Error Detected: 0 = Parity error not detected. 1 = Parity error detected on data to the System Bus. (NON-FATAL) 0b RWC Internal PMWB to DRAM Parity Error Detected: 0 = Parity error not detected. 1= Parity error detected when PMWB is flushed to DRAM. (NON-FATAL) 0b RWC Table 16-82. Offset 72h: BUF_NERR - Memory Buffer Next Error Register (Sheet 2 of 2) Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 72h 72h Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access Table 16-83.Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register Description: View: PCI BAR: Configuration Bus:Device:Function: 0:0:1 Offset Start: Offset End: 74h 74h Size: 8 bit Default: 00h Power Well: Core Bit Range Bit Acronym Bit Description Sticky Bit Reset Value Bit Access 07 : 04 Reserved Reserved 0b

03 BUF_EMASK03

Mask Error bit 03: 0 = Disable mask. 1 = Enable mask. 0b RW

02 BUF_EMASK02

Mask Error bit 02: 0 = Disable mask. 1 = Enable mask. 0b RW

01 BUF_EMASK01

Mask Error bit 01: 0 = Disable mask. 1 = Enable mask. 0b RW

00 BUF_EMASK00

Mask Error bit 00: 0 = Disable mask. 1 = Enable mask. 0b RW

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Intel짰 EP80579 Integrated Processor Product Line

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Intel짰 EP80579 Integrated Processor Product Line

Source title EP80579 Datasheet(PDF) - Intel Corporation

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