NLXT914PE-B3 INTEL | Alldatasheet
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Technical content
Datasheet sections
- 1.0 LXT914 Pin Assignments and Signal Descriptions
- 2.0 Functional Description
- 2.1 Introduction
- 2.2 External Interfaces
- 2.2.4 Inter-Repeater Backplane
- 2.2.4.1 Synchronous IRB Operation
- 2.2.4.2 Asynchronous IRB Operation
- 2.3 Internal Repeater Circuitry
- 2.4 Initialization
- 2.4.1 Local Management Mode Initialization
- 2.4.2 External Management Mode Initialization
- 2.5.1.1 Programmable Internal Squelch Level
- 2.5.1.2 Polarity Detection and Correction
- 2.6 AUI Port Operation
- 2.6.1 AUI Reception
- 2.6.2 AUI Transmission
- 2.6.3 AUI Mode Selection (DTE/MAU)
- 2.7 Collision Handling
- 2.8 Security Mode
- 2.9 LED Display
- 3.0 Application Information
- 3.1 Layout Requirements
- 3.1.1 The Twisted Pair Interface
- 3.1.2 The RBIAS Pin
- 4.0 Test Specifications
- 5.0 Package Specifications
- 5.1 Top-Label Marking
- 6.0 Product Ordering Information
Order Number: 248989, Revision: 003 31-Oct-2005 Intel® LXT914 Flexible Quad Ethernet Repeater Datasheet The Intel® LXT914 Flexible Quad Ethernet Repeater (called hereafter the LXT914 Repeater) is an integrated multi-port repeater designed for mixed-media networks. It provides all the active circuitry required for the repeater function in a single CMOS device. It includes one Attachment Unit Interface (AUI) port and four 10BASE-T transceivers. The AUI port is mode selectable: DTE mode allows connection of an external transceiver (10BASE2, 10BASE5, 10BASE-T or FOIRL) or a drop cable. MAU mode creates a MAU output allowing direct connection to another DTE interface. The 10BASE-T transceivers are entirely self-contained with internal filters which simplify the design work required for FCC-compliant EMI performance. An inter-repeater backplane interface allows 128 or more 10BASE-T ports to be cascaded together. In addition, a serial port provides information for network management. The LXT914 Repeater requires only a single 5-volt power supply due to an advanced CMOS fabrication process. Product Features
Applications
■ Four integrated 10BASE-T transceivers and one AUI transceiver on a single chip ■ Programmable DTE/MAU interface on AUI port ■ Seven integrated LED drivers with four unique operational modes ■ On-chip transmit and receive filtering ■ Automatic partitioning of faulty ports, enabled on an individual port basis ■ Automatic polarity detection and correction ■ Programmable squelch level allows extended range in low-noise environments ■ Synchronous or asynchronous inter- repeater backplane supports “hot swapping” ■ Inter-repeater backplane allows cascaded repeaters, linking 128 or more 10BASE-T ports ■ Serial port for selecting programmable options ■ 68-pin PLCC (Commercial or Extended temp range) ■ 100-pin PQFP (Commercial temp range) ■ LAN Repeaters ■ Integrated Repeaters ■ Switched Repeater Clusters
Intel® LXT914 Flexible Quad Ethernet Repeater
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Intel® LXT914 Flexible Quad Ethernet Repeater 31-Oct-2005 Datasheet Intel® LXT914 Flexible Quad Ethernet Repeater
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16 Sample PLCC Package - Intel
22 I/O Electrical Characteristics
Intel® LXT914 Flexible Quad Ethernet Repeater Datasheet 31-Oct-2005 Intel® LXT914 Flexible Quad Ethernet Repeater Order Number: 248989, Revision: 003 5
Intel® LXT914 Flexible Quad Ethernet Repeater 31-Oct-2005 Datasheet Intel® LXT914 Flexible Quad Ethernet Repeater
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Revision History
Added Section 5.1 and Figure 16 through Figure 19 (RoHS top labels). Added Section 6.0, “Product Ordering Information” on page 44 with Table 29 “Product Ordering Information” on page 44 and Figure 20 “Ordering Information Matrix – Sample” on page 45. Feb 2001 002 Added Layout Requirements section under Application Information. Modified I/O Electrical Characteristics table: Change Max value under Supply Current from 180 to 240; Add text under Test Conditions: “100 test load, no LEDs”; add table note 3.
1.0 LXT914 Pin Assignments and Signal Descriptions
Figure 1. Block Diagram
4 TP1 - 4
provided through shared usage of the JM LED pin.
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Figure 2. Pin Assignments
Table 1. Power, Ground, and Clock Signal Descriptions Power Supply Inputs. These pins each require a +5 VDC power supply. bias current is provided through an external 12.4 k Ω resistor to ground. for the duration of the transmission. 11 6 SYSCLK I System Clock. The required 20 MHz system clock is input at this pin. Clock must have a 40-60 duty cycle with < 10 ns rise time.
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Table 2. Inter-Repeater Backplane Signal Descriptions transmission. IRDEN must be pulled up locally by a 330 Ω resistor.
- IRENA and IRDAT can be buffered between boards in multi-board configurations. Where buffering is used,
impedance should be no less than 330 Ω.
- IRCFS and IRCOL cannot be buffered. In multi-board configurations, the total impedance on IRCOL should
be no smaller than 330 Ω. IRCFS should be pulled up only once, by a single 330 Ω, 1% resistor. Table 3. Mode Select and Control Signal Descriptions Backplane Sync Mode Select. This pin selects the backplane sync mode. the backplane and an external 10 MHz backplane clock source is required. setup parameters, the repeater functions independently. default LED mode (Refer to Table 7) is not available.
40 LEDM0
Table 4. Serial Port Signal Descriptions (External Management Mode) Low for the duration of the serial input transaction. remains Low for the duration of the serial transmission. clock source. In synchronous mode, SCLK and BCLK may be tied together. Table 5. Serial Port Signal Descriptions (Local Management Mode) Select output used to enable the EEPROM. remain Low for the duration of the serial input transaction. the devices have read in their 48 bits of setup data. (48 bits).This pin should be tied Low if no EEPROM is present. download its stored data. In subsequent devices this pin is not used. have their SCLKIO pins tied together.
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Table 6. Miscellaneous Control Signal Descriptions 19 18 TEST I Test Mode Select. This pin must be tied Low for normal operation. 20 19 RESET I RESET. This pin resets the LXT914 circuitry when pulled High for ≥ 1 ms. SQE function of the AUI port is disabled. When Low, SQE is enabled. must be tied Low if external security control is not required. previous LXT914s in the data chain. Table 7. LED Driver Signal Descriptions monitor and report both conditions independently. simultaneously monitor and report both conditions independently. a pair of LEDs (to the anode of one LED and the cathode of a second LED). (receive, transmit, link integrity, reverse polarity and auto partition). jabber, receive collision and auto partition.
Table 8. Repeater Port Signal Descriptions connected to the DI pins of the DTE. connected to the DO pins of the DTE. these pins output a collision indication to the DTE. from the respective twisted-pair ports. the respective twisted-pair ports.
Intel® LXT914 Flexible Quad Ethernet Repeater 31-Oct-2005 Datasheet Intel® LXT914 Flexible Quad Ethernet Repeater
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2.0 Functional Description
2.1 Introduction
The LXT914 Repeater is an integrated hub repeater for 10BASE-T networks. The hub repeater is the central point for information transfer across the network. The LXT914 Repeater offers multiple operating modes to suit a broad range of applications ranging from simple 4-port stand-alone hubs or attachments for print and file servers, up to intelligent 128-port enterprise systems with microprocessor/gate arLXT914 Repeater ray management. The main functions of the LXT914 Repeater hub repeater are data recovery and re-transmission and collision propagation. Data packets received at the AUI or 10BASE-T ports are detected and recovered by the port receivers before being passed to the repeater core circuitry for re-timing and re-transmission. Data packets received through the IRB port are essentially passed directly to the core for retransmission. After recovery of a valid data packet, the repeater broadcasts it to all enabled stations, except the originator station.
2.2 External Interfaces
The LXT914 Repeater includes four 10BASE-T ports with internal filters. The LXT914 Repeater also includes an Attachment Unit Interface (AUI) port, a serial port and an Inter-Repeater Backplane (IRB) port. The serial port allows an external device such as an EEPROM to download setup parameters to the repeater. In more complex designs the serial port can also be used to monitor repeater status. The IRB port enables multiple LXT914 Repeater devices to be cascaded, creating a large, multi-port repeater. 2.2.1 10BASE-T Ports The four 10BASE-T transceiver ports are completely self-contained. Since the transmitters and receivers include the required filtering, only simple, inexpensive transformers are required to complete the 10BASE-T interface. Each individual Twisted-Pair (TP) port is implemented in accordance with the IEEE 802.3 10BASE-T standard.
2.2.2 AUI Port
The AUI port mode is selectable (DTE mode or MAU mode). With DTE mode selected, the AUI port allows connection of an external transceiver (10BASE2, 10BASE5, 10BASE-T or FOIRL) or a drop cable. With MAU mode selected, the AUI port establishes a MAU output allowing direct connection to another DTE interface.
2.2.3 Serial Port
The serial port provides the management interface to the LXT914 Repeater. Refer to Test Specifications for serial port timing. The serial port can be either unidirectional or bidirectional, depending on the management mode selected. In the Local management mode the serial port is
Intel® LXT914 Flexible Quad Ethernet Repeater Datasheet 31-Oct-2005 Intel® LXT914 Flexible Quad Ethernet Repeater Order Number: 248989, Revision: 003 15 unidirectional (input only), and is used only to download setup parameters during initialization. The Local mode is intended for use with a simple EEPROM, but the serial port may be tied Low if an EEPROM is not required. In the External management mode, the serial port is bi-directional (input for setup parameters, output for status reports). The External mode is intended for use with an External Management Device (EMD) and a Media Access Controller (MAC). The EMD (typically a gate array) communicates with a microprocessor (e.g., Intel 8051) and can control up to three LXT914 Repeaters. This simplifies design of a relatively standard 12-port repeater on a single printed circuit board.
2.2.4 Inter-Repeater Backplane
The Inter-Repeater Backplane (IRB) allows several LXT914 Repeaters to function as a single repeater. Refer to Test Specifications for IRB timing. The IRB also allows several multi-repeater boards to be integrated in a standard rack and to function as a single unit. The IRB supports “hot swapping” for easy maintenance and troubleshooting. Each individual repeater distributes recovered and re-timed data to other repeaters on the IRB for broadcast on all ports simultaneously. This simultaneous rebroadcast allows the multi-repeater system to act as a single large repeater unit. The maximum number of repeaters on the IRB is limited by bus loading factors such as parasitic capacitance. The IRB can be operated synchronously or asynchronously.
2.2.4.1 Synchronous IRB Operation
In the synchronous mode, a common external source provides the 10 MHz backplane clock (BCLKIO) and the 20 MHz system clock (SYSCLK) to all repeaters. BCLKIO must be synchronous to SYSCLK and may be derived from SYSCLK using a divide-by-two circuit. In the synchronous mode 32 or more LXT914 Repeaters may be connected on the IRB, providing 128 10BASE-T ports and 32 AUI ports.
2.2.4.2 Asynchronous IRB Operation
In the asynchronous mode an external BCLKIO source is not required. The repeaters run independently until one takes control of the IRB. The transmitting repeater then outputs its own 10 MHz clock onto the BCLKIO line. All other repeaters sync to that clock for the duration of the transmission. In the asynchronous mode 12 or more LXT914 Repeater may be connected to the IRB, providing 48 10BASE-T ports and 12 AUI ports. The maximum number of repeaters which may be linked on the backplane is limited by board design factors. The numbers listed above are engineering estimates only. Stronger drivers and reduced capacitive loading in PCB layout may allow an increased device count.
2.3 Internal Repeater Circuitry
The basic repeater circuitry is shared among all the ports within the LXT914 Repeater. It consists of a global repeater state machine, several timers and counters and the timing recovery circuit. The timing recovery circuit includes a FIFO for re-timing and recovery of the clock which is used to clock the receive data out onto the IRB.
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The shared functional blocks of the LXT914 Repeater are controlled by the global state machine (Figure 3). This diagram and all associated notations used are in strict accordance with section 9.6 of the IEEE 802.3 standard. The LXT914 Repeater also implements the Partition State Diagram as defined by the IEEE 802.3 standard and shown in Figure 4. The value of CCLimit as implemented in the LXT914 Repeater is 64. The CCLimit value sets the number of consecutive collisions that must occur before the port is subjected to automatic partitioning. Auto-partition/re-connection is also supported by the LXT914 Repeater with Tw5 conforming to the standard requirement of 450 to 560 bit times.
2.4 Initialization
The following description applies to the initial power-on reset and to any subsequent hardware reset. When a reset occurs (RESET pin pulled High for > 1 ms), the device senses the levels at the various control pins (see Figure 3) to determine the correct operating modes for Management, LEDs, and the AUI port functions.
2.4.1 Local Management Mode Initialization
An internal pull-up causes the LXT914 Repeater to default to the Local management mode unless the LOC/EXT pin is tied Low. In the Local mode the serial port is a unidirectional interface used only to download setup parameters from an external device. In a Locally managed multiple-repeater (daisy chain) configuration, the first repeater in the chain performs special functions. The First Position Select (FPS) pin is used to establish position (FPS High = First, FPS Low = Not First). After establishing the Hardware mode, each LXT914 Repeater monitors the FPS pin to determine its position. If FPS is High (First Position), the repeater performs the following functions: Outputs a 1 MHz Serial Clock (SCLK). SCLK is derived from the 20 MHz SYSCLK input in ASYNC mode and from BCLKIO in SYNC mode; it is supplied to the SCLK inputs of all other repeaters on the bus and to the EEPROM. Asserts Chip Select (CS) High to enable the EEPROM. Outputs a serial 9-bit request-to-send (RTS) strobe. The programmable device responds to the RTS strobe with a serial data stream containing the setup parameters for all repeaters in the chain. Clocks the first 48 serial data input (SDI) bits from the EEPROM into its setup register. Refer to Table 9 and Table 10 for Setup Register bit assignments. Asserts Serial Enable Output (SENO) Low to enable the next repeater in line. The second repeater has FPS tied Low and Serial Enable Input (SENI) connected to the Serial Enable Output (SENO) of the first repeater. When enabled by a Low on SENI, each repeater downloads its portion of the stream, then stops accepting data and asserts SENO Low. The SENO pin is linked to the SENI input of the next repeater. This enables the next repeater to clock in its 48- bit word and so on. If FPS is Low (Not First Position), the repeater performs the following functions:
- Syncs to the 1 MHz Serial Clock (SCLK) input. SCLK is supplied by the First Position
- Responds to SENI Low by enabling the SDI port.
- Clocks 48 bits from the EEPROM into its setup register through the SDI port.
- Asserts SENO Low to enable the next repeater in line.
Figure 3. Global State Machine
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Figure 4. Partitioning State Machine
2.4.2 External Management Mode Initialization
- Syncs to the 10 MHz Serial Clock (SCLK) input. SCLK must be supplied from an external
Low by enabling the SDI port.
- Clocks 48 bits from the EMD into its setup register through the SDI port.
- Once initialized, the LXT914 Repeater reports its status in a 48-bit serial stream after every
bit assignments and definitions. Table 9. Setup Register Bit Assignments Table 10. Setup Register Bit Definitions RES Reserved. Must be set to 0.
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Table 11. Packet Status Register Bit Assignments Table 12. Packet Status Register Bit Definitions
- The notation ABCD x means bit ABCD associated with port x, which can be any of the four Twisted-
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2.5.1.1 Programmable Internal Squelch Level
The 10BASE-T port receivers have two squelch levels: a normal level or default setting and a reduced level squelch (-4.5 dB) selected when the ERSQx is set in the Setup register. When used with Low noise media such as shielded twisted-pair cabling, the reduced squelch level allows longer loop lengths in the network.
2.5.1.2 Polarity Detection and Correction
The LXT914 Repeater 10BASE-T ports detect and correct for reversed polarity by monitoring link pulses and end-of-frame sequences. A reversed polarity condition is declared when the port receives sixteen or more incorrect link pulses consecutively, or four frames with reversed start-of- idle sequence. In these cases the receiver reverses the polarity of the signal and thereby corrects for this failure condition. If the port enters the link fail state and no valid data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. (If Link Integrity Testing is disabled, polarity detection is based only on received data.) 2.5.2 10BASE-T Transmission Each LXT914 Repeater 10BASE-T port receives NRZ data from the repeater core and passes it through a Manchester encoder. The encoded data is then transmitted to the twisted-pair network (the DO circuit). The advanced integrated pulse shaping and filtering network produces the pre- distorted and pre-filtered output signal to meet the 10BASE-T jitter template. An internal continuous resistor-capacitor filter is used to remove any high-frequency clocking noise from the pulse shaping circuitry. Integrated filters simplify the design work required for FCC compliant EMI performance. During idle periods, the LXT914 Repeater 10BASE-T ports transmit link integrity test pulses in accordance with the 802.3 10BASE-T standard. Data packets transmitted by the LXT914 Repeater contain a minimum of 56 preamble bits before the start of frame delimiter (SFD). In the Asynchronous mode, preamble regeneration takes place on the transmit side. In the Synchronous mode, the preamble is regenerated on the receive side and distributed via the IRB. If the total packet is less than 96 bits including the preamble, the LXT914 Repeater extends the packet length to 96 bits by appending a Jam signal (1010...) at the end. 2.5.3 10BASE-T Link Integrity Testing The LXT914 Repeater fully supports the 10BASE-T Link Integrity test function. The link integrity test determines the status of the receive side twisted-pair cable. Link integrity testing is enabled unless disabled via the DISLIx bit in the Setup register. When enabled, the receiver recognizes link integrity pulses transmitted in the absence of data traffic. With no data packets or link integrity pulses within 100 (±50) ms, the port enters a link fail state and disables its transmitter. The port remains in the link fail state until it detects three or more data packets or link integrity pulses.
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2.6 AUI Port Operation
2.6.1 AUI Reception
bit times (typical), the AUI receiver enters the idle state.
2.6.2 AUI Transmission
Manchester encoder. The encoded data then goes out on the network (AUIDOP/AUIDON).
2.6.3 AUI Mode Selection (DTE/MAU)
interface is selected and the LEDJM/AUISEL function is unavailable. Table 13. AUI Mode Selection (DTE/MAU)
1 Low Low DTE default, 0-3
3 High Low MAU default, 0-3
4 High High MAU 1-3
Note: Application 3 is valid only when using the 100-pin PQFP .
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2.7 Collision Handling
A collision occurs when two or more repeater ports receive simultaneously, or when the AUI CIP/ CIN signal is active. The LXT914 Repeater fully complies with the IEEE 802.3 collision specifications, both in individual and multi-repeater applications. In multiple-repeater configurations, collision signaling on the IRB allows all repeaters to share collision parameters, acting as a single large repeater. IRCOL is a digital open-drain pin. IRCFS is an analog/digital port. The IRCOL and IRCFS lines are pulled up globally (i.e., each signal requires one pull-up resistor for all boards). If there are eight 3-repeater boards in the system, all eight boards share a single pull-up resistor for IRCOL and a single pull-up resistor for IRCFS . The global pull-up may be located on one of the boards, or on the backplane. The IRCFS line requires a precision (± 1%) resistor. The IRENA, IRDAT and IRDEN lines are each pulled up locally (one pull-up resistor per board) if external bus drivers are used. If no bus drivers are used then only one global pull-up per signal is used.
2.8 Security Mode
The LXT914 Repeater security mode is fully transparent to the user. In the External management mode, the security feature is available for all four TP ports and the AUI port. In the Local mode, security is available for the TP ports only (the SECAUI input is reassigned as FPS). The security inputs are normally held Low to disable the security feature. Any input can independently be pulled High to scramble the respective port for any given length of time. For applications which do not require security control, the SEC pins must be tied Low. The security mode pins are real time response inputs. This allows the board designer to screen the destination address with an application specific device and (on match of the destination address) to assert the security input to jam the respective port for the given frame. This real time detection and jam assertion method provides the flexibility to implement customer specific solutions. The destination address decoding and security signal assertion functions can be integrated into the external management device.
2.9 LED Display
The LED display interface consists of seven integrated LED drivers, one for each of the five network ports and two for common functions. Each pin provides a three-state pulsed output (+5 V , high Z, and 0 V) which allows multiple conditions to be monitored and reported independently. Table 14 shows the LED Mode selected with each LEDM1 and LEDM0 combination. Figure 5 shows the LED Driver output conditions, and Table 15 through Table 18 list the repeater states associated with each of the five conditions. Note: If LED mode 0 is selected and the LEDJM/AUISEL pin is High (which selects MAU Mode), the device defaults to LED Mode 1. LED Mode 0 is not available when LEDJM/AUISEL is pulled High.
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the LED Mode defaults to Mode 1. is pulled High by a pull-up resistor. Refer to Table 16. and LEDM0 is floating or pulled Low. Refer to Table 17. and LEDM0 is also pulled High by a pull-up resistor. Refer to Table 18. Table 14. LED Mode Selection
- This mode is not available when using the LEDJM/AUISEL pin to
Table 15. Mode 0 (Default) LED Truth Table
1 Rx Link Pulse N/A FIFO Error Manchester Code Violation
2 Tx Packet Tx Packet N/A N/A
3 Reversed Polarity N/A Collision MAU Jabber Lockup
4 Rx Packet Rx Packet N/A N/A
5 Partitioned Out Partitioned Out N/A N/A
Table 16. Mode 1 LED Truth Table
1 Rx Link Pulse N/A MAU Jabber Lockup
2 N/A N/A N/A N/A
3 N/A N/A Collision N/A
5 N/A N/A N/A N/A
Table 17. Mode 2 LED Truth Table
2 Partitioned Out Partitioned Out N/A N/A
Table 18. Mode 3 LED Truth Table
2 Rx Packet Rx Packet N/A N/A
3 Partitioned Out Partitioned Out Collision N/A
4 N/A N/A N/A N/A
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Figure 5. Integrated LED Driver Indications
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3.0 Application Information
3.1 Layout Requirements
3.1.1 The Twisted Pair Interface
The four, twisted-pair output circuits are identical. Each TPDOP/TPDON signal has a 24.9 Ω, 1%, series resistor and a 120pF capacitor differentially across the positive and negative outputs. These signals go directly to a 1: √2 transformer creating the necessary 100 Ω termination for the cable. The TPDIP/TPDIN signals have a 100 Ω resistor across the positive and negative input signals to terminate the 100 Ω signal received from the line. To calculate the impedance on the output line interface, use: The layout of the twisted-pair ports is critical in complex designs. Run the signals directly from the device to the discrete termination components (located close to the transformers). The signals running from the transformers to the connector should run in close pairs directly to the connector. Be careful not to cross the transmit and receive pairs. One way to avoid a problem is to run the receive pairs on the component side and the transmit pairs on the solder side. Careful planning during the schematic and layout stages can avoid these problems. The PCB layout should have no ground or power planes from the transformers to the connectors. The data signals should be the only traces in this area. Place the chassis ground for the connectors near the edge of the PCB, away from the signals, connecting the connector shield with the chassis.
3.1.2 The RBIAS Pin
The RBIAS signal sets the levels for the output drivers of the LXT914 Repeater. Any emissions or common mode noise entering the device here could be measured on the twisted pair output signals. The LXT914 Repeater requires a 12.4 k Ω, 1% resistor directly connected to RBIAS. This connection should be as short as possible. The ground rails from the adjacent ground pins should come directly off of the device to enclose the resistor and pin forming a shielded area between the RBIAS connection and the switching signals on the PCB. 3.2 12-Port Hub Repeater Figure 6 through Figure 9 (Sheets 1 through 4) show a simple 12-port hub repeater application with three LXT914 Repeaters. This application also provides two additional AUI ports—one DB-15 connector and one coaxial port. The application shown uses the asynchronous backplane mode so no external backplane clock source is required. Figure 6 (Sheet 1) shows the XL93C46 EEPROM which downloads the setup parameters for all the LXT914 Repeater devices at initialization. (This EEPROM could be replaced with a simple pull down resistor on the SDI pin. This will select the default conditions of the set up register.) A single 20 MHz crystal provides the SYSCLK for all three LXT914 Repeater. The LXT914 Repeater hub repeater on Sheet 1 provides the AUI DB-15 connector as well as four twisted-pair ports. Table 19 lists transformers suggested for use with the LXT914 Repeater.
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remaining LXT914 Repeaters, along with the LED operation table. with both LXT914 Repeaters in the first position. pulling LEDM1 Low with pin 35 attached to ground.
- However, the AUI port has been configured as a MAU interface. This is selected when LEDJM/
hub, eliminating the need for additional external equipment. Table 19. Manufacturers Magnetics List
Figure 6. 12-Port Application Schematic, 68-Pin PLCC Package (Sheet 1 of 4)
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Figure 7. 12-Port Application Schematic, 68-Pin PLCC Package (Sheet 2 of 4)
Figure 8. 12-Port Application Schematic, 68-Pin PLCC Package (Sheet 3 of 4)
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Figure 9. 12-Port Application Schematic, 68-Pin PLCC Package (Sheet 4 of 4)
Figure 10. 8-Port Application Schematic, LED Mode 1 with AUISEL = MAU (Sheet 1 of 2)
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Figure 11. 8-Port Application Schematic, LED Mode 1 with AUISEL = MAU (Sheet 2 of 2)
4.0 Test Specifications
operating conditions specified in Table 21. Table 20. Absolute Maximum Ratings for extended periods may affect device reliability. Table 21. Recommended Operating Conditions Table 22. I/O Electrical Characteristics 1 (Sheet 1 of 2)
- Not applicable to IRB signals. IRB electrical characteristics are specified in Table 25.
- Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to
- Supply current may vary depending on the transformer, LED, and resistor selections.
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Table 23. AUI Electrical Characteristics
- Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to
Table 24. Twisted-Pair Electrical Characteristics
- Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to
- IEEE 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder,
Table 22. I/O Electrical Characteristics 1 (Sheet 2 of 2)
- Not applicable to IRB signals. IRB electrical characteristics are specified in Table 25.
- Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to
- Supply current may vary depending on the transformer, LED, and resistor selections.
Table 25. IRB Electrical Characteristics
- Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to
Table 26. Switching Characteristics
- Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to
Table 27. Serial Port Timing—External Mode
- Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to
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Figure 12. Serial Port Timing Table 28. Inter-Repeater Bus Timing
- Typical values are at 25° C and are for design aid only; they are not guaranteed and not subject to
Figure 13. Inter-Repeater Bus Timing
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5.0 Package Specifications
Figure 14. LXT914PC/PE Package Specifications
Figure 15. LXT914QC Package Specifications
0.026 BSC1
0.65 BSC
- BSC = Basic Spacing Between Centers
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5.1 Top-Label Marking
Figure 16 shows a sample PLCC package for the LXT914 Repeater. do not have the “e3” symbol in the last line of the package label. Figure 17 shows a sample Pb-Free (RoHS-compliant) PLCC package for the LXT914 Repeater. Figure 16. Sample PLCC Package - Intel ® LXT914 Repeater Figure 17. Sample Pb-Free (RoHS-Compliant) PLCC Package - Intel ® LXT914 Repeater
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6.0 Product Ordering Information
Figure 29 and Figure 20 provide IXF1110 MAC product ordering information. Table 29. Product Ordering Information
Figure 20. Ordering Information Matrix – Sample