EE87C196NT

Intel Corporation

Chmos microntroller

Manufacturer: Intel Corporation

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8XC196NT . CHMOS MICROCONTROLLER WITH

1 MBYTE LINEAR ADDRESS SPACE

@ 20 MHz Operation @ Oscillator Fail Detection Circultry @ High Performance CHMOS 16-Bit CPU @ High Speed Peripheral Transaction @ Up to 32 Kbytes of On-Chip OTPROM Server (PTS) m Up to 1 Kbyte of On-Chip Register RAM = TWO aan High-Speed . z to 512 ove of Internal RAM ™ 10 High Speed Capture/Compare (EPA) im Register-Register Architecture m= Full Duplex Synchronous Serial 1/0 @ 4 Channei/10-Bit A/D with Sample/Hold Port (SSIO) @ 37 Prioritized Interrupt Sources @ Two Flexible 16-Bit Timer/Counters m Up to Seven 8-Bit (56) I/O Ports @ Quadrature Counting Inputs @ Full Duplex Serial I/O Port @ Flexible 8-/16-Bit External Bus m Dedicated Baud Rate Generator (Programmable) @ Interprocessor Communication Slave m Programmable Bus (HOLD/HLDA) Port @ 1.4 ys 16 x 16 Multiply @ Selectable Bus Timing Modes for @ 2.4 ps 32/16 Divide Flexible External Memory Interfacing m 68-Pin Package Add Ce [mmm [ome |B re Jom Lexcieenr | espricc | sex [ax | siz | imoye [se | so [4 | X= 7 OTPROM Device X = 0 ROMLESS The 8XC196NT 16-bit microcontroller is a high performance member of the MCS® 96 microcontroller family. The 8XC196NT is an enhanced 8XC196KR device with 1 Mbyte of linear address space, 1000 bytes of register RAM, 512 bytes of internal RAM, 20 MHz operation and an optional 32 Kbytes of OTPROM. Intel's CHMOS III-E process provides a high performance processor along with low power consumption. Ten high-speed capture/compare modules are provided. As capture modules event times with 200 ns resolu- tion can be recorded and generate interrupts. As compare modules events such as toggling of a port pin, starting an A/D conversion, pulse width modulation, and software timers can be generated. Events can be based on the timer or up/down counter. a

4.268 September 1994

MH 4826175 0144884 477? Mm Onsen Mabe 272267 298

0 COQ,

8XC196NT | ntel 8XC196NT Memory Map FFFFFFH FFAOO0H External Memory FFOFFFH internal OTPROM or External Memory (Determined by EA Pin) FF2080H RESET at FF2080H FF207FH Reserved Memary (intemal OTPROM or External Moon) FF2000H (Determined by EA Pin) FFIFFFI Prosar External Memory FFOSFFH , - Internal RAM (|dentically Mapped into 00400H-005F FH) FFOSFFH FFO100H External Memory FFOOFFH Frooont Reserved for ICE ‘eaocor External Memory for future devices FFFFFH boneoo 984 Kbytes External Memory oooooon Internal OTPROM or External Memory (Note 1) (00207FH Reserved Memory (Internal OTPROM or External Memory) 002000H (Notes 1, 3, and 6) OOIEEOH Memory Mapped Special Function Registers (SFR's) ooreoant Internal Special Function Registers (SFR's) (Note 5) oooseans External Memory OO0SFFH internal RAM 000400H (Address with indirect or Indexed Modes) 0003FFH Upper Register File (Address with Indirect or Register RAM 0001004 Indexed Modes or through Windows.) (Note 2) (000FFH Lower Register File 000018H Register RAM (Address with Direct, Indirect, or Indexed (000017H . ‘000000H CPU SFR's Modes.) (Notes 2, 4) NOTES: 1, These areas are mapped internal OTPROM if the REMAP bit (CCB2.2) is set and EA = 5V. Otherwise they are external memory. 2. Code executed in locations 00000H to 003FFH will be forced external. ‘3. Reserved memory locations must contain OFFH unless noted. 4, Reserved SFR bit locations must be written with 0. 5. Refer to 8XC196NT User's Guide and Quick Reference for SFR descriptions. 6. WARNING: The contents or functions of reserved memory locations may change with future revisions of the device. Therefore, a program that relies on one or more of these locations may not function property. 7. The 8XC196NT internally uses 24 bit address, but only 20 address lines are bonded out allowing 1 Mbyte external address space. 4-268 ADVANCE INFORMATION MB 4826175 O14488b CUT

Figure 3. 68-Pin PLCC Package Diagram

excres intel. PIN DESCRIPTIONS Name and Function Wain supply votage (+ 5¥) Vss, Vss1. Vss1 Digital circuit ground (0V). There are multiple Vsg pins, all of which MUST be connected. Ver Reference for the A/D converter (+ 5V). Vrer is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. Vpp Programming voltage for the OTPROM parts. It should be + 12.5V for programming. It is also the timing pin for the return from powerdown circuit. Connect to Vcc if powerdown not being used. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as Vss. XTAL1 Input of the oscillator inverter and the internal clock generator. XTAL2 Output of the oscillator inverter. «| P2.7/CLKOUT Output of the internal clock generator. The frequency is / the oscillator frequency. Ithas a 50% duty cycle. Also LSIO pin. RESET Reset input to and open-drain output from the chip. RESET has an internal pullup. P5.7/BUSWIDTH Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin dyamically controls the Buswidth of the bus cycle in progress. if BUSWIDTH is low, an 8-bit cycle occurs, if BUSWIDTH is high, a 16-bit cycle ocours. If CCR bit 1 is “0” and CCA1 bit 2is "1", all bus cycles are 8-bit, if CCR bit 1 is “1” and CCR1 bit 2 is “0”, all bus cycles are 16-bit. CCR bit 1 = “0” and CCR bit 2 = “0” is illegal. Also an LSIO pin when not used as BUSWIDTH. A positive transition causes a non maskable interrupt vector through memory location 203EH. P5.1/INST/SLPCS | Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. INST is active only during external memory fetches, during internal OTPROM fetches INST is held low. Also LSIO when not INST. SLPCS is the Slave Port Chip Select. EA Input for memory select (External Access). EA equal to a high causes memory accesses to locations 0FF2000H through OFF9FFFH to be directed to on-chip OTPROM. EA equal to a low causes accesses to these locations to be directed to. off-chip memory. EA = + 12.5V causes execution to begin in the Programming Mode. EA is latched at reset. Bus Hold Input requesting control of the bus. Bus Hold acknowledge output indicating release of the bus. Bus Request output activated when the bus controller has a pending external memory cycle. P5.0/ALE/ADV/ | Address Latch Enable or Address Valid output, as selected by CCR. Both pin SLPADDR/ options provide a latch to demultiplex the address from the address/data bus. When SLPALE the pin is ADV, it goes inactive (high) at the end of the bus cycle. ADV can be used as a chip select for external memory. ALE/ADV is active only during external memory accesses. Also LSIO when not used as ALE. SLPADDR is the Slave Port ‘Address Control Input and SLPALE is the Slave Port Address Latch Enable Input. P5,3/RD/SLPRD | Read signal output to external memory. RD is active only during external memory reads oF LSIO when not used as AD. SLPRD is the Slave Port Read Control Input. 4-270 ADVANCE INFORMATION M@ 4826175 0144888 O12 a |

. . intel ° 8XC196NT PIN DESCRIPTIONS (Continued) P5.2/WR/WRL/SLPWR | Write and Write Low output to external memory, as selected by the CCR, WR will go low for every external write, while WAL will ge low only for external . writes where an even byte is being written. WA/\\ is active during external memory writes. Aiso an LSIO pin when not used as WR/WAL. SLPWR is the Slave Port Write Control Input P5.5/BHE/WRH Byte High Enable or Write High output, as selected by the CCR. BHE=0 selects the bank of memory that is connected to the high byte of the data bus. A0=0 selects that bank of memory that is connected to the low byte. Thus accesses to a 16-bit wide memory can be to the low byte only (AO=0, BHE = 1), to the ver byte only (AO= 1, BHE =0) or both bytes (AO=0, BHE =0). If the function is selected, the pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH is only valid during 16-bit external memory read/write cycles. Also an LSIO pin when not BHE/WRH. P5.6/READY Ready input to lengthen external memory cycles, for interfacing with slow or dynamic memory, or for bus sharing. If the pin is high, CPU operation continues in anormal manner. If the pin is low prior to the falling edge of CLKOUT, the memory controller goes into a wait state mode until the next positive transition in CLKOUT occurs with READY high. When external memory is not used, READY has no effect. The max number of wait states inserted into the bus cycle is controlled by the CCR/CCR1. Also an LSIO pin when READY is not selected. PS5.4/SLPINT Dual function I/O pin. As a bidirectional port pin or as a system function. The system function is a Stave Port Interrupt Output Pin. P6.2/TICLK Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however, it may also be used as a TIMER1 Clock input. The TIMER? will increment or decrement on both positive and negative edges of this pin. P6.3/TIDIR Dual function I/O pin. Primary function is that of a bidirectional 1/O pin, however, it may also be used as a TIMER1 Direction input. The TIMER1 will increment when this pin is high and decrements when this pin is low. PORT1/EPAO-7 Dual function I/O port pins. Primary function is that of bidirectional I/O. System P6,0-6.1/EPA8-9 function is that of High Speed capture and compare. EPAO and EPA2 have yet another function of T2CLK and T2DIR of the TIMER2 timer/counter. PORT 0/ACH4-7 4-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. These pins are also used as inputs to OTPROM parts to select the Programming Mode. P6.3-6.7/SSIO Dual function |/O ports that have a system function as Synchronous Serial I/O. Two pins are clocks and two pins are data, providing full duplex capability. PORT 2 8-bit multi-functional port. All of its pins are shared with other functions. PORT 3 and 4 8-bit bidirectional 1/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. EPORT 8-bit bidirectional standard and !/O port. These bits are shared with the extended address bus, A16-A19. Pin function is selected on a per pin basis. Interrupt Output. This active-low output indicates that a pending interrupt requires use of the external bus. Slave Port Address/Data Bus ADVANGE INFORMATION 4271 BH 4826175 0144889 159

. . 8XC196NT intel ° ABSOLUTE MAXIMUM RATINGS* NOTICE: This data sheet contains information on products in the sampling and initial production phases: Voltage change without notice. Verify with your local Intel Ven ere FAto ~05Vto +13,0V _ | Sales office that you have the latest data sheet be- vere ° fore finalizing a design. ul veta veg or ANGND. oP cen 05t0+70V CANS tae a device beyond the "Abeokne This includes Vpp on ROM and CPU devices. Maximen Ratings” ting, Galy. Cperation damage. tended exposure beyond the “Operating Conditions” may affect device reliability. OPERATING CONDITIONS symbol [Parameter | Min. | Max [Units Ambient Temperature UnderBias | 0 | +70 [sc | Digital Supply Voltage [vaso [sso [ov | Analog Supply Voltage [450 [sso [ov | L_Fosc | Oscillator Frequency ee ee NOTE: : ANGND and Vgs should be nominally at the same potential. DC CHARACTERISTICS (Under Listed Operating Conditions) [Symbo![ Parameter | in_ [Typ] max [unite] TestConattions | Voc Supply Current XTAL1 = 20 MHz, Voc = Vpp = Vrer = 5.5V AlDReterence Supply Curent ||| s__| ma | Whledevicelneseo Idle Mode Current XTALt = 20 MHz, Voc = Vpp = Ver = 5.5V InputLow Voltage atipiney | -o8v | | 03Voo | v_|ForPoRToto [vin [inputhignvottage | 0.7Voc | [Voc +05] v _[ForpoRToto Input High Voltage on RESET | 0.7 Vcc | [Voc + 05| V_|RESET input pin only Vo. _ | Output Low Voltage Vio. = 200 2A85) (Outputs Configured as V flop = 3.2mA Complementary) V_ [lot = 7.0mA Vox | Output High Voltage Voc - 0.3 V_ |lon = —200pA@.5) (Outputs Configured as Veo - 0.7 V_ [io = —3.2mA Complementary) Voo - 1.5 V_ |lon = -7.0mA InputLeakage Curent (Std inputs)| [10 | wa [Vas <Viv<Voo | Logical © Input Current [TT =70 [na |v = o48ven

4.272 ADVANCE INFORMATION

intel . @XC196NT DC CHARACTERISTICS (Under Listed Operating Conditions) (Continued) [ symbot | __Parameter [in| tye | wax | unite | Test Conditions OuiputLowvotageinneser | || oe | v_ | woten Vout ‘SLPINT (P5.4) and HLDA (P2.6) v lon = 0.8 mA Output High Voltage in RESET Weak Pulup Resistance | | sok | aT ote NOTES: 1, AILBD {Gicirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to their not being weakly, wa high in reset. BD pins include Port1, Port2, Port3, Port4, Port5, Porté and EPORT except SPLINT (P5.4) and HLDA 2. Standard input pins include XTAL1, EA, RESET, and Port 1/2/5/6 and EPORT when setup as inputs. ‘3. All bidirectional I/O pins when configured as Outputs (Push/Pull). 4. Device is static and should operate below 1 Hz, but only tested down to 4 MHz. 5. Maximum io. /Ioy currents per pin will be characterized and published at a later date. 6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and Vaer = Voc = 5.5V. 7. Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6). 8. TBD = To Be Determined. 9. Pullup present during return from powerdown condition. 10. When PO is used as analog inputs, refer to A/D specifications. 11. For temperatures < 100°C typical is 10 wA. 4 ADVANGE INFORMATI 4-273 | MP 4626175 014489) bO7 mm

8XC196NT intel : 8XC196NT ADDITIONAL BUS TIMING MODES The 8XC196NT device has 3 additional bus timing MODE 1: modes for external memory interfacing. Mode 1 is the long R/W mode. This mode advances : RD and WR signals by 1 Tosc creating a 2 Tosc MODE 3: RD/WR low time. ALE is also advanced by 0.5 Tosc Mode 3 is the standard timing mode. Use this mode Put ALE high time remains 1 Toso. for systems that emulate the 8XC196KR bus tim- ings. MODE 2: Mode 2 is the long R/W mode with Early Address. MODE 0: Mode 2 is similar to Mode 1 with respect to RD, WR, Mode 0 is th timing mode, but 1 (mini. 24 ALE signals. Additionally, the address is output wows oie me oi siwaye haurted . Cutt mink ‘on the bus 0.5 Tosc earlier in the bus cycle. cycles. ‘ose xTAL Bn CLKOUT Ae ‘MODE (3) MODE (1,2) «mee i ne Cn i ooo Seeee:, TT MODE (1,2) a oe. Figure 4, Detalled MODE 1, 2, 3, Comparison 4-274 ADVANGE INFORMATION WB 4826175 O144ad2 543 me

intel ° 8XC196NT EXPLANATION OF AC SYMBOLS Conditions: Signals: ; ; H—High A—Address HA—HLDA Each symbol is two pairs of letters prefixed by “T" Low B-BHE L—ALE/ADV for time. The characters in a pair indicate a signal Valli and its condition, respectively. Symbols represent, 0 BR BAEC. Data Ou the time between the two signal/condition points. io Longer D—RD Valid D-DATA — W—WR/WRH/WAI ZFloating — G—Buswidth X—XTALt H-HOLD — Y—READY BUS MODE 0 and 3—AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns, The system must meet these specifications to work with the BXC196NT. [_symbor [Parameter [Min [Max | Unite | Address Valid to Ready Setup a ee Non READY Time No Upper Limit [ ns | READY HodaterGiKOUTIow | 0] Tego 90 | rot] Address ValidtoBUSWIDTHSetup | | 2 Tosc—75 | ns) _| BUSWIDTHHoldattercLKOUTLow | 0 [|r| ‘Address Valid to input Data Valid es ee 4 End of FD to input Data Float re ee ee NOTES: 1. If Max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 Togc x n, where n = number of wait states. 3. If mode 0 is selected, one wait state minimum is always added. If additional wait states are required, add 2 Tosc to the ‘specification. | ADVANCE INFORMATION” 4-275 BS 4626175 0144893 4oT

8XC196NT intel : BUS MODE 0 and 3—AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns. The 8XC196NT wilt meet these specifications Frequency on XTALt [40 | aot | XTALI Period (1/Fxra) [| so | esos XTALIHightoGLKOUTHighortow [+20 | ons GlockFaietoResetPuledtow [4 [ao fas CLKOUT Period [a tosc ns CLKOUT High Period | Toso-10 | Tosc+ 30 | ns | CLKOUTLowtoALe/ADVHgh — [ -10 | +15 ns ALE/ADVLowtoGuKoUTHignh | =28 | 5 ns ALE/ABV Gycle Time ee ALE/ADV High Time | Toso- 10 | Tosc+10 | ns | Address Vaid to ALE Low [Toso is | Tne AddressHold After ALE/ADVLow | Toso- 40 | | ns ALE/RDV Low to RD Low | Toso= 40 [| | ns FID Low to GLKOUT Low [sas | ns FD Low Period [Tose 5 [ns FD High to ALE/ADV High Toso? 25 | ns _| FD Low to Addross Float [ts ns ALE/RDV Low to WR Low [ Tosco | | ns CLKOUT Low to WH Low [=o | tess Data Valid before WA High Toso-23 [rs GLKOUT High to WR High [=o [+s | ns | WR Low Period ee ee Data Hold after WF High [ Toso 8 | | ns | WR High to ALE/ABV High [Toso = 10 [Toso +15 | nse | BRE,INSTHoldatterWAHigh | Toso- 10 | [nes AD8~15 Hold after WA High Toso 30 [| nse | BRE,INSTHoldatterFOHigh | Tosc—10 [| ns AD8—15 Hold after AD High [Foso= 30 [| ns NOTES: 1. Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4. B-bit bus only. 5. If wait states are used, add 2 Tosc x n, where n = number of wait states. if mode 0 (1 automatic walt state added) ‘operation is selected, add 2 Togc to specification. 6. Toro is the time tor the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is enabled by programming the UPROM location 0778H with the value 0004H. NT/NQ customer QROM codes need to equate location 2016H to the value OCDEH if the oscillator fail detect (OFD) function is desired. Intel manufacturing uses location 2016H_ as a flag to determine whether or not to program the Clock Detect Enable (CDE) bit. Programming the CDE bit ‘enables oscillator fail detection.

4278 ADVANGE INFORMATION

intel ° 8XC196NT BUS MODE 0 and 3—8XC196NT SYSTEM BUS TIMING Tose XTALt Toren Tne CLOCKOUT Tou Tuch Tun” ~ ALE/ADV \\ Tua . Ture TruRH TRHLH — Truoy RD TRHOZ TrHox ous ReAD (Comm) Tavov WR fe Tov Twwox —of Twuex °F TrHBx BE, st TwHax °F Traax 272267-5 *lf mode 0 operation is selected, add 2 Tosc to this time. ADVANGE INFORMATION 4-277 MHP 4826175 0144895 252 Me

8XC196NT intel. 8XC196NT MODE 0 and 3—READY TIMINGS (ONE WAIT STATE) Tosc . XTALT Tanne CLKOUT Tact Tou Tue Toure (win) READY WW Tavev * 2 Tose* Trurn * 2 Tosc® Tayov * 2 Tosct ———+| Je wor aus reaD _ )))) GE)», Twown * 2 Tose” WR BUS WRITE (a , (272267-6 “If mode 0 selected, one wait state is always added. If additional wait states are required, add 2 Togc to these specifica- tions. MODE 0 and 3—8XC196NT BUSWIDTH TIMINGS Tose CLKOUT ALE Tuev® | Teox BUS WRITE ee (GE CN 272677 “If mode 0 selected, add 2 Tosc to these specifications. 4-278 ADVANGE INFORMATION BP 4626175 Ol44a5b 195

intel ° BXC196NT BUS MODE 1—AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns. The system must meet these specifications to work with the 8XC196NT. [_svmbot [Parameter | win | Max [unite [tanw | _AdtossvaistoReewySaup [| Bose 75 | ne _| [trum | NenAicaby Tine | NoUmperumt | ne [Teun [READY HoldaterGixouTtow | 0 | Toso-30 | ret [Twvey | AdtessvaietoBuswioTHsetp [| Pose 75 | ne | [Tucv | Atetowiosusminriseue || 18 Toso- 60 | ns | [Tewex | BUSWITHHoWatercuxouTiow | o | | ms [Taw | Atos vaistoipuOaavola |_| SToso=60 | ro | [Toy | PBacivotoinputDaavals | |? Tosco | nat _| [tau | xOUTLow inp oaavaid | [Toso =60 | ne [Twoz | Entei RB oineuaaron || Tos | ms | [Two | oataHoaaterRDHgn | [| re | NOTES: 1. If Max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 Togo * n, where n = number of wait states. | ADVANCE INFORMATION 4.279 MH 4426175 0144897 O2S

bd ’ MODE 1—8XC196NT SYSTEM BUS TIMING Tose XTALI Tenet Tesco TxHcH LOCKOUT Tou Tuy ALE/ADV \\ Tumut Ture Tru TRHUH = —— RD feo ous RAD )) a (SCT), = ‘om We - ia Two Twuexs TRHex aE (ee) Twuaxe TrHax Twn Trix e288 | Al ol 4-281 DYANCE INFORMATION MH 4626175 0144899 578

8XC196NT intel ° MODE 1—8XC196NT READY TIMINGS (ONE WAIT STATE) Tose XTALT Tawa CLKOUT Tore ALE hy READY TL) Taw Teun * 2 Tose RD . BUS READ yy)», CE)» Twum * 2 Tose WR . blow? Tose wus wae D(C 272267-9 MODE 1—8XC196NT BUSWIDTH TIMINGS Tose CLKOUT ALE Tuov —| Touex Bus WRITE (romessor X(Q__ enor ire ot XK 272267-10 4-282 ADVANCE INFORMATION MM 4426175 O144900 4oT a

8XC196NT intel . BUS MODE 2—AC CHARACTERISTICS (Over Specified Operating Conditions) Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns. The 8XC196NT will meet these specifications ["symoot [Parameter [win [wa | Unt [Fear] Freweneyonxtarr fo | a0 || [toss | TAL Perea vecad ‘| 50 | es |_| [tesca[ TAL Hono cuxoUTHghortow | +20 | as | rw _| [Tas | ciKoutrees | SSRs Si | | Ton. | CLKouTHighPerod | Toso 10 | Tosc+27 | ne | [Troan | cLKOUT Hokie LEMABV Han | 08 Tose = 18 | 05 Toso + 1 | ve _| [Teun | CUROUTLOW Ww ALE/ADVLow | 05Tose=25 | 08 Tose +15 | me | [Town | ACADVGeeTe tao | [Tua | ALEADVHign Time | tose =| Toso 10 |e _| [Tae | Aatosealeso ALE Low | Toso =15 | | rw | [Tux | Adios Hol ater ALE/ADViow | @8Tosc- 20 |_| nw | [usm | AERO Low oD Low | 05Toso 15 | ——~dt | [tuo | FBtowecixourtow | Toso 10 | Toso? | me _| [Tan | ABtowPoiod | Pose 20 | idm [tawn | ABHgnwALe/ADVHeh | 05Tosc-5 | O5Tosc? 25 | _rat_| [tau | ABLowioAdseserot |e [Tum | ALEMAOVLow Willow | osTose=v0 | ———~+| rw | [Tam | CLKOUTLowtoWRLow | Toso #2 | Toso 28 me | | Tov | OataValsbotoreWAHgh | eToso-as_[ |e | [ows | UKOUTHgnoWHn | 10 | tse | [ twicx | DataHoaterWrigh | 05Toso-1@ | ——~dSC—Sre | [Twn | Weigh te ALE/ADVHeh | 05Toso—10 | O5Tose + 10] na6_| [Twiox | SREHolaneWR Hon | Tose [is _| [Twn | NSTHoWaterWRvign | O5Toso- | Sd Sid [Twn | AD8-16 HoldatorWAHgh | 05Tosc 90 | ———~d at [Tex | BREHowaterROHon | Toss @e@ [|| [taux | INSTHoIaterADHign | O5Toso-a@ | —=«dYSC—*d L_ Trax | Ad8-15HoldatterADHign [| 0STosc—90 [| nat NOTES: 1, Testing performed at 8.0 MHz, however, the device is static by design and will typically operate below 1 Hz. 2. Typical specifications, not guaranteed. 3. Assuming back-to-back bus cycles. 4, B-bit bus only. 5. If wait states are used, add 2 Togc = n, where n = number of wait states. 4-284 ADVANCE INFORMATION | M™ 4826175 0144902 212

intel ° 8XC196NT MODE 2—8XC196NT SYSTEM BUS TIMING Tose XTALY Towee Torco TxweH CLOCKOUT Tou Tun ALE/ADV \\ TuHe Ture Tra TRURH - RD be Fave BUS READ (Camnnas_) = vm 4 wR }¥—_ Tovw TwHox aus WRITE Twaexe TrHex. BFE (a) Twaxe TRHAX 408 ~ A015 Twos Trex. Breer" | ADVANCE INFORMATION ge yaeui7s o144903 159 mm 8S

8XC196NT intel . MODE 2—8XC196NT READY TIMINGS (ONE WAIT STATE) Tose XTALT CLKOUT ALE (MIN) 7 READY 11) } Taw Trams * 2 Tose RD wus tao J) Xena) axcD))) Twowk * 2 Tose WR Tom * 2 ose ous ware Xan XQ amar MODE 2—8XC196NT BUSWIDTH TIMINGS CLKOUT ALE Tuov — Tex usw aus were Cae ))) phoma 4206 wm yg2b175 0144904 095 mm ADVANGE INFORMATION |

intel ° 8XC196NT BUS MODE 0, 1, 2, and 3—HOLD/HLDA TIMINGS (Over Specified Operation Conditions) Test Conditions: Capacitance Load on All Pins = 100 pF, Rise and Fall Times = 10 ns. [tines | ROB Seuptine Yes ||| CAKOUT Loto FUDA Low [= [se [oe CLKOUT Low BRE Low [=i [+8 |e | | Thasz | FUDALowtoAddressFiot | S| 428 | ns CDK ow oR, NST, RO, WAWeakvDmen [| +8 | re | CLOUT Low o HCD in [=e [6 [om CLKOUT Lo FES Heh [a [6 [os NOTE: 1, To guarantee recognition at next clock. 8XC196NT HOLD/HLDA TIMINGS Tose CLKOUT \\ / \\ y The ‘wor HOLD woo waroney eam vem sy HLDA Tevet Tevrw sg BREQ TwaLaz Taanax Twauez Taba BHE, INST, _ F.C 7 = v 7 Towua ALE —_ $$ 5 272267-14 ADVANCE INFORMATION wm 426175 oL44905 Te) mm “77

AC CHARACTERISTICS—SLAVE PORT SLAVE PORT WAVEFORM—{SLPL = 0) a" — TsRHAY neat FF % On} Pe Le * LY) (272267-15, ‘SLAVE PORT TIMING—{SLPL = 0) [_symbot_ [Parameter [Min |= sMax (| Unite | [Teun | Adose vaio tow or | DLow Paes [tose [rs [tems | “WRLowPwies [Foss re it Ona seupioWRHin | 70 | |r» | [Tomax | _WRvignoOuaimaig [0 |] NOTES: 1. Test Conditions: Fogg = 20 MHz, Tosc = 50 ns. Rise/Fall Time = 10 ns. Capacitive Pin Load = 100 pF. 2, These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. Specifications above are advanced information and are ‘subject to change. 4-288 mm 4826175 024490b 968 ma =ADVANCE INFORMATION |

intel ° 8XC196NT AC CHARACTERISTICS—SLAVE PORT (Continued) SLAVE PORT WAVEFORM—{SLPL = 1) Tse TsrHEN 8 | — « {| [mun Sam ® ——{ w [Teo], Tomo —_| Tswuwe 272287-16 SLAVE PORT TIMING—{SLPL = 1) Ao WRvigh oeSrin [eo | | ns FD Low Prod [Tose [| | Wi Low Period [Toso || es _| Wirigniodaaivals | af |e NOTES: 1, Test Conditions: Fogc = 20 MHz, Tosc = 50 ns. Rise/Fall Time = 10 ns. Capacitive Pin Load = 100 pF. 2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. Specifications above are advanced information and are subject to change. ADVANCE INFORMATION 4-289 MH 4826175 O144907 BTy

8XC196NT intel. EXTERNAL CLOCK DRIVE symbol | __ Parameter [Min [Max [Unite OscilatorFrequency | #20 |e OscilatorPeriod Tose) [| so | 280 Tn | High Time 0.88 x Toso o66Tosc | ns

035 Tose | 988Tosp | ns |

[tux | Risotime Pts Fall Time ee ee EXTERNAL CLOCK DRIVE WAVEFORMS. Tex Tux Text 0.7¥¢¢40.89. 7 ec O.7Veq"0.50 won O.7Veq "0.5 Troe, 2r2287-17 ‘AC TESTING INPUT, OUTPUT WAVEFORMS FLOAT WAVEFORMS sav INPUTS OUTPUTS: Vioapt®-15¥ Voy 0-15 J TEST FONTS NS Vioap70-15V Vo. 40.15 ¥ o.4sv - 272267~19 272287-18 For timing purposes a Port Pin is no longer floating AC Testing inputs are driven at 3.5V for a logic 1” and when a 150 mV change from load voltage occurs and 0.45¥ for a logic “0”. Timing measurements are made begins to float when a 150 mV change from the loading at 2.0V for a logic “1” and 0.8V for logic “0”. Vox/Vot level occurs loy/loy < 15 mA. 4-290 ADVANCE INFORMATION | M@™@ 4426175 0144908 730 a

The A/D converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VRE: 10-BIT MODE A/D OPERATING CONDITIONS fation Tonpertire [0 | +70 | 0] Dita! SupiyVotage | aso | 580 | v4 Araleg Supp Volage | 450 | ss | wn] [teow | Comerson Tine 19 | 8 | NOTES: 1. Ver must be within 0.5V of Voc. 2. The value of AD_TIME is selected to meet these specifications. 10-BIT MODE A/D CHARACTERISTICS (Using Above Operating Conditions)(®) [__ Parameter tye) Twin Mae nite] 1 1024 Level ee ee Absolute Error a = e Full Scale Error o2sz0s [| tse | Zeroorsetérr | ozszos [Tits | woa20 | 30 ss | DiterentalNon-tinearty [| 0.76 [+075 | tsas | Channelto-CrannelMatching | soi [| oT 10 LSBs | Repeatability soa [oT ttn Temperature Coefficients: Offset 0.009 LsB/c() Full Scale 0.009 LSB/C(1) Differential Non-Linearity 0.009 LSB/C(1) Of otter a a Vee Power Supp Raion [eo ||] asta iat Roitanee [ee J DC input Leakage Se VotagsonAraopinputPin |__| ANGNO05 | Vag +08 | va | *An “LSB” as used here has a value of approximately § mV. NOTES: 1. These values are expected for most parts at 25°C, but are not tested or guaranteed, 2. DC to 100 KHz. 3, Multiplexer break-before-make is guaranteed. 4, Resistance from device pin, through internal MUX, to sample capacitor. 5. Applying voltages beyond these specifications will dagrade the accuracy of other channels being converted. 6. All conversions performed with processor in IDLE mode. 4-292 ADVANCE INFORMATION MH 4426175 0144910 399 me |

intel ° 8XC196NT 8-BIT MODE A/D OPERATING CONDITIONS Description [min Tax] unite AmbiontTemperature | | evo |e Analog Suppyvotage [450 | 660 |) Sample Time ee [Tony | Conversiontime | 7 | 20] [Foso | __OscilatorFrequoncy | 40 | 20 [Me NOTES: 1, Ver must be within 0.5V of Voc. 2. The value of AD_TIME is selected to meet these specifications. 8-BIT MODE A/D CHARACTERISTICS (Using Above Operating Conditions)(® pwamewr [te [wn | Mex [Un - 256 256 Level ee Absolute Error [os to tse | Full Scale Error [sos [ts Zero Ortset Eror [sos [ts | 4 [Nontineaty | | ST tts DiferoniatNontinearty | | 05 | os ise | Ghannelto-ChannelMatching | | oto | tse Temperature Coefficients: Offset 0.003 LsB/ct) Full Scale 0.003 LsB/Ct1) Differential Non-Linearity 0,003, LsB/C(1) Feedthrough ae VooPowersuppiyRelesion | eo [| | Lana) Input Resistance a OC pu Loatas [sie fe | a0 | | Voltage onAnaloginputPin |__| ANGND 05 | Vaer+os | we | Sampling Capacitor [so [Oe *An “LSB” as used here has @ value of approximately § mV. NOTES: 1. These values are expected for most parts at 25°C, but are not tested or guaranteed. 2. DC to 100 KHz. 3, Multiplexer break-before-make is guaranteed. 4, Resistance from device pin, through internal MUX, to sample capacitor. 5, Applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 6. All conversions performed with processor in IDLE mode. ADVANCE INFORMATION 4-293 | ME 4826175 0144911 225 mm

8XC196NT intel . OTPROM SPECIFICATIONS OPERATING CONDITIONS [_symbor | Description | Min | Max | Units | |_ ta [Ambient Temperature During Programming | 20 | 30 | °c ‘| | Voc | Supply Voltage During Programming =| as | 88 |v) |_vaer | Reference Supply Vottage During Programming | 45 | 85 | vi | | vee | ProgrammingVotage |= tas =| 275 | ve | | Vea | EAPinvoltage |S tts | ts | | a ee and Slave Mode Programming = Teese ett Run-Time Programming NOTES: 1. Voc and Vagr should nominally be at the same voltage during programming, 2. Vpp and Vea must never exceed the maximum specification, or the device may be damaged. 3. Vgg and ANGND should nominally be at the same potential (OV), 4, Load capacitance during Auto and Slave Mode programming = 150 pF. AC OTPROM PROGRAMMING CHARACTERISTICS (SLAVE MODE) | Tam. | Addressseuptime | ||| | Tum | AddrossHoigtine | t00 |S ~SCToso | | Tove | Dataseuptime | | SSCs | [Tex | Datatioidtime | 400 | dS Toso | | tun | PatEPusewan [50 | SS Tose | | Then | PROGPusewian@ | gO] | Toso | | Tine. | PALEHigh toPROGLow =| = ceo | S| Tose _—| | Tem | PROGHightonenPALELow | 220 | | Tose | | Tenox | WordDumpHoisTime | | 80S Tose | | Town | PROGHightonen PROG Low | 220 «| =| Toso | | Tu. | PALEHigntoPROGLow | za0 | S| tosc =| | Ts. | RESETHightoFistPALELow | 1100 =| | Tose. _| | Tun | ANCPusewiamn | Seto] SSCs | Tuva | PVERHoldaterANCLow | 0] S| Toso _—| | Tun | AINCLowtoPROGLow | 170] =| Tos L_ Tem | PROGHightoPVERVaid | | S220 «| Toso _—| NOTES: 1. Run-time programming is done with Fogc = 6.0 MHz to 10.0 MHz, Voc: Veo, Vaer = 5V +0.5V, To = 25°C +5°C and Vpp = 12.5V +0,25V. For run-time programming over a full operating range, contact factory. 2, This specification is for the word dump mode. For programming pulses use Modified Quick Pulse Algorithm. “O* wm ya2bi75 o1uuai2 161 mm AOVANGE INFORMATION |

intel . @XCI96NT DC OTPROM PROGRAMMING CHARACTERISTICS [““symbot [Parameter [win [ax [Unite | [be | rp Programing Supply Curent | [00 | ma NOTE: Do not apply Vpp unti Vog is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. OTPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE Reser Tan Tom FE m ee a, Tou ante Tr ‘PALE PROG pao We / Tu mae NOTE: 3.0 must be high ("1") SLAVE PROGRAMMING MODE IN WORD DUMP MODE WITH AUTO INCREMENT ‘RESET Tsu ADDR: ADDR + 2 ma Camron} Troy Towox PROC Ture ThHPL, ‘INC (272267-22 NOTE: P3.0 must be low ("0") ROM. 4-295 | ADVANGE INFORMATION = gy yg26175 OL4N9L3 OTS Mi

SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE AND AUTO INCREMENT RESET / PALE P21 \\ / Tour Tun Pave P ’2 Tun tao NERC ce, Tun ine Poe Town 272267-28 This data sheet (272267-004) applies to devices —_The following are differences between the 272267- marked with a “D” at the end of the top side tracking 003 and 272267-004 datasheets: number. 1. Changed all references of “EPROM” to “OTPROM". 8XC196NT Design Considerations 2 Added all the Slave er Pins 10 the package 1. When operating in bus timing modes 1 or 2, the igram and pi tions. upper and lower address/data lines must be 3. Added INTOUT pin to pin descriptions. latched. Even in 8-bit bus mode, the upper ad- 4, Changed ILI1 (input leakage current for Port 0) dress lines must be latched. In modes 0 and 3, from +1 pA to £3 pA. the upper address lines DO NOT NEED to be latched in 8-bit bus width mode. But in 16-bit 5 Removed Tuy from AC characterises and buswidth mode the upper address lines need to a be latched. 6. TaLet in Mode 0 and 3, changed from +4 ns min. to —5 ns min. 7. TwHax in Mode 0 and 3, changed from Tosc 8XC196NT ERRATA see Faxback — 30 min. to Togo — 35 min. #2344 8. Clarified the Ready waveform timings for Mode 1. ILLEGAL Opcode interrupt vector. O and 3, by adding "+2 Togc*”. 2. Aborted Interrupt vectors to lowest priority. 9. TuHuL in Mode 1, changed from Togo — 10 min. 3. PTS Request during Interrupt latency. to Tosc ~ 20 min. 10. Tavit in Mode 1, changed from 0.6 Tos¢ — 15 min. to 0.5 Tog¢ — 20 min. DATA SHEET REVISION HISTORY 11. Tutax in Mode 1, changed from 0.5 Toso — 20 This datasheet applies to devices marked with a “D” min. to 0.5 Tosc ~ 25 min. at the end of the topside tracking number. The top- 12. T.HLL in Mode 2, changed from Togc — 10 min. side tracking number consists of nine characters to Tosc ~ 20 min. and is the second line on the top side of the device. 43. Ty x1 and Tx.xH for the Serial Port timings Datasheets are changed as new device information were changed to reflect the minimum baudrate becomes available. Verify with your local Intel sales for receive and transmit modes. office that you have the latest version before finaliz- ; ing a design or ordering devices. 14, Added the 8XC196NT ERRATA section. 4-296 ADVANCE INFORMATION MH 4826175 O14491L4 734 Me |

Product Information

EE87C196NT specifications and overview.

Summary

Chmos microntroller

Description

Chmos microntroller

Source title EE87C196NT Datasheet(PDF) - Intel Corporation

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