28F320J5_02 INTEL | Alldatasheet
Document overview
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- PDF pages: 51
Technical content
Datasheet sections
- 1.0 ProductOverview
- 2.0 PrinciplesofOperation
- 2.1 Data Protection
- 3.0 BusOperation
- 3.1 Read
- 3.2 Output Disable
- 3.3 Standby
- 3.4 Reset/Power-Down
- 3.5 Read Query
- 3.6 Read Identifier Codes
- 3.7 Write
- 4.0 CommandDefinitions
- 4.1 Read Array Command
- 4.2 Read Query Mode Command
- 4.2.1 Query Structure Output
- 4.2.2 Query Structure Overview
- 4.2.3 Block Status Register
- 4.2.4 CFI Query Identification String
- 4.2.5 System Interface Information
- 4.2.6 Device Geometry Definition
- 4.2.7 Primary-Vendor Specific Extended Query Table
- 4.3 Read Identifier Codes Command
- 4.4 Read Status Register Command
- 4.5 Clear Status Register Command
- 4.6 Block Erase Command
- 4.7 Block Erase Suspend Command
- 4.8 Write to Buffer Command
- 4.9 Byte/Word Program Commands
- 4.10 Configuration Command
- 4.11 Set Block and Master Lock-Bit Commands
- 4.12 Clear Block Lock-Bits Command
- 5.0 DesignConsiderations
- 5.1 Three-Line Output Control
- 5.2 STS and Block Erase, Program, and Lock-Bit Configuration Polling
- 5.3 Power Supply Decoupling
- 5.4 InputSignal Transitions – Reducing Overshoots and Undershoots When Using
- 5.6 Power-Up/Down Protection
- 5.7 Power Dissipation
- 6.0 ElectricalSpecifications
- 6.1 Absolute Maximum Ratings
5VoltIntelStrataFlash ®Memory 28F320J5 and 28F640J5 (x8/x16) Datasheet ProductFeatures Capitalizingontwo-bit-per-celltechnology,5VoltIntelStrataFlash ®memoryproductsprovide2Xthebits in1Xthespace.Offeredin64-Mbit(8-Mbyte)and32-Mbit(4-Mbyte)densities,IntelStrataFlashmemory devicesarethefirsttobringreliable,two-bit-per-cellstoragetechnologytotheflashmarket. IntelStrataFlashmemorybenefitsinclude:moredensityinlessspace,lowestcost-per-bitNORdevices, supportforcodeanddatastorage,andeasymigrationtofuturedevices. UsingthesameNOR-basedETOX™technologyasIntel’sone-bit-per-cellproducts,IntelStrataFlash memorydevicestakeadvantageof400millionunitsofmanufacturingexperiencesince1988.Asaresult, IntelStrataFlashcomponentsareidealforcodeordataapplicationswherehighdensityandlowcostare required.Examplesincludenetworking,telecommunications,audiorecording,anddigitalimaging. IntelStrataFlashmemorycomponentsdeliveranewgenerationofforward-compatiblesoftwaresupport. ByusingtheCommonFlashInterface(CFI)andtheScalableCommandSet(SCS),customerscantake advantageofdensityupgradesandoptimizedwritecapabilitiesoffutureIntelStrataFlashmemorydevices. ManufacturedonIntel’s0.4micronETOX™VprocesstechnologyandIntel’s0.25micronETOXVI processtechnology,5VoltIntelStrataFlashmemoryprovidesthehighestlevelsofqualityandreliability. I High-DensitySymmetrically-Blocked Architecture —64128-KbyteEraseBlocks(64M) —32128-KbyteEraseBlocks(32M) I 4.5V–5.5VV CCOperation —2.7V–3.6Vand4.5V–5.5VI/O Capable I 120nsReadAccessTime(32M) 150nsReadAccessTime(64M) I EnhancedDataProtectionFeatures —AbsoluteProtectionwith VPEN=GND —FlexibleBlockLocking —BlockErase/ProgramLockoutduring PowerTransitions I Industry-StandardPackaging —SSOPPackage(32,64M) TSOPPackage(32M) I Cross-CompatibleCommandSupport —IntelBasicCommandSet —CommonFlashInterface —ScalableCommandSet I 32-ByteWriteBuffer —6µsperByteEffectiveProgramming Time I 6,400,000TotalEraseCycles(64M) 3,200,000TotalEraseCycles(32M) —100,000EraseCyclesperBlock I AutomationSuspendOptions —BlockEraseSuspendtoRead —BlockEraseSuspendtoProgram I SystemPerformanceEnhancements —STSStatusOutput I OperatingTemperature–20°Cto+85°C (–40°Cto+85°Con.25 micronETOXVI) processtechnologyparts) Order Number: 290606-015 April2002 Notice:This document contains information on products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizinga desig n.
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Information in this document isprovided in connection with Intel products.No license, express or implied,by estoppel or otherwise, to anyintellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever,and Intel disclaims anyexpressor implied warranty, relatingto sale and/or use ofIntel products includingliabilityor warrantiesrelatingto fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arisingfrom future chang es to them. The 28F320J5 and 28F640J5 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placingyour product order. Copies of documents which have an orderingnumber and are referenced in this document, or other Intel literature may be obtained by calling1-800- 548-4725 or by visitingIntel's website at http://www.intel.com. Copyright © Intel Corporation 1997–2002. *Other names and brands may be claimed as the property of others.
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Revision History
Revision Version Description 09/01/97 -001 Original version 09/17/97 -002 Modifications made to cover sheet 12/01/97 -003 V CC/GNDPinsConvertedtoNoConnectsSpecificationChange added ICCS,ICCD,ICCW andI CCE SpecificationChange added OrderCodesSpecificationChange added 01/31/98 -004 The µBGA* chip-scale packagein Figure 2 was changed toa 52-ballpackage andappropriatedocumentationadded.The64-MbµBGApackagedimensions were changed in Figure 2. Changed Figure 4 to read SSOP instead of TSOP. 03/23/98 -005 32-Mbit Intel StrataFlash memory read access timeadded.Thenumberof block erase cycles was changed.Thewrite buffer program time was changed. The operatingtemperature was chang ed. Aread parameterwas added. Sev- eral program, erase, and lock-bit specifications werechanged. Minor docu- mentation changes were made as well. Datasheet designation changed from Advance Information to Preliminary. 07/13/98 -006 Intel StrataFlash memory 32-Mbit µBGA package removed. t EHEL read specifi- cation reduced.Table 4 was modified.TheOrdering Informationwas updated. 12/01/98 -007 Removed 32 Mbit,100 ns references and orderinginformation forsame. Pro- vided clearerVOH specifications. Provided maximum program/erase specifica- tion. AddedInputSignalTransitions—ReducingOvershootsandUndershoots WhenUsingBuffers/Transceivers toDesignConsiderations section. Nameofdocumentchangedfrom Intel®StrataFlash™MemoryTechnology32 an d64Mb it. 09/16/99 -009 OperatingTemperature Rang e Specification was increased to –20 °C to +85° C. The 32-Mbit Read Access at +85 °C was changed (Section 6.5,AC Characteristics-ReadOnlyOperations ). 10/20/99 -010 Modified Write Pulse Width definition Added lock-bit default status (Section 4.11) Added order code information for–20 °C to +85 °C 11/08/99 -011 Modified Chip Enable Truth Table 12/16/99 -012 Corrected error in command table Removed erase queuingoption from Fig ure 9,Block Erase Flowchart 06/26/00 -013 Add reference to 0.25 micron process on coverpage Corrected error in Table 10, Maximum buffer write time. Updated section 6.7 program/erase times. Corrected error in table 19 maximum temperature range 03/28/01 -014 Changed Clear Block-Lock BitTime in Section 6.7. 04/23/02 -015 Added .25 micronETOXVIprocesstechnologyorderinginformation Removed µBGA CSP information
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1.0 ProductOverview
TheIntelStrataFlash ®memoryfamilycontainshigh-densitymemoriesorganizedas8Mbytesor4 Mwords(64-Mbit)and4Mbytesor2Mwords(32-Mbit).Thesedevicescanbeaccessedas8-or 16-bitwords.The64-Mbitdeviceisorganizedassixty-four128-Kbyte(131,072bytes)erase blockswhilethe32-Mbitsdevicecontainsthirty-two128-Kbyteeraseblocks.Blocksare selectivelyandindividuallylockableandunlockablein-system.Seethememorymapin Figure4 onpage12 . ACommonFlashInterface(CFI)permitssoftwarealgorithmstobeusedforentirefamiliesof devices.Thisallowsdevice-independent,JEDECID-independent,andforward-andbackward- compatiblesoftwaresupportforthespecifiedflashdevicefamilies.Flashvendorscanstandardize theirexistinginterfacesforlong-termcompatibility. ScaleableCommandSet(SCS)allowsasingle,simplesoftwaredriverinallhostsystemstowork withallSCS-compliantflashmemorydevices,independentofsystem-levelpackaging(e.g., memorycard,SIMM,ordirect-to-boardplacement).Additionally,SCSprovidesthehighest system/devicedatatransferratesandminimizesdeviceandsystem-levelimplementationcosts. ACommandUserInterface(CUI)servesastheinterfacebetweenthesystemprocessorand internaloperationofthedevice.AvalidcommandsequencewrittentotheCUIinitiatesdevice automation.AninternalWriteStateMachine(WSM)automaticallyexecutesthealgorithmsand timingsnecessaryforblockerase,program,andlock-bitconfigurationoperations. Ablockeraseoperationerasesoneofthedevice’s128-Kbyteblockstypicallywithinonesecond— independentofotherblocks.Eachblockcanbeindependentlyerased100,000times.Blockerase suspendmodeallowssystemsoftwaretosuspendblockerasetoreadorprogramdatafromany otherblock. EachdeviceincorporatesaWriteBufferof32bytes(16words)toallowoptimumprogramming performance.ByusingtheWriteBuffer,dataisprogrammedinbufferincrements.Thisfeaturecan improvesystemprogramperformancebyupto20timesovernon-WriteBufferwrites. Individualblocklockingusesacombinationofbits,blocklock-bitsandamasterlock-bit,tolock andunlockblocks.Blocklock-bitsgateblockeraseandprogramoperationswhilethemasterlock- bitgatesblocklock-bitmodification.Threelock-bitconfigurationoperationssetandclearlock-bits (SetBlockLock-Bit,SetMasterLock-Bit,andClearBlockLock-Bitscommands). ThestatusregisterindicateswhentheWSM’sblockerase,program,orlock-bitconfiguration operationisfinished. TheSTS(STATUS)outputgivesanadditionalindicatorofWSMactivitybyprovidingbotha hardwaresignalofstatus(versussoftwarepolling)andstatusmasking(interruptmaskingfor backgroundblockerase,forexample).StatusindicationusingSTSminimizesbothCPUoverhead andsystempowerconsumption.Whenconfiguredinlevelmode(defaultmode),itactsasaRY/ BY#pin.Whenlow,STSindicatesthattheWSMisperformingablockerase,program,orlock-bit configuration.STS-highindicatesthattheWSMisreadyforanewcommand,blockeraseis suspended(andprogrammingisinactive),orthedeviceisinreset/power-downmode. Additionally,theconfigurationcommandallowstheSTSpintobeconfiguredtopulseon completionofprogrammingand/orblockerases.
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ThreeCEpinsareusedtoenableanddisablethedevice.AuniqueCElogicdesign(see Table2, “ChipEnableTruthTable”onpage12 )reducesdecoderlogictypicallyrequiredformulti-chip designs.Externallogicisnotrequiredwhendesigningasinglechip,adualchip,ora4-chip miniaturecardorSIMMmodule. TheBYTE#pinallowseitherx8orx16read/writestothedevice.BYTE#atlogiclowselects8-bit mode;addressA 0selectsbetweenthelowbyteandhighbyte.BYTE#atlogichighenables16-bit operation;addressA 1becomesthelowestorderaddressandaddressA 0isnotused(don’tcare).A deviceblockdiagramisshownin Figure1. Whenthedeviceisdisabled(see Table2onpage12 )andtheRP#pinisatV CC,thestandbymode isenabled.WhentheRP#pinisatGND,afurtherpower-downmodeisenabledwhichminimizes powerconsumptionandprovideswriteprotectionduringreset.Aresettime(t PHQV)isrequired fromRP#switchinghighuntiloutputsarevalid.Likewise,thedevicehasawaketime(t PHWL) fromRP#-highuntilwritestotheCUIarerecognized.WithRP#atGND,theWSMisresetandthe statusregisteriscleared. TheIntelStrataFlashmemorydevicesareavailableinseveralpackagetypes.The64-Mbitis availablein56-leadSSOP(ShrinkSmallOutlinePackage)andµBGA*package(microBallGrid Array).The32-Mbitisavailablein56-leadTSOP(ThinSmallOutlinePackage)and56-lead SSOP.Figures2,3,and4showthepinouts. Figure1. IntelStrataFlash ®MemoryBlockDiagram 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-KbyteBlocks InputBuffer Output Multiplexer Y-Gating Program/Erase VoltageSwitch Data Comparator Status Register Identifier Register Data Register I/O Logic Address Latch Address Counter X-Decoder Y-Decoder InputBuffer OutputBuffer GND VCC VPEN CE0 CE1 CE2 WE# OE# RP# BYTE# Command User Interface 32-Mbit: A0-A21 64-Mbit: A0- A22 DQ0 -D Q15 VCC Write Buffer WriteState Machine Multiplexer Query STS VCCQ CE Logic
Table1. LeadDescriptions Symbol Type NameandFunction A0 INPUT BYTE-SELECTADDRESS: Selects between high and low byte when the device is in x8 mode. This address is latched duringa x8program cycle.Notusedinx16mode (i.e.,theA 0 input buffer is turned offwhen BYTE# is high). A1–A22 INPUT ADDRESSINPUTS: Inputs for addresses duringread and prog ram operations.Addresses are internally latched duringa prog ram cycle. 32-Mbit: A 0–A21 64-Mbit: A0–A22 DQ0–DQ7 INPUT/ OUTPUT LOW-BYTEDATABUS: Inputs data during bufferwrites and programming, and inputs commandsduringCommandUserInterface(CUI)writes.Outputsarray,query,identifier,orstatus data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled.OutputsDQ 6–DQ0 arealsofloatedwhentheWriteStateMachine(WSM)isbusy.Check SR.7 (status register bit 7) to determine WSM status. DQ8–DQ15 INPUT/ OUTPUT HIGH-BYTEDATABUS: Inputs data duringx16 bufferwrites and prog rammingoperations. Outputs array, query, or identifier data in the appropriate read mode; not used forstatus register reads. Floated when the chip is de-selected, the outputs are disabled, orthe WSM is busy. CE CE1, CE2 INPUT CHIPENABLES: Activates the device’s control logic, input buffers,decoders, and sense amplifiers. When the device is de-selected (seeT a b l e2o np a ge1 2, powerreduces to standby levels. Alltimingspecifications arethesameforthesethreesignals.Deviceselectionoccurswiththefirst edgeofCE 0,CE1,orCE 2 thatenablesthedevice.Devicedeselectionoccurswiththefirstedgeof CE0,C E1,o rC E2 that disables the device (seeTable 2). RP# INPUT RESET/POWER-DOWN: Resets internal automation and puts the device in power-down mode. RP#-high enables normal operation. Exit from resetsets the device to read array mode.When driven low,RP# inhibits write operations which provides data protection duringpower transitions. RP# at V HH enables masterlock-bit settingand block lock-bits config uration when the master lock-bit is set. RP# = VHH overrides block lock-bits thereby enablingblock erase and programming operations to locked memory blocks. Do not permanently connect RP# to VHH. OE# INPUT OUTPUTENABLE: Activates the device’s outputs through the data buffers during a read cycle. O E #i sa c t i v el o w . WE# INPUT WRITEENABLE: Controls writes to the Command User Interface, the Write Buffer, and array blocks.WE# is active low. Addresses and data arelatched on the risingedg e ofthe WE# pulse. STS OPEN DRAIN OUTPUT STATUS:Indicates the status of the internal state machine. When configured in level mode (defaultmode),itactsasaRY/BY#pin.Whenconfiguredinoneofitspulsemodes,itcanpulseto indicate program and/orerase completion. For alternateconfigurations of the STATUS pin,see the Configurations command. Tie STSto V CCQ with a pull-up resistor. BYTE# INPUT BYTEENABLE: BYTE# low places the device in x8 mode. All data is then input or outputon DQ0–DQ7,whileDQ 8–DQ15 float.AddressA 0 selectsbetweenthehighandlowbyte.BYTE#high places the device in x16 mode,and turns offthe A0 input buffer.Address A1 then becomes the lowest order address. VPEN INPUT ERASE/PROGRAM/BLOCKLOCKENABLE: Forerasingarrayblocks,prog rammingdata,or configuring lock-bits. With VPEN ≤ VPENLK, memory contents cannot be altered. VCC SUPPLY DEVICEPOWERSUPPLY: With VCC ≤ VLKO,allwrite attemptstotheflashmemory areinhibited. VCCQ OUTPUT BUFFER SUPPLY OUTPUTBUFFERPOWERSUPPLY: This voltage controls the device’s outputvoltages. To obtain output voltages compatible with system data bus voltages, connect VCCQ to the system supply voltage. GND SUPPLY GROUND:Do notfloat any ground pins. NC NOCONNECT: Lead is not internally connected; it may be driven orfloated.
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NOTES: 1. VCC (Pin 37) and GND (Pin 48) are notinternally connected.Forfuture device revisions,itis recommended thatthese pins be connected totheirrespected powersupplies (i.e., Pin 37 = VCC and Pin 48 = GND). 2. For compatibility withfuturegenerations ofIntel StrataFlash® memory, this NC (pin 56) should be connected to GND. NOTES: 1. VCC (Pin 42) and GND (Pin 15) are notinternally connected.Forfuture device revisions,itis recommended thatthese pins be connected totheirrespected powersupplies (i.e., Pin 42 = VCC and Pin 15 = GND). 2. For compatibility withfuturegenerations ofIntel StrataFlash® memory, this NC (pin 23) should be connected to GND. Figure2. TSOPLeadConfiguration(32Mbit) 28F320J5 IntelStrataFlash®Memory 56-LeadTSOP StandardPinout 14mmx20mm TopView NC A21 A20 CE1 A19 A17 A16 A18 VCC A14 A13 A15 A12 VPEN RP# CE0 A11 A10 GND 28F016SV 28F016SA 28F032SA 3/5# NC A20 CE1 A19 A17 A16 A18 VCC A14 A13 A15 A12 VPP RP# CE0 A11 A10 GND 3/5# CE2 A20 CE1 A19 A17 A16 A18 VCC A14 A13 A15 A12 VPP RP# CE0 A11 A10 Highlights pinout changes GND 28F160S5 NC NC A20 CE1 A19 A17 A16 A18 VCC A14 A13 A15 A12 VPP RP# CE0 A11 A10 GND NC OE# STS WE# DQ15 DQ14 DQ6 DQ7 GND DQ5 DQ12 DQ13 DQ4 GND DQ11 VCCQ DQ3 DQ2 VCC DQ10 DQ9 DQ8 DQ0 DQ1 NC CE BYTE# 28F016SV 28F016SA 28F032SA WP# OE# RY/BY# WE# DQ15 DQ14 DQ6 DQ7 GND DQ5 DQ12 DQ13 GND DQ11 DQ3 DQ2 VCC DQ10 DQ9 DQ8 DQ0 DQ1 NC NC BYTE# WP# OE# RY/BY# WE# DQ DQ14 DQ6 DQ7 GND DQ5 DQ12 DQ13 DQ11 DQ3 DQ2 VCC DQ10 DQ9 DQ8 DQ0 DQ1 NC NC BYTE# 28F320J5 28F160S5 WP# OE# STS WE# DQ15 DQ14 DQ6 DQ7 GND DQ5 DQ12 DQ13 GND DQ11 DQ3 DQ2 VCC DQ10 DQ9 DQ8 DQ0 DQ1 NC NC BYTE# VCC DQ4 GND VCC VCC DQ4 DQ4 Figure3. SSOPLeadConfiguration(64Mbitand32Mbit) Intel StrataFlash® Memory 56-LeadSSOP StandardPinout 16mmx23.7mm TopView VPEN A11 A10 RP# GND VCC DQ9 DQ1 DQ0 DQ8 BYTE# CE DQ2 NC DQ10 DQ11 GND DQ3 VPEN A11 A10 RP# GND VCC DQ9 DQ1 DQ0 DQ8 BYTE# CE DQ2 NC DQ10 DQ11 GND DQ3 VPP A11 A10 RP# GND VCC DQ9 DQ1 DQ0 DQ8 BYTE# NC DQ NC DQ10 DQ11 GND DQ3 28F640J5 28F320J5 28F320S5 28F640J528F320J5 Highlights pinout changes. 28F320S5 RY/BY# 28F160S5 28F016SV 28F016SA CE0 A13 A14 A12 A15 CE1 A21 NC A20 A18 A17 A19 A16 DQ6 VCC DQ14 DQ15 STS DQ7 OE# NC DQ13 WE# DQ5 DQ4 VCCQ DQ12 GND CE0 A13 A14 A12 A15 CE1 A21 A20 A18 A17 A19 A16 DQ6 VCC DQ14 DQ15 STS DQ7 OE# NC DQ13 WE# DQ5 DQ4 VCCQ DQ12 A22 GND CE0# A13 A14 A12 A15 CE1# NC A20 A18 A17 A19 A16 GND DQ6 VCC DQ14 DQ15 RY/BY# DQ7 OE# WP# DQ13 WE# DQ5 DQ4 VCC DQ12 A21 CE0# A13 A14 A12 A15 CE1# NC A20 A18 A17 A19 A16 GND DQ6 VCC DQ14 DQ15 DQ7 OE# WP# DQ13 WE# DQ5 DQ4 VCC DQ12 NC CE0# A13 A14 A12 A15 CE1# 3/5# A20 A18 A17 A19 A16 GND DQ6 VCC DQ14 DQ15 RY/BY# DQ7 OE# WP# DQ13 WE# DQ5 DQ4 VCC DQ12 NC VPP A11 A10 RP# A GND VCC DQ9 DQ1 DQ0 DQ8 BYTE# NC DQ NC DQ10 DQ11 GND DQ3 28F160S5 VPP A11 A10 RP# GND VCC DQ9 DQ1 DQ0 DQ8 BYTE# NC DQ NC DQ10 DQ11 GND DQ3 28F016SV 28F016SA
2.0 PrinciplesofOperation
TheIntelStrataFlashmemorydevicesincludeanon-chipWSMtomanageblockerase,program, andlock-bitconfigurationfunctions.Itallowsfor100%TTL-levelcontrolinputs,fixedpower suppliesduringblockerasure,program,lock-bitconfiguration,andminimalprocessoroverhead withRAM-likeinterfacetimings. Afterinitialdevicepower-uporreturnfromreset/power-downmode(see BusOperations),the devicedefaultstoreadarraymode.Manipulationofexternalmemorycontrolpinsallowsarray read,standby,andoutputdisableoperations. Readarray,statusregister,query,andidentifiercodescanbeaccessedthroughtheCUI(Command UserInterface)independentoftheV PENvoltage.VPENHonVPENenablessuccessfulblock erasure,programming,andlock-bitconfiguration.Allfunctionsassociatedwithalteringmemory contents—blockerase,program,lock-bitconfiguration—areaccessedviatheCUIandverified throughthestatusregister. Commandsarewrittenusingstandardmicro-processorwritetimings.TheCUIcontentsserveas inputtotheWSM,whichcontrolstheblockerase,program,andlock-bitconfiguration.The internalalgorithmsareregulatedbytheWSM,includingpulserepetition,internalverification,and marginingofdata.Addressesanddataareinternallylatchedduringprogramcycles. Interfacesoftwarethatinitiatesandpollsprogressofblockerase,program,andlock-bit configurationcanbestoredinanyblock.ThiscodeiscopiedtoandexecutedfromsystemRAM duringflashmemoryupdates.Aftersuccessfulcompletion,readsareagainpossibleviatheRead Arraycommand.Blockerasesuspendallowssystemsoftwaretosuspendablockerasetoreador programdatafrom/toanyotherblock.
2.1 DataProtection
Dependingontheapplication,thesystemdesignermaychoosetomaketheV PEN switchable (availableonlywhenmemoryblockerases,programs,orlock-bitconfigurationsarerequired)or hardwiredtoV PENH.Thedeviceaccommodateseitherdesignpracticeandencourages optimizationoftheprocessor-memoryinterface. WhenVPEN≤ VPENLK,memorycontentscannotbealtered.TheCUI’stwo-stepblockerase,byte/ wordprogram,andlock-bitconfigurationcommandsequencesprovideprotectionfromunwanted operationsevenwhenV PENHisappliedtoV PEN.AllprogramfunctionsaredisabledwhenV CCis belowthewritelockoutvoltageV LKOorwhenRP#isV IL.Thedevice’sblocklockingcapability providesadditionalprotectionfrominadvertentcodeordataalterationbygatingeraseandprogram operations.
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3.0 BusOperation
ThelocalCPUreadsandwritesflashmemoryin-system.Allbuscyclestoorfromtheflash memoryconformtostandardmicroprocessorbuscycles. NOTES: 1. See Application Note,AP-6475VoltIntelStrataFlash ® MemoryDesignGuide for typical CE configurations. 2. For single-chip applications CE2 and CE1 c a nb es t r a p p e dt oG N D . Figure4. MemoryMap Table2. ChipEnableTruthTable CE2 CE1 CE0 DEVICE VIL VIL VIL Enabled VIL VIL VIH Disabled VIL VIH VIL Disabled VIL VIH VIH Disabled VIH VIL VIL Enabled VIH VIL VIH Enabled VIH VIH VIL Enabled VIH VIH VIH Disabled 64-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block WordWide(x16)Mode 1FFFFF 1F0000 3FFFFF 3F0000 01FFFF 01000000FFFF 000000 A [22-1]:64-Mbit A [21-1]:32-Mbit 128-Kbyte Block 128-Kbyte Block 128-Kbyte Block 128-Kbyte Block Byte-Wide(x8)Mode 3FFFFF 3E0000 7FFFFF 7E0000 03FFFF 02000001FFFF 000000 A [22-0]:64-Mbit A [21-0]:32-Mbit 32-Mbit 64-Mbit
3.1 Read
Informationcanbereadfromanyblock,query,identifiercodes,orstatusregisterindependentof theVPENvoltage.RP#canbeateitherV IHorVHH. Uponinitialdevicepower-uporafterexitfromreset/power-downmode,thedeviceautomatically resetstoreadarraymode.Otherwise,writetheappropriatereadmodecommand(ReadArray,Read Query,ReadIdentifierCodes,orReadStatusRegister)totheCUI.Sixcontrolpinsdictatethedata flowinandoutofthecomponent:CE 0,CE1,CE2,OE#,WE#,andRP#.Thedevicemustbe enabled(see Table2),andOE#mustbedrivenactivetoobtaindataattheoutputs.CE 0,CE1,and CE2arethedeviceselectioncontrolsand,whenenabled(see Table2),selectthememorydevice. OE#isthedataoutput(DQ 0–DQ15)controland,whenactive,drivestheselectedmemorydata ontotheI/Obus.WE#mustbeatV IH.
3.2 OutputDisable
WithOE#atalogic-highlevel(V IH),thedeviceoutputsaredisabled.OutputpinsDQ 0–DQ15are placedinahigh-impedancestate.
3.3 Standby
CE0,CE1,andCE 2candisablethedevice(see Table2)andplaceitinstandbymodewhich substantiallyreducesdevicepowerconsumption.DQ 0–DQ15outputsareplacedinahigh- impedancestateindependentofOE#.Ifdeselectedduringblockerase,program,orlock-bit configuration,theWSMcontinuesfunctioning,andconsumingactivepoweruntiltheoperation completes.
3.4 Reset/Power-Down
RP#atV ILinitiatesthereset/power-downmode. Inreadmodes,RP#-lowdeselectsthememory,placesoutputdriversinahigh-impedancestate,and turnsoffnumerousinternalcircuits.RP#mustbeheldlowforaminimumoft PLPH.Timet PHQVis requiredafterreturnfromresetmodeuntilinitialmemoryaccessoutputsarevalid.Afterthiswake- upinterval,normaloperationisrestored.TheCUIisresettoreadarraymodeandstatusregisteris setto80H. Duringblockerase,program,orlock-bitconfigurationmodes,RP#-lowwillaborttheoperation.In defaultmode,STStransitionslowandremainslowforamaximumtimeoft PLPH+tPHRHuntilthe resetoperationiscomplete.Memorycontentsbeingalteredarenolongervalid;thedatamaybe partiallycorruptedafteraprogramorpartiallyalteredafteraneraseorlock-bitconfiguration.Time t PHWLisrequiredafterRP#goestologic-high(V IH)beforeanothercommandcanbewritten. Aswithanyautomateddevice,itisimportanttoassertRP#duringsystemreset.Whenthesystem comesoutofreset,itexpectstoreadfromtheflashmemory.Automatedflashmemoriesprovide statusinformationwhenaccessedduringblockerase,program,orlock-bitconfigurationmodes.If aCPUresetoccurswithnoflashmemoryreset,properinitializationmaynotoccurbecausethe
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flashmemorymaybeprovidingstatusinformationinsteadofarraydata.Intel ®Flashmemories allowproperinitializationfollowingasystemresetthroughtheuseoftheRP#input.Inthis application,RP#iscontrolledbythesameRESET#signalthatresetsthesystemCPU.
3.5 ReadQuery
Thereadqueryoperationoutputsblockstatusinformation,CFI(CommonFlashInterface)ID string,systeminterfaceinformation,devicegeometryinformation,andIntel-specificextended queryinformation.
3.6 ReadIdentifierCodes
Thereadidentifiercodesoperationoutputsthemanufacturercode,devicecode,blocklock configurationcodesforeachblock,andthemasterlockconfigurationcode(see Figure5).Using themanufactureranddevicecodes,thesystemCPUcanautomaticallymatchthedevicewithits properalgorithms.Theblocklockandmasterlockconfigurationcodesidentifylockedand unlockedblocksandmasterlock-bitsetting.
NOTE: A0 is not usedin eitherx8 orx16 modeswhen obtainingthese identifiercodes. Data is alwaysg iven on the low byte in x16 mode (upperbyte contains 00h). Figure5.DeviceIdentifierCodeMemoryMap Reserved for Future Implementation Reserved for Future Implementation (Blocks 32 through 62) Reserved for Future Implementation Reserved for Future Implementation (Blocks 2 through 30) Reserved for Future Implementation Reserved for Future Implementation Block63 Block31 Block1 Block0LockConfiguration Reserved for Future Implementation Block0 MasterLockConfiguration ManufacturerCode DeviceCode 3FFFFF 3F0003 3F0002 3F0000 3EFFFF 1EFFFF 1F0003 1F0002 1F0000 01FFFF 010003 010002 010000 00FFFF 000004 000003 000002 000001 000000
32 Mbit
64 Mbit
A[22-1]: 64 Mbit A[21-1]: 32 Mbit Block31LockConfiguration Block63LockConfiguration Block1LockConfiguration
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3.7 Write
WritingcommandstotheCUIenablesreadingofdevicedata,query,identifiercodes,inspection andclearingofthestatusregister,and,whenV PEN=VPENH,blockerasure,program,andlock-bit configuration. TheBlockErasecommandrequiresappropriatecommanddataandanaddresswithintheblockto beerased.TheByte/WordProgramcommandrequiresthecommandandaddressofthelocationto bewritten.SetMasterandBlockLock-Bitcommandsrequirethecommandandaddresswithinthe device(MasterLock)orblockwithinthedevice(BlockLock)tobelocked.TheClearBlockLock- Bitscommandrequiresthecommandandaddresswithinthedevice. TheCUIdoesnotoccupyanaddressablememorylocation.Itiswrittenwhenthedeviceisenabled andWE#isactive.Theaddressanddataneededtoexecuteacommandarelatchedontherising edgeofWE#orthefirstedgeofCE 0,CE1,orCE 2thatdisablesthedevice(see Table2on page12).Standardmicroprocessorwritetimingsareused. NOTES: 1. SeeTable 2for valid CE configurations. 2. OE# and WE# should neverbe enabled simultaneously. 3. DQ refers to DQ 0–DQ7 ifBYTE# is low and DQ0–DQ15 if BYTE# is high. 4. Referto DCCharacteristics . When VPEN ≤ VPENLK, memory contents can be read,butnotaltered. 5. X can be VIL or VIH for control and address pins, and VPENLK orV PENH for VPEN.Se eDC Characteristicsfor VPENLK and VPENH voltages. 6. In defaultmode, STSis VOL when the WSM is executinginternal block erase, prog ram, or lock-bit configuration algorithms. It is VOH when the WSM is not busy,in block erase suspend mode (with programming inactive),orreset/power-down mode. 7. High Z will be VOH with an external pull-up resistor. 8. SeeReadIdentifierCodesCommand section for read identifiercode data. 9. SeeReadQueryModeCommand section forread query data. 10.Commandwritesinvolvingblockerase,program,orlock-bitconfigurationarereliably executedwhenV PEN = VPENH and VCC is within specification. Block erase, program, or lock-bit configuration with VIH <R P#<V HH produce spurious results and should notbe attempted. 11.Referto Table 4for valid DIN duringa write operation. Table3. BusOperations Mode Notes RP# CE 0,1,2 (1) OE#(2) WE#(2) Address V PEN DQ(3) STS (default mode) Read Array 4,5,6 V IH or VHH Enabled V IL VIH XX D OUT High Z(7) Output Disable V IH or VHH Enabled V IH VIH XX H i gh Z X Standby V IH or VHH Disabled X X X X High Z X Reset/Power- Down Mode VIL X X X X X H i ghZ H i ghZ (7) Read Identifier Codes VIH or VHH Enabled V IL VIH See Figure 5 X N o t e8 H i ghZ (7) Read Query V IH or VHH Enabled V IL VIH See Table 7 X N o t e9 H i ghZ (7) Read Status (WSM off) VIH or VHH Enabled V IL VIH XX D OUT Read Status (WSM on) VIH or VHH Enabled V IL VIH XV PENH DQ7=D OUT DQ15–8 =H i ghZ DQ6–0 =H i ghZ Write 6,10,11 V IH or VHH Enabled V IH VIL XX D IN X
4.0 CommandDefinitions
WhentheV PENvoltage≤ VPENLK,onlyreadoperationsfromthestatusregister,query,identifier codes,orblocksareenabled.PlacingV PENHonVPENadditionallyenablesblockerase,program, andlock-bitconfigurationoperations. DeviceoperationsareselectedbywritingspecificcommandsintotheCUI. Table4 definesthese commands. NOTES: 1. Commands otherthan those shown above are reserved by Intel forfuture device implementations and should not be used. 2. If theWSM is running, only DQ7 is valid;DQ15–DQ8 and DQ6–DQ0 f l o a t ,w h i c hp l a c e st h e mi nah i gh - impedance state. Table4. IntelStrataFlash ®MemoryCommandSetDefinitions (1,2) Command Scaleable orBasic Command Set(2) Bus Cycles Req’d. Notes FirstBusCycle SecondBusCycle Oper(3) Addr(4) Data(5,6) Oper(3) Addr(4) Data(5,6) Read Array SCS/BCS 1 Write X FFH Read Identifier Codes SCS/BCS ≥ 2 7 Write X 90H Read IA ID Read Query SCS ≥ 2 Write X 98H Read QA QD Read Status Register SCS/BCS 2 8 Write X 70H Read X SRD Clear Status Register SCS/BCS 1 Write X 50H W r i t et oB u f f e r S C S / B CS >29, 10,
11 Write BA E8H Write BA N
Program SCS/BCS 2 12,13 Write X 40H or 10H Write PA PD Block Erase SCS/BCS 2 11,12 Write X 20H Write BA D0H Block Erase, Program Suspend SCS/BCS 1 12,14 Write X B0H Block Erase, Program Resume SCS/BCS 1 12 Write X D0H Configuration SCS 2 Write X B8H Write X CC Set Read Configuration 2 Write X 60H Write RCD 03H Set Block Lock- Bit SCS 2 Write X 60H Write BA 01H Clear Block Lock-Bits SCS 2 15 Write X 60H Write X D0H Protection Program 2W r i t e X C 0 H W r i t e P A P D
18 Datasheet
- The Basic Command Set (BCS) is the same as the 28F008SA Command Set or IntelStandard Command Set. The Scaleable Command Set(SCS) is also referred to as the Intel Extended Command Set. 4. Bus operations are defined inTable 3. 5. X = Any valid address within the device. BA = Address within the block. IA = IdentifierCode Address: seeFigure 5and Table 13. QA = Query database Address. PA= Address ofmemory location to be programmed. 6. ID = Data read from IdentifierCodes. QD = Dataread from Query database. SRD = Data read from status register.SeeTable 16for a description of the status register bits. PD = Data to be programmed atlocation PA. Data is latched on the rising edge ofWE#. CC = Configuration Code. 7. The upperbyte ofthe data bus (DQ 8–DQ15)duringcommand writes is a“Don’tCare”in x16 operation. 8. FollowingtheReadIdentifierCodescommand,readoperationsaccessmanufacturer,device,blocklock,and master lock codes. SeeReadIdentifierCodes Command section for read identifiercode data. 9. Afterthe Write to Buffer command is issued check the XSR to make sure abuffer is available forwriting. 10.The numberofbytes/words to be written to the Write Buffer= N + 1, where N = byte/word count argument. Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N = 000FH.The third and consecutive bus cycles, as determined by N,are forwritingdata into the Write Buffer. TheConfirmcommand(D0H)isexpectedafterexactlyN+1writecycles;anyothercommandatthatpointin the sequence aborts the write to bufferoperation. Please seeF i gu r e6 ,“ W r i t et oB u f f e rF l o w c h a r t ”o n page 32,for additionalinformation. 11.Prog rammingthe write buffer to flash or initiatingthe erase operation does not beg in until a confirm command (D0h) is issued. 12.If the block is locked, RP# mustbe at V HH to enable block erase or program operations. Attempts to issue a block erase or program to a locked block while RP#is VIH will fail. 13.Either 40H or 10H are recognized by the WSM as the byte/word program setup. 14.Ifthemasterlock-bitisset,RP# mustbeatV HH to setablock lock-bit.RP#mustbeatV HH tosetthemaster lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is VIH. 15.If the master lock-bit is set, RP# must be at VHH to clearblock lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits.Ifthe masterlock-bit is notset, the Clear Block Lock-Bits command c a nb ed o n ew h i l eR P #i sV IH.
4.1 ReadArrayCommand
Uponinitialdevicepower-upandafterexitfromreset/power-downmode,thedevicedefaultsto readarraymode.ThisoperationisalsoinitiatedbywritingtheReadArraycommand.Thedevice remainsenabledforreadsuntilanothercommandiswritten.OncetheinternalWSMhasstarteda blockerase,program,orlock-bitconfiguration,thedevicewillnotrecognizetheReadArray commanduntiltheWSMcompletesitsoperationunlesstheWSMissuspendedviaanErase Suspendcommand.TheReadArraycommandfunctionsindependentlyoftheV PENvoltageand RP#canbeV IHorVHH.
4.2 ReadQueryModeCommand
Thissectiondefinesthedatastructureor“database”returnedbytheCommonFlashInterface(CFI) Querycommand.Systemsoftwareshouldparsethisstructuretogaincriticalinformationsuchas blocksize,density,x8/x16,andelectricalspecifications.Oncethisinformationhasbeenobtained, thesoftwarewillknowwhichcommandsetstousetoenableflashwrites,blockerases,and otherwisecontroltheflashcomponent.TheQueryispartofanoverallspecificationformultiple commandsetandcontrolinterfacedescriptionscalledCommonFlashInterface,orCFI.
4.2.1 QueryStructureOutput
TheQuery“database”allowssystemsoftwaretogaininformationforcontrollingtheflash component.Thissectiondescribesthedevice’sCFI-compliantinterfacethatallowsthehostsystem toaccessQuerydata. Querydataarealwayspresentedonthelowest-orderdataoutputs(DQ 0–DQ7)only.Thenumerical offsetvalueistheaddressrelativetothemaximumbuswidthsupportedbythedevice.Onthis familyofdevices,theQuerytabledevicestartingaddressisa10h,whichisawordaddressforx16 devices. Foraword-wide(x16)device,thefirsttwobytesoftheQuerystructure,“Q”and“R”inASCII, appearonthelowbyteatwordaddresses10hand11h.ThisCFI-compliantdeviceoutputs00H dataonupperbytes.Thus,thedeviceoutputsASCII“Q”inthelowbyte(DQ 0–DQ7)and00hin thehighbyte(DQ 8–DQ15). AtQueryaddressescontainingtwoormorebytesofinformation,theleastsignificantdatabyteis presentedattheloweraddress,andthemostsignificantdatabyteispresentedatthehigheraddress. Inallofthefollowingtables,addressesanddataarerepresentedinhexadecimalnotation,sothe “h”suffixhasbeendropped.Inaddition,sincetheupperbyteofword-widedevicesisalways “00h,”theleading“00”hasbeendroppedfromthetablenotationandonlythelowerbytevalueis shown.Anyx16deviceoutputscanbeassumedtohave00hontheupperbyteinthismode. NOTE: 1. The system mustdrive the lowestorderaddresses to access all the device's array data when the device is configuredin x8 mode. Therefore, word addressing,where these lower addresses are nottoggled by the system,is "Not Applicable" for x8-configured devices. Table5. SummaryofQueryStructureOutputasaFunctionofDeviceandMode Device Type/ Mode Querystartlocationin maximumdevicebus widthaddresses Querydatawithmaximum devicebus widthaddressing Querydatawithbyte addressing Hex Offset Hex Code ASCII Value Hex Offset Hex Code ASCII Value x16 device 10h 10: 0051 “Q” 20: 51 “Q” x16 mode 11: 0052 “R” 21: 00 “Null” x16 device 20: 51 “Q” x8 mode N/A 22: 52 “R”
20 Datasheet
4.2.2 QueryStructureOverview
TheQuerycommandcausestheflashcomponenttodisplaytheCommonFlashInterface(CFI) Querystructureor“database.”See AP-646CommonFlashInterface(CFI)andCommandSets (ordernumber292204)forafulldescriptionofCFI. ThefollowingsectionsdescribetheQuerystructuresub-sectionsindetail. NOTES: 1. Referto the Query Structure Output section and offset28h forthe detailed definition of offsetaddress as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e.,02000h is block 2’s beginning location when the block size is 128 Kbyte). 3. Offset 15 defines “P” which points to the Primary Intel-Specific Extended Query Table. Table6. ExampleofQueryStructureOutputofax16-andx8-CapableDevice WordAddressing ByteAddressing Offset HexCode Value Offset HexCode Value A15–A0 D15–D0 A7–A0 D7–D0 0010h 0051 “Q” 20h 51 “Q” 0011h 0052 “R” 21h 51 “Q” 0012h 0059 “Y” 22h 52 “R” 0013h P_ID LO PrVendor 23h 52 “R” 0014h P_ID HI ID # 24h 59 “Y” 0015h P LO PrVendor 25h 59 “Y” 0016h P HI TblAdr 26h P_ID LO PrVendor 0017h A_ID LO AltVendor 27h P_ID LO ID # 0018h A_ID HI ID # 28h P_ID HI ID # Table7. QueryStructure (1) Offset Sub-SectionName Description 00h ManufacturerCode 01h Device Code (BA+2)h(2) Block Status Register Block-Specific Information 04-0Fh Reserved Reserved for Vendor-Specific Information 10h CFIQuery Identification StringReserved for Vendor-Specific Information 1Bh System Interface Information Command Set ID and Vendor Data Offset 27h Device Geometry Definition Flash Device Layout P(3) Primary Intel-Specific Extended Query Table Vendor-DefinedAdditionalInformationSpecifictothePrimary VendorAlgorithm
4.2.3 BlockStatusRegister
TheBlockStatusRegisterindicateswhetheraneraseoperationcompletedsuccessfullyorwhether agivenblockislockedorcanbeaccessedforflashprogram/eraseoperations. BlockEraseStatus(BSR.1)allowssystemsoftwaretodeterminethesuccessofthelastblockerase operation.BSR.1canbeusedjustafterpower-uptoverifythattheV CCsupplywasnot accidentallyremovedduringaneraseoperation.Thisbitisonlyresetbyissuinganothererase operationtotheblock.TheBlockStatusRegisterisaccessedfromwordaddress02hwithineach block. NOTE: 1. BA = The beginning location of a Block Address (i.e.,008000h is block 1’s (64-KBblock) beginning location in word mode).
4.2.4 CFIQueryIdentificationString
TheIdentificationStringprovidesverificationthatthecomponentsupportstheCommonFlash Interfacespecification. Italsoindicatesthespecificationversionandsupportedvendor-specified commandset(s). Table8. BlockStatusRegister Offset Length Description Address Value (BA+2)h(1) 1 Block Lock Status Register BA+2: --00 or --01 BSR.0 Block Lock Status 0=U n l o c k e d 1 = Locked BA+2: (bit 0): 0 or 1 BSR.1 Block Erase Status 0 = Last erase operation completed successfully 1 = Last erase operation didnotcompletesuccessfully BA+2: (bit 1): 0 or 1 BSR 2–7:ReservedforFutureUse BA+2: (bit 2–7):0 Table9. CFIIdentification Offset Length Description Add. Hex Code Value 10h 3 Query-unique ASCII string“QRY” 10 --51 “Q” 11: --52 “R” 12: --59 “Y” 13h 2 Primary vendorcommand set and control interface ID code. 13: --01 16-bit ID code forvendor-specifiedalgorithms 14: --00 15h 2 Extended Query Table primary algorithm address 15: --31 16: --00 17h 2 Alternate vendor command set and control interface ID code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 Secondary algorithm Extended Query Table address. 19: --00 0000h means none exists 1A: --00
22 Datasheet
4.2.5 SystemInterfaceInformation
Thefollowingdeviceinformationcanoptimizesysteminterfacesoftware. Table10. SystemInterfaceInformation Offset Length Description Add. Hex Code Value 1Bh 1 VCC logic supply minimum program/erase voltage bits 0–3 BCD 100 mV bits 4–7 BCD volts 1B: --45 4.5 V 1Ch 1 V CC logic supply maximum program/erase voltage bits 0–3 BCD 100 mV bits 4–7 BCD volts 1C: --55 5.5 V 1Dh 1 V PP [programming]supply minimum program/erase voltage bits 0–3 BCD 100 mV bits 4–7 HEX volts 1D: --00 0.0 V 1Eh 1 V PP [programming]supply maximum program/erase voltage bits 0–3 BCD 100 mV bits 4–7 HEX volts 1E: --00 0.0 V 1Fh 1 “n” such that typical single word program time-out = 2 n µs 1F: --07 128 µs 20h 1 “n”such that typical max. bufferwrite time-out = 2 n µs 20: --07 128 µs 21h 1 “n”such that typical block erase time-out= 2 n ms 21: --0A 1 s 22h 1 “n”such that typical fullchip erase time-out = 2 n ms 22: --00 NA 23h 1 “n”such that maximum word program time-out = 2n times typical 23: --04 2 ms 24h 1 “n”such thatmaximum bufferwrite time-out= 2 n times typical 24: --04 2 ms 25h 1 “n”suchthatmaximumblockerasetime-out= 2 n times typical 25: --04 16 s 26h 1 “n”such that maximum chip erase time-out = 2 n times typical 26: --00 NA
4.2.6 DeviceGeometryDefinition
Thisfieldprovidescriticaldetailsoftheflashdevicegeometry.
4.2.7 Primary-VendorSpecificExtendedQueryTable
Certainflashfeaturesandcommandsareoptional.The PrimaryVendor-SpecificExtendedQuery tablespecifiesthisandothersimilarinformation. Table11. DeviceGeometryDefinition Offset Length Description CodeSeeTable Below 27h 1 “n”such that device size = 2 n in number of bytes 27: 28h 2 Flash device interface: x8 async x16 async x8/x16 async 28: --02 x8/ x16 2Ah 2 “n”such that maximum numberof bytes in write buffer = 2 n 2A: --05 32 2B: --00 2Ch 1 Number of erase block regions within device: 1.x = 0 means no erase blocking;the device erases in “bulk” 2.x specifies the numberofdevice or partition regions with one or more contiguous same-size erase blocks 3.Symmetrically blocked partitions have one blockingreg ion 4.Partition size = (total blocks) x (individual block size) 2C: --01 1 2Dh 4 Erase Block Region 1 Information 2D: bits 0–15 = y, y+1 = numberofidentical-size erase blocks 2E: bits 16–31 = z,region erase block(s) size are z x 256 bytes 2F: 30: Table12. DeviceGeometryDefinition Address 32Mbit 64Mbit 128Mbit (InfoOnly 27: --16 --17 --18 28: --02 --02 --02 29: --00 --00 --00 2A: --05 --05 --05 2B: --00 --00 --00 2C: --01 --01 --01 2D: --1F --3F --7F 2E: --00 --00 --00 2F: --00 --00 --00 30: --02 --02 --02
24 Datasheet
NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h.
4.3 ReadIdentifierCodesCommand
TheidentifiercodeoperationisinitiatedbywritingtheReadIdentifierCodescommand.Following thecommandwrite,readcyclesfromaddressesshownin Figure5 retrievethemanufacturer, device,blocklockconfigurationandmasterlockconfigurationcodes(see Table13 foridentifier codevalues).Toterminatetheoperation,writeanothervalidcommand.LiketheReadArray command,theReadIdentifierCodescommandfunctionsindependentlyoftheV PENvoltageand RP#canbeV IHorVHH.ThiscommandisvalidonlywhentheWSMisofforthedeviceis suspended.FollowingtheReadIdentifierCodescommand,thefollowinginformationcanberead: Table13. PrimaryVendor-SpecificExtendedQuery Offset(1) P=31h Length Description (OptionalFlashFeaturesandCommands) Add. Hex Code Value (P+0)h 3 Primary extended query table 31: --50 “P” (P+1)h Unique ASCII string“PRI” 32: --52 “R” (P+3)h 1 Majorversion number,ASCII 34: --31 “1” (P+4)h 1 Minorversion number,ASCII 35: --31 “1” (P+5)h 4 Optionalfeature and command support(1=yes, 0=no) 36: --0A (P+6)h bits9–31arereserved;undefinedbitsare“0.” Ifbit31is 37: --00 (P+7)h “1”thenanother31bitfieldofoptionalfeaturesfollowsat 38: --00 (P+8)h th een doft heb it -30f ie ld . 39: --00 bit 0 Chip erase supported bit 0 = 0 No bit 1 Suspend erase supported bit 1 = 1 Yes bit 2 Suspend program supported bit 2 = 0 No bit 3 Legacy lock/unlock supported bit 3 = 1 Yes bit 4 Queued erase supported bit 4 = 0 No (P+9)h 1 Supported functions aftersuspend: read Array, Status, Query Othersupported operations are: bits1–7reserved;undefinedbitsare“0” 3A: --01 bit 0 Program supported aftererase suspend bit 0 = 1 Yes (P+A)h 2 Block status register mask 3B: --01 (P+B)h bits2–15areReserved; undefinedbitsare“0” 3C: --00 bit 0 Block Lock-Bit Status registeractive bit 0 = 1 Yes bit 1 Block Lock-Down Bit Status active bit 1 = 0 No (P+C)h 1 V CC logic supply highestperformance program/erase voltage bits 0–3 BCD value in 100 mV bits 4–7 BCD value in volts 3D: --50 5.0 V (P+D)h 1 V PP optimum program/erase supply voltage bits 0–3 BCD value in 100 mV bits 4–7 HEX value in volts 3E: --00 0.0 V (P+E)h ReservedforFutureUse 3F:
NOTES: 1. A0 isnotusedineitherx8orx16modeswhenobtainingtheidentifiercodes.Thelowestorderaddresslineis A1.Data is always presented on the low byte in x16 mode (upper byte contains 00h). 2. Xselects the specific block’s lock configuration code. SeeFigure 5for the device identifier code memory map.
4.4 ReadStatusRegisterCommand
Thestatusregistermaybereadtodeterminewhenablockerase,program,orlock-bitconfiguration iscompleteandwhethertheoperationcompletedsuccessfully.Itmaybereadatanytimeby writingtheReadStatusRegistercommand.Afterwritingthiscommand,allsubsequentread operationsoutputdatafromthestatusregisteruntilanothervalidcommandiswritten.Thestatus registercontentsarelatchedonthefallingedgeofOE#orthefirstedgeofCE 0,CE1,orCE 2that enablesthedevice(see Table2).OE#musttoggletoV IHorthedevicemustbedisabled( Table2) beforefurtherreadstoupdatethestatusregisterlatch.TheReadStatusRegistercommand functionsindependentlyoftheV PENvoltage.RP#canbeV IHorVHH. Duringaprogram,blockerase,setlock-bit,orclearlock-bitcommandsequence,onlySR.7isvalid untiltheWSMcompletesorsuspendstheoperation.DeviceI/OpinsDQ 0–DQ6andDQ8–DQ15 areplacedinahigh-impedancestate.Whentheoperationcompletesorsuspends(checkstatus registerbit7),allcontentsofthestatusregisterarevalidwhenread.
4.5 ClearStatusRegisterCommand
StatusregisterbitsSR.5,SR.4,SR.3,andSR.1aresetto“1”sbytheWSMandcanonlyberesetby theClearStatusRegistercommand.Thesebitsindicatevariousfailureconditions(see Table16). Byallowingsystemsoftwaretoresetthesebits,severaloperations(suchascumulativelyerasingor lockingmultipleblocksorwritingseveralbytesinsequence)maybeperformed.Thestatusregister maybepolledtodetermineifanerroroccurredduringthesequence. Toclearthestatusregister,theClearStatusRegistercommand(50H)iswritten.Itfunctions independentlyoftheappliedV PEN voltage.RP#canbeV IHorVHH.TheClearStatusRegister commandisonlyvalidwhentheWSMisofforthedeviceissuspended. Table14. IdentifierCodes Code Address(1) Data Manufacture Code 00000 (00)89 Device Code 32-Mbit 00001 (00)14 64-Mbit 00001 (00)15 Block Lock Configuration X0002(2)
- B l o c kI sU n l o c k e d D Q 0 =0
- B l o c kI sL o c k e d D Q 0 =1
- Reserved for Future Use DQ 1–7 Master Lock Configuration 00003
- Device Is Unlocked DQ 0 =0
- Device Is Locked DQ 0 =1
- Reserved for Future Use DQ 1–7
26 Datasheet
4.6 BlockEraseCommand
Eraseisexecutedoneblockatatimeandinitiatedbyatwo-cyclecommand.Ablockerasesetupis firstwritten,followedbyanblockeraseconfirm.Thiscommandsequencerequiresanappropriate addresswithintheblocktobeerased(erasechangesallblockdatatoFFH).Blockpreconditioning, erase,andverifyarehandledinternallybytheWSM(invisibletothesystem).Afterthetwo-cycle blockerasesequenceiswritten,thedeviceautomaticallyoutputsstatusregisterdatawhenread(see Figure8,“BlockEraseFlowchart”onpage34 ).TheCPUcandetectblockerasecompletionby analyzingtheoutputoftheSTSpinorstatusregisterbitSR.7.ToggleOE#,CE 0,CE1,orCE 2to updatethestatusregister. Whentheblockeraseiscomplete,statusregisterbitSR.5shouldbechecked.Ifablockeraseerror isdetected,thestatusregistershouldbeclearedbeforesystemsoftwareattemptscorrectiveactions. TheCUIremainsinreadstatusregistermodeuntilanewcommandisissued. Thistwo-stepcommandsequenceofset-upfollowedbyexecutionensuresthatblockcontentsare notaccidentallyerased.AninvalidBlockErasecommandsequencewillresultinbothstatus registerbitsSR.4andSR.5beingsetto“1.”Also,reliableblockerasurecanonlyoccurwhenV CC isvalidandV PEN=VPENH.IfblockeraseisattemptedwhileV PEN≤ VPENLK,SR.3andSR.5will besetto“1.”Successfulblockeraserequiresthatthecorrespondingblocklock-bitbeclearedor,if set,thatRP#=V HH.Ifblockeraseisattemptedwhenthecorrespondingblocklock-bitissetand RP#=V IH,SR.1andSR.5willbesetto“1.”BlockeraseoperationswithV IH<RP#<V HH producespuriousresultsandshouldnotbeattempted.
4.7 BlockEraseSuspendCommand
TheBlockEraseSuspendcommandallowsblock-eraseinterruptiontoreadorprogramdatain anotherblockofmemory.Oncetheblockeraseprocessstarts,writingtheBlockEraseSuspend commandrequeststhattheWSMsuspendtheblockerasesequenceatapredeterminedpointinthe algorithm.ThedeviceoutputsstatusregisterdatawhenreadaftertheBlockEraseSuspend commandiswritten.PollingstatusregisterbitSR.7thenSR.6candeterminewhentheblockerase operationhasbeensuspended(bothwillbesetto“1”).Indefaultmode,STSwillalsotransitionto V OH.Specificationt WHRHdefinestheblockerasesuspendlatency. Atthispoint,aReadArraycommandcanbewrittentoreaddatafromblocksotherthanthatwhich issuspended.Aprogramcommandsequencecanalsobeissuedduringerasesuspendtoprogram datainotherblocks.Duringaprogramoperationwithblockerasesuspended,statusregisterbit SR.7willreturnto“0”andtheSTSoutput(indefaultmode)willtransitiontoV OL. TheonlyothervalidcommandswhileblockeraseissuspendedareReadQuery,ReadStatus Register,ClearStatusRegister,Configure,andBlockEraseResume.AfteraBlockEraseResume commandiswrittentotheflashmemory,theWSMwillcontinuetheblockeraseprocess.Status registerbitsSR.6andSR.7willautomaticallyclearandSTS(indefaultmode)willreturntoV OL. AftertheEraseResumecommandiswritten,thedeviceautomaticallyoutputsstatusregisterdata whenread(see Figure9,“BlockEraseSuspend/ResumeFlowchart”onpage35 ).V PENmust remainatV PENH(thesameV PENlevelusedforblockerase)whileblockeraseissuspended.RP# mustalsoremainatV IHorVHH(thesameRP#levelusedforblockerase).Blockerasecannot resumeuntilprogramoperationsinitiatedduringblockerasesuspendhavecompleted.
4.8 WritetoBufferCommand
Toprogramtheflashdevice,aWritetoBuffercommandsequenceisinitiated.Avariablenumber ofbytes,uptothebuffersize,canbeloadedintothebufferandwrittentotheflashdevice.First,the WritetoBuffersetupcommandisissuedalongwiththeBlockAddress(see Figure6,“Writeto BufferFlowchart”onpage32 ).Atthispoint,theeXtendedStatusRegister(XSR,see Table17, “StatusRegisterDefinition”onpage31 )informationisloadedandXSR.7revertsto“buffer available”status.IfXSR.7=0,thewritebufferisnotavailable.Toretry,continuemonitoring XSR.7byissuingtheWritetoBuffersetupcommandwiththeBlockAddressuntilXSR.7=1. WhenXSR.7transitionstoa“1,”thebufferisreadyforloading. Nowaword/bytecountisgiventothepartwiththeBlockAddress.Onthenextwrite,adevice startaddressisgivenalongwiththewritebufferdata.Subsequentwritesprovideadditionaldevice addressesanddata,dependingonthecount.Allsubsequentaddressesmustliewithinthestart addressplusthecount. Internally,thisdeviceprogramsmanyflashcellsinparallel.Becauseofthisparallelprogramming, maximumprogrammingperformanceandlowerpowerareobtainedbyaligningthestartaddressat thebeginningofawritebufferboundary(i.e.,A 4–A0ofthestartaddress=0). Afterthefinalbufferdataisgiven,aWriteConfirmcommandisissued.ThisinitiatestheWSM (WriteStateMachine)tobegincopyingthebufferdatatotheflasharray.Ifacommandotherthan WriteConfirmiswrittentothedevice,an“InvalidCommand/Sequence”errorwillbegenerated andstatusregisterbitsSR.5andSR.4willbesettoa“1.”Foradditionalbufferwrites,issue anotherWritetoBuffersetupcommandandcheckXSR.7. Ifanerroroccurswhilewriting,thedevicewillstopwriting,andstatusregisterbitSR.4willbeset toa“1”toindicateaprogramfailure.TheinternalWSMverifyonlydetectserrorsfor“1”sthatdo notsuccessfullyprogramto“0”s.Ifaprogramerrorisdetected,thestatusregistershouldbe erase),thedevicewillnotacceptanymoreWritetoBuffercommands.Additionally,iftheuser attemptstoprogrampastaneraseblockboundarywithaWritetoBuffercommand,thedevicewill abortthewritetobufferoperation.Thiswillgeneratean“InvalidCommand/Sequence”errorand statusregisterbitsSR.5andSR.4willbesettoa“1.” ReliablebufferedwritescanonlyoccurwhenV PEN =VPENH.Ifabufferedwriteisattempted whileVPEN≤ VPENLK,statusregisterbitsSR.4andSR.3willbesetto“1.”Bufferedwriteattempts withinvalidV CCandVPENvoltagesproducespuriousresultsandshouldnotbeattempted.Finally, successfulprogrammingrequiresthatthecorrespondingBlockLock-Bitberesetor,ifset,thatRP# HH.IfabufferedwriteisattemptedwhenthecorrespondingBlockLock-BitissetandRP#= VIH,SR.1andSR.4willbesetto“1.”BufferedwriteoperationswithV IH<RP#<V HHproduce spuriousresultsandshouldnotbeattempted.
4.9 Byte/WordProgramCommands
Byte/Wordprogramisexecutedbyatwo-cyclecommandsequence.Byte/Wordprogramsetup (standard40Horalternate10H)iswrittenfollowedbyasecondwritethatspecifiestheaddressand data(latchedontherisingedgeofWE#).TheWSMthentakesover,controllingtheprogramand programverifyalgorithmsinternally.Aftertheprogramsequenceiswritten,thedevice automaticallyoutputsstatusregisterdatawhenread(see Figure7,“Byte/WordProgram Flowchart”onpage33 ).TheCPUcandetectthecompletionoftheprogrameventbyanalyzingthe STSpinorstatusregisterbitSR.7.
28 Datasheet
Whenprogramiscomplete,statusregisterbitSR.4shouldbechecked.Ifaprogramerroris detected,thestatusregistershouldbecleared.TheinternalWSMverifyonlydetectserrorsfor“1”s thatdonotsuccessfullyprogramto“0”s.TheCUIremainsinreadstatusregistermodeuntilit receivesanothercommand. Reliablebyte/wordprogramscanonlyoccurwhenV CCandVPENarevalid.Ifabyte/word programisattemptedwhileV PEN≤ VPENLK,statusregisterbitsSR.4andSR.3willbesetto“1.” Successfulbyte/wordprogramsrequirethatthecorrespondingblocklock-bitbeclearedor,ifset, thatRP#=V HH.Ifabyte/wordprogramisattemptedwhenthecorrespondingblocklock-bitisset andRP#=V IH,SR.1andSR.4willbesetto“1.”Byte/wordprogramoperationswithV IH<RP#< VHHproducespuriousresultsandshouldnotbeattempted.
4.10 ConfigurationCommand
TheStatus(STS)pincanbeconfiguredtodifferentstatesusingtheConfigurationcommand.Once theSTSpinhasbeenconfigured,itremainsinthatconfigurationuntilanotherconfiguration commandisissuedorRP#isassertedlow.Initially,theSTSpindefaultstoRY/BY#operation whereRY/BY#lowindicatesthatthestatemachineisbusy.RY/BY#highindicatesthatthestate machineisreadyforanewoperationorsuspended. Table15,“WriteProtectionAlternatives”on page30 displaysthepossibleSTSconfigurations. ToreconfiguretheStatus(STS)pintoothermodes,theConfigurationcommandisgivenfollowed bythedesiredconfigurationcode.Thethreealternateconfigurationsareallpulsemodeforuseasa systeminterruptasdescribedbelow.Fortheseconfigurations,bit0controlsEraseComplete interruptpulse,andbit1controlsProgramCompleteinterruptpulse.Supplyingthe00h configurationcodewiththeConfigurationcommandresetstheSTSpintothedefaultRY/BY# levelmode.Thepossibleconfigurationsandtheirusagearedescribedin Table15.The Configurationcommandmayonlybegivenwhenthedeviceisnotbusyorsuspended.CheckSR.7 fordevicestatus.AninvalidconfigurationcodewillresultinbothstatusregisterbitsSR.4and SR.5beingsetto“1.”Whenconfiguredinoneofthepulsemodes,theSTSpinpulseslowwitha typicalpulsewidthof250ns.
4.11 SetBlockandMasterLock-BitCommands
Aflexibleblocklockingandunlockingschemeisenabledviaacombinationofblocklock-bitsand amasterlock-bit.Outofthefactory,theblocklock-bitsandthemasterlock-bitareunlocked.The blocklock-bitsgateprogramanderaseoperationswhilethemasterlock-bitgatesblock-lockbit modification.Withthemasterlock-bitnotset,individualblocklock-bitscanbesetusingtheSet BlockLock-Bitcommand.TheSetMasterLock-Bitcommand,inconjunctionwithRP#=V HH, setsthemasterlock-bit.Afterthemasterlock-bitisset,subsequentsettingofblocklock-bits requiresboththeSetBlockLock-BitcommandandV HHontheRP#pin.Thesecommandsare invalidwhiletheWSMisrunningorthedeviceissuspended.See Table14,“IdentifierCodes”on page25 forasummaryofhardwareandsoftwarewriteprotectionoptions. Setblocklock-bitandmasterlock-bitcommandsareexecutedbyatwo-cyclesequence.Theset blockormasterlock-bitsetupalongwithappropriateblockordeviceaddressiswrittenfollowed byeitherthesetblocklock-bitconfirm(andanaddresswithintheblocktobelocked)ortheset masterlock-bitconfirm(andanydeviceaddress).TheWSMthencontrolsthesetlock-bit algorithm.Afterthesequenceiswritten,thedeviceautomaticallyoutputsstatusregisterdatawhen read(see Figure10,“SetBlockLock-BitFlowchart”onpage36 ).TheCPUcandetectthe completionofthesetlock-biteventbyanalyzingtheSTSpinoutputorstatusregisterbitSR.7.
Whenthesetlock-bitoperationiscomplete,statusregisterbitSR.4shouldbechecked.Ifanerror isdetected,thestatusregistershouldbecleared.TheCUIwillremaininreadstatusregistermode untilanewcommandisissued. Thistwo-stepsequenceofset-upfollowedbyexecutionensuresthatlock-bitsarenotaccidentally set.AninvalidSetBlockorMasterLock-BitcommandwillresultinstatusregisterbitsSR.4and SR.5beingsetto“1.”Also,reliableoperationsoccuronlywhenV CCandVPEN arevalid.With VPEN≤ VPENLK,lock-bitcontentsareprotectedagainstalteration. Asuccessfulsetblocklock-bitoperationrequiresthatthemasterlock-bitbezeroor,ifthemaster lock-bitisset,thatRP#=V HH.Ifitisattemptedwiththemasterlock-bitsetandRP#=V IH,SR.1 andSR.4willbesetto“1”andtheoperationwillfail.Setblocklock-bitoperationswhileV IH< RP#<V HHproducespuriousresultsandshouldnotbeattempted.Asuccessfulsetmasterlock-bit operationrequiresthatRP#=V HH.IfitisattemptedwithRP#=V IH,SR.1andSR.4willbesetto “1”andtheoperationwillfail.Setmasterlock-bitoperationswithV IH<RP#<V HHproduce spuriousresultsandshouldnotbeattempted.
4.12 ClearBlockLock-BitsCommand
Allsetblocklock-bitsareclearedinparallelviatheClearBlockLock-Bitscommand.Withthe masterlock-bitnotset,blocklock-bitscanbeclearedusingonlytheClearBlockLock-Bits command.Ifthemasterlock-bitisset,clearingblocklock-bitsrequiresboththeClearBlockLock- BitscommandandV HHontheRP#pin.ThiscommandisinvalidwhiletheWSMisrunningorthe deviceissuspended.See Table14,“IdentifierCodes”onpage25 forasummaryofhardwareand softwarewriteprotectionoptions. Clearblocklock-bitscommandisexecutedbyatwo-cyclesequence.Aclearblocklock-bitssetup isfirstwritten.Thedeviceautomaticallyoutputsstatusregisterdatawhenread(see Figure11, “ClearBlockLock-BitFlowchart”onpage37 ).TheCPUcandetectcompletionoftheclearblock lock-bitseventbyanalyzingtheSTSpinoutputorstatusregisterbitSR.7. Whentheoperationiscomplete,statusregisterbitSR.5shouldbechecked.Ifaclearblocklock-bit errorisdetected,thestatusregistershouldbecleared.TheCUIwillremaininreadstatusregister modeuntilanothercommandisissued. Thistwo-stepsequenceofset-upfollowedbyexecutionensuresthatblocklock-bitsarenot accidentallycleared.AninvalidClearBlockLock-Bitscommandsequencewillresultinstatus registerbitsSR.4andSR.5beingsetto“1.”Also,areliableclearblocklock-bitsoperationcan onlyoccurwhenV CCandVPENarevalid.Ifaclearblocklock-bitsoperationisattemptedwhile VPEN≤ VPENLK,SR.3andSR.5willbesetto“1.”Asuccessfulclearblocklock-bitsoperation requiresthatthemasterlock-bitisnotsetor,ifthemasterlock-bitisset,thatRP#=V HH.Ifitis attemptedwiththemasterlock-bitsetandRP#=V IH,SR.1andSR.5willbesetto“1”andthe operationwillfail.Aclearblocklock-bitsoperationwithV IH<RP#<V HHproducespurious resultsandshouldnotbeattempted. Ifaclearblocklock-bitsoperationisabortedduetoV PENorVCCtransitioningoutofvalidrangeor RP#activetransition,blocklock-bitvaluesareleftinanundeterminedstate.Arepeatofclear blocklock-bitsisrequiredtoinitializeblocklock-bitcontentstoknownvalues.Oncethemaster lock-bitisset,itcannotbecleared.
30 Datasheet
NOTE: 1. Whenthedeviceisconfiguredinoneofthepulsemodes,theSTSpinpulseslowwithatypicalpulsewidthof 250 ns. Table15. WriteProtectionAlternatives Operation Master Lock-Bit Block Lock-Bit RP# Effect Block Erase or Program 0 VIH or VHH Block Erase and Program Enabled X1 V IH Block is Locked. Block Erase and Program Disabled VHH Block Lock-Bit Override. Block Erase and Program Enabled Set or Clear Block Lock-Bits 0 X VIH or VHH Set or ClearBlock Lock-Bit Enabled 1X V IH Master Lock-BitIs Set. Setor Clear Block Lock-Bit Disabled VHH Master Lock-BitOverride. SetorClear Block Lock-Bit Enabled Set Master Lock-Bit X X V IH Set Master Lock-Bit Disabled VHH Set Master Lock-Bit Enabled Table16. ConfigurationCodingDefinitions Reserved Pulseon Program Complete(1) Pulseon Erase Complete(1) Bits7—2 Bit1 Bit0 DQ7–DQ2= Reserved DQ1–DQ0= STSPin Configuration Codes 00 = default, level mode RY/BY# (device ready)indication 01 = pulse on Erase complete 10 = pulse on Program complete 11 = pulse on Erase or Program Complete Configuration Codes 01b,10b, and 11bare all pulse mode suchthatthe STSpinpulseslow thenhighwhentheoperation indicated by the given configuration is completed. Configuration Command Sequences for STSpinconfiguration (maskingbits DQ 7–DQ2 to 00h) are as follows: Default RY/BY# level mode: B8h,00h ER INT (Erase Interrupt): B8h,01h Pulse-on-Erase Complete PR INT (Program Interrupt): B8h,02h Pulse-on-Program Complete ER/PR INT (Erase or Program Interrupt): B8h, 03h Pulse-on-Erase or Program Complete DQ 7–DQ2 are reserved forfuture use. default (DQ1–DQ0 = 00) RY/BY#, level mode —u s e dt oc o n t r o lH O L Dt oam e m o r yc o n t r o l l e rt op r e v e n t accessinga flash memory subsystem while any flash device's WSM is busy. configuration 01 ER INT,pulse mode — used to generate a system interrupt pulse when any flash deviceinanarrayhascompletedaBlockEraseorsequenceof Queued Block Erases. Helpful forreformattingblocks afterfile system free space reclamation or“cleanup” configuration 10 PR INT,pulse mode — used to generate a system interrupt pulse when any flash deviceinanarrayhascompleteaProgramoperation.Provides highestperformance forservicing continuous buffer write operations. configuration 11 ER/PR INT,pulse mode — used to generate system interrupts to triggerservicing of flash arrays when eithererase or program operations are completed when a common interruptserviceroutine is desired.
Table17. StatusRegisterDefinition WSMS ESS ECLBS PSLBS VPENS R DPS R bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 HighZWhen Busy? StatusRegisterBits Notes No Yes Yes Yes Yes Yes Yes Yes SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0=B u s y SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASEAND CLEAR LOCK-BITS STATUS 1 = Error in Block Erasure orClear Lock-Bits 0 = SuccessfulBlock Erase or ClearLock-Bits SR.4 = PROGRAM AND SET LOCK-BIT STATUS 1 = Error in Programming or SetMaster/Block Lock-Bit 0 = SuccessfulProgramming orSet Master/Block Lock Bit SR.3 = PROGRAMMINGVOLTAGESTATUS 1 = Low Programming Voltage Detected, Operation Aborted 0 = P r o gr a m m i n g V o l t a geO K SR.2 = RESERVED FOR FUTURE ENHANCEMENTS SR.1 = DEVICE PROTECT STATUS 1 = Master Lock-Bit,Block Lock-Bitand/or RP# Lock Detected,Operation Abort 0=U n l o c k SR.0 = RESERVED FOR FUTURE ENHANCEMENTS Check STSorSR.7to determine block erase, program,or lock-bit configuration completion. SR.6–SR.0 are not driven while SR.7 = “0.” If both SR.5 and SR.4 are “1”s after a block erase orlock-bit configuration attempt, an improper command sequence was entered. SR.3 does not provide a continuous programming voltage level indication. The WSM interrogates and indicates the programming voltage level only afterBlock Erase,Program,SetBlock/MasterLock-Bit,or ClearBlock Lock-Bits command sequences. SR.1does not provide acontinuousindication ofmasterandblocklock-bitvalues.TheWSM interrogatesthemasterlock-bit,blocklock-bit, and RP# only afterBlock Erase, Program, or Lock-Bitconfigurationcommandsequences.It informs the system, dependingon the attemptedoperation,iftheblocklock-bitisset, master lock-bitis set,and/or RP# is not V HH. Read the block lock and masterlock configuration codes using the Read Identifier Codes command to determine masterand block lock-bit status. SR.2 and SR.0 are reserved for future use andshouldbemaskedwhenpollingthestatus register. Table18. eXtendedStatusRegisterDefinition WBS Reserved bit7 bits6—0 HighZWhen Busy? StatusRegisterBits Notes No Yes XSR.7 = WRITE BUFFER STATUS 1 = Write bufferavailable 0 = Write buffernotavailable XSR.6–XSR.0 = RESERVED FOR FUTURE ENHANCEMENTS After a Buffer-Write command, XSR.7 = 1 indicates that a Write Bufferis available. SR.6–SR.0 are reserved for future use and s h o u l db em a s k e dwh e np o l l i n gt h es t a t u s register.
32 Datasheet
0606_07 Figure6. WritetoBufferFlowchart Start WriteWordorByte Count, Block Address WriteBuffer Data, Start Address X=0 X=X+1 WriteNext Buffer Data, DeviceAddress AbortWriteto BufferCommand? Check X=N? Another Writeto Buffer? ReadStatus Register SR.7= Programming Complete ReadExtended Status RegisterXSR.7= No Yes No No WritetoBuffer Aborted Yes NoYes FullStatus Check if Desired ProgramBuffertoFlash ConfirmD0H IssueWritetoBuffer CommandE8H,Block Address WritetoAnother Block Address Writeto BufferTime-Out? SetTime-Out IssueRead StatusCommand Yes Bus Operation Command Comments Write WritetoBuffer Data=E8H Block Address Read XSR.7=Valid Addr = Block Address Standby CheckXSR.7 1 = WriteBuffer Available 0 = WriteBuffer Not Available Write (Note1,2) Da t a=N=Wo r d / By t eCo unt N = 0 Corresponds toCount = 1 Addr = Block Address Write (Note3,4) Data= WriteBuffer Data Addr = DeviceStart Address Write (Note5,6) Data= WriteBuffer Data Addr = DeviceAddress Write ProgramBuffer toFlash Confirm Data=D0H Addr = Block Address Read (Note7) Status Register Datawith the DeviceEnabled, OE# Low Updates SR Addr = Block Address Standby CheckSR.7 1 = WSM Ready 0=WSMBus y 1. Byteor wordcount values on DQ0 -DQ7 areloadedintothe count register. Count ranges on this devicefor bytemodeare N =00H to1FH andforwordmodeareN =0000H to000FH. 2. Thedevicenowoutputs thestatus register when read(XSR is nolonger available). 3. WriteBuffer contents will beprogrammedat thedevicestart address or destination flash address. 4. Align thestart address on aWriteBuffer boundary for maximumprogrammingperformance(i.e.,A 4 -A0 of thestart address = 0). 5. Thedeviceaborts theWritetoBuffer commandif thecurrent address is outsideof theoriginal block address. 6. Thestatus register indicates an "improper command sequence" if theWritetoBuffer commandis aborted. Followthis with aClear Status Register command. 7. TogglingOE# (lowtohigh tolow) updates thestatus register. This can bedonein placeof issuingtheReadStatus Register command. Full status check can bedoneafter all eraseandwritesequences complete. WriteFFH after thelast operation toreset thedeviceto readarray mode.
0606_08 Figure7. Byte/WordProgramFlowchart Start Write 40H, Address Write Data and Address Read Status Register SR.7 = Full Status Check if Desired Byte/Word ProgramComplete Read Status Register Data (See Above) Voltage Range Error Device Protect Error Programming Error Byte/Word Program Successful SR.3 = SR.1 = SR.4 = FULLSTATUSCHECKPROCEDURE Bus Operation Write Write Standby 1. Toggling OE# (low to high to low) updates thestatus register. This can bedonein placeof issuingtheRead Status Reg ister command. Repeat for subsequent programming operations. SR full status check can bedoneafter each program operation, or after a sequenceof programming operations. WriteFFH after thelast program operation to placedevicein read array mode. Bus Operation Standby Standby Toggling OE# (low to high to low) updates thestatus register. This can bedonein placeof issuingtheRead Status Reg ister command. Repeat for subsequent programming operations. SR.4, SR.3 and SR.1 areonly cleared by theClear Status Register command in cases wheremultiplelocations areprogrammed before full status is checked. If an error is detected, clear thestatus register beforeattempting retry or other error recovery. Command Setup Byte/ Word Program Byte/Word Program Comments Data = 40H Addr = Location to BeProgrammed D a t a=D a t at oB eP r o gr a mme d Addr = Location to BeProgrammed Check SR.7 1 = WSM Ready 0=WS MB u s y Command Comments Check SR.3 1 = Programming to VoltageError Detect Check SR.4 1 = Programming Error Read (Note1) Status Register Data Standby Check SR.1 1 = Device Protect Detect RP# = VIH, Block Lock-Bit Is Set Only required for systems implemetinglock-bit config uration.
34 Datasheet
0606_09 Figure8. BlockEraseFlowchart Start Read Status Register SR.7 = Erase Flash Block(s) Complete Full Status Check if Desired Suspend Erase Issue Single Block Erase Command 20H, Block Address Suspend Erase Loop Write Confirm D0H Block Address Yes No Bus Operation Command Comments Write Erase Block Data = 20H Addr = Block Address Write(Note1) Erase Confirm Data = D0H Addr = X Read Status register data With the device enabled, OE# lowupdates SR Addr = X Standby Check SR.7 1 = WSM Ready 0=WS MB u s y 1. The Erase Confirm byte must followErase Setup. This device does not support erase queuing. Please see Application note AP-646 For software erase queuing compatibility. Full status check can be done after all erase and write sequences complete. Write FFH after the last operation to reset the device to read array mode.
0606_10 Figure9. BlockEraseSuspend/ResumeFlowchart Start WriteB0H Read StatusRegister SR.7= SR.6= Block EraseCompleted Read or Program? Done? WriteD0H Block Erase Resumed Write FFH Read ArrayData Program Program Loop Read Array Data Read No Yes Bus Operation Command Comments Write Erase Suspend Data =B0H Addr = X Read StatusRegister Data Addr = X Standby Check SR.7 1 - WSM Ready 0=WSMBu s y Standby Check SR.6 1 = Block Erase Suspended 0=Bl o c kEr a s eC o mp l e t e d Write Erase Resume Data =D0H Addr = X
36 Datasheet
0606_11 Figure10.SetBlockLock-BitFlowchart Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register SR.7 = Full Status Check if Desired Set Lock-Bit Complete FULLSTATUSCHECKPROCEDURE Bus Operation Write Write Standby Repeat for subsequent lock-bit operations. Full status check can bedoneafter each lock-bit set operation or after a sequenceof lock-bit set operations WriteFFH after thelast lock-bit set operation to placedevicein read array mode. Bus Operation Standby SR.5, SR.4, SR.3 and SR.1 areonly cleared by theClear Status Register command, in cases wheremultiplelock-bits areset beforefull status is checked. If an error is detected, clear thestatus register beforeattempting retry or other error recovery. Standby Command Set Block/Master Lock-Bit Setup Set Block or Master Lock-Bit Confirm Comments Data = 60H Addr =Block Address (Block), DeviceAddress (Master) Data = 01H (Block) F1H (Master) Addr = Block Address (Block), DeviceAddress (Master) Check SR.7 1 = WSM Ready 0=WS MB u s y Command Comments Check SR.3 1 = Programming VoltageError Detect Check SR.1 1 = DeviceProtect RP# = V IH (Set Master Lock-Bit Operation) RP# = V IH, Master Lock-Bit Is Set (set Block Lock-Bit Operation) Read Status Register Data (See Above) Voltage Range Error Device Protect Error SR.3 = SR. 1 = Command Sequence ErrorSR.4,5 = Set Lock-Bit ErrorSR.4 = Read Status Register Data Standby Check SR.4, 5 Both 1 = Command Sequence Error Standby Check SR.4 1 = Set Lock-Bit Error Set Lock-Bit Successful
0606_12 Figure11.ClearBlockLock-BitFlowchart Start Write 60H WriteD0H Read Status Register SR.7 = Full Status Check if Desired Clear Block Lock-Bits Complete FULLSTATUSCHECKPROCEDURE Bus Operation Write Write Standby WriteFFH after theclear lock-bits operation to placedevicein read array mode. Bus Operation Standby SR.5, SR.4, SR.3 and SR.1 areonly cleared by theClear Status Register command. If an error is detected, clear thestatus register beforeattempting retry or other error recovery. Standby Command Clear Block Lock-Bits Setup Clear Block or Lock-Bits Confirm Comments Data = 60H Addr = X Data = D0H Addr = X Check SR.7 1 = WSM Ready 0=WS MB u s y Command Comments Check SR.3 1 = Programming VoltageError Detect Check SR.1 1 = Device Protect RP# = V IH, Master Lock-Bit Is Set Read Status Register Data (See Above) Voltage Range Error Device Protect Error SR.3 = SR. 1 = Command Sequence ErrorSR.4,5 = Clear Block Lock-Bits ErrorSR.5 = Read Status Register Data Standby Check SR.4, 5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Clear Block Lock-Bits Error Clear Block Lock-Bits Successful
38 Datasheet
5.0 DesignConsiderations
5.1 Three-LineOutputControl
Thedevicewilloftenbeusedinlargememoryarrays.Intelprovidesfivecontrolinputs(CE 0,CE1, CE2,OE#,andRP#)toaccommodatemultiplememoryconnections.Thiscontrolprovidesfor:
- Lowestpossiblememorypowerdissipation.
- Completeassurancethatdatabuscontentionwillnotoccur. Tousethesecontrolinputsefficiently,anaddressdecodershouldenablethedevice(see Table2) whileOE#shouldbeconnectedtoallmemorydevicesandthesystem’sREAD#controlline.This assuresthatonlyselectedmemorydeviceshaveactiveoutputswhilede-selectedmemorydevices areinstandbymode.RP#shouldbeconnectedtothesystemPOWERGOODsignaltoprevent unintendedwritesduringsystempowertransitions.POWERGOODshouldalsotoggleduring systemreset.
5.2 STSandBlockErase,Program,andLock-BitConfiguration
STSisanopendrainoutputthatshouldbeconnectedtoV CCQbyapull-upresistortoprovidea hardwaremethodofdetectingblockerase,program,andlock-bitconfigurationcompletion.In defaultmode,ittransitionslowafterblockerase,program,orlock-bitconfigurationcommandsand returnstoHighZwhentheWSMhasfinishedexecutingtheinternalalgorithm.Foralternate configurationsoftheSTSpin,seetheConfigurationcommand. STScanbeconnectedtoaninterruptinputofthesystemCPUorcontroller.Itisactiveatalltimes. STS,indefaultmode,isalsoHighZwhenthedeviceisinblockerasesuspend(withprogramming inactive)orinreset/power-downmode.
5.3 PowerSupplyDecoupling
Flashmemorypowerswitchingcharacteristicsrequirecarefuldevicedecoupling.Systemdesigners areinterestedinthreesupplycurrentissues;standbycurrentlevels,activecurrentlevelsand transientpeaksproducedbyfallingandrisingedgesofCE 0,CE1,CE2,andOE#.Transientcurrent magnitudesdependonthedeviceoutputs’capacitiveandinductiveloading.Two-linecontroland properdecouplingcapacitorselectionwillsuppresstransientvoltagepeaks.SinceIntelStrataFlash memorydevicesdrawtheirpowerfromthreeV CCpins(thesedevicesdonotincludeaV PPpin),it isrecommendedthatsystemswithoutseparatepowerandgroundplanesattacha0.1µFceramic capacitorbetweeneachofthedevice’sthreeV CCpins(thisincludesV CCQ)andground.These high-frequency,low-inductancecapacitorsshouldbeplacedascloseaspossibletopackageleads oneachIntelStrataFlashmemorydevice.Eachdeviceshouldhavea0.1µFceramiccapacitor connectedbetweenitsV CCandGND.Thesehigh-frequency,lowinductancecapacitorsshouldbe placedascloseaspossibletopackageleads.Additionally,foreveryeightdevices,a4.7µF electrolyticcapacitorshouldbeplacedbetweenV CCandGNDatthearray’spowersupply connection.ThebulkcapacitorwillovercomevoltageslumpscausedbyPCboardtrace inductance.
5.4 InputSignalTransitions–ReducingOvershootsand
UndershootsWhenUsingBuffers/Transceivers Asfaster,high-drivedevicessuchastransceiversorbuffersdriveinputsignalstoflashmemory devices,overshootsandundershootscansometimescauseinputsignalstoexceedflashmemory specifications(seeSection6.1, AbsoluteMaximumRatings ).Manybuffer/transceivervendorsnow carrybus-interfacedeviceswithinternaloutput-dampingresistorsorreduced-driveoutputs. Internaloutput-dampingresistorsdiminishthenominaloutputdrivecurrents,whilestillleaving sufficientdrivecapabilityformostapplications.Theseinternaloutput-dampingresistorshelp reduceunnecessaryovershootsandundershoots.Transceiversorbufferswithbalanced-orlight- driveoutputsalsoreduceovershootsandundershootsbydiminishingoutput-drivecurrents.When selectingabuffer/transceiverinterfacedesigntoflash,deviceswithinternaloutput-damping resistorsorreduced-driveoutputsshouldbeconsideredtominimizeovershootsandundershoots. Foradditionalinformation,pleasereferto AP-647,5VoltIntelStrataFlash ®MemoryDesignGuide (order292205).
5.5 V CC,VPEN,RP#Transitions
Blockerase,program,andlock-bitconfigurationarenotguaranteedifV PENorVCCfallsoutsideof thespecifiedoperatingranges,orRP# ≠ VIHorVHH.IfRP#transitionstoV ILduringblockerase, program,orlock-bitconfiguration,STS(indefaultmode)willremainlowforamaximumtimeof t PLPH+tPHRHuntiltheresetoperationiscomplete.Then,theoperationwillabortandthedevice willenterreset/power-downmode.Theabortedoperationmayleavedatapartiallycorruptedafter programming,orpartiallyalteredafteraneraseorlock-bitconfiguration.Therefore,blockerase andlock-bitconfigurationcommandsmustberepeatedafternormaloperationisrestored.Device power-offorRP#=V ILclearsthestatusregister. TheCUIlatchescommandsissuedbysystemsoftwareandisnotalteredbyV PEN,CE0,CE1,or CE2transitions,orWSMactions.Itsstateisreadarraymodeuponpower-up,afterexitfromreset/ power-downmode,orafterV CCtransitionsbelowV LKO.VCCmustbekeptatoraboveV PEN duringVCCtransitions. Afterblockerase,program,orlock-bitconfiguration,evenafterV PENtransitionsdowntoV PENLK, theCUImustbeplacedinreadarraymodeviatheReadArraycommandifsubsequentaccessto thememoryarrayisdesired.V PENmustbekeptatorbelowV CCduringVPENtransitions.
5.6 Power-Up/DownProtection
Thedeviceisdesignedtoofferprotectionagainstaccidentalblockerasure,programming,orlock- bitconfigurationduringpowertransitions.InternalcircuitryresetstheCUItoreadarraymodeat power-up. AsystemdesignermustguardagainstspuriouswritesforV CCvoltagesaboveV LKOwhenVPENis active.SinceWE#mustbelowandthedeviceenabled(see Table2)foracommandwrite,driving WE#toV IHordisablingthedevicewillinhibitwrites.TheCUI’stwo-stepcommandsequence architectureprovidesaddedprotectionagainstdataalteration. KeepingVPEN belowVPENLKpreventsinadvertentdataalteration.In-systemblocklockand unlockcapabilityprotectsthedeviceagainstinadvertentprogramming.Thedeviceisdisabled whileRP#=V ILregardlessofitscontrolinputs.
40 Datasheet
5.7 PowerDissipation
Whendesigningportablesystems,designersmustconsiderbatterypowerconsumptionnotonly duringdeviceoperation,butalsofordataretentionduringsystemidletime.Flashmemory’s nonvolatilityincreasesusablebatterylifebecausedataisretainedwhensystempowerisremoved.
6.0 ElectricalSpecifications
6.1 AbsoluteMaximumRatings
NOTES: 1. AllspecifiedvoltagesarewithrespecttoGND.MinimumDCvoltageis–0.5Voninput/outputpinsand–0.2 V on VCC and VPEN pins. Duringtransitions,this level may undershoot to –2.0 Vfor periods <20 ns. Maximum DC voltage on input/output pins, VCC,and VPEN is VCC +0.5 V which, duringtransitions, may overshoot to VCC +2.0 V forperiods <20 ns. 2. Maximum DC voltage on RP# may overshoot to +14.0V for periods <20 ns. 3. RP# voltage is normally at V IL orV IH. Connectionto supply ofVHH is allowed for a maximum cumulative period of 80 hours. 4. Output shorted for no more than one second. No more than one output shorted ata time. 5. Extended temperature for 0.4 micronETOX TM V process technology is from -20° C to +85°C. Warning: Stressingthedevicebeyondthe“AbsoluteMaximumRatings”maycausepermanentdamage.Thesearestressratingsonly. Operationbeyondthe“OperatingConditions”isnotrecommendedandextendedexposurebeyondthe“OperatingConditions” mayaffectdevicereliability.
6.2 OperatingConditions
Temperature underBias Expanded –20 °C to +70 °C –40 °C to +85 °C 5 Storage Temperature –65 °C to +125 °C –65 °C to +125 °C V o l t a geO nA n yP i n( e x c e p tRP # ) – 2 . 0Vt o+ 7 . 0V – 2 . 0Vt o+ 7 . 0V 1 RP# Voltage with Respect to GND during Lock-Bit Configuration Operations – 2 . 0Vt o+ 1 4 . 0V – 2 . 0Vt o+ 1 4 . 0V 1 , 2 , 3 Output Short Circuit Current 100 mA 100 mA 4 NOTICE: This datasheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Table19. TemperatureandV CCOperatingConditions Symbol Parameter Notes Min Max Unit TestCondition TA OperatingTemperature –20 +85 °C Ambient Temperature VCC VCC1 Supply Voltage (5 V±10%) 4.50 5.50 V VCCQ1 VCCQ1 Supply Voltage (5 V±10%) 4.50 5.50 V VCCQ2 VCCQ2 Supply Voltage (2.7 V—3.6 V) 2.70 3.60 V
6.3 Capacitance
TA=+25°C,f=1MHz NOTE: 1. Sampled, not 100% tested.
6.4 DCCharacteristics
Symbol Parameter (1) Typ Max Unit Condition CIN Input Capacitance 6 8 pF V IN =0 . 0V COUT Output Capacitance 8 12 pF V OUT =0 . 0V Symbol Parameter Notes Typ Max Unit TestConditions ILI Input and VPEN Load Current 1 ±1 µAV CC =V CC Max,V IN =V CC orGND ILO Output Leakage Current 1 ±10 µAV CC =V CC Max,V IN =V CC orGND ICCS VCC Standby Current 1,2,3 80 150 µA CMOS Inputs, VCC =V CC Max, CE0 =C E1 =C E2 =RP #=V CCQ1 ±0.2V 450 900 µA CMOS Inputs, RP# = VCC =V CC Max, CE0 =C E1 =C E2 =V CCQ2 Min 325 650 µA CMOS Inputs, RP# = VCC =V CC Max, CE2 = GND, CE0 =C E1 =V CCQ2 Min 210 400 µA CMOS Inputs, RP# = VCC =V CC Max, CE1 =C E2 =G N D,C E0 =V CCQ2 Min or CE0 =C E2 =G N D,C E1 =V CCQ2 Min 0.71 2 mA TTL Inputs, VCC =V CC Max, CE0 =C E1 =C E2 =RP #=V IH ICCD VCC Power-DownCurrent 80 125 µA R P #=G N D±0 . 2V IOUT (STS) = 0 mA ICCR VCC Read Current 1,3,4 35 55 mA CMOS Inputs, VCC =V CCQ =VCC Max Device is enabled (seeTable 2) f=5MH z I OUT =0m A 45 65 mA TTL Inputs ,VCC =V CC Max Device is enabled (seeTable 2) f=5MH z I OUT =0m A ICCW VCC Program or Set Lock-Bit Current 1,4,5 35 60 mA CMOS Inputs, V PEN =V CC 40 70 mA TTL Inputs, V PEN =V CC ICCE VCC Block Erase or ClearBlock Lock-Bits Current 1,4,5 35 70 mA CMOS Inputs, V PEN =V CC 40 80 mA TTL Inputs, V PEN =V CC ICCES VCC Block EraseSuspend Current 1,6 10 mA Device is disabled (see Table 2)
42 Datasheet
DCCharacteristics,Continued NOTES: 1. All currents are in RMSunless otherwise noted. Thesecurrents are valid for all product versions (packages andspeeds).ContactIntel’sApplicationSupportHotlineoryourlocalsalesofficeforinformationabouttypical specifications. 2. Includes STS. 3. CMOS inputs are eitherV CC ±0.2 Vor GND ±0.2 V.TTL inputs are eitherVIL orV IH. 4. Add 5 mA forVCCQ =V CCQ2 min. 5. Sampled, not 100% tested. 6. I CCES is specified with the device de-selected.Ifthe device is read or written while in erase suspend mode, the device’s currentdraw is ICCR or ICCW. 7. Tie VPEN to VCC (4.5 V–5.5 V). 8. Block erases, programming, and lock-bit configurations are inhibited when VPEN ≤ VPENLK,and not guaranteed in the range between VPENLK (max)and VPENH (min), and above VPENH(max). 9. Block erases, programming, and lock-bit configurations are inhibited when VCC <V LKO,andnotguaranteed in the range between VLKO (min)and VCC (min), and above VCC (max). 10.Master lock-bitsetoperations are inhibited when RP# = VIH. Block lock-bit configuration operations are inhibited when the masterlock-bit is set and RP# = VIH. Block erases and programming are inhibited when the correspondingblock-lock bit is setand RP# = VIH. Block erase, program,and lock-bit configuration operations are not guaranteed and should not be attempted with VIH <RP #<V HH. 11.RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours. Symbol Parameter Notes Min Max Unit TestConditions VIL InputLow Voltage 5 –0.5 0.8 V VIH InputHigh Voltage 5 2.0 VCC +0 . 5 V VOL Output Low Voltage 2,5 0.45 V V CCQ =V CCQ1 Min, IOL =5 . 8m A
0.4 V V CCQ =V CCQ2 Min, IOL =2m A
VOH Output High Voltage 3,7 2.4 V VCCQ =V CCQ1 Min or VCCQ =V CCQ2 Min IOH =–2 .5m A( VCCQ1) –2 mA(VCCQ2) 0.85 X VCCQ V VCCQ =V CCQ1 Min or VCCQ =V CCQ2 Min IOH =– 2 .5m A VCCQ –0.4 V VCCQ =V CCQ1 Min or VCCQ =V CCQ2 Min IOH =– 1 0 0µA VPENLK VPEN Lockout duringNormal Operations 5,7,8 3.6 V VPENH VPEN duringBlock Erase, Program, or Lock-BitOperations 7,8 4.5 5.5 V VLKO VCC LockoutVoltage 9 3.25 V VHH RP# Unlock Voltage 10,11 11.4 12.6 V Set master lock-bit Override lock-bit
NOTE: AC test inputs are driven at VOH (2.4 VTTL) for a Logic “1” and VOL (0.45 VTTL) for a Logic "0." Input timing begins at NOTE: AC test inputsare driven at 2.7 V for a Logic “1” and 0.0 V for a Logic “0.” Input timing begins, and output timing ends, at 1.35 V (50% of V CCQ). Input rise and fall times (10% to 90%) <10 ns. NOTE: CL Includes JigCapacitance Figure12.TransientInput/OutputReferenceWaveformforV CCQ=5.0V±10%(Standard TestingConfiguration) OutputTest PointsInput 2.0 0.8 2.0 0.8 2.4 0.45 Figure13.TransientInput/OutputReferenceWaveform OutputTest PointsInput 1.35 2.7 0.0 1.35 Figure14.TransientEquivelentTestingLoadCircuit Device UnderTest Out RL =3. 3kΩ 1N914 1.3V CL Table20. TestConfigurationCapacitanceLoadingValue TestConfiguration C L(pF) VCCQ =5 . 0V± 10% 100 VCCQ =2 . 7V−3.6 V 50
44 Datasheet
6.5 ACCharacteristics—Read-OnlyOperations (1)
NOTE: CEX lowisdefinedas thefirstedge ofCE 0,C E1,orCE 2 thatenablesthedevice.CE X highisdefinedat t h ef i r s te d geo fC E0,C E1,o rC E2 that disables the device (seeTable 2). 1. SeeFigure 15,“AC Waveform forReadOperations”on page 45for the maximum allowable input slew rate. 2. SeeFigure 12,Figure 13,a n dF i gu r e1 4o np a ge4 3, fortestingcharacteristics 3 .O E #m a yb ed e l a y e du pt otELQV-tGLQV after the first edge of CE0,C E1,o rC E2 thatenables the device (see Table 2) withoutimpact on tELQV. 4. Sampled, not 100% tested. Versions 5V±10%V CCQ –120/–150(2) (Allunitsinnsunlessotherwisenoted) 2.7V—10%V CCQ –120/–150(2) # Sym Parameter Notes Min Max R1 t AVAV Read/Write Cycle Time
32 Mbit 120
130 at +85° C
64 Mbit 150
R2 t AVQV Address to OutputDelay 130 at +85° C R3 t ELQV CEX to Output Delay
32 Mbit 3 120
130 at +85° C
64 Mbit 3 150
R4 t GLQV OE# to OutputDelay 3 50 R5 t PHQV R P #H i ght oO u t p u tD e l a y
32 Mbit 180
64 Mbit 210
R6 t ELQX CEX to Output in Low Z 4 0 R7 t GLQX OE# to Outputin Low Z 4 0 R8 t EHQZ CEX H i ght oO u t p u ti nH i ghZ 4 5 5 R9 t GHQZ O E #H i ght oO u t p u ti nH i ghZ 4 1 5 R10 t OH Output Hold from Address, CEX, orOE# Change, WhicheverOccurs First 40 R11 tELFL tELFH CEX Low to BYTE# High orLow 4 10 R12 tFLQV tFHQV BYTE# to Output Delay 1000 R13 t FLQZ BYTE# to Output in High Z 4 1000 R14 t EHEL CEx Disable Pulse Width 4 10
0606_16 NOTE: CEX low is defined as the firstedge of CE0,C E1,orC E2 that enables the device.CEX high is defined at t h ef i r s te d geo fC E0,CE 1,o rC E2 thatdisables the device (seeTable 2, “Chip Enable Truth Table” on page 12). Figure15.ACWaveformforReadOperations R1 R14 R10 High Z R13 R11 R12 Valid Output AddressStable Data ValidDevice AddressSelectionStandby ADDRESSES[A] VIH VIL VIH VIL Disabled (VIH) Enabled (VIL) CEX [E] VIH VIL VOH VOL VIH VIL VIH VIL VIH VIL OE#[G] WE#[W] DATA[D/Q] DQ0-DQ15 VCC RP#[P] BYTE#[F] High Z
46 Datasheet
6.6 ACCharacteristics—WriteOperations (1,2)
NOTE: CEX lowisdefinedas thefirstedge ofCE 0,C E1,orCE 2 thatenablesthedevice.CE X highisdefinedat t h ef i r s te d geo fC E0,C E1,o rC E2 that disables the device (seeT a b l e2o np a ge1 2). 1. Readtimingcharacteristics duringblock erase,prog ram, and lock-bit config uration operations are the same as duringread-only operations. Refer toACCharacteristics–Read-Only Operations. 2. A write operation can be initiated and terminated with eitherCEX or WE#. 3. Sampled, not 100% tested. 4. Writepulsewidth(t WP)isdefinedfromCE X orWE#goinglow(whichevergoeslowlast)toCE X orWE#going high (whichevergoes high first). Hence,tWP =t WLWH =tELEH =t WLEH =tELWH.I fC EX is drivenlow 10 ns before WE# going low, WE# pulse width requirementdecreases to tWP -10ns . 5. Referto T a b l e4o np a ge1 7for valid AIN and DIN for block erase, program,orlock-bit configuration. 6 .W r i t ep u l s ew i d t hh i gh( tWPH) is defined from CEX or WE# going high (whichevergoes high first)to CEX or WE# going low (whichevergoes low first). Hence,tWPH =t WHWL =tEHEL =t WHEL =tEHWL. 7. For array access,tAVQVis required in addition to tWHGL for any accesses aftera write. 8. STS timings are based on STS configured in its RY/BY# default mode. 9. V PEN should be held at VPENH (and if necessary RP# should be held atVHH) until determination ofblock erase, program, orlock-bit configuration success (SR.1/3/4/5 = 0). Versions ValidforAll Speeds # Sym Parameter Notes Min Max Unit W1 t PHWL (tPHEL) RP# High Recovery to WE# (CE X ) GoingLow 3 1 µs W2 t ELWL (tWLEL)C E X (WE#)Lowto WE# (CEX)GoingLow 4 0 ns W3 t WP Write Pulse Width 4 70 ns W4 t DVWH (tDVEH) Data Setup to WE# (CE X )GoingHig h 5 50 ns W5 t AVWH (tAVEH) A d d r e s sS e t u pt oW E #( CEX )GoingHig h 5 50 ns W6 t WHEH (tEHWH)C E X (WE#) Hold from WE# (CEX)H i gh 1 0 n s W7 t WHDX (tEHDX) D a t aH o l df r o mW E #( C EX )H i gh 0 n s W8 t WHAX (tEHAX) Address Hold from WE# (CE X )H i gh 0 n s W9 t WPH W r i t eP u l s eW i d t hH i gh 6 3 0 n s W10 t PHHWH (tPHHEH)R P # V HH S e t u pt oW E #( C EX ) GoingHig h 3 0 ns W11 t VPWH (tVPEH)V PEN S e t u pt oW E #( CEX )GoingHig h 3 0 ns W12 t WHGL (tEHGL) Write Recovery before Read 7 35 ns W13 t WHRL (tEHRL)W E # ( C E X )H i ght oS T SG o i n g L o w 8 9 0 n s W14 t QVPH RP# VHH Hold from Valid SRD, STS GoingHig h 3,8,9 0 ns W15 t QVVL VPEN Hold from Valid SRD, STS GoingHig h 3,8,9 0 ns
0606_17 NOTE: CEX low is definedasthe firstedgeofCE 0,C E1,o rC E2 thatenablesthe device.CE X highis definedat t h ef i r s te d geo fC E0,C E1,orCE 2 that disables the device (seeT a b l e2o np a ge1 2). STS is shown in its default mode (RY/BY#). a. VCC power-up and standby. b. Write block erase,write buffer, orprogram setup. c. Write block erase orwrite bufferconfirm, orvalid address and data. d. Automated erase delay. e. Read status registerorquery data. f. Write Read Array command. Figure16.ACWaveformforWriteOperations AIN AIN AB C D E F W15 DIN W11 W10 Valid SRDDINDIN W13 W14 High Z W2 W9 W16 W12W6 W5 W8 VIH VIL ADDRESSES[A] Disabled(V IH) Enabled (VIL) CEX,(WE#)[E(W)] VIH VIL OE#[G] Disabled(V IH) Enabled (VIL) WE#,(CEX)[W(E)] VIH VIL DATA[D/Q] VOH VOL STS[R] VIH VIL RP#[P] VHH VPENLK VIL VPEN[V] VPENH
48 Datasheet
0606_18 NOTE: STS is shown in its default mode (RY/BY#). NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted while a block erase, program,orlock-bit configuration operation is not executing then the minimum required RP# Pulse Low Time is 100 ns. 3. A reset time, t PHQV, is required from the latter of STS(in RY/BY# mode)orRP# going high until outputs are valid. Figure17.ACWaveformforResetOperation STS(R) RP#(P) VIH VIL VIH VIL Table21. ResetSpecifications(1) # Sym Parameter Notes Min Max P1 t PLPH RP# Pulse Low Time (If RP# is tied to VCC, this specification is not applicable) 23 5 P2 t PHRH R P #H i ght oR e s e td u r i n g B l o c kE r a s e ,P r o gr a m ,o rL o c k - B i t Configuration 3 100
6.7 BlockErase,Program,andLock-BitConfiguration
Performance(1,2) NOTES: 1. These performance numbers are valid for all speed versions. 2. Sampled butnot 100% tested. 3. Typicalvalues measuredatT A =+25°Candnominalvoltages.Assumescorresponding lock-bitsarenotset. Subject to change based on device characterization. 4. Excludes system-level overhead. 5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. 6. Effective per-byte program time (t WHQV1,t EHQV1) is 6.8 µs/byte (typical). 7. Effective per-word program time (tWHQV2,t EHQV2) is 13.6 µs/byte (typical). #S y m P a r a m e t e r N o t e s T y p (3) Max Unit W16 Write Buffer Program Time 4,5,6,7 218 654 µs W16 tWHQV3 tEHQV3 Byte Program Time (Using Word/Byte Program Command) 4 210 630 µs Block Program Time (Using Write to Buffer Command) 4 0.8 2.4 sec W16 tWHQV4 tEHQV4 Block Erase Time 4 1.0 5.0 sec W16 tWHQV5 tEHQV5 SetLock-Bit Time 4 64 75 µs W16 tWHQV6 tEHQV6 ClearBlock Lock-Bits Time 4 .50 7.0 sec W16 tWHRH tEHRH Erase Suspend Latency Time to Read 26 35 µs
50 Datasheet
7.0 AdditionalInformation
NOTES: 1. Please callthe Intel Literature Centerat(800)548-4725 to requestIntel documentation. International customers should contact theirlocal Intelor distribution sales office. 2. Visit Intel’s World Wide Web home page athttp://www.intel.com fortechnical documentation and tools. Forthe mostcurrent information on IntelStrataFlash memory, visit our website at http://developer.intel.com/ design/flash/isf. OrderNumber Document/Tool Contact Intel/Distribution Sales Office 5 VoltIntel StrataFlash® Memory0.25µ Generation/32-,and64-MbitDensities EAS 290667 3 VoltIntel StrataFlash® Memory;28F128J3A,28F640J3A,28F320J3A datasheet 290608 3VoltFlashFile™Memory;28F160S3and28F320S3 datasheet 290609 5VoltFlashFile™Memory;28F160S5and28F320S5 datasheet 290429 5VoltFlashFile™Memory;28F008SA datasheet 290598 3VoltFlashFile™Memory;28F004S3,28F008S3,28F016S3 datasheet 290597 5VoltFlashFile™Memory;28F004S5,28F008S5,28F016S5 datasheet
292235 AP-687 5 VoltIntel StrataFlash® MemoryInterfacetotheSA-1100
297859 AP-677IntelStrataFlash ® MemoryTechnology
292222 AP-664 Designing IntelStrataFlash® MemoryintoIntel ® Architecture
292221 AP-663 Using the Intel StrataFlash® MemoryWriteBuffer
292218 AP-660MigrationGuideto3VoltIntelStrataFlash ® Memory
292205 AP-647 5 VoltIntel StrataFlash® MemoryDesignGuide
292204 AP-646CommonFlashInterface(CFI)andCommandSets
292202 AP-644MigrationGuideto5VoltIntelStrataFlash ® Memory
297846 ComprehensiveUser’sGuideforµBGA*Packages
8.0 OrderingInformation
NOTE: Extended temperature for0.4 micron ETOXTM Vprocess technology is from -20° C to +85° C. DA2 8F640 J 5 - Package E = 56-Lead TSOP DA = 56-Lead SSOP (Commercial Temp) DT= 56-Lead SSOP (ExtendedTemp) Productlinedesignator forallIntel ® Flash products ProductFamily J = Intel StrataFlash® memory, 2 bits-per-cell DeviceDensity 640 = x8/x16 (64 Mbit) 320 = x8/x16 (32 Mbit) Voltage(VCC/VPEN) 5=5V/ 5V A 1 5 0 AccessSpeed(ns) 32Mbit=120 64Mbit=150 Intel® . 25m i c r o nE T O XV ITM Process Technology OrderCodebyDensity ValidOperationalConditions5VV CC 32Mbit 64Mbit 2.7V–3.6VV CCQ 5V±10%V CCQ DA28F320J5-120 DA28F640J5-150 Yes Yes E28F320J5-120 DT28F640J5-150 Yes Yes DT28F320J5-120 DA28F640J5A-150 Yes Yes DA28F320J5A-120 DT28F640J5A-150 Yes Yes E28F320J5A-120 Yes Yes DT28F320J5A-120 Yes Yes