28F200BV-TB INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 PRODUCT FAMILY OVERVIEW
- 1.1 New Features in the SmartVoltage Products
- 1.2 Main Features
- 1.3 Applications
- 1.4 Pinouts
- 1.5 Pin Descriptions
- 2.0 PRODUCT DESCRIPTION
- 2.1 Memory Blocking Organization
- 2.1.1 One 16-KB Boot Block
- 2.1.2 Two 8-KB Parameter Blocks
- 3.0 PRODUCT FAMILY PRINCIPLES OF
- 3.1 Bus Operations
- 3.2 Read Operations
- 3.2.1 Read Array
- 3.2.2 Intelligent Identifiers
- 3.3 Write Operations
- 3.3.1 Command User Interface (CUI)
- 3.3.2 Status Register
- 3.3.3 Program Mode
- 3.3.4 Erase Mode
- 3.4 Boot Block Locking
- 3.4.2 WP# = VIL for Boot Block Locking
- 3.4.3 RP# = VHH or WP# = VIH for Boot Block
- 3.4.4 Upgrade Note for 8-Mbit 44-PSOP
- 3.5 Power Consumption
- 3.5.1 Active Power
- 3.5.2 Automatic Power Savings (APS)
- 3.5.3 Standby Power
- 3.5.4 Deep Power-Down Mode
- 3.6 Power-Up/Down Operation
- 3.6.1 RP# Connected To System Reset
- 3.7 Power Supply Decoupling
- 4.0 ELECTRICAL SPECIFICATIONS
- 4.1 Absolute Maximum Ratings
- 4.2 Commercial Operating Conditions
- 4.2.1 Applying V
- 4.3 Capacitance
- 4.4 DC Characteristics—Commercial
- 4.5 AC Characteristics—Commercial
- 4.6 AC Characteristics—WE#-Controlled Write
- 4.7 AC Characteristics—CE#-Controlled Write
- 4.9 Extended Operating Conditions
- 4.9.1 Applying V
- 4.10 Capacitance
- 4.11 DC Characteristics—Extended
- 4.12 AC Characteristics—Read Only
- 4.13 AC Characteristics—WE#-Controlled Write
- 4.14 AC Characteristics—CE#-Controlled Write
- 4.15 Erase and Program Timings—Extended
- 5.0 ORDERING INFORMATION
- 6.0 ADDITIONAL INFORMATION
E SEE NEW DESIGN RECOMMENDATIONS December 1997 Order Number: 290531-005 /c110 Intel SmartVoltage Technology 5 V or 12 V Program/Erase 3.3 V or 5 V Read Operation /c110 Very High-Performance Read 5 V: 60 ns Access Time 3 V: 110 ns Access Time /c110 Low Power Consumption Max 60 mA Read Current at 5 V Max 30 mA Read Current at 3.3 V–3.6 V /c110 x8/x16-Selectable Input/Output Bus 28F200 for High Performance 16- or 32-bit CPUs /c110 x8-Only Input/Output Architecture 28F002B for Space-Constrained 8-bit Applications /c110 Optimized Array Blocking Architecture One 16-KB Protected Boot Block Two 8-KB Parameter Blocks 96-KB and 128-KB Main Blocks Top or Bottom Boot Locations /c110 Extended Temperature Operation –40 °C to +85 °C /c110 Extended Block Erase Cycling 100,000 Cycles at Commercial Temp 10,000 Cycles at Extended Temp /c110 Automated Word/Byte Program and Block Erase Command User Interface Status Registers Erase Suspend Capability /c110 SRAM-Compatible Write Interface /c110 Automatic Power Savings Feature /c110 Reset/Deep Power-Down Input 0.2 µA ICC Typical Provides Reset for Boot Operations /c110 Hardware Data Protection Feature Absolute Hardware-Protection for Boot Block Write Lockout during Power Transitions /c110 Industry-Standard Surface Mount Packaging 40-, 48-, 56-Lead TSOP 44-Lead PSOP /c110 Footprint Upgradeable to 4-Mbit and 8-Mbit Boot Block Flash Memories /c110 ETOX™ IV Flash Technology New Design Recommendations: For new 2.7 V–3.6 V VCC designs with this device, Intel recommends using the Smart 3 Advanced Boot Block. Reference Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family datasheet, order number 290580. For new 5 V VCC designs with this device, Intel recommends using the 2-Mbit Smart 5 Boot Block. Reference Smart 5 Flash Memory Family 2, 4, 8 Mbit datasheet, order number 290599. These documents are also available at Intel’s website, http://www.intel.com/design/flcomp. REFERENCE ONLY 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY 28F200BV-T/B, 28F200CV-T/B, 28F002BV-T/B
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F200BV-T/B, 28F200CV-T/B, 28F002BV-T/B may contain design defects or errors known as errata. Current characterized errata are available on request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 8021-9808 or call 1-800-548-4725 or visit Intel’s website at http://www.intel.com COPYRIGHT © INTEL CORPORATION, 1997 CG-041493 *Third-party brands and names are the property of their respective owners..
2-MBIT SmartVoltage BOOT BLOCK FAMILY E
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REVISION HISTORY
-001 Initial release of datasheet. -002 Status changed from Product Preview to Preliminary 28F200CV/CE/BE references and information added throughout. 2.7 V CE/BE specs added throughout. Note 2 added to Figure 3 to clarify 28F008B pinout vs. 28F008SA. Erroneous arrows leading out of error states deleted from flowcharts in Figs. 9, 10. Sections 5.1, 6.1 changed to “Applying V CC Voltages.” These sections completely changed to clarify VCC ramp requirements. IPPD 3.3 V Commercial spec changed from 10 to 5 µA. Capacitance tables added after commercial and extended DC Characteristics tables. Test and slew rate notes added to Figs. 12, 13, 19, 20, 21. Test configuration drawings (Fig. 14, 22) consolidated into one, with component values in table. (Component values also rounded off). t ELFL , tELFH , tAVFL changed from 7 to 5 ns for 3.3 V BV-60 commercial and 3.3 V TBV-80 extended, 10 to 5 ns for 3.3 V BV-80 and BV-120 commercial. tWHAX and tEHAX changed from 10 to 0 ns. tPHWL changed from 1000 ns to 800 ns for 3.3 V BV-80, BV-120 commercial. tPHEL changed from 1000 ns to 800 ns for 3.3 V BV-60, BV-80, and BV-120 commercial. -003 Applying V CC voltages (Sections 5.1 and 6.1) rewritten for clarity. Minor cosmetic changes/edits. -004 Corrections: “This pin not available on 44-PSOP” inaccurate statement removed from pin description for WP# pin; Spec “tQWL ” corrected to “tQVVL; ” intelligent identifier values corrected; Intel386™ EX block diagram updated because new 386 specs require less glue logic. Max program times for parameter and 96-KB main block added. Specs t ELFL and tELFH changed from 5 ns (max) to 0 ns (min). Specs tEHQZ and tHQZ improved. New specs tPLPH and tPLQZ added from Specification Update document (297612). -005 Corrections: Figure 4, corrected pin designation 3 to “NC” from A17 on PA28F200. Corrected typographical errors in Ordering Information. Added New Design Recommendations section to cover page. Updated Erase Suspend/Resume Flowchart
1.0 PRODUCT FAMILY OVERVIEW
1.1 New Features in the
- WP# pin has replaced a DU (Don’t Use) pin. Connect the WP# pin to control signal or to V CC or GND (in this case, a logic-level signal can be placed on DU pin). Refer to Tables 2 and 9 to see how the WP# pin works.
- 5 V program/erase operation has been added. If switching V PP for write protection, switch to GND (not 5 V) for complete write protection. To take advantage of 5 V write-capability, allow for connecting 5 V to V PP and disconnecting 12 V from VPP line.
- Enhanced circuits optimize low V CC performance, allowing operation down to VCC = 3.0 V. If you are using BX/BL 12 V VPP boot block products today, you should account for the differences listed above and also allow for connecting 5 V to V PP and disconnecting 12 V from VPP line, if 5 V writes are desired.
1.2 Main Features
256 Kwords of 16 bits each (28F200 only) or
512 Kbytes of 8 bits each (28F200 and 28F002B). Table 1. SmartVoltage Provides Total Voltage Flexibility
5 V ± 10%
5 V ± 10% 12 V ± 5%
2-MBIT SmartVoltage BOOT BLOCK FAMILY E
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Separately erasable blocks, including a hardware- lockable boot block (16,384 bytes), two parameter blocks (8,192 bytes each) and main blocks (one block of 98,304 bytes and one block of 131,072 bytes), define the boot block flash family architecture. See Figures 7 and 8 for memory maps. Each block can be independently erased and programmed 100,000 times at commercial temperature or 10,000 times at extended temperature. The boot block is located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for boot code location. The hardware-lockable boot block provides complete code security for the kernel code required for system initialization. Locking and unlocking of the boot block is controlled by WP# and/or RP# (see Section 3.4 for details). The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the boot block flash memory products. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller of these tasks. The Status Register (SR) indicates the status of the WSM and whether it successfully completed the desired program or erase operation. Program and Erase Automation allows program and erase operations to be executed using an industry- standard two-write command sequence to the CUI. Data programming is performed in word (28F200 family) or byte (28F200 or 28F002B families) increments. Each byte or word in the flash memory can be programmed independently of other memory locations, unlike erases, which erase all locations within a block simultaneously. The 2-Mbit SmartVoltage boot block flash memory family is also designed with an Automatic Power Savings (APS) feature which minimizes system battery current drain, allowing for very low power designs. To provide even greater power savings, the boot block family includes a deep power-down mode which minimizes power consumption by turning most of the flash memory’s circuitry off. This mode is controlled by the RP# pin and its usage is discussed in Section 3.5, along with other power consumption issues. Additionally, the RP# pin provides protection against unwanted command writes due to invalid system bus c onditions that may occur during system reset and power-up/down sequences. For example, when the flash memory powers-up, it automatically defaults to the read array mode, but during a warm system reset, where power continues uninterrupted to the system components, the flash memory could remain in a non-read mode, such as erase. Consequently, the system Reset signal should be tied to RP# to reset the memory to normal read mode upon activation of the Reset signal. See Section 3.6. The 28F200 provides both byte-wide or word-wide input/output, which is controlled by the BYTE# pin. Please see Table 2 and Figure 16 for a detailed description of BYTE# operations, especially the usage of the DQ 15/A–1 pin. The 28F200 products are available in a ROM/EPROM-compatible pinout and housed in the 44-lead PSOP (Plastic Small Outline) package, the 48-lead TSOP (Thin Small Outline, 1.2 mm thick) package and the 56-lead TSOP as shown in Figures 4, 5 and 6, respectively. The 28F002 products are available in the 40-lead TSOP package as shown in Figure 3. Refer to the DC Characteristics, Section 4.4 (commercial temperature) and Section 4.11 (extended temperature), for complete current and voltage specifications. Refer to the AC Characteristics, Section 4.5 (commercial temperature) and Section 4.12 (extended temperature), for read, write and erase performance specifications.
1.3 Applications
The 2-Mbit boot block flash memory family combines high-density, low-power, high- performance, cost-effective flash memories with blocking and hardware protection capabilities. Their flexibility and versatility reduce costs throughout the product life cycle. Flash memory is ideal for Just-In- Time production flow, reducing system inventory and costs, and eliminating component handling during the production phase. When your product is in the end-user’s hands, and updates or feature enhancements become necessary, flash memory reduces the update costs by allowing user-performed code changes instead of costly product returns or technician calls.
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 7SEE NEW DESIGN RECOMMENDATIONS The 2-Mbit boot block flash memory family provides full-function, blocked flash memories suitable for a wide range of applications. These applications include extended PC BIOS and ROM-able applications storage, digital cellular phone program and data storage, telecommunication boot/firmware, printer firmware/font storage and various other embedded applications where program and data storage are required. Reprogrammable systems, such as pers onal computers, are ideal applications for the 2-Mbit flash memory products. Increasing software sophistication greatens the probability that a code update will be required after the PC is shipped. For example, the emerging of “plug and play” standard in desktop and portable PCs enables auto- configuration of ISA and PCI add-in cards. However, since the plug and play specification continues to evolve, a flash BIOS provides a cost- effective capability to update existing PCs. In addition, the parameter blocks are ideal for storing the required auto-configuration parameters, allowing you to integrate the BIOS PROM and parameter storage EEPROM into a single component, reducing parts costs while increasing functionality. The 2-Mbit flash memory products are also excellent design solutions for digital cellular phone and telecommunication switching applications requiring very low power consumption, high- performance, high-density storage capability, modular software designs, and a small form factor package. The 2-Mbit’s blocking scheme allows for easy segmentation of the embedded code with
16 Kbytes of hardware-protected boot code, four
main blocks of program code and two parameter blocks of 8 Kbytes each for frequently updated data storage and diagnostic messages (e.g., phone numbers, authorization codes). Intel’s boot block architecture provides a flexible voltage solution for the different design needs of various applications. The asymmetrically-blocked memory map allows the integration of several memory components into a single flash device. The boot block provides a secure boot PROM; the parameter blocks can emulate EEPROM functionality for parameter store with proper software techniques; and the main blocks provide code and data storage with access times fast enough to execute code in place, decreasing RAM requirements.
1.4 Pinouts
Intel’s SmartVoltage Boot Block architecture provides upgrade paths in every package pinout to the 4 or 8-Mbit density. The 28F002B 40-lead TSOP pinout for space-constrained designs is shown in Figure 3. The 28F200 44-lead PSOP pinout follows the industry-standard ROM/EPROM pinout, as shown in Figure 4. For designs that require x16 operation but have space concerns, refer to the 48-lead pinout in Figure 5. Furthermore, the 28F200 56-lead TSOP pinout shown in Figure 6 provides compatibility with BX/BL family product packages. Pinouts for the corresponding 4-Mbit and 8-Mbit components are also provided for convenient reference. 2-Mbit pinouts are given on the chip illustration in the center, with 4-Mbit and 8-Mbit pinouts going outward from the center.
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A data bus buffer may be needed for processor speeds above 25 MHz. Figure 1. 28F200 Interface to Intel386™ EX Microprocessor Figure 2. 28F002B Interface to Intel80C188EB 8-Bit Embedded Microprocessor
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Figure 5. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation Figure 6. The 56-Lead TSOP Offers Compatibility between 2 and 4 Mbits
1.5 Pin Descriptions
Table 2. 28F200/002 Pin Descriptions don’t care in the signature mode when BYTE# is low. when CE# and WE# are active. Data is internally latched during the write cycle. tri-state when the chip is de-selected or the outputs are disabled. during a Program command. Data is internally latched during the write cycle. 15/A–1 becomes the lowest order address for data output on DQ0–DQ 7. The 28F002B does not include these DQ8–DQ 15 pins. through the CE# and RP# input stages. a read cycle. OE# is active low. WE# INPUT WRITE ENABLE: Controls writes to the Command Register and array blocks. unlocking. It is backwards-compatible with the BX/BL/BV products. transitions from logic-low to logic-high, the device defaults to the read array mode. erased. This overrides any control from the WP# input.
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HH . See Section 3.4 for details on write protection. read and programmed on DQ0–DQ 15. against Program and Erase commands. GND GROUND: For all internal circuitry. NC NO CONNECT: Pin may be driven or left floating.
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 13SEE NEW DESIGN RECOMMENDATIONS
2.0 PRODUCT DESCRIPTION
2.1 Memory Blocking Organization
This product family features an asymmetrically- blocked architecture providing system memory integration. Each erase block can be erased independently of the others up to 100,000 times for commercial temperature or up to 10,000 times for extended temperature. The block sizes have been chosen to optimize their functionality for common applications of nonvolatile storage. The combination of block sizes in the boot block architecture allow the integration of several memories into a single chip. For the address locations of the blocks, see the memory maps in Figures 4 and 5.
2.1.1 ONE 16-KB BOOT BLOCK
The boot block is intended to replace a dedicated boot PROM in a microprocessor or microcontroller- based system. The 16-Kbyte (16,384 bytes) boot block is located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map to accommodate different microprocessor protocols for boot code location. This boot block features hardware controllable write-protection to protect the crucial microprocessor boot code from accidental modification. The protection of the boot block is controlled using a combination of the V PP , RP#, and WP# pins, as is detailed in Section 3.4.
2.1.2 TWO 8-KB PARAMETER BLOCKS
The boot block architecture includes parameter blocks to facilitate storage of frequently updated small parameters that would normally require an EEPROM. By using software techniques, the byte- rewrite functionality of EEPROMs can be emulated. These techniques are detailed in Intel’s application note AP-604, Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM. Each boot block component contains two parameter blocks of 8 Kbytes (8,192 bytes) each. The parameter blocks are not write-protectable.
2.1.3 ONE 96-KB + ONE 128-KB MAIN
After the allocation of address space to the boot and parameter blocks, the remainder is divided into main blocks for data or code storage. Each 2-Mbit device contains one 96-Kbyte (98,304 byte) block and one 128-Kbyte (131,072 byte) block. See the memory maps for each device for more information.
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Figure 7. Word-Wide x16-Mode Memory Maps NOTE: These memory maps apply to the 28F002B or the 28F200 in x8 mode. Figure 8. Byte-Wide x8-Mode Memory Maps
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 15SEE NEW DESIGN RECOMMENDATIONS
3.0 PRODUCT FAMILY PRINCIPLES
Flash memory combines EPROM functionality with in-circuit electrical program and erase. The boot block flash family utilizes a Command User Interface (CUI) and automated algorithms to simplify program and erase operations. The CUI allows for 100% TTL-level control inputs, fixed power supplies during erasure and programming, and maximum EPROM compatibility. When V PP < VPPLK , the device will only successfully execute the following commands: Read Array, Read Status Register, Clear Status Register and intelligent identifier mode. The device provides standard EPROM read, standby and output disable operations. Manufacturer identification and device identification data can be accessed through the CUI or through the standard EPROM A 9 high voltage access (VID) for PROM programming equipment. The same EPROM read, standby and output disable functions are available when 5 V or 12 V is applied to the V PP pin. In addition, 5 V or 12 V on VPP allows program and erase of the device. All functions associated with altering memory contents: Program and Erase, Intelligent Identifier Read, and Read Status are accessed via the CUI. The internal Write State Machine (WSM) completely automates program and erase, beginning operation signaled by the CUI and reporting status through the status register. The CUI handles the WE# interface to the data and address latches, as well as system status requests during WSM operation.
3.1 Bus Operations
Flash memory reads, erases and programs in- system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. These bus operations are summarized in Tables 3 and 4.
3.2 Read Operations
3.2.1 READ ARRAY
When RP# transitions from VIL (reset) to VIH, the device will be in the read array mode and will respond to the read control inputs (CE#, address inputs, and OE#) without any commands being written to the CUI. When the device is in the read array mode, five control signals must be controlled to obtain data at the outputs.
- RP# must be logic high (V IH)
- WE# must be logic high (VIH)
- BYTE# must be logic high or logic low
- CE# must be logic low (VIL)
- OE must be logic low (VIL) In addition, the address of the desired location must be applied to the address pins. Refer to Figures 15 and 16 for the exact sequence and timing of these signals. If the device is not in read array mode, as would be the case after a program or erase operation, the Read Mode command (FFH) must be written to the CUI before reads can take place. During system design, consideration should be taken to ensure address and control inputs meet required input slew rates of <10 ns as defined in Figures 12 and 13.
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Table 3. Bus Operations for Word-Wide Mode (BYTE# = VIH) Table 4. Bus Operations for Byte-Wide Mode (BYTE# = VIL)
- Refer to DC Characteristics.
- X can be VIL, VIH for control pins and addresses, VPPLK or VPPH for VPP .
- See DC Characteristics for VPPLK , VPPH1 , VPPH2 , VHH , VID voltages.
- Manufacturer and device codes may also be accessed via a CUI write sequence, A1–A16 = X, A1–A17 = X.
- See Table 5 for device IDs.
- Refer to Table 7 for valid D
IN during a write operation.
- Command writes for block erase or word/byte program are only executed when VPP = VPPH1 or VPPH2 .
- To program or erase the boot block, hold RP# at VHH or WP# at VIH. See Section 3.4.
- RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.
3.2.2 INTELLIGENT IDENTIFIERS
Table 5. Intelligent Identifier Table
3.3 Write Operations
3.3.1 COMMAND USER INTERFACE (CUI)
3.3.1.1 Command Function Description
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Table 6. Command Codes and Descriptions
00 Invalid/
these codes for future functions.
40 Program
when OE# is enabled. To read the array, issue a Read Array command.
10 Alternate
20 Erase
this can not cancel that operation in progress. address and data, and begin erasing the block indicated on the address pins. Suspend commands and will output status register data when OE# is toggled low. Status register data is updated by toggling either OE# or CE# low.
70 Read Status
outputs status register data, regardless of the address presented to the device. The device automatically enters this mode after program or erase has completed. This is one of the two commands that is executable while the WSM is operating.
Table 6. Command Codes and Descriptions (Continued)
50 Clear Status
90 Intelligent
A0 = 1 for device, all other address inputs are ignored). See Section 3.2.2. Table 7. Command Bus Definitions
- Bus operations are defined in Tables 3 and 4.
- IA = Identifier Address: A0 = 0 for manufacturer code, A0 = 1 for device code.
- SRD = Data read from status register.
- IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and
- BA = Address within the block being erased.
- PA = Address to be programmed. PD = Data to be programmed at location PA.
- Either 40H or 10H commands is valid.
- When writing commands to the device, the upper data bus [DQ
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Table 8. Status Register Bit Definition before checking Program or Erase Status bits. still unable to verify successful block erasure. but failed to program a byte or word. be masked out when polling the status register.
3.3.2 STATUS REGISTER
DQ 15/A–1 retains the low order address function. status register contents change while being read. completion of a program or erase operation. successful in performing the desired operation.
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 21SEE NEW DESIGN RECOMMENDATIONS
3.3.2.1 Clearing the Status Register
The WSM sets status bits 3 through 7 to “1,” and clears bits 6 and 7 to “0,” but cannot clear status bits 3 through 5 to “0.” Bits 3 through 5 can only be cleared by the controlling CPU through the use of the Clear Status Register (50H) command, because these bits indicate various error conditions. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. Clear the status register before beginning another command or sequence. Note, again, that a Read Array command must be issued before data can be read from the memory or intelligent identifier.
3.3.3 PROGRAM MODE
Programming is executed using a two-write sequence. The Program Set-Up command is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to: 1. Program the desired bits of the addressed memory word or byte. 2. Verify that the desired bits are sufficiently programmed. Programming of the memory results in specific bits within a byte or word being changed to a “0.” If the user attempts to program “1”s, there will be no change of the memory cell content and no error occurs. The status register indicates programming status: while the program sequence is executing, bit 7 of the status register is a “0.” The status register can be polled by toggling either CE# or OE#. While programming, the only valid command is Read Status Register. When programming is complete, the program status bits should be checked. If the programming operation was unsuccessful, bit 4 of the status register is set to a “1” to indicate a Program Failure. If bit 3 is set to a “1,” then V PP was not within acceptable limits, and the WSM did not execute the programming sequence. The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, reads from the memory array or intelligent identifier cannot be accomplished until the CUI is given the appropriate command.
3.3.4 ERASE MODE
To erase a block, write the Erase Set-Up and Erase Confirm commands to the CUI, along with the addresses identifying the block to be erased. These addresses are latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only one block can be erased at a time. The WSM will execute a sequence of internally timed events to: 1. Program all bits within the block to “0.” 2. Verify that all bits within the block are sufficiently programmed to “0.” 3. Erase all bits within the block to “1.” 4. Verify that all bits within the block are sufficiently erased. While the erase sequence is executing, bit 7 of the status register is a “0.” When the status register indicates that erasure is complete, check the erase status bit to verify that the erase operation was successful. If the erase operation was unsuccessful, bit 5 of the status register will be set to a “1,” indicating an Erase Failure. If V PP was not within acceptable limits after the Erase Confirm command is issued, the WSM will not execute an erase sequence; instead, bit 5 of the status register is set to a “1” to indicate an Erase Failure, and bit 3 is set to a “1” to identify that V PP supply voltage was not within acceptable limits. Clear the status register before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, reads from the memory array, status register, or intelligent identifier cannot be accomplished until the CUI is given the Read Array command.
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3.3.4.1 Suspending and Resuming Erase
operation has been suspended. command or Read Status Register command. reduces active current draw. and the next instruction issued in order to continue.
3.4 Boot Block Locking
3.4.2 WP# = V
3.4.3 RP# = V HH OR WP# = VIH FOR BOOT
3.4.4 UPGRADE NOTE FOR 8-MBIT
density-package combinations have WP# pins. Table 9. Write Protection Truth Table
attempts are allowed by the Write State Machine. where multiple bytes are programmed before full status is checked. Repeat for subsequent word/byte program operations. or after a sequence of word/byte programs. Figure 9. Automated Word/Byte Programming Flowchart
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attempts are allowed by the Write State Machine. cases where multiple blocks are erase before full status is checked. retry or other error recovery. Repeat for subsequent block erasures. Write FFH after the last operation to reset device to read array mode. Figure 10. Automated Block Erase Flowchart
Figure 11. Erase Suspend/Resume Flowchart
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3.5 Power Consumption
3.5.1 ACTIVE POWER
With CE# at a logic-low level and RP# at a logic- high level, the device is placed in the active mode. Refer to the DC Characteristics table for I CC current values.
3.5.2 AUTOMATIC POWER SAVINGS (APS)
Automatic Power Savings (APS) provides low- power operation during active mode. Power Reduction Control (PRC) circuitry allows the device to put itself into a low current state when not being accessed. After data is read from the memory array, PRC logic controls the device’s power consumption by entering the APS mode where typical I CC current is less than 1 mA. The device stays in this static state with outputs valid until a new location is read.
3.5.3 STANDBY POWER
With CE# at a logic-high level (V IH), and the CUI in read mode, the memory is placed in standby mode, which disables much of the device’s circuitry and substantially reduces power consumption. Outputs (DQ 0–DQ 15 or DQ 0–DQ 7) are placed in a high- impedance state independent of the status of the OE# signal. When CE# is at logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed.
3.5.4 DEEP POWER-DOWN MODE
The SmartVoltage boot block family supports a low typical I CC in deep power-down mode, which turns off all circuits to save power. This mode is activated by the RP# pin when it is at a logic-low (GND ± 0.2 V). NOTE Note: BYTE# pin must be at CMOS levels to meet the I CCD specification. During read modes, the RP# pin going low de- selects the memory and places the output drivers in a high impedance state. Recovery from the deep power-down state, requires a minimum access time of t PHQV (see AC Characteristics table). During erase or program modes, RP# low will abort either erase or program operations, but the memory contents are no longer valid as the data has been corrupted by the RP# function. As in the read mode above, all internal circuitry is turned off to achieve the power savings. RP# transitions to V IL, or turning power off to the device will clear the status register.
3.6 Power-Up/Down Operation
The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, V PP or VCC , powers-up first. The CUI is reset to the read mode after power-up, but the system must drop CE# low or present a new address to ensure valid data at the outputs. A system designer must guard against spurious writes when V CC voltages are above VLKO and VPP is active. Since both WE# and CE# must be low for a command write, driving either signal to V IH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RP# is brought to V IH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.
3.6.1 RP# CONNECTED TO SYSTEM
The use of RP# during system reset is important with automated program/erase devices because the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization would not occur because the flash memory may be providing status information instead of array data. Intel’s Flash memories allow proper CPU initialization following a system reset by connecting the RP# pin to the same RESET# signal that resets the system CPU.
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 27SEE NEW DESIGN RECOMMENDATIONS
3.6.2 V CC , VPP AND RP# TRANSITIONS
The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from deep power-down mode, or after V CC transitions above VLKO (lockout voltage), is read array mode. After any word/byte program or block erase operation is complete and even after VPP transitions down to VPPLK , the CUI must be reset to read array mode via the Read Array command if accesses to the flash memory are desired. Please refer to Intel’s application note AP-617 Additional Flash Data Protection Using VPP , RP#, and WP# for a circuit-level description of how to implement the protection discussed in Section 3.6.
3.7 Power Supply Decoupling
Flash memory’s power switching characteristics require careful device decoupling methods. System designers should consider three supply current issues: 1. Standby current levels (I CCS ) 2. Active current levels (ICCR ) 3. Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each V CC and GND, and between its VPP and GND. These high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 3.7.1 V PP TRACE ON PRINTED CIRCUIT BOARDS Designing for in-system programming of the flash memory requires special consideration of the VPP power supply trace by the printed circuit board designer. The V PP pin supplies the flash memory cells current for programming and erasing. One should use similar trace widths and layout considerations given to the V CC power supply trace. Adequate V PP supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots. NOTE: Table headings in the DC and AC characteristics tables (i.e., BV-60, BV-80, BV-120, TBV-80, TBE- 120) refer to the specific products listed below. See Section 5.0 for more information on product naming and line items. Abbreviation Applicable Product Names BV-60 E28F002BV-T60, E28F002BV-B60, PA28F200BV-T60, PA28F200BV-B60, E28F200CV-T60, E28F200CV-B60, E28F200BV-T60, E28F200BV-B60 BV-80 E28F002BV-T80, E28F002BV-B80, PA28F200BV-T80, PA28F200BV-B80, E28F200CV-T80, E28F200CV-B80, E28F200BV-T80, E28F200BV-B80 BV-120 E28F002BV-T120, E28F002BV-B120, PA28F200BV-T120, PA28F200BV-B120 TBV-80 TE28F002BV-T80, TE28F002BV-B80, TB28F200BV-T80, TB28F200BV-B80, TE28F200CV-T80, TE28F200CV-B80, TE28F200BV-T80, TE28F200BV-B80
28 SEE NEW DESIGN RECOMMENDATIONS
4.0 ELECTRICAL SPECIFICATIONS
4.1 Absolute Maximum Ratings*
- Operating temperature is for commercial product
defined by this specification.
- Minimum DC voltage is –0.5 V on input/output pins.
VCC + 2.0 V for periods <20 ns.
- Maximum DC voltage on VPP may overshoot to +14.0 V
may overshoot to 13.5 V for periods <20 ns.
- Output shorted for no more than one second. No more
than one output shorted at a time.
4.2 Commercial Operating Conditions
Table 10. Commercial Temperature and VCC Operating Conditions
- 10% V CC specifications apply to the 60 ns, 80 ns and 120 ns product versions in their standard test configuration.
- 5% V CC specifications apply to the 60 ns version in its high-speed test configuration.
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 29SEE NEW DESIGN RECOMMENDATIONS
4.2.1 APPLYING V CC VOLTAGES
When applying VCC voltage to the device, a delay may be required before initiating device operation, depending on the V CC ramp rate. If VCC ramps slower than 1V/100 µs (0.01 V/µs) then no delay is required. If VCC ramps faster than 1V/100 µs (0.01 V/µs), then a delay of 2 µs is required before initiating device operation. RP# = GND is recommended during power-up to protect against spurious write signals when V CC is between VLKO and VCCMIN . VCC Ramp Rate Required Timing ≤ 1V/100 µs No delay required. > 1V/100 µs A delay time of 2 µs is required before any device operation is initiated, including read operations, command writes, program operations, and erase operations. This delay is measured beginning from the time VCC reaches VCCMIN (3.0 V for 3.3 ± 0.3 V operation; and 4.5 V for 5 V operation). NOTES: 1. These requirements must be strictly followed to guarantee all other read and write specifications. 2. To switch between 3.3 V and 5 V operation, the system should first transition V CC from the existing voltage range to GND, and then to the new voltage. Any time the VCC supply drops below VCCMIN , the chip may be reset, aborting any operations pending or in progress. 3. These guidelines must be followed for any VCC transition from GND.
4.3 Capacitance
TA = 25 °C, f = 1 MHz Symbol Parameter Note Typ Max Unit Conditions C IN Input Capacitance 1 6 8 pF V IN = 0 V C OUT Output Capacitance 1, 2 10 12 pF V OUT = 0 V NOTES: 1. Sampled, not 100% tested. 2. For the 28F002B, address pin A 10 follows the COUT capacitance numbers.
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4.4 DC Characteristics—Commercial
Sym Parameter V CC 3.3 ± 0.3 V 5 V ± 10% Unit Test Conditions Note Typ Max Typ Max IIL Input Load Current 1 ± 1.0 ± 1.0 µA VCC = VCC Max VIN = VCC or GND ILO Output Leakage Current 1 ± 10 ± 10 µA VCC = VCC Max VIN = VCC or GND ICCS VCC Standby Current 1,3 0.4 1.5 0.8 2.0 mA VCC = VCC Max CE# = RP# = BYTE# = WP# = VIH 60 110 50 130 µA VCC = VCC Max CE# = RP# = VCC ± 0.2 V ICCD VCC Deep Power-Down Current 1 0.2 8 0.2 8 µA VCC = VCC Max VIN = VCC or GND RP# = GND ± 0.2 V ICCR VCC Read Current for Word or Byte 1,5,6 15 30 50 60 mA CMOS INPUTS VCC = VCC Max CE# = GND, OE# = VCC f = 10 MHz (5 V), 5 MHz (3.3 V) IOUT = 0 mA, Inputs = GND ± 0.2 V or VCC ± 0.2 V 15 30 55 65 mA TTL INPUTS VCC = VCC Max CE# = VIL, OE# = VIH f = 10 MHz (5 V), 5 MHz (3.3 V) IOUT = 0 mA, Inputs = VIL or VIH ICCW VCC Program Current for Word or Byte 1,4 13 30 30 50 mA VPP = VPPH 1 (at 5 V) Program in Progress 10 25 30 45 mA VPP = VPPH 2 (at 12 V) Program in Progress ICCE VCC Erase Current 1,4 13 30 18 35 mA VPP = VPPH 1 (at 5 V) Block Erase in Progress 10 25 18 30 mA VPP = VPPH 2 (at 12 V) Block Erase in Progress
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 31SEE NEW DESIGN RECOMMENDATIONS
4.4 DC Characteristics—Commercial (Continued)
Sym Parameter V CC 3.3 ± 0.3 V 5 V ± 10% Unit Test Conditions Note Typ Max Typ Max ICCES VCC Erase Suspend Current 1,2 3 8.0 5 10 mA CE# = VIH Block Erase Suspend IPPS VPP Standby Current 1 ± 0.5 ± 15 ± 0.5 ± 10 µA V PP < VPPH 2 IPPD VPP Deep Power-Down Current IPPR VPP Read Current 1 50 200 30 200 µA V PP ≥ VPPH 2 IPPW VPP Program Current for Word or Byte 1,4 13 30 13 25 mA VPP = VPPH 1 (at 5 V) Program in Progress 82 582 0 VPP = VPPH 2 (at 12 V) Program in Progress IPPE VPP Erase Current 1,4 13 30 10 20 mA VPP = VPPH 1 (at 5 V) Block Erase in Progress 82 551 5 VPP = VPPH 2 (at 12 V) Block Erase in Progress IPPES VPP Erase Suspend Current 1 50 200 30 200 µA VPP = VPPH Block Erase Suspend in Progress IRP# RP# Boot Block Unlock Current 1,4 500 500 µA RP# = V HH IID A9 Intelligent Identifier Current 1,4 500 500 µA A 9 = VID
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Sym Parameter V CC 3.3 ± 0.3 V 5 V ± 10% Unit Test Conditions Note Min Max Min Max VID A9 Intelligent Identifier Voltage 11.4 12.6 11.4 12.6 V VIL Input Low Voltage –0.5 0.8 –0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.5V
2.0 VCC +
0.5V V VOL Output Low Voltage 0.45 0.45 V VCC = VCC Min IOL = 5.8 mA VOH 1 Output High Voltage (TTL) 2.4 2.4 V VCC = VCC Min IOH = –2.5 mA VOH 2 Output High Voltage (CMOS) 0.85 × VCC 0.85 × VCC V VCC = VCC Min IOH = –2.5 mA VCC – 0.4V VCC – 0.4V V VCC = VCC Min IOH = –100 µA VPPLK VPP Lock-Out Voltage 3 0.0 1.5 0.0 1.5 V Total Write Protect VPPH 1V PP (Prog/Erase Operations) 4.5 5.5 4.5 5.5 V V PP at 5 V VPPH 2V PP (Prog/Erase Operations) 11.4 12.6 11.4 12.6 V V PP at 12 V VLKO VCC Erase/Prog Lock Voltage 8 2.0 2.0 V VHH RP# Unlock Voltage 11.4 12.6 11.4 12.6 V Boot Block Unlock NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, T = +25 °C. These currents are valid for all product versions (packages and speeds). 2. ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR . 3. Block erases and word/byte programs are inhibited when VPP = VPPLK , and not guaranteed in the range between VPPH 1 and VPPLK . 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces I CCR to less than 1 mA typical, in static operation. 7. For the 28F002B, address pin A10 follows the COUT capacitance numbers. 8. For all BV/CV parts, VLKO = 2.0 V for both 3.3 V and 5 V operations.
Input rise and fall times (10% to 90%) <10 ns. Figure 12. 3.3 V Inputs and Measurement Points and VIL (0.8 VTTL) . Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns. Figure 13. 5 V Inputs and Measurement Points NOTE: See table for component values. Figure 14. Test Configuration
3.3 V Standard Test 50 990 770
5 V Standard Test 100 580 390
5 V High-Speed Test 30 580 390
NOTE: CL includes jig capacitance.
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4.5 AC Characteristics—Commercial
Sym Parameter V CC 3.3 ± 0.3 V(5) 5 V ± 5%(6) 5 V ± 10%(7) Unit Load 50 pF 30 pF 100 pF Note Min Max Min Max Min Max tAVAV Read Cycle Time 110 60 70 ns tAVQV Address to Output Delay 110 60 70 ns tELQV CE# to Output Delay 2 110 60 70 ns tPHQV RP# to Output Delay 0.8 0.45 0.45 µs tGLQV OE# to Output Delay 2 65 30 35 ns tELQX CE# to Output in Low Z 3 0 0 0 ns tEHQZ CE# to Output in High Z 3 45 20 20 ns tGLQX OE# to Output in Low Z 3 0 0 0 ns tGHQZ OE# to Output in High Z 3 45 20 20 ns tOH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 3 000 n s tELFL tELFH CE# Low to BYTE# High or Low 3 000 n s tAVFL Address to BYTE# High or Low 3 555 n s tFLQV tFHQV BYTE# to Output Delay 3,4 110 60 70 ns tFLQZ BYTE# Low to Output in High Z 34 52 02 5 n s tPLPH Reset Pulse Width Low 8 150 60 60 ns tPLQZ RP# Low to Output High-Z 150 60 60 ns
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 35SEE NEW DESIGN RECOMMENDATIONS
4.5 AC Characteristics—Commercial (Continued)
Sym Parameter V CC 3.3 ± 0.3V(5) 5V ± 10%(7) 3.3 ± 0.3V(5) 5V ± 10%(7) Unit Load 50 pF 100 pF 50 pF 100 pF Notes Min Max Min Max Min Max Min Max tAVAV Read Cycle Time 150 80 180 120 ns tAVQV Address to Output Delay 150 80 180 120 ns tELQV CE# to Output Delay 2 150 80 180 120 ns tPHQV RP# to Output Delay 0.8 0.45 0.8 0.45 µs tGLQV OE# to Output Delay 2 90 40 90 40 ns tELQX CE# to Output in Low Z 3 0 0 0 0 ns tEHQZ CE# to Output in High Z 3 45 20 45 25 ns tGLQX OE# to Output in Low Z 3 0 0 0 0 ns tGHQZ OE# to Output in High Z 3 45 20 45 20 ns tOH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 30 0 0 0 n s tELFL tELFH CE# Low to BYTE# High or Low 30 0 0 0 n s tAVFL Address to BYTE# High or Low 35 5 5 5 n s tFLQV tFHQV BYTE# to Output Delay 3,4 150 80 180 120 ns tFLQZ BYTE# Low to Output in High Z 3 6 03 06 03 0 n s tPLPH Reset Pulse Width Low 8 150 60 150 60 ns tPLQZ RP# Low to Output High-Z 150 60 150 60 ns NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE# may be delayed up to t CE –tOE after the falling edge of CE# without impact on tCE . 3. Sampled, but not 100% tested. 4. t FLQV , BYTE# switching low to valid output delay will be equal to tAVQV , measured from the time DQ15/A–1 becomes valid. 5. See Test Configuration (Figure 14), 3.3 V Standard Test component values. 6. See Test Configuration (Figure 14), 5 V High-Speed Test component values. 7. See Test Configuration (Figure 14), 5 V Standard Test component values. 8. The specification tPLPH is the minimum time that RP# must be held low in order to product a valid reset of the device.
36 SEE NEW DESIGN RECOMMENDATIONS
Figure 15. AC Waveforms for Read Operations Figure 16. BYTE# Timing Diagram for Read Operations
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 37SEE NEW DESIGN RECOMMENDATIONS
4.6 AC Characteristics—WE#-Controlled Write Operations(1)—Commercial
Sym Parameter V CC 3.3 ± 0.3 V(9) 5 V ± 5%(10) 5 V ± 10%(10) Unit Load 50 pF 30 pF 100 pF Note Min Max Min Max Min Max tAVAV Write Cycle Time 110 60 70 ns tPHWL RP# Setup to WE# Going Low 0.8 0.45 0.45 µs tELWL CE# Setup to WE# Going Low 0 0 0 ns tPHHWH Boot Block Lock Setup to WE# Going High 6,8 200 100 100 ns tVPWH VPP Setup to WE# Going High 5,8 200 100 100 ns tAVWH Address Setup to WE# Going High 3 9 05 05 0 n s tDVWH Data Setup to WE# Going High 4 90 50 50 ns tWLWH WE# Pulse Width 90 50 50 ns tWHDX Data Hold Time from WE# High 4 0 0 0 ns tWHAX Address Hold Time from WE# High 3 000 n s tWHEH CE# Hold Time from WE# High 0 0 0 ns tWHWL WE# Pulse Width High 20 10 20 ns tWHQV1 Duration of Word/Byte Program 2,5 6 6 6 µs tWHQV2 Duration of Erase (Boot) 2,5,6 0.3 0.3 0.3 s tWHQV3 Duration of Erase (Parameter) 2,5 0.3 0.3 0.3 s tWHQV4 Duration of Erase (Main) 2,5 0.6 0.6 0.6 s tQVVL VPP Hold from Valid SRD 5,8 0 0 0 ns tQVPH RP# VHH Hold from Valid SRD 6,8 0 0 0 ns tPHBR Boot-Block Lock Delay 7,8 200 100 100 ns
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(Continued) Prod BV-80 BV-120 Sym Parameter V CC 3.3 ±0.3V(9) 5V±10% (11) 3.3 ± 0.3V(9) 5V±10% (11) Unit Load 50 pF 100 pF 50 pF 100 pF Notes Min Max Min Max Min Max Min Max tAVAV Write Cycle Time 150 80 180 120 ns tPHWL RP# Setup to WE# Going Low 0.8 0.45 0.8 0.45 µs tELWL CE# Setup to WE# Going Low 0000 n s tPHHWH Boot Block Lock Setup to WE# Going High 6,8 200 100 200 100 ns tVPWH VPP Setup to WE# Going High 5,8 200 100 200 100 ns tAVWH Address Setup to WE# Going High 3 120 50 150 50 ns tDVWH Data Setup to WE# Going High 4 120 50 150 50 ns tWLWH WE# Pulse Width 120 50 150 50 ns tWHDX Data Hold Time from WE# High 40 0 0 0 n s tWHAX Address Hold Time from WE# High 30 0 0 0 n s tWHEH CE# Hold Time from WE# High 0000 n s tWHWL WE# Pulse Width High 30 30 30 30 ns tWHQV1 Word/Byte Program Time 2,5 6 6 6 6 µs tWHQV2 Erase Duration (Boot) 2,5,6 0.3 0.3 0.3 0.3 s tWHQV3 Erase Duration (Param) 2,5 0.3 0.3 0.3 0.3 s tWHQV4 Erase Duration (Main) 2,5 0.6 0.6 0.6 0.6 s tQVVL VPP Hold from Valid SRD 5,8 0 0 0 0 ns tQVPH RP# VHH Hold from Valid SRD 6,8 0 0 0 0 ns tPHBR Boot-Block Lock Delay 7,8 200 100 200 100 ns
- Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC
Characteristics during read mode.
- The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.
- Refer to command definition table for valid AIN. (Table 7)
- Refer to command definition table for valid DIN. (Table 7)
- Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
- For boot block program/erase, RP# should be held at V
- Time tPHBR is required for successful locking of the boot block.
- Sampled, but not 100% tested.
Test Configuration (Figure 14), 3.3 V Standard Test component values.
- See Test Configuration (Figure 14), 5 V High-Speed Test component values.
- See Test Configuration (Figure 14), 5 V Standard Test component values.
- VCC Power-Up and Standby.
- Write program or Erase Set-Up Command.
- Write Valid Address and Data (Program) or Erase Confirm Command.
- Automated Program or Erase Delay.
- Read Status Register Data.
- Write Read Array Command.
Figure 17. AC Waveforms for Write Operations (WE#–Controlled Writes)
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4.7 AC Characteristics—CE#-Controlled Write Operations(1, 12)—Commercial
Sym Parameter V CC 3.3 ± 0.3 V(9) 5 V ± 5%(10) 5 V ± 10%(11) Unit Load 50 pF 30 pF 100 pF Note Min Max Min Max Min Max tAVAV Write Cycle Time 110 60 70 ns tPHEL RP# High Recovery to CE# Going Low 0.8 0.45 0.45 µs tWLEL WE# Setup to CE# Going Low 0 0 0 ns tPHHEH Boot Block Lock Setup to CE# Going High 6,8 200 100 100 ns tVPEH VPP Setup to CE# Going High 5,8 200 100 100 ns tAVEH Address Setup to CE# Going High 3 9 05 05 0 n s tDVEH Data Setup to CE# Going High 4 90 50 50 ns tELEH CE# Pulse Width 90 50 50 ns tEHDX Data Hold Time from CE# High 4 0 0 0 ns tEHAX Address Hold Time from CE# High 3 000 n s tEHWH WE # Hold Time from CE# High 0 0 0 ns tEHEL CE# Pulse Width High 20 10 20 ns tEHQV1 Duration of Word/Byte Programming Operation 2,5 6 6 6 µs tEHQV2 Erase Duration (Boot) 2,5,6 0.3 0.3 0.3 s tEHQV3 Erase Duration (Param) 2,5 0.3 0.3 0.3 s tEHQV4 Erase Duration(Main) 2,5 0.6 0.6 0.6 s tQVVL VPP Hold from Valid SRD 5,8 0 0 0 ns tQVPH RP# VHH Hold from Valid SRD 6,8 0 0 0 ns tPHBR Boot-Block Lock Delay 7,8 200 100 100 ns
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 41SEE NEW DESIGN RECOMMENDATIONS (Continued) Prod BV-80 BV-120 Sym Parameter V CC 3.3 ± 0.3V(9) 5V±10% (11) 3.3 ± 0.3V(9) 5V±10% (11) Unit Load 50 pF 100 pF 50 pF 100 pF Notes Min Max Min Max Min Max Min Max tAVAV Write Cycle Time 150 80 180 120 ns tPHEL RP# High Recovery to CE# Going Low 0.8 0.45 0.8 0.45 µs tWLEL WE# Setup to CE# Going Low 0000 n s tPHHEH Boot Block Lock Setup to CE# Going High 6,8 200 100 200 100 ns tVPEH VPP Setup to CE# Going High 5,8 200 100 200 100 ns tAVEH Address Setup to CE# Going High 3 120 50 150 50 ns tDVEH Data Setup to CE# Going High 4 120 50 150 50 ns tELEH CE# Pulse Width 120 50 150 50 ns tEHDX Data Hold Time from CE# High 40 0 0 0 n s tEHAX Address Hold Time from CE# High 30 0 0 0 n s tEHWH WE # Hold Time from CE# High 0000 n s tEHEL CE# Pulse Width High 30 30 30 30 ns tEHQV1 Duration of Word/Byte Programming Operation 2 , 5 6666 µs tEHQV2 Erase Duration (Boot) 2,5,6 0.3 0.3 0.3 0.3 s tEHQV3 Erase Duration (Param) 2,5 0.3 0.3 0.3 0.3 s tEHQV4 Erase Duration(Main) 2,5 0.6 0.6 0.6 0.6 s tQVVL VPP Hold from Valid SRD 5,8 0 0 0 0 ns tQVPH RP# VHH Hold from Valid SRD 6,8 0 0 0 0 ns tPHBR Boot-Block Lock Delay 7,8 200 100 200 100 ns
42 SEE NEW DESIGN RECOMMENDATIONS
See AC Characteristics—WE#-Controlled Write Operations for notes 1 through 11.
- Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in sy stems where
be measured relative to the CE# waveform.
- VCC Power-Up and Standby.
- Write program or Erase Set-Up Command.
- Write Valid Address and Data (Program) or Erase Confirm Command.
- Automated Program or Erase Delay.
- Read Status Register Data.
- Write Read Array Command.
Figure 18. Alternate AC Waveforms for Write Operations (CE#–Controlled Writes)
4.8 Erase and Program Timings —Commercial
- All numbers are sampled, not 100% tested.
- Max erase times are specified under worst case conditions. The max erase times are tested at the same value
CC and VPP . See Note 3 for typical conditions.
- Typical conditions are +25 °C with VCC and VPP at the center of the specified voltage range. Production programming using
VCC = 5.0 V, VPP = 12.0 V typically results in a 60% reduction in programming time.
- Contact your Intel representative for information regarding maximum byte/ word program specifications.
4.9 Extended Operating Conditions
Table 11. Extended Temperature and VCC Operating Conditions
- AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
- 10% V CC specifications apply to 80 ns and 120 ns versions in their standard test configuration.
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4.9.1 APPLYING V CC VOLTAGES
When applying VCC voltage to the device, a delay may be required before initiating device operation, depending on the V CC ramp rate. If VCC ramps slower than 1V/100 µs (0.01 V/µs) then no delay is required. If VCC ramps faster than 1V/100 µs (0.01 V/µs), then a delay of 2 µs is required before initiating device operation. RP# = GND is recommended during power-up to protect against spurious write signals when V CC is between VLKO and VCCMIN . VCC Ramp Rate Required Timing ≤ 1V/100 µs No delay required. > 1V/100 µs A delay time of 2 µs is required before any device operation is initiated, including read operations, command writes, program operations, and erase operations. This delay is measured beginning from the time VCC reaches VCCMIN ( 3.0 V for 3.3 ± 0.3 V operation; and 4.5 V for 5 V operation). NOTES: 1. These requirements must be strictly followed to guarantee all other read and write sp ecifications. 2. To switch between 3.3 V and 5 V operation, the system should first transition V CC from the existing voltage range to GND, and then to the new voltage. Any time the VCC supply drops below VCCMIN , the chip may be reset, aborting any operations pending or in progress. 3. These guidelines must be followed for any VCC transition from GND.
4.10 Capacitance
TA = 25 °C, f = 1 MHz Symbol Parameter Note Typ Max Unit Conditions C IN Input Capacitance 1 6 8 pF V IN = 0V C OUT Output Capacitance 1 10 12 pF V OUT = 0V NOTE: 1. Sampled, not 100% tested.
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 45SEE NEW DESIGN RECOMMENDATIONS
4.11 DC Characteristics—Extended Temperature Operations
Sym Parameter V CC 3.3 ± 0.3 V 5 V ± 10% Unit Test Conditions Notes Typ Max Typ Max IIL Input Load Current 1 ± 1.0 ± 1.0 µA VCC = VCC Max VIN = VCC or GND ILO Output Leakage Current 1 ± 10 ± 10 µA VCC = VCC Max VIN = VCC or GND ICCS VCC Standby Current 1,3 60 110 70 150 µA CMOS Levels VCC = VCC Max CE# = RP# = WP# = VCC ± 0.2 V 0.4 1.5 0.8 2.5 mA TTL Levels VCC = VCC Max CE# = RP# = BYTE# = VIH ICCD VCC Deep Power-Down Current 1 0.2 8 0.2 8 µA VCC = VCC Max VIN = VCC or GND RP# = GND ± 0.2 V ICCR VCC Read Current for Word or Byte 1,5,6 15 30 50 65 mA CMOS INPUTS VCC = VCC Max CE = VIL f = 10 MHz (5 V) 5 MHz (3.3 V) IOUT = 0 mA Inputs = GND ± 0.2 V or VCC ± 0.2 V 15 30 55 70 mA TTL INPUTS VCC = VCC Max CE# = VIL f = 10 MHz (5 V) 5 MHz (3.3 V) IOUT = 0 mA Inputs = VIL or VIH
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46 SEE NEW DESIGN RECOMMENDATIONS
4.11 DC Characteristics—Extended Temperature Operations (Continued)
Sym Parameter V CC 3.3 ± 0.3 V 5 V ± 10% Unit Test Conditions Note Typ Max Typ Max ICCW VCC Program Current for Word or Byte 1,4 13 30 30 50 mA VPP = VPPH 1 (at 5 V) Program in Progress 10 25 30 45 mA VPP = VPPH 2 (at 12 V) Program in Progress ICCE VCC Erase Current 1,4 13 30 22 45 mA VPP = VPPH 1 (at 5 V) Block Erase in Progress 10 25 18 40 mA VPP = VPPH 2 (at 12 V) Block Erase in Progress ICCES VCC Erase Suspend Current 1,2 3 8.0 5 12.0 mA CE# = VIH Block Erase Suspend VPP = VPPH 1 (at 5 V) IPPS VPP Standby Current 1 ± 5 ± 15 ± 5 ± 15 µA V PP < VPPH 2 IPPD VPP Deep Power-Down Current 1 0.2 10 0.2 10 µA RP# = GND ± 0.2 V IPPR VPP Read Current 1 50 200 50 200 µA V PP ≥ VPPH 2 IPPW VPP Program Current for Word or Byte 1,4 13 30 13 30 mA VPP = VPPH 1 (at 5 V) 8 25 8 25 mA VPP = VPPH 2 (at 12 V) IPPE VPP Erase Current 1,4 13 30 15 25 mA VPP = VPPH 1 (at 5 V) Block Erase in Progress 82 5 1 0 2 0 m A VPP = VPPH 2 (at 12 V) Block Erase in Progress IPPES VPP Erase Suspend Current 1 50 200 50 200 µA VPP = VPPH Block Erase Suspend in Progress IRP# RP# Boot Block Unlock Current 1,4 500 500 µA RP# = VHH VPP = 12 V IID A9 Intelligent Identifier Current 1,4 500 500 µA A 9 = VID
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 47SEE NEW DESIGN RECOMMENDATIONS Sym Parameter V CC 3.3 ± 0.3 V 5 V ± 10% Unit Test Conditions Notes Typ Max Typ Max VID A9 Intelligent Identifier Voltage 11.4 12.6 11.4 12.6 V VIL Input Low Voltage –0.5 0.8 –0.5 0.8 V VIH Input High Voltage 2.0 VCC 0.5V
2.0 VCC
0.5V V VOL Output Low Voltage 0.45 0.45 V VCC = VCC Min IOL = 5.8 mA (5 V) 2 mA (3.3 V) VPP = 12V VOH 1 Output High Voltage (TTL) 2.4 2.4 V VCC = VCC Min IOH = –2.5 mA VOH 2 Output High Voltage (CMOS) 0.85 VCC 0.85 VCC V VCC = VCC Min IOH = –2.5 mA VCC – 0.4V VCC – 0.4V V VCC = VCC Min IOH = –100 µA VPPLK VPP Lock-Out Voltage 3 0.0 1.5 0.0 1.5 V Complete Write Protection VPPH 1V PP during Program/Erase 4.5 5.5 4.5 5.5 V V PP at 5 V VPPH 2 Operations 11.4 12.6 11.4 12.6 V V PP at 12 V VLKO VCC Program/Erase Lock Voltage 8 2.0 2.0 V VHH RP# Unlock Voltage 11.4 12.6 11.4 12.6 V VPP = 12 V Boot Block Program/ Erase
48 SEE NEW DESIGN RECOMMENDATIONS
- All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, T = +25 °C. These currents are valid for all
product versions (packages and speeds).
- ICCES is specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR .
- Block erases and word/byte programs inhibited when VPP = VPPLK , and not guaranteed in the range between VPPH 1 and
- Sampled, not 100% tested.
- Automatic Power Savings (APS) reduces I
CCR to less than 1 mA typical, in static operation.
- For the 28F002B address pin A10 follows the COUT capacitance numbers.
Input rise and fall times (10% to 90%) <10 ns. Figure 19. 3.3 V Input Range and Measurement Points and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns. Figure 20. 5 V Input Range and Measurement Points NOTE: See table for component values. Figure 21. Test Configuration NOTE: CL includes jig capacitance.
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 49SEE NEW DESIGN RECOMMENDATIONS
4.12 AC Characteristics—Read Only Operations(1)—Extended Temperature
Symbol Parameter V CC 3.3 ± 0.3 V(5) 5 V ± 10%(6) Unit Load 50 pF 100 pF Notes Min Max Min Max tAVAV Read Cycle Time 110 80 ns tAVQV Address to Output Delay 110 80 ns tELQV CE# to Output Delay 2 110 80 ns tPHQV RP# to Output Delay 0.8 0.45 µs tGLQV OE# to Output Delay 2 65 40 ns tELQX CE# to Output in Low Z 3 0 0 ns tEHQZ CE# to Output in High Z 3 45 25 ns tGLQX OE# to Output in Low Z 3 0 0 ns tGHQZ OE# to Output in High Z 3 45 25 ns tOH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 30 0 n s tELFL tELFH CE# Low to BYTE# High or Low 3 00 ns tAVFL Address to BYTE# High or Low 3 5 5 ns tFLQV tFHQV BYTE# to Output Delay 3,4 110 80 ns tFLQZ BYTE# Low to Output in High Z 3 45 30 ns tPLPH Reset Pulse Width 7 150 60 ns tPLQZ RP# Low to Output High-Z 150 60 ns NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE# may be delayed up to t CE –tOE after the falling edge of CE# without impact on tCE . 3. Sampled, but not 100% tested. 4. t FLQV , BYTE# switching low to valid output delay will be equal to tAVQV , measured from the time DQ15/A–1 becomes valid. 6. See Test Configuration (Figure 21), 5 V Standard Test component values. 7. The specification tPLPH is the minimum time that RP# must be held low in order to product a valid reset of the device.
2-MBIT SmartVoltage BOOT BLOCK FAMILY E
50 SEE NEW DESIGN RECOMMENDATIONS
4.13 AC Characteristics—WE#-Controlled Write Operations(1)—
Sym Parameter V CC 3.3 ±0.3 V(9) 5 V±10% (10) Unit Load 50 pF 100 pF Notes Min Max Min Max tAVAV Write Cycle Time 110 80 ns tPHWL RP# High Recovery to WE# Going Low 0.8 0.45 µs tELWL CE# Setup to WE# Going Low 0 0 ns tPHHWH Boot Block Lock Setup to WE# Going High 6,8 200 100 ns tVPWH VPP Setup to WE# Going High 5,8 200 100 ns tAVWH Address Setup to WE# Going High 3 90 60 ns tDVWH Data Setup to WE# Going High 4 70 60 ns tWLWH WE# Pulse Width 90 60 ns tWHDX Data Hold Time from WE# High 4 0 0 ns tWHAX Address Hold Time from WE# High 3 0 0 ns tWHEH CE# Hold Time from WE# High 0 0 ns tWHWL WE# Pulse Width High 20 20 ns tWHQV1 Word/Byte Program Time 2,5,8 6 6 µs tWHQV2 Erase Duration (Boot) 2,5,6,8 0.3 0.3 s tWHQV3 Erase Duration (Param) 2,5,8 0.3 0.3 s tWHQV4 Erase Duration (Main) 2,5,8 0.6 0.6 s tQVVL VPP Hold from Valid SRD 5,8 0 0 ns tQVPH RP# VHH Hold from Valid SRD 6,8 0 0 ns tPHBR Boot-Block Lock Delay 7,8 200 100 ns
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 51SEE NEW DESIGN RECOMMENDATIONS NOTES: 1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC Characteristics during read mode. 2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations. 3. Refer to command definition table for valid AIN. (Table 7) 4. Refer to command definition table for valid DIN. (Table 7) 5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1) 6. For boot block program/erase, RP# should be held at V HH or WP# should be held at VIH until operation completes successfully. 7. Time tPHBR is required for successful locking of the boot block. 8. Sampled, but not 100% tested. 9. See Test Configuration (Figure 21), 3.6 V and 3.3 ± 0.3 V Standard Test component values. 10. See Test Configuration (Figure 21), 5 V Standard Test component values.
2-MBIT SmartVoltage BOOT BLOCK FAMILY E
52 SEE NEW DESIGN RECOMMENDATIONS
4.14 AC Characteristics—CE#-Controlled Write Operations(1, 11)—
Sym Parameter V CC 3.3 ±0.3 V(9) 5 V±10% (10) Unit Load 50 pF 100 pF Notes Min Max Min Max tAVAV Write Cycle Time 110 80 ns tPHEL RP# High Recovery to CE# Going Low 0.8 0.45 µs tWLEL WE# Setup to CE# Going Low 0 0 ns tPHHEH Boot Block Lock Setup to CE# Going High 6,8 200 100 ns tVPEH VPP Setup to CE# Going High 5,8 200 100 ns tAVEH Address Setup to CE# Going High 90 60 ns tDVEH Data Setup to CE# Going High 3 70 60 ns tELEH CE# Pulse Width 4 90 60 ns tEHDX Data Hold Time from CE# High 0 0 ns tEHAX Address Hold Time from CE# High 4 0 0 ns tEHWH WE# Hold Time from CE# High 3 0 0 ns tEHEL CE# Pulse Width High 20 20 ns tEHQV1 Word/Byte Program Time 2,5 6 6 µs tEHQV2 Erase Duration (Boot) 2,5,6 0.3 0.3 s tEHQV3 Erase Duration (Param) 2,5 0.3 0.3 s tEHQV4 Erase Duration (Main) 2,5 0.6 0.6 s tQVVL VPP Hold from Valid SRD 5,8 0 0 ns tQVPH RP# VHH Hold from Valid SRD 6,8 0 0 ns tPHBR Boot-Block Lock Delay 7,8 200 100 ns NOTES: See AC Characteristics—WE#-Controlled Write Operations for notes 1 through 10. 11. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be measured relative to the CE# waveform.
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 53SEE NEW DESIGN RECOMMENDATIONS
4.15 Erase and Program Timings—Extended Temperature
TA = –40 °C to +85 °C VPP 5 V ± 10% 12 V ± 5% VCC 3.3 ± 0.3 V 5 V ± 10% 3.3 ± 0.3 V 5 V ± 10% Parameter Typ Max Typ Max Typ Max Typ Max Unit Boot/Parameter Block Erase Time 0.84 7 0.8 7 0.44 7 0.34 7 s Main Block Erase Time 2.4 14 1.9 14 1.3 14 1.1 14 s Main Block Program Time (Byte) 1.7 1.4 1.6 1.2 s Main Block Program Time (Word) 1.1 0.9 0.8 0.6 s Byte Program Time 10 10 8 8 µs Word Program Time 13 13 8 8 µs NOTES: 1. All numbers are sampled, not 100% tested. 2. Max erase times are specified under worst case conditions. The max erase times are tested at the same value independent of V CC and VPP . See Note 3 for typical conditions. 3. Typical conditions are +25 °C with VCC and VPP at the center of the specified voltage range. Production programming using VCC = 5.0 V, VPP = 12.0 V typically results in a 60% reduction in programming time. 4. Contact your Intel representative for information regarding maximum byte/word program specifications.
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54 SEE NEW DESIGN RECOMMENDATIONS
5.0 ORDERING INFORMATION
for all Intel Flash products Density / Organization X00 = x8/x16 Selectable (X = 2, 4, 8) Access Speed(ns) BV/CV: VCC = 5V Architecture B = Boot Block C = Compact 48-Lead TSO Boot Block Operating Temperature T = Extended Temp Blank = Commercial Temp Package E = TSOP PA = 44-Lead PSOP TB = Ext. Temp 44-Lead PSOP E28F2 00 CV - T 08 T =Top Boot B =Bottom Boot T Voltage Options (VPP/VCC) V = (5 or 12 / 3.3 or 5) 0530_23 VALID COMBINATIONS: 40-Lead TSOP 44-Lead PSOP 48-Lead TSOP 56-Lead TSOP Commercial E28F002BVT60 PA28F200BVT60 E28F200CVT60 E28F200BVT60 E28F002BVB60 PA28F200BVB60 E28F200CVB60 E28F200BVB60 E28F002BVT80 PA28F200BVT80 E28F200CVT80 E28F200BVT80 E28F002BVB80 PA28F200BVB80 E28F200CVB80 E28F200BVB80 E28F002BVT120 PA28F200BVT120 E28F002BVB120 PA28F200BVB120 Extended TE28F002BVT80 TB28F200BVT80 TE28F200CVT80 TE28F200BVT80 TE28F002BVB80 TB28F200BVB80 TE28F200CVB80 TE28F200BVB80 Summary of Line Items VCC VPP 40-Ld 44-Ld 48-Ld 56-Ld 0 °C – –40 °C – Name 2.7 V 3.3 V 5 V 5 V 12 V TSOP PSOP TSOP TSOP +70 °C +85 °C
E 2-MBIT SmartVoltage BOOT BLOCK FAMILY 55SEE NEW DESIGN RECOMMENDATIONS
6.0 ADDITIONAL INFORMATION
Related Intel Information(1,2) Order Number Document 290530 4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet 290539 8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290599 Smart 5 Boot Block Flash Memory Family 2, 4, 8 Mbit Datasheet
290580 Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family Datasheet
292200 AP-642 Designing for Upgrade to Smart 3 Advanced Boot Block Flash Memory
292172 AP-617 Additional Flash Data Protection Using VPP , RP#, and WP#
292148 AP-604 Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM
292194 AB-65 Migrating SmartVoltage Boot Block Flash Designs to Smart 5 Flash
297612 28F200BV/CV 28F002BV Specification Update NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentati on. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.