TE28F256J3C INTEL | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1.0 Introduction
  • 1.1 Nomenclature
  • 1.2 Conventions
  • 2.0 Functional Overview
  • 2.1 Block Diagram
  • 2.2 Memory Map
  • 3.0 Package Information
  • 3.2 Easy BGA (J3) Package
  • 4.0 Ballout and Signal Descriptions
  • 4.1 Easy BGA Ballout (32/64/128/256 Mbit)
  • 4.3 VF BGA Ballout (32 and 64 Mbit)
  • 4.4 Signal Descriptions
  • 5.0 Maximum Ratings and Operating Conditions
  • 5.1 Absolute Maximum Ratings
  • 5.2 Operating Conditions
  • 6.0 Electrical Specifications
  • 7.0 AC Characteristics
  • 7.1 Read Operations
  • 7.2 Write Operations
  • 7.3 Block Erase, Program, and Lock-Bit Configuration Performance
  • 7.4 Reset Operation
  • 7.5 AC Test Conditions
  • 7.6 Capacitance
  • 8.0 Power and Reset Specifications
  • 8.1 Power-Up/Down Characteristics
  • 8.2 Power Supply Decoupling
  • 8.3 Reset Characteristics
  • 9.0 Bus Operations
  • 9.1 Bus Operations Overview
  • 9.1.1 Bus Read Operation
  • 9.1.2 Bus Write Operation
  • 9.1.3 Output Disable
  • 9.1.5 Reset/Power-Down

Datasheet sections

  • 4 Datasheet
  • 9.2 Device Commands
  • 10.0 Read Operations
  • 10.1 Read Array
  • 10.1.1 Asynchronous Page Mode Read
  • 10.1.2 Enhanced Configuration Register (ECR)
  • 10.2 Read Identifier Codes
  • 10.2.1 Read Status Register
  • 10.3 Read Query/CFI
  • 11.0 Programming Operations
  • 11.1 Byte/Word Program
  • 11.2 Write to Buffer
  • 11.3 Program Suspend
  • 11.4 Program Resume
  • 12.0 Erase Operations
  • 12.1 Block Erase
  • 12.3 Erase Resume
  • 13.0 Security Modes
  • 13.1 Set Block Lock-Bit
  • 13.2 Clear Block Lock-Bits
  • 13.3 Protection Register Program
  • 13.3.1 Reading the Protection Register
  • 13.3.2 Programming the Protection Register
  • 13.3.3 Locking the Protection Register
  • 13.4 Array Protection
  • 14.0 Special Modes
  • 14.1 Set Read Configuration Register Command
  • 14.2 Status (STS)

Datasheet sections

Datasheet sections

  • 6 Datasheet

Intel StrataFlash® Memory (J3) 256-Mbit (x8/x16) Datasheet Product Features Capitalizing on Intel’s 0.25 and 0.18 micron, two-bit-per-cell technology, the Intel StrataFlash® Memory (J3) device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 256- Mbit (32-Mbyte), 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bit- per-cell storage technology to the flash market segment. Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future devices. Using the same NOR-based ETOX™ technology as Inte l’s one-bit-per-cell products, the J3 device takes advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components are ideal for code and data applications where high density and low cost are required. Examples include networking, telecommunications, digital set top boxes, audio recording, and digital imaging. By applying FlashFile™ memory family pinouts, J3 memory components allow easy design migrations from existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash memory (28F640J5 and 28F320J5) devices. J3 memory components deliver a new generation of forward-compatible software support. By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density upgrades and optimized write capabilities of future Intel StrataFlash® memory devices. Manufactured on Intel® 0.18 micron ETOX™ VII (J3C) and 0.25 micron ETOX™ VI (J3A) process technology, the J3 memory device provides the highest levels of quality and reliability. ■ Performance —110/115/120/150 ns Initial Access Speed —125 ns Initial Access Speed (256 Mbit density only) —25 ns Asynchronous Page mode Reads —30 ns Asynchronous Page mode Reads (256Mbit density only) —32-Byte Write Buffer —6.8 µs per byte effective programming time ■ Software —Program and Erase suspend support —Flash Data Integrator (FDI), Common Flash Interface (CFI) Compatible ■ Security —128-bit Protection Register —64-bit Unique Device Identifier —64-bit User Programmable OTP Cells —Absolute Protection with V PEN = GND —Individual Block Locking —Block Erase/Program Lockout during Power Transitions ■ Architecture —Multi-Level Cell Technology: High Density at Low Cost —High-Density Symmetrical 128-Kbyte Blocks —256 Mbit (256 Blocks) (0.18µm only) —128 Mbit (128 Blocks) — 64 Mbit (64 Blocks) —32 Mbit (32 Blocks) ■ Quality and Reliability —Operating Temperature: -40 °C to +85 °C —100K Minimum Erase Cycles per Block —0.18 µm ETOX™ VII Process (J3C) —0.25 µm ETOX™ VI Process (J3A) ■ Packaging and Voltage —56-Lead TSOP Package —64-Ball Intel ® Easy BGA Package —Lead-free packages available —48-Ball Intel ® VF BGA Package (32 and

64 Mbit) (x16 only)

—V CC = 2.7 V to 3.6 V —V CCQ = 2.7 V to 3.6 V Order Number: 290667-021 March 2005 Notice: This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

2 Datasheet

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY , RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY , OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 3 Volt Intel StrataFlash® Memory may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © 2005, Intel Corporation. All rights reserved. Intel and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others.

256-Mbit J3 (x8/x16) Datasheet 7

1.0 Introduction

This document describes the Intel StrataFlash® Memory (J3) device. It includes a description of device features, operations, and specifications.

1.1 Nomenclature

AMIN: AMIN = A0 for x8 AMIN = A1 for x16 AMAX: 32 Mbit AMAX = A21

64 Mbit AMAX = A22

128 Mbit AMAX = A23

256 Mbit AMAX = A24

Block: A group of flash cells that share common erase circuitry and erase simultaneously Clear: Indicates a logic zero (0) CUI: Command User Interface MLC: Multi-Level Cell OTP: One Time Programmable PLR: Protection Lock Register PR: Protection Register PRD Protection Register Data Program: To write data to the flash array RFU: Reserved for Future Use Set: Indicates a logic one (1) SR: Status Register SRD: Status Register Data VPEN: Refers to a signal or package connection name V PEN: Refers to timing or voltage levels WSM: Write State Machine ECR: Extended Configuration Register XSR: eXtended Status Register

1.2 Conventions

0x: Hexadecimal prefix 0b: Binary prefix k (noun): 1,000 M (noun): 1,000,000 Nibble 4 bits Byte: 8 bits Word: 16 bits Kword: 1,024 words Kb: 1,024 bits KB: 1,024 bytes Mb: 1,048,576 bits MB: 1,048,576 bytes Brackets: Square brackets ([]) will be used to designate group membership or to define a group of signals with similar function (i.e., A[21:1], SR[4,1] and D[15:0]).

256-Mbit J3 (x8/x16)

8 Datasheet

2.0 Functional Overview

The Intel StrataFlash® memory family contains high-density memories organized as 32 Mbytes or 16Mwords (256-Mbit, available on the 0.18µm lithography process only), 16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized as one-hundred- twenty-eight 128-Kbyte (131,072 bytes) erase blocks . The 64-Mbit device is organized as sixty- four 128-Kbyte erase blocks while the 32-Mbit device contains thirty-two 128-Kbyte erase blocks. A 128-bit Protection Register has multiple uses, including unique flash device identification. The device’s optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems. A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward- compatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second— independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software to suspend programming (byte/ word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended. Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments. This feature can improve system program performance more than 20 times over non-Write Buffer writes. Blocks are selectively and individually lockable in-system.Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit and Clear Block Lock-Bits commands). The Status Register indicates when the WSM’s block erase, program, or lock-bit configuration operation is finished. The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/ BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lock- bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is

pulse on completion of programming and/or block erases. chip miniature card or SIMM module. device block diagram is shown in Figure 4 on page 14. and the Status Register is cleared.

2.1 Block Diagram

Figure 1. 3 Volt Intel StrataFlash ® Memory Block Diagram

10 Datasheet

2.2 Memory Map

Figure 2. Intel StrataFlash ® Memory (J3) Memory Map

3.0 Package Information

Figure 3. 56-Lead TSOP Package Drawing and Specifications Table 1. 56-Lead TSOP Dimension Table

12 Datasheet

3.2 Easy BGA (J3) Package

  1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging T echnology Web page at;
  2. For Packaging Shipping Media information see www.intel.com/design/packtech/index.htm

Figure 4. Intel StrataFlash ® Memory (J3) Easy BGA Mechanical Specifications Table 2. Easy BGA Package Dimensions

3.3 VF-BGA (J3) Package

  1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web
  2. For Packaging Shipping Media information refer to the Intel Flash Memory Packaging Technology Web page

Figure 5. Intel StrataFlash ® Memory (J3) VF BGA Mechanical Specifications and are sub j ect to chan g e.

14 Datasheet

4.0 Ballout and Signal Descriptions

4.1 Easy BGA Ballout (32/64/128/256 Mbit)

  1. Address A22 is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC).
  2. Address A23 is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC).
  3. Address A24 is only valid on 256-Mbit densities and above, otherwise, it is a no connect (NC).

Figure 6. Intel StrataFlash® Memory Easy BGA Ballout (32/64/128/256 Mbit)

  1. A22 exists on 64-, 128- and 256-Mbit densities. On 32-Mbit densities this signal is a no-connect (NC).
  2. A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC).
  3. A24 exists on 256-Mbit densities. On 32-, 64- and 128-Mbit densities this signal is a no-connect (NC).

4.3 VF BGA Ballout (32 and 64 Mbit)

  1. CE# is equivalent to CE0, and CE1 and CE2 are internally grounded.
  2. A22 exists on the 64 Mb density only. On the 32-Mbit density, this signal is a no-connect (NC).
  3. STS not supported in this package.
  4. x8 not supported in this package.

Figure 7. Intel StrataFlash ® Memory 56-Lead TSOP (32/64/128/256 Mbit)

3 Volt Intel

Figure 8. Intel StrataFlash ® Memory VF BGA Ballout (32 and 64 Mbit)

16 Datasheet

4.4 Signal Descriptions

Table 3 describes active signals used. Table 3. Signal Descriptions (Sheet 1 of 2) BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. is turned off when BYTE# is high). internally latched during a program cycle. mode. Data is internally latched during write operations. HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations. edge of CE0, CE1, or CE2 that disables the device (see Table 13 on page 33). OE# Input OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle. low. Addresses and data are latched on the rising edge of WE#. see the Configurations command. STS is to be tied to VCCQ with a pull-up resistor. PEN ≤ VPENLK, memory contents cannot be altered. when VCC ≤ VLKO. Device operation at invalid Vcc voltages should not be attempted. VCCQ Power I/O POWER SUPPLY: I/O Output-driver source voltage. This ball can be tied to V CC.

GND Supply GROUND: Do not float any ground signals. NC — NO CONNECT: Lead is not internally connected; it may be driven or floated. functionality and enhancement . Table 3. Signal Descriptions (Sheet 2 of 2)

18 Datasheet

5.0 Maximum Ratings and Operating Conditions

5.1 Absolute Maximum Ratings

before finalizing a design. Absolute maximum ratings are shown in Table 4. Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. Table 4. Absolute Maximum Ratings

  1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output signals and

may overshoot to VCC +2.0 V for periods <20 ns.

  1. Output shorted for no more than one second. No more than one output shorted at a time.

Table 5. Temperature and V CC Operating Conditions

6.0 Electrical Specifications

6.1 DC Current Characteristics

Table 6. DC Current Characteristics (Sheet 1 of 2) Max using standard 4 word page mode reads. Max using standard 4 word page mode reads.

  • CMOS Inputs, V CC = VCC Max, VCCQ = VCCQ Max using standard 8 word page mode reads.
  • Device is enabled (see Table 13) f = 5 MHz, IOUT = 0 mA 30 54 mA
  • CMOS Inputs,V CC = VCC Max, VCCQ = VCCQ Max using standard 8 word page mode reads.
  • Device is enabled (see Table 13) f = 33 MHz, IOUT = 0 mA
  • Density: 128-, 64-, and 32- Mbit 26 46 mA
  • CMOS Inputs,V CC = VCC Max, VCCQ = VCCQ Max using standard 8 word page mode reads.
  • Device is enabled (see Table 13) f = 33 MHz, IOUT = 0 mA
  • Density: 256Mbit ICCW VCC Program or Set Lock- Bit Current 35 60 mA CMOS Inputs, V PEN = VCC 1,4 40 70 mA TTL Inputs, V PEN = VCC

20 Datasheet

6.2 DC Voltage Characteristics

  1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and

CC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH.

  1. Sampled, not 100% tested.

Table 7. DC Voltage Characteristics

0.4 V VCCQ = VCCQ Min

0.2 V VCCQ = VCCQ Min

Table 6. DC Current Characteristics (Sheet 2 of 2)

  1. Sampled, not 100% tested.
  2. Block erases, programming, and lock-bit configurations are inhibited when V
  3. Typically, VPEN is connected to VCC (2.7 V–3.6 V).
  4. Block erases, programming, and lock-bit configurations are inhibited when V CC < VLKO, and

not guaranteed in the range between V LKO (min) and VCC (min), and above VCC (max).

  1. Includes all operational modes of the device including standby and power-up sequences.
  2. VCC operating condition for standby has to meet typical operationg coditons.

22 Datasheet

7.0 AC Characteristics

7.1 Read Operations

Table 8. Read Operations (Sheet 1 of 2)

32 Mbit 110 1,2

64 Mbit 115 120 1,2

128 Mbit 120 150 1,2

256 Mbit 125 1,2

32 Mbit 150 1,2

64 Mbit 180 180 1,2

128 Mbit 210 210 1,2

256 Mbit 210

defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 13).

  1. See AC Input/Output Reference Waveforms for the maximum allowable input slew
  2. OE# may be delayed up to tELQV-tGLQV after the first edge of CE0, CE1, or CE2 that

enables the device (see Table 13) without impact on tELQV.

  1. See Figure 15, “Transient Input/Output Reference Waveform for VCCQ = 2.7 V–3.6

page 30 for testing characteristics.

  1. When reading the flash array a faster t GLQV (R16) applies. Non-array reads refer to

Status Register reads, query reads, or device identifier reads.

  1. Sampled, not 100% tested.
  2. For devices configured to standard word/byte read mode, R15 (t

Figure 9. Single Word Asynchronous Read Waveform Table 8. Read Operations (Sheet 2 of 2)

24 Datasheet

  1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CE X high is defined at the

first edge of CE0, CE1, or CE2 that disables the device (see Table 13).

  1. When reading the flash array a faster t GLQV (R16) applies. For non-array reads, R4 applies (i.e.: Status

Register reads, query reads, or device identifier reads). the first edge of CE0, CE1, or CE2 that disables the device (see Table 13). Figure 10. 4-Word Page Mode Read Waveform

  1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CE X high is defined at the

first edge of CE0, CE1, or CE2 that disables the device (see Table 13).

  1. In this diagram, BYTE# is asserted high.

Figure 11. 8-word Asynchronous Page Mode Read

26 Datasheet

7.2 Write Operations

Table 9. Write Operations or CE2 that disables the device (see Table 13).

  1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as

during read-only operations. Refer to AC Characteristics–Read-Only Operations .

  1. A write operation can be initiated and terminated with either CE X or WE#.
  2. Sampled, not 100% tested.

high (whichever goes high first). Hence, t WP = tWLWH = tELEH = tWLEH = tELWH.

  1. Refer to Table 14 for valid AIN and DIN for block erase, program, or lock-bit configuration.
  2. Write pulse width high (t WPH) is defined from CEX or WE# going high (whichever goes high first) to CE X or WE#

going low (whichever goes low first). Hence, t WPH = tWHWL = tEHEL = tWHEL = tEHWL.

  1. For array access, t AVQV is required in addition to tWHGL for any accesses after a write.
  2. STS timings are based on STS configured in its RY/BY# default mode.

7.3 Block Erase, Program, and Lock-Bit Configuration

Table 10. Configuration Performance

  1. Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are

not set. Subject to change based on device characterization.

  1. These performance numbers are valid for all speed versions.
  2. Sampled but not 100% tested.
  3. Excludes system-level overhead.
  4. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.
  5. Effective per-byte program time (t

WHQV1, tEHQV1) is 6.8 µs/byte (typical).

  1. Effective per-word program time (t WHQV2, tEHQV2) is 13.6 µs/word (typical).
  2. Max values are measured at worst case temperature and V CC corner after 100k cycles (except as
  3. Max values are expressed at -25 °C/-40 °C.

10.Max values are expressed at 25 °C/-40 °C.

28 Datasheet

Figure 12. Asynchronous Write Waveform Figure 13. Asynchronous Write to Read Waveform

7.4 Reset Operation

NOTE: STS is shown in its default mode (RY/BY#).

7.5 AC Test Conditions

output timing ends, at VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns. Figure 14. AC Waveform for Reset Operation Table 11. Reset Specifications

  1. These specifications are valid for all product versions (packages and speeds).
  2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not

executing then the minimum required RP# Pulse Low Time is 100 ns. Figure 15. Transient Input/Output Reference Waveform for VCCQ = 2.7 V–3.6 V

30 Datasheet

NOTE: CL Includes Jig Capacitance.

7.6 Capacitance

Figure 16. Transient Equivalent Testing Load Circuit

  1. Sampled, not 100% tested.

256-Mbit J3 (x8/x16) Datasheet 31

8.0 Power and Reset Specifications

This section provides an overview of system level considerations for the Intel StrataFlash ® memory family device. This section provides a brief description of power-up, power-down, decoupling and reset design considerations.

8.1 Power-Up/Down Characteristics

In order to prevent any condition that may result in a spurious write or erase operation, it is recommended to power-up and power-down VCC and VCCQ together. It is also recommended to power-up VPEN with or slightly after VCC. Conversely, VPEN must power down with or slightly before VCC.

8.2 Power Supply Decoupling

When the device is enabled, many internal conditions change. Circuits are energized, charge pumps are switched on, and internal voltage nodes are ramped. All of this internal activities produce transient signals. The magnitude of the transient signals depends on the device and system loading. To minimize the effect of these transient signals, a 0.1 µF ceramic capacitor is required across each VCC/VSS and VCCQ signal. Capacitors should be placed as close as possible to device connections. Additionally, for every eight flash devices, a 4.7 µF electrolytic capacitor should be placed between VCC and VSS at the power supply connection. This 4.7 µF capacitor should help overcome voltage slumps caused by PCB (printed circuit board) trace inductance.

8.3 Reset Characteristics

By holding the flash device in reset during power-up and power-down transitions, invalid bus conditions may be masked. The flash device enters reset mode when RP# is driven low. In reset, internal flash circuitry is disabled and outputs are placed in a high-impedance state. After return from reset, a certain amount of time is required before the flash device is able to perform normal operations. After return from reset, the flash device defaults to asynchronous page mode. If RP# is driven low during a program or erase operation, the program or erase operation will be aborted and the memory contents at the aborted block or address are no longer valid. See Figure 14, “AC Waveform for Reset Operation” on page 29 for detailed information regarding reset timings.

32 Datasheet

9.0 Bus Operations

system read, write, and erase operations of the device via the system bus. Device commands are written to the CUI to control all of the flash memory device’s operations.

9.1 Bus Operations Overview

memory conform to standard microprocessor bus cycles. Table 12. Bus Operations

  1. See Table 13 on page 33 for valid CE configurations.
  2. OE# and WE# should never be enabled simultaneously.
  3. D refers to D[7:0] if BYTE# is low and D[15:0] if BYTE# is high.
  4. Refer to DC Characteristics. When V

PEN ≤ VPENLK, memory contents can be read, but not altered.

  1. X can be VIL or VIH for control and address signals, and V PENLK or VPENH for VPEN. See DC Characteristics for VPENLK and
  2. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It
  3. High Z will be VOH with an external pull-up resistor.
  4. See Section 10.2, “Read Identifier Codes” on page 39 for read identifier code data.
  5. See Section 10.3, “Read Query/CFI” on page 41 for read query data.

9.1.1 Bus Read Operation

To perform a bus read operation, CEx (refer to Table 13 on page 33) and OE# must be asserted. read states, WE# and RP# must be de-asserted. See Section 7.1, “Read Operations” on page 22.

9.1.2 Bus Write Operation

PEN = VPENH, block erasure, program, and lock-bit configuration. locked. The Clear Block Lock-Bits command requires the command and address within the device. page 33). Standard microprocessor write timings are used.

9.1.3 Output Disable

signals D[15:0] are placed in a high-impedance state. Table 13. Chip Enable Truth Table NOTE: For single-chip applications, CE2 and CE1 can be connected to VIL.

256-Mbit J3 (x8/x16)

34 Datasheet

9.1.4 Standby

CE0, CE1, and CE2 can disable the device (see Table 13 on page 33) and place it in standby mode. This manipulation of CEx substantially reduces device power consumption. D[15:0] outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the WSM continues functioning, and consuming active power until the operation completes.

9.1.5 Reset/Power-Down

RP# at VIL initiates the reset/power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. After this wake- up interval, normal operation is restored. The CUI is reset to read array mode and Status Register is set to 0x80. During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In default mode, STS transitions low and remains low for a maximum time of t PLPH + tPHRH until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time t PHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. Intel StrataFlash memory family devices allow proper initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.

9.2 Device Commands

Table 14. Command Bus-Cycle Definitions (Sheet 1 of 2)

36 Datasheet

  1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
  2. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scalable

Command Set (SCS) is also referred to as the Intel Extended Command Set.

  1. Bus operations are defined in Table 12.
  2. X = Any valid address within the device.

BA = Address within the block. IA = Identifier Code Address: see Table 17. QA = Query database Address. PA = Address of memory location to be programmed.

  1. ID = Data read from Identifier Codes.

QD = Data read from Query database. SRD = Data read from Status Register. See T able 18 for a description of the Status Register bits. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.

  1. The upper byte of the data bus (D[15:8]) during command writes is a “Don’t Care” in x16 operation.
  2. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock codes. See

Section 10.2 for read identifier code data.

  1. If the WSM is running, only D7 is valid; D[15:8] and D[6:0] float, which places them in a high-impedance state.
  2. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.

11.The write to buffer or erase operation does not begin until a Confirm command (0xD0) is issued. 12.Attempts to issue a block erase or program to a locked block. 13.Either 0x40 or 0x10 are recognized by the WSM as the byte/word program setup. 14.Program suspends can be issued after either the Write-to-Buffer or Word/Byte-Program operation is initiated. 15.The clear block lock-bits operation simultaneously clears all block lock-bits. Table 14. Command Bus-Cycle Definitions (Sheet 2 of 2)

256-Mbit J3 (x8/x16) Datasheet 37

10.0 Read Operations

The device supports four types of read modes: Read Array, Read Identifier, Read Status, and CFI query. Upon power-up or return from reset, the device defaults to read array mode. To change the device’s read mode, the appropriate read-mode command must be written to the device. (See Section 9.2, “Device Commands” on page 35.) See Section 14.0, “Special Modes” on page 50 for details regarding read status, read ID, and CFI query modes. Upon initial device power-up or after exit from reset/power-down mode, the device automatically resets to read array mode. Otherwise, write the appropriate read mode command (Read Array, Read Query, Read Identifier Codes, or Read Status Register) to the CUI. Six control signals dictate the data flow in and out of the component: CE0, CE1, CE2, OE#, WE#, and RP#. The device must be enabled (see Table 13, “Chip Enable Truth Table” on page 33), and OE# must be driven active to obtain data at the outputs. CE0, CE1, and CE2 are the device selection controls and, when enabled (see Table 13), select the memory device. OE# is the data output (D[15:0]) control and, when active, drives the selected memory data onto the I/O bus. WE# must be at V IH.

10.1 Read Array

Upon initial device power-up and after exit from reset/power-down mode, the device defaults to read array mode. The device defaults to four-word asynchronous read page mode. The Read Array command also causes the device to enter read array mode. The device remains enabled for reads until another command is written. If the internal WSM has started a block erase, program, or lock- bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase or Program Suspend command. The Read Array command functions independently of the V PEN voltage.

10.1.1 Asynchronous Page Mode Read

There are two Asynchronous Page mode configurations that are available depending on the user’s system design requirements:

  • Four-Word Page mode: This is the default mode on power-up or reset. Array data can be sensed up to four words (8 Bytes) at a time.
  • Eight-Word Page mode: Array data can be sensed up to eight words (16 Bytes) at a time. This mode must be enabled on power-up or reset by using the command sequence found in Table 14, “Command Bus-Cycle Definitions” on page 35. Address bits A[3:1] determine which word is output during a read operation, and A[3:0] determine which byte is output for a x8 bus width. After the initial access delay, the first word out of the page buffer corresponds to the initial address. In Four-Word Page mode, address bits A[2:1] determine which word is output from the page buffer for a x16 bus width, and A[2:0] determine which byte is output from the page buffer for a x8 bus width. Subsequent reads from the device come fr om the page buffer. These reads are output on D[15:0] for a x16 bus width and D[7:0] for a x8 bus width after a minimum delay as long as A[2:0] (Four-Word Page mode) or A[3:0] (Eight-Word Page mode) are the only address bits that change. Data can be read from the page buffer multiple times, and in any order. In Four-Word Page Mode, if address bits A[MAX:3] (A[MAX:4] for Eight-Word Page Mode) change at any time, or if CE# is toggled, the device will sense and load new data into the page buffer. Asynchronous Page Mode is the default read mode on power-up or reset.

38 Datasheet

to access register information. During register access, only one word is loaded into the page buffer.

10.1.2 Enhanced Configuration Register (ECR)

Configuration Register” on page 38. Definition” on page 38 for further details. NOTE: Any reserved bits should be set to 0. NOTE: X = Any valid address within the device. ECD = Enhanced Configuration Register Data. Table 15. Enhanced Configuration Register

  • “0” = 4Word Page mode ECR[12:0] Reserved Reserved for Future Use. Set to 0 until further notice.

Table 16. J3C Asynchronous 8-Word Page Mode Command Bus-Cycle Definition

3 Write ECD 0x60 Write ECD 0x04 Write X 0x50

10.2 Read Identifier Codes

Identifier Codes command, the following information can be read.

10.2.1 Read Status Register

SR.7), all contents of the Status Register are valid when read. Table 17. Read Identifier Codes

  • Block Is Unlocked D0 = 0
  • Block Is Locked D0 = 1
  • Reserved for Future Use D[7:1] NOTES: 1. A0 is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest order address line is A1. Data is always presented on the low byte in x16 mode (upper byte contains 00h). 2. X selects the specific block’s lock configuration code. 3. D[7:1] are invalid and should be ignored.

40 Datasheet

Table 18. Status Register Definitions program, or lock-bit configuration completion. command sequence was entered. Block Lock-Bits command sequences. Codes command to determine block lock-bit status. masked when polling the Status Register. Table 19. Extended Status Register Definitions that a Write Buffer is available. masked when polling the Status Register.

256-Mbit J3 (x8/x16) Datasheet 41

10.3 Read Query/CFI

The query register contains an assortment of flash product information such as block size, density, allowable command sets, electrical specifications and other product information. The data contained in this register conforms to the Common Flash Interface (CFI) protocol. To obtain any information from the query register, execute the Read Query Register command. See Section 9.2, “Device Commands” on page 35 for details on issuing the CFI Query command. Refer to Appendix A, “Query Structure Overview” on page 53 for a detailed explanation of the CFI register. Information contained in this register can only be accessed by executing a single-word read.

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42 Datasheet

11.0 Programming Operations

The device supports two different programming methods: word programming, and write-buffer programming. Successful programming requires the addressed block to be unlocked. An attempt to program a locked block will result in the operation aborting, and SR.1 and SR.4 being set, indicating a programming error. The following sections describe device programming in detail.

11.1 Byte/Word Program

Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup (standard 0x40 or alternate 0x10) is written followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and program verify algorithms internally. After the program sequence is written, the device automatically outputs SRD when read (see Figure 20, “Byte/Word Program Flowchart” on page 61). The CPU can detect the completion of the program event by analyzing the STS signal or SR.7. When program is complete, SR.4 should be checked. If a program error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for “1”s that do not successfully program to “0”s. The CUI remains in Read Status Register mode until it receives another command. Reliable byte/word programming can only occur when V CC and VPEN are valid. If a byte/word program is attempted while VPEN ≤ VPENLK, SR.4 and SR.3 will be set. Successful byte/word programs require that the corresponding block lock-bit be cleared. If a byte/word program is attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set.

11.2 Write to Buffer

To program the flash device, a Write to Buffer command sequence is initiated. A variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the Write to Buffer Setup command is issued along with the Block Address (see Figure 18, “Write to Buffer Flowchart” on page 59). At this point, the eXtended Status Register (XSR, see Table 19) information is loaded and XSR.7 reverts to “buffer available” status. If XSR.7 = 0, the write buffer is not available. To retry, continue monitoring XSR.7 by issuing the Write to Buffer setup command with the Block Address until XSR.7 = 1. When XSR.7 transitions to a “1,” the buffer is ready for loading. Next, a word/byte count is given to the part with the Block Address. On the next write, a device start address is given along with the write buffer data. Subsequent writes provide additional device addresses and data, depending on the count. All subsequent addresses must lie within the start address plus the count. Internally, this device programs many flash cells in parallel. Because of this parallel programming, maximum programming performance and lower power are obtained by aligning the start address at the beginning of a write buffer boundary (i.e., A[4:0] of the start address = 0).

256-Mbit J3 (x8/x16) Datasheet 43 After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM (Write State Machine) to begin copying the buffer data to the flash array. If a command other than Write Confirm is written to the device, an “Invalid Command/Sequence” error will be generated and SR.5 and SR.4 will be set. For additional buffer writes, issue another Write to Buffer Setup command and check XSR.7. If an error occurs while writing, the device will stop writing, and SR.4 will be set to indicate a program failure. The internal WSM verify only detects errors for “1”s that do not successfully program to “0”s. If a program error is detected, the Status Register should be cleared. Any time SR.4 and/or SR.5 is set (e.g., a media failure occurs during a program or an erase), the device will not accept any more Write to Buffer commands. Additionally, if the user attempts to program past an erase block boundary with a Write to Buffer command, the device will abort the write to buffer operation. This will generate an “Invalid Command/Sequence” error and SR.5 and SR.4 will be set. Reliable buffered writes can only occur when V PEN = VPENH. If a buffered write is attempted while VPEN ≤ VPENLK, SR.4 and SR.3 will be set. Buffered write attempts with invalid V CC and VPEN voltages produce spurious results and should not be attempted. Finally, successful programming requires that the corresponding block lock-bit be reset. If a buffered write is attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set.

11.3 Program Suspend

The Program Suspend command allows program interruption to read data in other flash memory locations. Once the programming process starts (either by initiating a write to buffer or byte/word program operation), writing the Program Suspend command requests that the WSM suspend the program sequence at a predetermined point in the algorithm. The device continues to output SRD when read after the Program Suspend command is written. Polling SR.7 can determine when the programming operation has been suspended. When SR.7 = 1, SR.2 should also be set, indicating that the device is in the program suspend mode. STS in level RY/BY# mode will also transition to V OH. Specification tWHRH1 defines the program suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while programming is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Program Resume. After a Program Resume command is written, the WSM will continue the programming process. SR.2 and SR.7 will automatically clear and STS in RY/BY# mode will return to V OL. After the Program Resume command is written, the device automatically outputs SRD when read. VPEN must remain at VPENH and VCC must remain at valid VCC levels (the same VPEN and VCC levels used for programming) while in program suspend mode. Refer to Figure 21, “Program Suspend/Resume Flowchart” on page 62.

11.4 Program Resume

To resume (i.e., continue) a program suspend operation, execute the Program Resume command. The Resume command can be written to any device address. When a program operation is nested within an erase suspend operation and the Program Suspend command is issued, the device will suspend the program operation. When the Resume command is issued, the device will resume and complete the program operation. Once the nested program operation is completed, an additional Resume command is required to complete the block erase operation. The device supports a maximum suspend/resume of two nested routines. See Figure 21, “Program Suspend/Resume Flowchart” on page 62).

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44 Datasheet

12.0 Erase Operations

Flash erasing is performed on a block basis; therefore, only one block can be erased at a time. Once a block is erased, all bits within that block will read as a logic level one. To determine the status of a block erase, poll the Status Register and analyze the bits. This following section describes block erase operations in detail.

12.1 Block Erase

Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires an appropriate address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs SRD when read (see Figure 22, “Block Erase Flowchart” on page 63). The CPU can detect block erase completion by analyzing the output of the STS signal or SR.7. Toggle OE#, CE0, CE1, or CE2 to update the Status Register. When the block erase is complete, SR.5 should be checked. If a block erase error is detected, the Status Register should be cleared before system software attempts corrective actions. The CUI remains in Read Status Register mode until a new command is issued. This two-step command sequence of setup followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both SR.4 and SR.5 being set. Also, reliable block erasure can only occur when V CC is valid and VPEN = VPENH. If block erase is attempted while VPEN ≤ VPENLK, SR.3 and SR.5 will be set. Successful block erase requires that the corresponding block lock-bit be cleared. If block erase is attempted when the corresponding block lock-bit is set, SR.1 and SR.5 will be set.

12.2 Block Erase Suspend

The Block Erase Suspend command allows block-erase interruption to read or program data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs SRD when read after the Block Erase Suspend command is written. Polling SR.7 then SR.6 can determine when the block erase operation has been suspended (both will be set). In default mode, STS will also transition to V OH. Specification tWHRH defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A program command sequence can also be issued during erase suspend to program data in other blocks. During a program operation with block erase suspended, SR.7 will return to “0” and STS output (in default mode) will transition to V OL. However, SR.6 will remain “1” to indicate block erase suspend status. Using the Program Suspend command, a program operation can also be suspended. Resuming a suspended programming operation by issuing the Program Resume command allows continuing of the suspended programming operation. To resume the suspended erase, the user must wait for the programming operation to complete before issuing the Block Erase Resume command.

256-Mbit J3 (x8/x16) Datasheet 45 The only other valid commands while block erase is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. SR.6 and SR.7 will automatically clear and STS (in default mode) will return to V OL. After the Erase Resume command is written, the device automatically outputs SRD when read (see Figure 23, “Block Erase Suspend/Resume Flowchart” on page 64). VPEN must remain at VPENH (the same VPEN level used for block erase) while block erase is suspended. Block erase cannot resume until program operations initiated during block erase suspend have completed.

12.3 Erase Resume

To resume (i.e., continue) an erase suspend operation, execute the Erase Resume command. The Resume command can be written to any device address. When a program operation is nested within an erase suspend operation and the Program Suspend command is issued, the device will suspend the program operation. When the Resume command is issued, the device will resume the program operations first. Once the nested program operation is completed, an additional Resume command is required to complete the block erase operation. The device supports a maximum suspend/resume of two nested routines. See Figure 22, “Block Erase Flowchart” on page 63.

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46 Datasheet

13.0 Security Modes

This device offers both hardware and software security features. Block lock operations, PRs, and VPEN allow the user to implement various levels of data protection. The following section describes security features in detail. Other security features are available that are not described in this datasheet. Please contact your local Intel Field Representative for more information.

13.1 Set Block Lock-Bit

A flexible block locking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations. Individual block lock-bits can be set using the Set Block Lock-Bit command. This command is invalid while the WSM is running or the device is suspended. Set block lock-bit commands are executed by a two-cycle sequence. The set block setup along with appropriate block address is followed by either the set block lock-bit confirm (and an address within the block to be locked). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs Status Register data when read (see Figure 24 on page 65). The CPU can detect the completion of the set lock-bit event by analyzing the STS signal output or SR.7. When the set lock-bit operation is complete, SR.4 should be checked. If an error is detected, the Status Register should be cleared. The CUI will remain in Read Status Register mode until a new command is issued. This two-step sequence of setup followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block Lock-Bit command will result in SR.4 and SR.5 being set. Also, reliable operations occur only when V CC and VPEN are valid. With VPEN ≤ VPENLK, lock-bit contents are protected against alteration.

13.2 Clear Block Lock-Bits

All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lock- bits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while the WSM is running or the device is suspended. Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup is first written. The device automatically outputs Status Register data when read (see Figure 25 on page 66). The CPU can detect completion of the clear block lock-bits event by analyzing the STS signal output or SR.7. When the operation is complete, SR.5 should be checked. If a clear block lock-bit error is detected, the Status Register should be cleared. The CUI will remain in Read Status Register mode until another command is issued.

256-Mbit J3 (x8/x16) Datasheet 47 This two-step sequence of setup followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in SR.4 and SR.5 being set. Also, a reliable clear block lock-bits operation can only occur when V CC and VPEN are valid. If a clear block lock-bits operation is attempted while V PEN ≤ VPENLK, SR.3 and SR.5 will be set. If a clear block lock-bits operation is aborted due to V PEN or VCC transitioning out of valid range, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values.

13.3 Protection Register Program

The Intel StrataFlash® memory (J3) includes a 128-bit Protection Register (PR) that can be used to increase the security of a system design. For example, the number contained in the PR can be used to “mate” the flash component with other system components such as the CPU or ASIC, preventing device substitution. The 128-bits of the PR are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unalterable. The other segment is left blank for customer designers to program as desired. Once the customer segment is programmed, it can be locked to prevent further programming.

13.3.1 Reading the Protection Register

The Protection Register is read in the identification read mode. The device is switched to this mode by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in Table 8 or Table 21 retrieve the specified information. To return to read array mode, write the Read Array command (0xFF).

13.3.2 Programming the Protection Register

Protection Register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time for word-wide configuration and eight bits at a time for byte-wide configuration. First write the Protection Program Setup command, 0xC0. The next write to the device will latch in address and data and program the specified location. The allowable addresses are shown in Table 8 or Table 21. See Figure 26, “Protection Register Programming Flowchart” on page 67 Any attempt to address Protection Program commands outside the defined PR address space will result in a Status Register error (SR.4 will be set). Attempting to program a locked PR segment will result in a Status Register error (SR.4 and SR.1 will be set).

13.3.3 Locking the Protection Register

The user-programmable segment of the Protection Register is lockable by programming Bit 1 of the PLR to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. Bit 1 is set using the Protection Program command to program “0xFFFD” to the PLR. After these bits have been programmed, no further changes can be made to the values stored in the Protection Register. Protection Program commands to a locked section will result in a Status Register error (SR.4 and SR.1 will be set). PR lockout state is not reversible.

48 Datasheet

addressing). For x8 mode A0 is used (See Table 21 for x8 addressing). Figure 17. Protection Register Memory Map Table 20. Word-Wide Protection Register Addressing

0 F a c t o r y 10000001

1 F a c t o r y 10000010

2 F a c t o r y 10000011

3 F a c t o r y 10000100

4 U s e r 10000101

5 U s e r 10000110

6 U s e r 10000111

7 U s e r 10001000

Table 21. Byte-Wide Protection Register Addressing (Sheet 1 of 2)

0 F a c t o r y 100000010

1 F a c t o r y 100000011

2 F a c t o r y 100000100

3 F a c t o r y 100000101

4 F a c t o r y 100000110

5 F a c t o r y 100000111

13.4 Array Protection

operation, poll the Status Register and analyze the bits.

6 F a c t o r y 100001000

7 F a c t o r y 100001001

8 U s e r 100001010

9 U s e r 100001011

Table 21. Byte-Wide Protection Register Addressing (Sheet 2 of 2)

50 Datasheet

14.0 Special Modes

14.1 Set Read Configuration Register Command

while the J3C device will result in an invalid command sequence (SR.4 and SR.5 =1).

14.2 Status (STS)

The Status (STS) signal can be configured to different states using the Configuration command. Definitions” on page 50 displays the possible STS configurations. STS signal pulses low with a typical pulse width of 250 ns. Table 22. STS Configuration Coding Definitions flash memory subsystem while any flash device's WSM is busy.

performance for servicing continuous buffer write operations. common interrupt service routine is desired.

  1. When configured in one of the pulse modes, STS pulses low with a typical pulse width of 250 ns.
  2. An invalid configuration code will result in both SR.4 and SR.5 being set.

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52 Datasheet

Appendix A Common Flash Interface The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specified flash device families. It allows flash vendors to standardize their existing interfaces for long-term compatibility. This appendix defines the data structure or “database” returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query command is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI. A.1 Query Structure Output The Query “database” allows system software to gain information for controlling the flash component. This section describes the device’s CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest-order data outputs (D[7:0]) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two bytes of the Query structure, “Q” and “R” in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII “Q” in the low byte (D[7:0]) and 0x00 (00h) in the high byte (D[15:8]). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always “00h,” the leading “00” has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.

a full description of CFI commands. The following sections describe the Query structure sub-sections in detail. Table 23. Summary of Query Structure Output as a Function of Device and Mode

  1. The system must drive the lowest order addresses to access all the device's array data when the device is

system, is "Not Applicable" for x8-configured devices. Table 24. Example of Query Structure Output of a x16- and x8-Capable Device

54 Datasheet

given block is locked or can be accessed for flash program/erase operations. Common Flash Interface specification. vendor-specified command set(s). Table 25. Query Structure

  1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset

address as a function of device bus width and mode.

  1. BA = Block Address beginning location (i.e., 02000h is block 2’s beginning location when the
  2. Offset 15 defines “P” which points to the Primary Intel-Specific Extended Query Table.

Table 26. Block Status Register

  1. BA = The beginning location of a Block Address (i.e., 008000h is block 1’s (64-KB block) beginning location

Table 27. CFI Identification (Sheet 1 of 2)

The following device information can optimize system interface software. This field provides critical details of the flash device geometry. Table 27. CFI Identification (Sheet 2 of 2) Table 28. System Interface Information Table 29. Device Geometry Definition (Sheet 1 of 2)

56 Datasheet

table specifies this and other similar information.

  1. x = 0 means no erase blocking; the device erases in “bulk”
  2. x specifies the number of device or partition regions with one or
  3. Symmetrically blocked partitions have one blocking region
  4. Partition size = (total blocks) x (individual block size)

Table 29. Device Geometry Definition (Sheet 2 of 2) Table 30. Primary Vendor-Specific Extended Query (Sheet 1 of 2)

  1. Future devices may not support the described “Legacy Lock/Unlock” function. Thus bit 3 would have a

Table 30. Primary Vendor-Specific Extended Query (Sheet 2 of 2)

58 Datasheet

Table 31. Protection Register Information (P+E)h 1 Number of Protection register fields in JEDEC ID space. pre-programmed and user-programmable.

  1. The variable P is a pointer which is defined at CFI offset 15h.

Table 32. Burst Read Information

  1. The variable P is a pointer which is defined at CFI offset 15h.

Figure 18. Write to Buffer Flowchart

60 Datasheet

Figure 19. Status Register Flowchart

Figure 20. Byte/Word Program Flowchart

  1. Toggling OE# (low to high to low) updates the status register. This

can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. after a sequence of programming operations. be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. implemeting lock-bit configuration.

62 Datasheet

Figure 21. Program Suspend/Resume Flowchart

Figure 22. Block Erase Flowchart

  1. The Erase Confirm byte must follow Erase Setup.

reset the device to read array mode.

64 Datasheet

Figure 23. Block Erase Suspend/Resume Flowchart

Figure 24. Set Block Lock-Bit Flowchart Repeat for subsequent lock-bit operations. a sequence of lock-bit set operations.

66 Datasheet

Figure 25. Clear Lock-Bit Flowchart

Figure 26. Protection Register Programming Flowchart Repeat for subsequent programming operations. Write FFH after the last program operation to reset device to read array mode. attempts are allowed by the Write State Machine.

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Appendix C Design Considerations C.1 Three-Line Output Control The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1, CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable the device (see Table 13) while OE# should be connected to all memory devices and the system’s READ# control line. This assures that only selected memory devices have active outputs while de-selected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. C.2 STS and Block Erase, Program, and Lock-Bit Configuration Polling STS is an open drain output that should be connected to VCCQ by a pull-up resistor to provide a hardware method of detecting block erase, program, and lock-bit configuration completion. It is recommended that a 2.5k resister be used between STS# and VCCQ. In default mode, it transitions low after block erase, program, or lock-bit configuration commands and returns to High Z when the WSM has finished executing the internal algorithm. For alternate configurations of the STS signal, see the Configuration command. STS can be connected to an interrupt input of the system CPU or controller. It is active at all times. STS, in default mode, is also High Z when the device is in block erase suspend (with programming inactive), program suspend, or in reset/power-down mode. C.3 Input Signal Transitions—Reducing Overshoots and Undershoots When Using Buffers or Transceivers As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory specifications. (See “DC V oltage Characteristics” on page 20.) Many buffer/transceiver vendors now carry bus-interface devices with internal out put-damping resistors or reduced-drive outputs. Internal output-damping resistors diminish the nominal output drive currents, while still leaving sufficient drive capability for most applications. These internal output-damping resistors help reduce unnecessary overshoots and undershoots. Transceivers or buffers with balanced- or light- drive outputs also reduce overshoots and undershoots by diminishing output-drive currents. When considering a buffer/transceiver interface design to flash, devices with internal output-damping resistors or reduced-drive outputs should be used to minimize overshoots and undershoots. For additional information, please refer to AP-647, 5 Volt Intel StrataFlash ® Memory Design Guide (Order Number: 292205).

256-Mbit J3 (x8/x16) Datasheet 69 C.4 V CC, VPEN, RP# Transitions Block erase, program, and lock-bit configuration are not guaranteed if VPEN or VCC falls outside of the specified operating ranges, or RP# ≠ VIH. If RP# transitions to VIL during block erase, program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of t PLPH + tPHRH until the reset operation is complete. Then, the operation will abort and the device will enter reset/power-down mode. The aborted operation may leave data partially corrupted after programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase and lock-bit configuration commands must be repeated after normal operation is restored. Device power-off or RP# = V IL clears the Status Register. The CUI latches commands issued by system software and is not altered by V PEN, CE0, CE1, or CE2 transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/ power-down mode, or after VCC transitions below VLKO. VCC must be kept at or above VPEN during VCC transitions. After block erase, program, or lock-bit configuration, even after VPEN transitions down to VPENLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. V PEN must be kept at or below VCC during VPEN transitions. C.5 Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed.

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Appendix D Additional Information Order Number Document/Tool

298130 Intel® StrataFlash™ Memory (J3); 28F256J3, 28F128J3, 28F640J3, 28F320J3

298136 Intel® Persistent Storage Manager (IPSM) User’s Guide Software Manual

297833 Intel® Flash Data Integrator (FDI) User’s Guide Software Manual

290737 Intel StrataFlash® Synchronous Memory (K3/K18); 28F640K3, 28F640K18,

28F128K3, 28F128K18, 28F256K3, 28F256K18

292280 AP-732 3 Volt Intel StrataFlash® Memory J3 to K3/K18 Migration Guide

292237 AP-689 Using Intel® Persistent Storage Manager

290606 5 Volt Intel® StrataFlash™ MemoryI28F320J5 and 28F640J5 datasheet

297859 AP-677 Intel® StrataFlash™ Memory Technology

292222 AP-664 Designing Intel® StrataFlash™ Memory into Intel ® Architecture

292221 AP-663 Using the Intel® StrataFlash™ Memory Write Buffer

292218 AP-660 Migration Guide to 3 Volt Intel® StrataFlash™ Memory

292204 AP-646 Common Flash Interface (CFI) and Command Sets

253418 Intel® Wireless Communications and Computing Package User’s Guide

  1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. 3. For the most current information on Intel StrataFlash memory, visit our website at http:// developer.intel.com/design/flash/isf.

256-Mbit J3 (x8/x16) Datasheet 71 Appendix E Ordering Information NOTE: 1. Speeds are for either the standard asynchronous read access times or for the first access of a page-mode read sequence. VALID COMBINATIONS P C 2 8 F 2 5 6 J 3 C - 1 2 Product line designator for all Intel® Flash products Access Speed (ns)1

256 Mbit = 125

128 Mbit = 150, 120

64 Mbit = 120, 115

32 Mbit = 110

J = Intel ® StrataFlash memory, 2 bits-per-cell Device Density 256 = x8/x16 (256 Mbit) 128 = x8/x16 (128 Mbit) 640 = x8/x16 (64 Mbit) 320 = x8/x16 (32 Mbit) Voltage (VCC/VPEN) 3 = 3 V/3 V A = Intel® 0.25 micron lithography C = Intel® 0.18 micron lithography Package E = 56-Lead TSOP (J3A, 802) TE= 56-Lead TSOP (J3C, 803) JS = Pb-Free 56-TSOP RC = 64-Ball Easy BGA GE = 48-Ball VFBGA PC = 64-Ball Pb-Free Easy BGA 56-Lead TSOP 64-Ball Easy BGA 48-Ball VF BGA E28F320J3A-110 RC28F320J3A-110 GE28F320J3A-110 E28F640J3A-120 RC28F640J3A-120 GE28F320J3C-110 E28F128J3A-150 RC28F128J3A-150 GE28F640J3C-115 TE28F320J3C-110 RC28F320J3C-110 GE28F640J3C-120 TE28F640J3C-115 RC28F640J3C-115 TE28F640J3C-120 RC28F640J3C-120 TE28F128J3C-120 RC28F128J3C-120 TE28F128J3C-150 RC28F128J3C-150 TE28F256J3C-125 RC28F256J3C-125 56-Lead Pb-Free TSOP 64-Ball Pb-Free Easy BGA JS28F256J3C125 PC28F256J3C125 JS28F128J3C120 PC28F128J3C120 JS28F640J3C115 PC28F640J3C115 JS28F320J3C110 PC28F320J3C110

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