28F016SV INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 INTRODUCTION
- 1.1 Enhanced Features
- 1.2 Product Overview
- 2.0 DEVICE PINOUT
- 2.1 Lead Descriptions
- 3.0 MEMORY MAPS
- 3.1 Extended Status Registers Memory Map
- 4.0 BUS OPERATIONS, COMMANDS AND
- 4.1 Bus Operations for Word-Wide Mode
- 4.2 Bus Operations for Byte-Wide Mode
- 4.5 Compatible Status Register
- 4.6 Global Status Register
- 4.7 Block Status Register
- 4.8 Device Configuration Code
- 5.0 ELECTRICAL SPECIFICATIONS
- 5.1 Absolute Maximum Ratings
- 5.2 Capacitance
- 5.3 DC Characteristics (V
- 5.5 Timing Nomenclature
- 5.6 AC Characteristics—Read Only Operations38
- 5.7 Power-Up and Reset Timings
- 5.8 AC Characteristics for WE#—Controlled
- 5.9 AC Characteristics for CE#—Controlled
- 5.10 AC Characteristics for WE#—Controlled
- 5.11 AC Characteristics for CE#—Controlled
- 5.12 Erase and Word/Byte Program
- 6.0 MECHANICAL SPECIFICATIONS
E 7/11/97 11:03 AM 29052807.DOC July 1997 Order Number: 290528-007 /c110 SmartVoltage Technology User-Selectable 3.3V or 5V VCC User-Selectable 5V or 12V VPP /c110 65 ns Access Time /c110 1 Million Erase Cycles per Block /c110 30.8 MB/sec Burst Write Transfer Rate /c110 0.48 MB/sec Sustainable Write Transfer Rate /c110 Configurable x8 or x16 Operation /c110 56-Lead TSOP and SSOP Type I Packages /c110 Backwards-Compatible with 28F016SA, 28F008SA Command Set /c110 Revolutionary Architecture Multiple Command Execution Program during Erase Command Super-Set of the Intel 28F008SA Page Buffer Program /c110 2 µA Typical Deep Power-Down /c110 32 Independently Lockable Blocks /c110 State-of-the-Art 0.6 µm ETOX™ IV Flash Technology Intel’s 28F016SV 16-Mbit FlashFile™ memory is a revolutionary architecture which is the ideal choice for designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative capabilities, low-power operation, user-selectable V PP voltage and high read/program performance, the 28F016SV enables the design of truly mobile, high-performance personal computing and communications products. The 28F016SV is the highest density, highest performance nonvolatile read/program solution for solid-state storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit and 28F016SA 16-Mbit FlashFile memories), extended cycling, flexible V CC and VPP voltage (SmartVoltage technology), fast program and read performance and selective block locking, provide a highly-flexible memory component suitable for Resident Flash Arrays, high-density memory cards and PCMCIA-ATA flash drives. The 28F016SV’s dual read voltage enables the design of memory cards which can be read/written in 3.3V and 5V systems interchangeably. Its x8/x16 architecture allows optimization of the memory-to-processor interface. The flexible block locking option enables bundling of executable application software in a Resident Flash Array or memory card. The 28F016SV is manufactured on Intel’s 0.6 µm ETOX IV process technology. 28F016SV 16-MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile™ MEMORY Includes Commercial and Extended Temperature Specifications
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F016SV may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 or visit Intel’s Website at http:\\\\www.intel.com COPYRIGHT © INTEL CORPORATION, 1997 CG-041493 *Third-party brands and names are the property of their respective owners.
28F016SV FlashFile™ MEMORY E
REVISION HISTORY
-001 Original Version -002 Added 28F016SV-065/-070 at 5V VCC and 28F016SV-075 at 3.3V VCC . Improved burst write transfer rate to 30.8 MB/sec. Added 56-lead SSOP Type I packaging information. Changed V PPLK from 2V to 1.5V. Increased ICCR at 5V VCC and 3.3V VCC : ICCR1 from 30 mA (typ)/35 mA (max) to 40 mA (typ)/50 mA (max) @ VCC = 3.3V ICCR2 from 15 mA (typ)/20 mA (max) to 20 mA (typ)/30 mA (max) @ VCC = 3.3V ICCR1 from 50 mA (typ)/60 mA (max) to 75 mA (typ)/95 mA (max) @ VCC = 5V ICCR2 from 30 mA (typ)/35 mA (max) to 45 mA (typ)/55 mA (max) @ VCC = 5V Moved AC Characteristics for Extended Register Reads into separate table. Increased V PP MAX from 13V to 14V. Added Erase Suspend Command Latency times to Section 5.12 Modified Device Nomenclature Section to include SSOP package option and Ordering Information -003 Changed definition of “NC.” Removed “No internal connection to die” from description. Added “xx” to Upper Byte of Command (Data) Definition in Sections 4.3 and 4.4. Added Note to Sleep Command (Section 4.4) denoting that the chip must be de-selected in order for the power consumption in sleep mode to reach deep power-down levels. Modified parameters “V” and “I” of Section 5.1 to apply to “NC” pins. Increased I PPR (VPP Read Current) for VPP > VCC to 200 µA at VCC = 3.3V and VCC = 5V Changed VCC = 5V DC Characteristics (Section 5.5) marked with Note 1 to indicate that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns and a TTL rise/fall time of <10 ns. Corrected the graphical representation of t WHGL and tEHGL in Figures 15 and 16. Increased Typical “Page Buffer Byte/Word Program Times” from 6.0 µs to 8.0 µs (Byte) and 12.1 µs to 16.0 µs (Word) @ VCC = 3.3V/5V and VPP = 5V: Increased Typ. “Byte/Word Program Times” (tWHRH1A /tWHRH1B ) for VPP = 5V (Section 5.12) t tWHRH1A from 11.0 µs to 20.0 µs and tWHRH1B from 16.0 µs to 25.0 µs at VCC = 5V Increased Typical “Block Program Times” (t WHRH2 /tWHRH3 )for VPP =5V (Section 5.12): t WHRH2 from 0.8 sec to 1.4 sec and t WHRH3 from 0.6 sec to 0.85 sec at VCC = 5V Changed “Time from Erase Suspend Command to WSM Ready” spec name to “Erase Suspend Latency Time to Read;” modified typical values and added Min/Max values at V CC =3.3/5V and VPP =5V/12V (Section 5.12) Added “Erase Suspend Latency Time to Program” Specifications to Section 5.12 Minor cosmetic changes throughout document
E 28F016SV FlashFile™ MEMORY REVISION HISTORY (Continued) Number Description -004 Added 3/5# pin to Block Diagram (Figure 1), Pinout Configurations (Figures 2 and 3), Product Overview (Section 1.1) and Lead Descriptions (Section 2.1) Added 3/5# pin to Test Conditions of ICCS Specifications Added 3/5# pin (Y) to Timing Nomenclature (Section 5.5) Increased t PHQV Specifications at 5V VCC to 400 ns for E28F016SV 065 devices and 480 ns for E28F106SV 070 devices. Modified Power-Up and Reset Timings (Section 5.9) to include 3/5# pin: Removed t5VPH and t3VPH specifications; Added tPLYL , tPLYH , tYLPH , and tYHPH specifications Added tPHEL3 and tPHEL5 specifications to Power-Up and Reset Timings (Section 5.9) Corrected TSOP Mechanical Specification A1 from 0.50 mm to 0.050 mm (Section 6.0) Corrected SSOP Mechanical Spec. B (max) from 0.20 mm to 0.40 mm (Section 6.0) Minor cosmetic changes throughout document. -005 Updated DC Specifications: ICCD , IPPES Updated AC Specifications: Page Buffer Reads: (tAVAV , tAVQV , tELQV , and tFLQV /tFHQV ) Page Buffer WE#-Controlled Command Writes (tELWL ) CE#-Controlled Command Write Parameters (tAVAV , tELEH , tEHEL ) Combined Commercial and Extended Temperature information into single datasheet. -006 Updated AC Specifications: Page Buffer Reads: (tAVAV , tAVQV , tELQV , and tFLQV /tFHQV ) -007 Updated Disclaimer
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E 28F016SV FlashFile™ MEMORY
1.0 INTRODUCTION
The documentation of the Intel 28F016SV memory device includes this datasheet, a detailed user’s manual, and a number of application notes and design tools, all of which are referenced in Appendix B. The datasheet is intended to give an overview of the chip feature-set and of the operating AC/DC specifications. The 16-Mbit Flash Product Family User’s Manual provides complete descriptions of the user modes, system interface examples and detailed descriptions of all principles of operation. It also contains the full list of software algorithm flowcharts, and a brief section on compatibility with the Intel 28F008SA. A significant 28F016SV change occurred between datasheet revisions 290528-003 and 290528-004. This change centers around the addition of a 3/5# pin to the device’s pinout configuration. Figures 2 and 3 show the 3/5# pin assignment for TSOP and SSOP Type 1 packages. Intel recommends that all customers obtain the latest revisions of 28F016SV documentation.
1.1 Enhanced Features
The 28F016SV is backwards compatible with the 28F016SA and offers the following enhancements:
- SmartVoltage Technology Selectable 5V or 12V V PP
- VPP Level Bit in Block Status Register
- Additional RY/BY# Configuration Pulse-On-Program/Erase
- Additional Upload Device Information Command Feedback Device Proliferation Code Device Configuration Code
1.2 Product Overview
The 28F016SV is a high-performance, 16-Mbit (16,777,216-bit) block erasable, nonvolatile random access memory, organized as either 1 Mword x 16 or 2 Mbyte x 8. The 28F016SV includes thirty-two 64-KB (65,536 byte) blocks or thirty-two 32-KW (32,768 word) blocks. A chip memory map is shown in Figure 4. The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and result in greater product reliability and ease-of-use. The 28F016SV incorporates SmartVoltage technology, providing V CC operation at both 3.3V and 5V and program and erase capability at VPP = 12V or 5V. Operating at VCC = 3.3V, the 28F016SV consumes approximately one half the power consumption at 5V V CC , while 5V V CC provides the highest read performance capability. VPP = 5V operation eliminates the need for a separate 12V converter, while VPP = 12V maximizes program/erase performance. In addition to the flexible program and erase voltages, the dedicated V PP gives complete code protection with VPP ≤ VPPLK . A 3/5# input pin configures the device’s internal circuitry for optimal 3.3V or 5V read/program operation. A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation. Internal Algorithm Automation allows byte/word programs and block erase operations to be executed using a Two-Program command sequence to the CUI in the same way as the 28F008SA 8-Mbit FlashFile™ memory. A super-set of commands has been added to the basic 28F008SA command-set to achieve higher program performance and provide additional capabilities. These new commands and features include:
- Page Buffer Programs to Flash
- Command Queuing Capability
- Automatic Data Programs during Erase
- Software Locking of Memory Blocks
- Two-Byte Successive Programs in 8-bit Systems
- Erase All Unlocked Blocks Writing of memory data is performed in either byte or word increments typically within 6 µs (12V V PP )—a 33% improvement over the 28F008SA. A block erase operation erases one of the 32 blocks in typically 0.6 sec (12V V PP ), independent of the other blocks, which is about a 65% improvement over the 28F008SA.
28F016SV FlashFile™ MEMORY E Each block can be written and erased a minimum of 100,000 cycles. Systems can achieve one million Block Erase Cycles by providing wear- leveling algorithms and graceful block retirement. These techniques have already been employed in many flash file systems and hard disk drive designs. The 28F016SV incorporates two Page Buffers of 256 bytes (128 words) each to allow page data programs. This feature can improve a system program performance by up to 4.8 times over previous flash memory devices, which have no Page Buffers. All operations are started by a sequence of Program commands to the device. Three Status Registers (described in detail later in this datasheet) and a RY/BY# output pin provide information on the progress of the requested operation. While the 28F008SA requires an operation to complete before the next operation can be requested, the 28F016SV allows queuing of the next operation while the memory executes the current operation. This eliminates system overhead when writing several bytes in a row to the array or erasing several blocks at the same time. The 28F016SV can also perform program operations to one block of memory while performing erase of another block. The 28F016SV provides selectable block locking to protect code or data such as Device Drivers, PCMCIA card information, ROM-Executable O/S or Application Code. Each block has an associated nonvolatile lock-bit which determines the lock status of the block. In addition, the 28F016SV has a master Write Protect pin (WP#) which prevents any modifications to memory blocks whose lock-bits are set. The 28F016SV contains three types of Status Registers to accomplish various functions:
- A Compatible Status Register (CSR) which is 100% compatible with the 28F008SA FlashFile memory Status Register. The CSR, when used alone, provides a straightforward upgrade capability to the 28F016SV from a 28F008SA- based design.
- A Global Status Register (GSR) which informs the system of command Queue status, Page Buffer status, and overall Write State Machine (WSM) status.
- 32 Block Status Registers (BSRs) which provide block-specific status information such as the block lock-bit status. The GSR and BSR memory maps for byte-wide and word-wide modes are shown in Figures 5 and 6. The 28F016SV incorporates an open drain RY/BY# output pin. This feature allows the user to OR-tie many RY/BY# pins together in a multiple memory configuration such as a Resident Flash Array. Other configurations of the RY/BY# pin are enabled via special CUI commands and are described in detail in the 16-Mbit Flash Product Family User’s Manual. The 28F016SV’s enhanced Upload Device Information command provides access to additional information that the 28F016SA previously did not offer. This command uploads the Device Revision Number, Device Proliferation Code and Device Configuration Code to the page buffer. The Device Proliferation Code for the 28F016SV is 01H, and the Device Configuration Code identifies the current RY/BY# configuration. Section 4.4 documents the exact page buffer address locations for all uploaded information. A subsequent Page Buffer Swap and Page Buffer Read command sequence is necessary to read the correct device information. The 28F016SV also incorporates a dual chip- enable function with two input pins, CE 0# and CE 1#. These pins have exactly the same functionality as the regular chip-enable pin, CE#, on the 28F008SA. For minimum chip designs, CE 1# may be tied to ground and system logic may use CE0# as the chip enable input. The 28F016SV uses the logical combination of these two signals to enable or disable the entire chip. Both CE 0# and CE 1# must be active low to enable the device. If either one becomes inactive, the chip will be disabled. This feature, along with the open drain RY/BY# pin, allows the system designer to reduce the number of control pins used in a large array of 16-Mbit devices. The BYTE# pin allows either x8 or x16 read/programs to the 28F016SV. BYTE# at logic low selects 8-bit mode with address A 0 selecting between the low byte and high byte. On the other hand, BYTE# at logic high enables 16-bit operation with address A 1 becoming the lowest
E 28F016SV FlashFile™ MEMORY order address and address A0 is not used (don’t care). A device block diagram is shown in Figure The 28F016SV is specified for a maximum access time of 65 ns (t ACC ) at 5V operation (4.75V to 5.25V) over the commercial temperature range (0°C to +70°C). A corresponding maximum access time of 75 ns at 3.3V (3.0V to 3.6V and 0°C to +70°C) is achieved for reduced power consumption applications. The 28F016SV incorporates an Automatic Power Saving (APS) feature, which substantially reduces the active current when the device is in static mode of operation (addresses not switching). In APS mode, the typical I CC current is 1 mA at 5V (3.0 mA at 3.3V). A deep power-down mode of operation is invoked when the RP# (called PWD# on the 28F008SA) pin transitions low. This mode brings the device power consumption to less than 2.0 µA, typically, and provides additional program protection by acting as a device reset pin during power transitions. A reset time of 400 ns (5V V CC operation) is required from RP# switching high until outputs are again valid. In the Deep Power- Down state, the WSM is reset (any current operation will abort) and the CSR, GSR and BSR registers are cleared. A CMOS standby mode of operation is enabled when either CE 0# or CE1# transitions high and RP# stays high with all input control pins at CMOS levels. In this mode, the device typically draws an I CC standby current of 70 µA at 5V VCC . The 28F016SV will be available in 56-lead, 1.2 mm thick, 14 mm x 20 mm TSOP and 56-lead, 1.8 mm thick, 16 mm x 23.7 SSOP Type I packages. The form factor and pinout of these two packages allow for very high board layout densities.
2.0 DEVICE PINOUT
The 28F016SV 56-lead TSOP and 56-lead SSOP Type I pinout configurations are shown in Figures 2 and 3.
Figure 1. 28F016SV Block Diagram
E 28F016SV FlashFile™ MEMORY
2.1 Lead Descriptions
Symbol Type Name and Function A0 INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8 mode. This address is latched in x8 data programs. Not used in x16 mode (i.e., the A 0 input buffer is turned off when BYTE# is high). A1–A15 INPUT WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block. A6–15 selects 1 of 1024 rows, and A1–5 selects 16 of 512 columns. These addresses are latched during data programs. A16–A20 INPUT BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These addresses are latched during data programs, erase and lock block operations. DQ 0–DQ 7 INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI program cycles. Outputs array, buffer, identifier or status data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. DQ 8–DQ 15 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 data program operations. Outputs array, buffer or identifier data in the appropriate read mode; not used for Status Register reads. Floated when the chip is de- selected or the outputs are disabled. CE 0#, CE1# INPUT CHIP ENABLE INPUTS : Activate the device’s control logic, input buffers, decoders and sense amplifiers. With either CE0# or CE1# high, the device is de-selected and power consumption reduces to standby levels upon completion of any current data program or erase operations. Both CE and CE1# must be low to select the device. All timing specifications are the same for both signals. Device Selection occurs with the latter falling edge of CE 0# or CE1#. The first rising edge of CE 0# or CE1# disables the device. RP# INPUT RESET/POWER-DOWN: RP# low places the device in a deep power- down state. All circuits that consume static power, even those circuits enabled in standby mode, are turned off. When returning from deep power-down, a recovery time of t PHQV is required to allow these circuits to power-up. When RP# goes low, any current or pending WSM operation(s) are terminated, and the device is reset. All Status Registers return to ready (with all status flags cleared). Exit from deep power-down places the device in read array mode. OE# INPUT OUTPUT ENABLE: Gates device data through the output buffers when low. The outputs float to tri-state off when OE# is high. NOTE: CE x# overrides OE#, and OE# overrides WE#. WE# INPUT WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers and Address Queue Latches. WE# is active low, and latches both address and data (command or array) on its rising edge. Page Buffer addresses are latched on the falling edge of WE#.
28F016SV FlashFile™ MEMORY E
2.1 Lead Descriptions (Continued)
Symbol Type Name and Function RY/BY# OPEN DRAIN OUTPUT READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the WSM is busy performing an operation. RY/BY# floating indicates that the WSM is ready for new operations (or WSM has completed all pending operations), or erase is suspended, or the device is in deep power-down mode. This output is always active (i.e., not floated to tri-state off when OE# or CE 0#, CE1# are high), except if a RY/BY# Pin Disable command is issued. WP# INPUT WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile lock-bit for each block. When WP# is low, those locked blocks as reflected by the Block-Lock Status bits (BSR.6), are protected from inadvertent data programs or erases. When WP# is high, all blocks can be written or erased regardless of the state of the lock-bits. The WP# input buffer is disabled when RP# transitions low (deep power-down mode). BYTE# INPUT BYTE ENABLE: BYTE# low places device in x8 mode. All data is then input or output on DQ0–7, and DQ8–15 float. Address A0 selects between the high and low byte. BYTE# high places the device in x16 mode, and turns off the A 0 input buffer. Address A1, then becomes the lowest order address. 3/5# INPUT 3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V operation. 3/5# low configures internal circuits for 5V operation. NOTE: Reading the array with 3/5# high in a 5V system could damage the device. Reference the power-up and reset timings (Section 5.7) for 3/5# switching delay to valid data. VPP SUPPLY PROGRAM/ERASE POWER SUPPLY (12V ± 0.6V, 5V ± 0.5V) : For erasing memory array blocks or writing words/bytes/pages into the flash array. V PP = 5V ± 0.5V eliminates the need for a 12V converter, while connection to 12V ± 0.6V maximizes Program/Erase Performance. NOTE: Successful completion of program and erase attempts is inhibited with VPP at or below 1.5V. Program and erase attempts with VPP between 1.5V and 4.5V, between 5.5V and 11.4V, and above 12.6V produce spurious results and should not be attempted. To switch 3.3V to 5V (or vice versa), first ramp VCC down to GND, and then power to the new VCC voltage. Do not leave any power pins floating. GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating. NC NO CONNECT: Lead may be driven or left floating.
56-lead TSOP Mechanical Diagrams and dimensions are shown at the end of this datasheet. Figure 2. 28F016SV 56-Lead TSOP Pinout Configuration
56-lead SSOP Mechanical Diagrams and dimensions are shown at the end of this datasheet. Figure 3. 56-Lead SSOP Pinout Configuration
3.0 MEMORY MAPS
Figure 4. 28F016SV Memory Maps (Byte-Wide and Word-Wide Modes)
3.1 Extended Status Registers Memory Map
Figure 5. Extended Status Register Memory Figure 6. Extended Status Register Memory
E 28F016SV FlashFile™ MEMORY
4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
4.1 Bus Operations for Word-Wide Mode (BYTE# = VIH)
Mode Notes RP# CE 1#C E 0# OE# WE# A 1 DQ 0–15 RY/BY# Read 1,2,7 V IH VIL VIL VIL VIH XD OUT X Output Disable 1,6,7 V IH VIL VIL VIH VIH X High Z X Standby 1,6,7 V IH VIL VIH VIH VIH VIL VIH X X X High Z X Deep Power-Down 1,3 V IL XXXXX High Z V OH Manufacturer ID 4 V IH VIL VIL VIL VIH VIL 0089H V OH Device ID 4,8 V IH VIL VIL VIL VIH VIH 66A0H V OH Write 1,5,6 V IH VIL VIL VIH VIL XD IN X
4.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL)
Mode Notes RP# CE 1#C E 0# OE# WE# A 0 DQ 0–7 RY/BY# Read 1,2,7 V IH VIL VIL VIL VIH XD OUT X Output Disable 1,6,7 V IH VIL VIL VIH VIH X High Z X Standby 1,6,7 V IH VIL VIH VIH VIH VIL VIH X X X High Z X Deep Power-Down 1,3 V IL XXXXX High Z V OH Manufacturer ID 4 V IH VIL VIL VIL VIH VIL 89H V OH Device ID 4,8 V IH VIL VIL VIL VIH VIH A0H V OH Write 1,5,6 V IH VIL VIL VIH VIL XD IN X NOTES: 1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH . 2. RY/BY# output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode. RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM operation is in progress. 3. RP# at GND ± 0.2V ensures the lowest deep power-down current. 4. A 0 and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. A0 and A1 at VIH provide device ID codes in x8 and x16 modes respectively. All other addresses are set to zero. 5. Commands for erase, data program, or lock-block operations can only be completed successfully when VPP = VPPH1 or VPP = VPPH2 . 6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes to VOH when the WSM is not busy or in erase suspend mode. 7. RY/BY# may be at VOL while the WSM is busy performing various operations (for example, a Status Register read during a program operation). 8. The 28F016SV shares an identical device identifier (66A0H in word-wide mode, A0H in byte-wide mode) with the 28F016SA. See application note AP-393 28F016SV Compatibility with 28F016SA for software and hardware techniques to differentiate between the 28F016SV and 28F016SA.
28F016SV FlashFile™ MEMORY E 4.3 28F008SA—Compatible Mode Command Bus Definitions First Bus Cycle Second Bus Cycle Command Notes Oper Addr Data (4) Oper Addr Data (4) Read Array Write X xxFFH Read AA AD Intelligent Identifier 1 Write X xx90H Read IA ID Read Compatible Status Register 2 Write X xx70H Read X CSRD Clear Status Register 3 Write X xx50H Word/Byte Program Write X xx40H Write PA PD Alternate Word/Byte Program Write X xx10H Write PA PD Block Erase/Confirm Write X xx20H Write BA xxD0H Erase Suspend/Resume Write X xxB0H Write X xxD0H ADDRESS DATA AA = Array Address AD = Array Data BA = Block Address CSRD = CSR Data IA = Identifier Address ID = Identifier Data PA = Program Address PD = Program Data X = Don’t Care NOTES: 1. Following the Intelligent Identifier command, two Read operations access the manufacturer and device signature codes. 2. The CSR is automatically available after device enters data program, erase, or suspend operations. definitions. 4. The upper byte of the data bus (DQ 8–15) during command writes is a “Don’t Care” in x16 operation of the device.
E 28F016SV FlashFile™ MEMORY 4.4 28F016SV—Performance Enhancement Command Bus Definitions Command Mode Notes First Bus Cycle Second Bus Cycle Third Bus Cycle Oper Addr Data (13) Oper Addr Data (13) Oper Addr Data Read Extended Status Register
1 Write X xx71H Read RA GSRD
Page Buffer Swap 7 Write X xx72H Read Page Buffer Write X xx75H Read PBA PD Single Load to Page Buffer Write X xx74H Write PBA PD Sequential Load to Page Buffer x8 4,6,10 Write X xxE0H Write X BCL Write X BCH x16 4,5,6,10 Write X xxE0H Write X WCL Write X WCH Page Buffer Write to Flash x8 3,4,9,10 Write X xx0CH Write A 0 BC(L,H) Write PA BC(H,L) x16 4,5,10 Write X xx0CH Write X WCL Write PA WCH Two-Byte Program x8 3 Write X xxFBH Write A 0 WD(L,H) Write PA WD(H,L) Lock Block/Confirm Write X xx77H Write BA xxD0H Upload Status Bits/Confirm
2 Write X xx97H Write X xxD0H
11 Write X xx99H Write X xxD0H
Write X xxA7H Write X xxD0H RY/BY# Enable to Level-Mode
8 Write X xx96H Write X xx01H
RY/BY# Pulse-On-Write
8 Write X xx96H Write X xx02H
RY/BY# Pulse-On-Erase
8 Write X xx96H Write X xx03H
RY/BY# Disable 8 Write X xx96H Write X xx04H RY/BY# Pulse-On- Write/Erase
8 Write X xx96H Write X xx05H
BA = Block Address AD = Array Data WC (L,H) = Word Count (Low, High) PBA = Page Buffer Address PD = Page Buffer Data BC (L,H) = Byte Count (Low, High) RA = Extended Register Address BSRD = BSR Data WD (L,H) = Write Data (Low, High) PA = Program Address GSRD = GSR Data X = Don’t Care
28F016SV FlashFile™ MEMORY E NOTES: 1. RA can be the GSR address or any BSR address. See Figures 4 and 5 for Extended Status Register memory maps. 2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the actual lock-bit status. 3. A 0 is automatically complemented to load second byte of data. BYTE# must be at VIL. A0 value determines which WD/BC is supplied first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH. 4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size, and to avoid writing the Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page Buffer expandability. 5. In x16 mode, only the lower byte DQ 0–7 is used for WCL and WCH. The upper byte DQ8–15 is a don’t care. 6. PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown. 7. This command allows the user to swap between available Page Buffers (0 or 1). 8. These commands reconfigure RY/BY# output to one of three pulse-modes or enable and disable the RY/BY# function. 9. Program address, PA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the 16-Mbit Flash Product Family User’s Manual. 10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1. 11. After writing the Upload Device Information command and the Confirm command, the following information is output at Page Buffer addresses specified below: Address Information 06H, 07H (Byte Mode) Device Revision Number 03H (Word Mode) Device Revision Number 1EH (Byte Mode) Device Configuration Code 0FH (DQ 0–7)(Word Mode) Device Configuration Code 1FH (Byte Mode) Device Proliferation Code (01H) 0FH (DQ 8–15)(Word Mode) Device Proliferation Code (01H) A page buffer swap followed by a page buffer read sequence is necessary to access this information. The contents of all other Page Buffer locations, after the Upload Device Information command is written, are reserved for future implementation by Intel Corporation. See Section 4.8 for a description of the Device Configuration Code. This code also corresponds to data written to the 28F016SV after writing the RY/BY# Reconfiguration command. 12.To ensure that the 28F016SV’s power consumption during sleep mode reaches the deep power-down current level, the system also needs to de-select the chip by taking either or both CE 0# or CE1# high. 13. The upper byte of the data bus (DQ8–15) during command writes is a “Don’t Care” in x16 operation of the device.
E 28F016SV FlashFile™ MEMORY
4.5 Compatible Status Register
WSMS ESS ES DWS VPPS R R R 76543210 NOTES: CSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy RY/BY# output or WSMS bit must be checked to determine completion of an operation (erase, erase suspend, or data program) before the appropriate Status bit (ESS, ES or DWS) is checked for success. CSR.6 = ERASE-SUSPEND STATUS 1 = Erase Suspended 0 = Erase in Progress/Completed CSR.5 = ERASE STATUS 1 = Error in Block Erasure 0 = Successful Block Erase If DWS and ES are set to “1” during an erase attempt, an improper command sequence was entered. Clear the CSR and attempt the operation again. CSR.4 = DATA-WRITE STATUS 1 = Error in Data Program 0 = Data Program Successful CSR.3 = VPP STATUS 1 = VPP Error Detect, Operation Abort 0 = VPP OK The VPPS bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates VPP ’s level only after the Data Program or Erase command sequences have been entered, and informs the system if V PP has not been switched on. VPPS is not guaranteed to report accurate feedback between V PPLK (max) and VPPH1 (min), between VPPH1 (max) and VPPH2 (min) and above VPPH2 (max). CSR.2–0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the CSR.
28F016SV FlashFile™ MEMORY E
4.6 Global Status Register
WSMS OSS DOS DSS QS PBAS PBS PBSS 76543210 NOTES: GSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy [1] RY/BY# output or WSMS bit must be checked to determine completion of an operation (block lock, suspend, any RY/BY# reconfiguration, Upload Status Bits, erase or data program) before the appropriate Status bit (OSS or DOS) is checked for success. GSR.6 = OPERATION SUSPEND STATUS 1 = Operation Suspended 0 = Operation in Progress/Completed GSR.5 = DEVICE OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running GSR.4 = DEVICE SLEEP STATUS 1 = Device in Sleep 0 = Device Not in Sleep MATRIX 5/4 0 0 = Operation Successful or Currently Running 0 1 = Device in Sleep Mode or Pending Sleep 1 0 = Operation Unsuccessful 1 1 = Operation Unsuccessful or Aborted If operation currently running, then GSR.7 = 0. If device pending sleep, then GSR.7 = 0. Operation aborted: Unsuccessful due to Abort command. GSR.3 = QUEUE STATUS 1 = Queue Full 0 = Queue Available GSR.2 = PAGE BUFFER AVAILABLE STATUS 1 = One or Two Page Buffers Available 0 = No Page Buffer Available The device contains two Page Buffers. GSR.1 = PAGE BUFFER STATUS 1 = Selected Page Buffer Ready 0 = Selected Page Buffer Busy Selected Page Buffer is currently busy with WSM operation GSR.0 = PAGE BUFFER SELECT STATUS 1 = Page Buffer 1 Selected 0 = Page Buffer 0 Selected NOTE: 1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued operations are completed.
E 28F016SV FlashFile™ MEMORY
4.7 Block Status Register
BS BLS BOS BOAS QS VPPS VPPL R 76543210 NOTES: BSR.7 = BLOCK STATUS 1 = Ready 0 = Busy [1] RY/BY# output or BS bit must be checked to determine completion of an operation (block lock, suspend, erase or data program) before the appropriate Status bits (BOS, BLS) is checked for success. BSR.6 = BLOCK LOCK STATUS 1 = Block Unlocked for Program/Erase 0 = Block Locked for Program/Erase BSR.5 = BLOCK OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running BSR.4 = BLOCK OPERATION ABORT STATUS 1 = Operation Aborted 0 = Operation Not Aborted The BOAS bit will not be set until BSR.7 = 1. MATRIX 5/4 0 0 = Operation Successful or Currently Running 0 1 = Not a Valid Combination 1 0 = Operation Unsuccessful 1 1 = Operation Aborted Operation halted via Abort command. BSR.3 = QUEUE STATUS 1 = Queue Full 0 = Queue Available BSR.2 = VPP STATUS 1 = VPP Error Detect, Operation Abort 0 = VPP OK BSR.1 = VPP LEVEL 1 = VPP Detected at 5V ± 10% 0 = VPP Detected at 12V ± 5% BSR.1 is not guaranteed to report accurate feedback between the VPPH1 and VPPH2 voltage ranges. Programs and erases with VPP between VPPLK (max) and VPPH1 (min), between VPPH1 (max) and VPPH2 (min), and above VPPH2 (max) produce spurious results and should not be attempted. BSR.1 was a RESERVED bit on the 28F016SA. BSR.0 = RESERVED FOR FUTURE ENHANCEMENTS This bits is reserved for future use; mask it out when polling the BSRs. NOTE: 1. When multiple operations are queued, checking BSR.7 only provides indication of completion or that particular block. GSR.7 provides indication when all queued operations are completed.
28F016SV FlashFile™ MEMORY E
4.8 Device Configuration Code
NOTES: DCC.2-DCC.0 = RY/BY# CONFIGURATION (RB2–RB0) 001 =Level Mode (Default) 010 =Pulse-On-Program 011 = Pulse-On-Erase 100 = RY/BY# Disabled 101 = Pulse-On-Program/Erase Undocumented combinations of RB2–RB0 are reserved by Intel Corporation for future implementations and should not be used. DCC.7 –DCC.3 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when reading the Device Configuration Code. Set these bits to “0” when writing the desired RY/BY# configuration to the device.
E 28F016SV FlashFile™ MEMORY
5.0 ELECTRICAL SPECIFICATIONS
5.1 Absolute Maximum Ratings*
NOTICE: This is a production datasheet. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. *WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. VCC = 3.3V ± 0.3V Systems Sym Parameter Notes Min Max Units Test Conditions TA Operating Temperature, Commercial 1 0 70 °C Ambient Temperature VCC VCC with Respect to GND 2 –0.2 7.0 V VPP VPP Supply Voltage with Respect to GND 2,3 –0.2 14.0 V V Voltage on Any Pin (except VCC ,VPP ) with Respect to GND 2,5 –0.5 VCC + 0.5 V I Current into Any Non-Supply Pin 5 ± 30 mA IOUT Output Short Circuit Current 4 100 mA VCC = 5V ± 0.5V, 5V ± 0.25V Systems(6) Sym Parameter Notes Min Max Units Test Conditions TA Operating Temperature, Commercial 1 0 70 °C Ambient Temperature VCC VCC with Respect to GND 2 –0.2 7.0 V VPP VPP Supply Voltage with Respect to GND 2,3 –0.2 14.0 V V Voltage on Any Pin (except VCC ,VPP ) with Respect to GND 2,5 –2.0 7.0 V I Current into Any Non-Supply Pin 5 ± 30 mA IOUT Output Short Circuit Current 4 100 mA NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is –0.5V on input/output pins. During transitions, this level may undershoot to –2.0V for periods <20 ns. Maximum DC voltage on input/output pins is V CC + 0.5V which, during transitions, may overshoot to VCC + 2.0V for periods <20 ns. 3. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. This specification also applies to pins marked “NC.” 6. 5% V CC specifications refer to the 28F016SV-065 and 28F016SV-070 in its high speed test configuration.
28F016SV FlashFile™ MEMORY E
5.2 Capacitance
For a 3.3V ± 0.3V System: Sym Parameter Notes Typ Max Units Test Conditions C IN Capacitance Looking into an Address/Control Pin 16 8 p F T A = +25°C, f = 1.0 MHz C OUT Capacitance Looking into an Output Pin 1 8 12 pF T A = +25°C, f = 1.0 MHz C LOAD Load Capacitance Driven by Outputs for Timing Specifications 1,2 50 pF For 5V ± 0.5V, 5V ± 0.25V System: Sym Parameter Notes Typ Max Units Test Conditions C IN Capacitance Looking into an Address/Control Pin 16 8 p F T A = +25°C, f = 1.0 MHz C OUT Capacitance Looking into an Output Pin 1 8 12 pF T A = +25°C, f = 1.0 MHz C LOAD Load Capacitance Driven by Outputs for Timing Specifications 1,2 100 pF For V CC = 5V ± 0.5V 30 pF For V CC = 5V ± 0.25V NOTE: 1. Sampled, not 100% tested. Guaranteed by design. 2. To obtain iBIS models for the 28F016SV, please contact your local Intel/Distribution Sales Office.
E 28F016SV FlashFile™ MEMORY
5.3 DC Characteristics
VCC = 3.3V ± 10%V, TA = 0°C to +70°C, –40°C to +70°C 3/5# = Pin Set High for 3.3V Operations Temp Commercial Extended Sym Parameter Notes Min Typ Max Min Typ Max Units Test Conditions ILI Input Load Current 1 ± 1 ± 1µ A V CC = VCC Max VIN = VCC or GND ILO Output Leakage Current 1 ± 10 ± 10 µA V CC = VCC Max VOUT = VCC or GND ICCS VCC Standby Current 1,5 70 130 70 130 µA V CC = VCC Max CE 0#, CE1#, RP# = VCC ± 0.2V BYTE#, WP#, 3/5# = VCC ±0.2V or GND ± 0.2V 1 4 1 4 mA V CC = VCC Max CE 0#, CE1#, RP# = VIH BYTE#, WP#, 3/5# = VIH or VIL ICCD VCC Deep Power-Down Current 1 2 10 5 15 µA RP# = GND ± 0.2V BYTE# = VCC ± 0.2V or GND ± 0.2V ICCR 1V CC Read Current 1,4,5 40 50 40 55 mA V CC = VCC Max CMOS: CE 0#, CE1# = GND ± 0.2V, BYTE# = GND ± 0.2V or V CC ± 0.2V, Inputs = GND ± 0.2V or V CC ± 0.2V TTL: CE0#, CE1# = VIL, BYTE# = VIL or V IH,Inputs = VIL or VIH f = 8 MHz, IOUT = 0 mA
28F016SV FlashFile™ MEMORY E
5.3 DC Characteristics (Continued)
VCC = 3.3V ± 10%V, TA = 0°C to +70°C, –40°C to +70°C 3/5# = Pin Set High for 3.3V Operations Temp Commercial Extended Sym Parameter Notes Min Typ Max Min Typ Max Units Test Conditions ICCR 2V CC Read Current 1,4, 5,6 20 30 20 35 mA V CC = VCC Max CMOS: CE 0#, CE1# = GND ± 0.2V, BYTE# = GND ± 0.2V or V CC ± 0.2V, Inputs = GND ± 0.2V or V CC ± 0.2V TTL: CE0#, CE1# = VIL, BYTE# = VIL or VIH, Inputs = VIL or VIH f = 4 MHz, IOUT = 0 mA ICCW VCC Program Current for Word or Byte 1,6 8 12 8 12 mA V PP = 12V ± 5% Program in Progress 8 17 8 17 mA V PP = 5V ± 10% Program in Progress ICCE VCC Block Erase Current 1,6 6 12 6 12 mA V PP = 12V ± 5% Block Erase in Progress 9 17 9 17 mA V PP = 5V ± 10% Block Erase in Progress ICCES VCC Erase Suspend Current 1,2 1 4 1 4 mA CE 0#, CE1# = VIH Block Erase Suspended IPPS VPP Standby/ 1 ± 1 ± 10 ± 3 ± 10 µA V PP ≤ VCC IPPR Read Current 30 200 70 200 µA V PP > VCC IPPD VPP Deep Power-Down Current 1 0.2 5 0.2 5 µA RP# = GND ± 0.2V
E 28F016SV FlashFile™ MEMORY VCC = 3.3V ± 10%V, TA = 0°C to +70°C, –40°C to +70°C 3/5# = Pin Set High for 3.3V Operations Temp Commercial Extended Sym Parameter Notes Min Typ Max Min Typ Max Units Test Conditions IPPW VPP Program Current for Word or Byte 1,6 10 15 10 15 mA V PP = 12V ± 5% Program in Progress 15 25 15 25 mA V PP = 5V ± 10% Program in Progress IPPE VPP Erase Current 1,6 4 10 4 10 mA V PP = 12V ± 5% Block Erase in Progress 14 20 14 20 mA V PP = 5V ± 10% Block Erase in Progress IPPES VPP Erase Suspend Current 1 30 200 70 200 µA V PP = VPPH1 or VPPH2 Block Erase Suspended VIL Input Low Voltage 6 –0.3 0.8 0.8 V VIH Input High Voltage 6 2.0 V CC + 0.3 VCC + 0.3 V VOL Output Low Voltage 6 0.4 0.4 V V CC = VCC Min and IOL = 4 mA
28F016SV FlashFile™ MEMORY E VCC = 3.3V ± 0.3V, TA = 0°C to +70°C, –40°C to +85°C 3/5# = Pin Set High for 3.3V Operations Temp Comm/Ext Sym Parameter Notes Min Typ Max Units Test Conditions VOH 1 Output High Voltage 6 2.4 VCC – VV CC = VCC Min IOH = –2.0 mA VOH 2 6 0.2 V V CC = VCC Min IOH = –100 µA VPPL K VPP Program/Erase Lock Voltage 3,6 0.0 1.5 V VPPH1 VPP during Program/Erase Operations 3 4.5 5.0 5.5 V VPPH2 VPP during Program/Erase Operations 3 11.4 12.0 12.6 V VLKO VCC Program/Erase Lock Voltage 2.0 V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, VPP = 12V or 5V, T = +25°C. These currents are valid for all product versions (package and speeds). 2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR . 3. Block erases, word/byte programs and lock block operations are inhibited when VPP ≤ VPPLK and not guaranteed in the ranges between VPPLK (max) and VPPH1 (min), between VPPH1 (max) and VPPH2 (min) and above VPPH2 (max). 4. Automatic Power Savings (APS) reduces ICCR to 3.0 mA typical in static operation. 6. Sampled, but not 100% tested. Guaranteed by design.
E 28F016SV FlashFile™ MEMORY
5.4 DC Characteristics
VCC = 5V ± 0.5V, 5V ± 0.25V, TA = 0°C to +70°C, –40°C to +85°C 3/5# = Pin Set Low for 5V Operations Temp Commercial Extended Sym Parameter Notes Min Typ Max Min Typ Max Units Test Conditions ILI Input Load Current 1± 1 ± 1 µ A V CC = VCC Max VIN = VCC or GND ILO Output Leakage Current 1 ± 10 ± 10 µA V CC = VCC Max VOUT = VCC or GND ICCS VCC Standby Current 1,5 70 130 70 130 µA V CC = VCC Max CE 0#, CE1#, RP# = VCC ± 0.2V BYTE#, WP#, 3/5# = VCC ± 0.2V or GND ± 0.2V 2 4 2 4 mA V CC = VCC Max, CE 0#, CE1#, RP# = VIH BYTE#, WP#, 3/5# = VIH or VIL ICCD VCC Deep Power-Down Current 1 2 10 5 15 µA RP# = GND ± 0.2V BYTE# = VCC ± 0.2V or GND ± 0.2V ICCR 1V CC Read Current 1,4,5 75 95 75 105 mA V CC = VCC Max CMOS: CE 0#, CE1# = GND ± 0.2V, BYTE# = GND ± 0.2V or V CC ± 0.2V, Inputs = GND ± 0.2V or, V CC ± 0.2V TTL: CE0#, CE1# = V IL, BYTE# = VIL or V IH, Inputs = V IL or VIH f = 10 MHz, IOUT = 0 mA
28F016SV FlashFile™ MEMORY E
5.4 DC Characteristics (Continued)
VCC = 5V ± 0.5V, 5V ± 0.25V, TA = 0°C to +70°C, –40°C to +85°C 3/5# = Pin Set Low for 5V Operations Temp Commercial Extended Sym Parameter Notes Min Typ Max Min Typ Max Units Test Conditions ICCR 2V CC Read Current 1,4, 5,6 45 55 45 60 mA V CC = VCC Max CMOS: CE 0#, CE1# = GND ± 0.2V, BYTE# = GND ± 0.2V or V CC ± 0.2V, Inputs = GND ± 0.2V or V CC ± 0.2V TTL: CE0#, CE1# = V IL, BYTE# = VIL or V IH, Inputs = V IL or VIH f = 5 MHz, IOUT = 0 mA ICCW VCC Program Current for Word or Byte 1,6 25 35 25 35 mA V PP = 12V ± 5% Program in Progress 25 40 25 40 mA V PP = 5V ± 10% Program in Progress ICCE VCC Block Erase Current 1,6 18 25 18 25 mA V PP = 12V ± 5% Block Erase in Progress 20 30 20 30 mA V PP = 5V ± 10% Block Erase in Progress ICCES VCC Erase Suspend Current 1,2 2 4 2 4 mA CE 0#, CE1# = VIH Block Erase Suspended IPPS VPP Standby /Read 1 ± 1 ± 10 ± 3 ± 10 µA V PP ≤ VCC IPPR Current 30 200 70 200 µA V PP > VCC IPPD VPP Deep Power- Down Current 1 0.2 5 0.2 5 µA RP# = GND ± 0.2V
E 28F016SV FlashFile™ MEMORY VCC = 5V ± 0.5V, 5V ± 0.25V, TA = 0°C to +70°C, –40°C to +85°C 3/5# = Pin Set Low for 5V Operations Temp Commercial Extended Sym Parameter Notes Min Typ Max Min Typ Max Units Test Conditions IPPW VPP Program Current for Word or Byte 1,6 7 12 7 12 mA V PP = 12V ± 5% Program in Progress 17 22 17 22 mA V PP = 5V ± 10% Program in Progress IPPE VPP Block Erase Current 1,6 5 10 5 10 mA V PP = 12V ± 5% Block Erase in Progress 16 20 16 20 mA V PP = 5V ± 10% Block Erase in Progress IPPES VPP Erase Suspend Current 1 30 200 30 200 µA V PP = VPPH1 or VPPH2 Block Erase Suspended VIL Input Low Voltage 6 –0.5 0.8 0.8 V VIH Input High Voltage 6 2.0 V CC + 0.5 VCC + 0.5 V
28F016SV FlashFile™ MEMORY E VCC = 5V ± 0.5V, 5V ± 0.25V, TA = 0°C to +70°C, –40°C to +85°C 3/5# = Pin Set Low for 5V Operations Temp Comm/Extended Sym Parameter Notes Min Typ Max Units Test Conditions VOL Output Low Voltage 6 0.45 V V CC = VCC Min IOL = 5.8 mA VOH 1 Output High Voltage 6 0.85 VCC VV CC = VCC Min IOH = –2.5 mA VOH 26 V CC – 0.4 VCC = VCC Min IOH = –100 µA VPPL K VPP Program/Erase Lock Voltage 3,6 0.0 1.5 V VPPH1 VPP during Program/Erase Operations 4.5 5.0 5.5 V VPPH2 VPP during Program/Erase Operations 11.4 12.0 12.6 V VLKO VCC Program/Erase Lock Voltage 2.0 V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5V, VPP = 12V or 5V, T = 25°C. These currents are valid for all product versions (package and speeds) and are specified for a CMOS rise/fall time (10% to 90%) of <5 ns and a TTL rise/fall time of <10 ns. 2. I CCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Block erases, word/byte programs and lock block operations are inhibited when VPP ≤ VPPLK and not guaranteed in the ranges between VPPLK (max) and VPPH1 (min), between VPPH1 (max) and VPPH2 (min) and above VPPH2 (max). 4. Automatic Power Saving (APS) reduces ICCR to 1 mA typical in Static operation. 6. Sampled, not 100% tested. Guaranteed by design.
E 28F016SV FlashFile™ MEMORY
5.5 Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.5V. For 5V systems use the standard JEDEC cross point definitions (standard testing) or from where signals cross 1.5V (high speed testing). Each timing parameter consists of 5 characters. Some common examples are defined below: tCE tELQV time(t) from CE# (E) going low (L) to the outputs (Q) becoming valid (V) tOE tGLQV time(t) from OE # (G) going low (L) to the outputs (Q) becoming valid (V) tACC tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V) tAS tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H) tDH tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X) Pin Characters Pin States A Address Inputs H High D Data Inputs L Low Q Data Outputs V Valid E CE# (Chip Enable) X Driven, but Not Necessarily Valid F BYTE# (Byte Enable) Z High Impedance G OE# (Output Enable) W WE# (Write Enable) P RP# (Deep Power-Down Pin) R RY/BY# (Ready Busy) V Any Voltage Level Y 3/5# Pin 5V V CC at 4.5V Minimum 3V V CC at 3.0V Minimum
28F016SV FlashFile™ MEMORY E
5.6 AC Characteristics—Read Only Operations(1)
VCC = 3.3V ± 0.3V, TA = 0°C to +70°C, –40°C to +85°C Temp Commercial Extended Commercial Sym Parameter Speed –75 –100 –120 Units Notes Min Max Min Max Min Max tAVAV Read Cycle Time 75 85(10) 100 120 ns tAVQV Address to Output Delay 75 85(10) 100 120 ns tELQV CE# to Output Delay 2,8 75 85(10) 100 120 ns tPHQV RP# High to Output Delay 480 620 620 ns tGLQV OE# to Output Delay 2 40 45 45 ns tELQX CE# to Output in Low Z 3,8 0 0 0n s tEHQZ CE# to Output in High Z 3,8 30 50 50 ns tGLQX OE# to Output in Low Z 3 0 0 0n s tGHQZ OE# to Output in High Z 3 20 20 20 ns tOH Output Hold from Address, CE# or OE# Change, Whichever Occurs First 3,8 0 0 0n s tFLQV tFHQV BYTE# to Output Delay 3 75 85(10) 100 120 ns tFLQZ BYTE# Low to Output in High Z 33 0 3 0 3 0 n s tELFL tELFH CE# Low to BYTE# High or Low 3,8 5 5 5 ns Extended Status Register Reads tAVEL Address Setup to CE# Going Low 3,4, 8,9 00 0 n s tAVGL Address Setup to OE# Going Low 3,4,9 0 0 0 ns
E 28F016SV FlashFile™ MEMORY
5.6 AC Characteristics—Read Only Operations(1) (Continued)
VCC = 5V ± 0.5V, 5V ± 0.25V, TA = 0°C to +70°C, –40°C to +85°C Temp Commercial Comm/Ext Speed –65 –70 –80 Sym Parameter V CC 5V ± 5%V 5V ± 10% 5V ± 10% Units Load 30 pF 50 pF 50 pF Notes Min Max Min Max Min Max tAVAV Read Cycle Time 65 70 80 ns tAVQV Address to Output Delay 65 70 80 ns tELQV CE# to Output Delay 2,8 65 70 80 ns tPHQV RP# to Output Delay 400 480 (6) 400(7) 480 ns tGLQV OE# to Output Delay 2 30 30 (6) 35(7) 35 ns tELQX CE# to Output in Low Z 3,8 0 0 0 ns tEHQZ CE# to Output in High Z 3,8 25 25 30 ns tGLQX OE# to Output in Low Z 3 0 0 0 ns tGHQZ OE# to Output in High Z 3 15 15 20 ns tOH Output Hold from Address, CE# or OE# Change, Whichever Occurs First 3,8 0 0 0 ns tFLQV tFHQV BYTE# to Output Delay 3 65 70 80 ns tFLQZ BYTE# Low to Output in High Z 3 2 52 53 0 n s tELFL tELFH CE# Low to BYTE# High or Low 3,8 5 5 5 ns Extended Status Register Reads tAVEL Address Setup to CE# Going Low 3,4,8,9 0 0 0 ns tAVGL Address Setup to OE# Going Low 3,4,9 0 0 0 ns
28F016SV FlashFile™ MEMORY E NOTES: 1. See AC Input/Output Reference Waveforms for timing measurements, Figures 7 and 8. 2. OE# may be delayed up to t ELQV -tGLQV after the falling edge of CE#, without impacting tELQV . 3. Sampled, not 100% tested. Guaranteed by design 4. This timing parameter is used to latch the correct BSR data onto the outputs. 5. Device speeds are defined as: 65/70 ns at V CC = 5V equivalent to 75 ns at VCC = 3.3V 70/80 ns at VCC = 5V equivalent to 120 ns at VCC = 3.3V 6. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit. 7. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit. 8. CE X# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high. 9. The address setup requirement for Extended Status Register reads must only be met referenced to the falling edge of the last control signal to become active (CE0#, CE1# or OE#). For example, if CE0# and CE1# are activated prior to OE# for an Extended Status Register read, specification tAVGL must be met. On the other hand, if either CE0# or CE1# (or both) are activated after OE#, specification tAVEL must be referenced. 10. Page Buffer Reads only.
CE X # is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high. Figure 12. Read Timing Waveforms
CE X # is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high. Figure 13. BYTE# Timing Waveforms
5.7 Power-Up and Reset Timings
Figure 14. VCC Power-Up and RP# Reset Waveforms CE 0#, CE1# and OE# are switched low after Power-Up.
- The tYLPH and/or tYHPH times must be strictly followed to guarantee all other read and program specifications for the
- The power supply may start to switch concurrently with RP# going low.
- The address access time and RP# high to data valid time are shown for 5V V
28F016SV FlashFile™ MEMORY E
5.8 AC Characteristics for WE#—Controlled Command Write Operations(1)
VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; –40°C to +85°C Temp Commercial Extended Commercial Sym Parameter Speed –75 –100 –120 Unit Notes Min Typ Max Min Typ Max Min Typ Max tAVAV Write Cycle Time 75 100 120 ns tVPWH 1,2 V PP Setup to WE# Going High 3 100 100 100 ns tPHEL RP# Setup to CE# Going Low 3,7 480 480 480 ns tELWL CE# Setup to WE# Going Low 3,7 0,10 (12) 10 10 ns tAVWH Address Setup to WE# Going High 2,6 60 70 75 ns tDVWH Data Setup to WE# Going High 2,6 60 70 75 ns tWLWH WE# Pulse Width 60 70 75 ns tWHDX Data Hold from WE# High 2 5 10 10 ns tWHAX Address Hold from WE# High 2 5 10 10 ns tWHEH CE# Hold from WE# High 3,7 5 10 10 ns tWHWL WE# Pulse Width High 15 30 45 ns tGHWL Read Recovery before Write 30 0 0 n s tWHRL WE# High to RY/BY# Going Low 3 100 100 100 ns tRHPL RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 30 0 0 n s tPHWL RP# High Recovery to WE# Going Low 3 0.480 1 1 µs tWHGL Write Recovery before Read 55 75 95 ns tQVVL 1,2 V PP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 30 0 0 µ s
E 28F016SV FlashFile™ MEMORY (Continued) VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; –40°C to +85°C Temp Commercial Extended Commercial Sym Parameter Speed –75 –100 –120 Unit Notes Min Typ Max Min Typ Max Min Typ Max tWHQV 1 Duration of Program Operation 3,4,5, 5 9 TBD 5 9 TBD 5 9 TBD µs tWHQV 2 Duration of Block Erase Operation
28F016SV FlashFile™ MEMORY E (Continued) VCC = 5V ± 0.5V, 5V ± 0.25V, TA = 0°C to +70°C, –40°C to +85°C Temp Commercial Extended Speed –65 –70 –80 Sym Parameter V CC 5V ± 5% 5V ± 10% 5V ± 10% Unit Load 30 pF 50 pF 50 pF Notes Min Typ Max Min Typ Max Min Typ Max tAVAV Write Cycle Time 65 70 80 ns tVPWH 1 tVPWH 2 VPP Setup to WE# Going High 3 100 100 100 ns tPHEL RP# Setup to CE# Going Low 3,7 300 480(9) 300(10) 480 ns tELWL CE# Setup to WE# Going Low 3,7 0 0 0 ns tAVWH Address Setup to WE# Going High 2,6 40 50 (9) 40(10) 50 ns tDVWH Data Setup to WE# Going High 2,6 40 50 (9) 40(10) 50 ns tWLWH WE# Pulse Width 40 40 (9) 45(10) 50 ns tWHDX Data Hold from WE# High 20 0 0 n s tWHAX Address Hold from WE# High 2 5 10 10 ns tWHEH CE# Hold from WE# High 3,7 5 10 (9) 5(10) 10 ns tWHWL WE# Pulse Width High 15 30 (9) 15(10) 30 ns tGHWL Read Recovery before Write 30 0 0 n s tWHRL WE# High to RY/BY# Going Low 3 100 100 100 ns tRHPL RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 30 0 0 n s
E 28F016SV FlashFile™ MEMORY (Continued) VCC = 5V ± 0.5V, 5V ± 0.25V, TA = 0°C to +70°C, –40°C to +85°C Temp Commercial Extended Speed –65 –70 –80 Sym Parameter V CC 5V ± 5% 5V ± 10% 5V ± 10% Unit Load 30 pF 50 pF 50 pF Notes Min Typ Max Min Typ Max Min Typ Max tPHWL RP# High Recovery to WE# Going Low 3 0.300 1 (9) 0.300(10) 1 µs tWHGL Write Recovery before Read 55 60 65 ns tQVVL 1 tQVV L2 VPP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 30 0 0 µ s tWHQV 1 Duration of Program Operation 3,4,5, 4.5 6 TBD 4.5 6 TBD 4.5 6 TBD µs tWHQV 2 Duration of Block Erase Operation NOTES: 1. Read timings during program and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, not 100% tested. Guaranteed by design. 4. Program/erase durations are measured to valid Status Register (CSR) Data. V PP = 12V ± 0.6V. 5. Word/byte program operations are typically performed with 1 Programming Pulse. 6. Address and Data are latched on the rising edge of WE# for all command write operations. 7. CE X# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high. 8. Device speeds are defined as: 65/70 ns at VCC = 5V equivalent to 75 ns at VCC = 3.3V 70/80 ns at VCC = 5V equivalent to 120 ns at VCC = 3.3V 9. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit. 10. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit. 11. The TBD information will be available in a technical paper. Please contact Intel’s Application Hotline or your local sales office for more information. 12. Page Buffer Programs only.
- This address string depicts data program/erase cycles with corresponding verification via ESRD.
- This address string depicts data program/erase cycles with corresponding verification via CSRD.
- This cycle is invalid when using CSRD for verification during data program/erase operations.
- CE X# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.
- RP# low transition is only to show tRHPL ; not valid for above read and program cycles.
- VPP voltage during program/erase operations valid at both 12V and 5V.
- VPP voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 15. AC Waveforms for Command Write Operations
E 28F016SV FlashFile™ MEMORY
5.9 AC Characteristics for CE#—Controlled Command Write Operations(1)
Temp Commercial Extended Commercial Sym Parameter Speed –80 –100 –120 Unit Notes Min Typ Max Min Typ Max Min Typ Max tAVAV Write Cycle Time 80 100 120 ns tVPEH 1,2 V PP Setup to CE# Going High 3,7 100 100 100 ns tPHWL RP# Setup to WE# Going Low 3 480 480 480 ns tWLEL WE# Setup to CE# Going Low 3,7 0 0 0 ns tAVEH Address Setup to CE# Going High 2,6,7 60 70 75 ns tDVEH Data Setup to CE# Going High 2,6,7 60 70 75 ns tELEH CE# Pulse Width 7 65 70 75 ns tEHDX Data Hold from CE# High 2,7 10 10 10 ns tEHAX Address Hold from CE# High 2,7 10 30 10 ns tEHWH WE# hold from CE# High 35 0 1 0 n s tEHEL CE# Pulse Width High 7 15 100 45 ns tGHEL Read Recovery before Write 30 0 0 n s tEHRL CE# High to RY/BY# Going Low 3,7 100 1 100 ns tRHPL RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 3 0 75 0 ns tPHEL RP# High Recovery to CE# Going Low 3,7 0.480 0 1 µs tEHGL Write Recovery before Read 55 95 ns
28F016SV FlashFile™ MEMORY E (Continued) Temp Commercial Extended Commercial Sym Parameter Speed –80 –100 –120 Unit Notes Min Typ Max Min Typ Max Min Typ Max tQVVL 1,2 V PP Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 30 0 µs tEHQV 1 Duration of Program Operation 3,4,5,11 5 9 TBD 5 9 TBD 5 9 TBD µs tEHQV 2 Duration of Block Erase Operation
E 28F016SV FlashFile™ MEMORY (Continued) VCC = 5V ± 0.5V, 5V ± 0.25V, TA = 0° to +70°C, –40°C to +85°C Temp Commercial Extended Speed –65 –70 –80 Sym Parameter V CC 5V ± 5% 5V ± 10% 5V ± 10% Unit Load 30 pF 50 pF 50 pF Notes Min Typ Max Min Typ Max Min Typ Max tAVAV Write Cycle Time 65 70 80 ns tVPEH 1,2 V PP Setup to CE# Going High 3,7 100 100 100 ns tPHWL RP# Setup to WE# Going Low 3 300 480 (9) 300(10) 480 ns tWLEL WE# Setup to CE# Going Low 3,7 0 0 0 ns tAVEH Address Setup to CE# Going High 2,6,7 40 50 (9) 45(10) 50 ns tDVEH Data Setup to CE# Going High 2,6,7 40 50 (9) 45(10) 50 ns tELEH CE# Pulse Width 7 45 45 (9) 50(10) 50 ns tEHDX Data Hold from CE# High 2,7 0 0 0 ns tEHAX Address Hold from CE# High 2,7 10 10 10 ns tEHWH WE# Hold from CE# High 3,7 5 10 (9) 5(10) 10 ns tEHEL CE# Pulse Width High 71 5 3 0 (9) 15(10) 30 ns tGHEL Read Recovery before Write 30 0 0 n s tEHRL CE# High to RY/BY# Going Low 3,7 100 100 100 ns tRHPL RP# Hold from Valid Status Register (CSR, GSR, BSR) Data and RY/BY# High 30 0 0 n s
28F016SV FlashFile™ MEMORY E (Continued) VCC = 5V ± 0.5V, 5V ± 0.25V, TA = 0° to +70°C, –40°C to +85°C Temp Commercial Extended Speed –65 –70 –80 Sym Parameter V CC 5V ± 5% 5V ± 10% 5V ± 10% Unit Load 30 pF 50 pF 50 pF Notes Min Typ Max Min Typ Max Min Typ Max tPHEL RP# High Recovery to CE# Going Low 3,7 0.300 1 (9) 0.300(10) 1 µs tEHGL Write Recovery before Read 55 60 65 ns tQVVL 1,2 V PP Hold from Valid Status Register (CSR, GSR, BSR) Data at RY/BY# High 30 0 0 µ s tEHQV 1 Duration of Program Operation 3,4,5,11 4.5 6 TBD 4.5 6 TBD 4.5 6 TBD µs tEHQV 2 Duration of Block Erase Operation NOTES: 1. Read timings during program and erase are the same as for normal read. 2. Refer to command definition tables for valid address and data values. 3. Sampled, not 100% tested. Guaranteed by design. 4. Program/erase durations are measured to valid Status Data. V PP = 12V ± 0.6V. 5. Word/byte program operations are typically performed with 1 Programming Pulse. 6. Address and Data are latched on the rising edge of CE# for all command w rite operations. 7. CE X# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high. 8. Device speeds are defined as: 65/70 ns at VCC = 5V equivalent to 75 ns at VCC = 3.3V 70/80 ns at VCC = 5V equivalent to 120 ns at VCC = 3.3V 9. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit. 10. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit. 11. The TBD information will be available in a technical paper. Please contact Intel’s Application Hotline or your local sales office for more information.
- This address string depicts data program/erase cycles with corresponding verification via ESRD.
- This address string depicts data program/erase cycles with corresponding verification via CSRD.
- This cycle is invalid when using CSRD for verification during data program/erase operations.
- CE X# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.
- RP# low transition is only to show tRHPL ; not valid for above read and write cycles.
- VPP voltage during program/erase operations valid at both 12V and 5V.
- VPP voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 16. Alternate AC Waveforms for Command Write Operations
28F016SV FlashFile™ MEMORY E
5.10 AC Characteristics for WE#—Controlled Page Buffer Write Operations(1)
VCC = 3.3V ± 0.3V, TA = 0°C to +70°C, –40°C to +85°C Temp Commercial/Extended Sym Parameter Speed –75, –100, –120 Unit Notes Min Typ Max tAVWL Address Setup to WE# Going Low 2 0 ns VCC = 5V ± 0.5V, 5V ± 0.25V, TA = 0°C to +70°C, –40°C to +85°C Temp Commercial Comm/Ext Speed –65 –70 –80 Sym Parameter V CC 5V ± 5% 5V ± 10% 5V ± 10% Unit Load 30 pF 50 pF 50 pF Notes Min Typ Max Min Typ Max Min Typ Max tAVWL Address Setup to WE# Going Low 20 0 0 n s NOTES: 1. All other specifications for WE#—Controlled Write Operations can be found in section 5.8. 2. Address must be valid during the entire WE# low pulse. 3. Device speeds are defined as: 65/70 ns at V CC = 5V equivalent to 75 ns at VCC = 3.3V 70/80 ns at VCC = 5V equivalent to 120 ns at VCC = 3.3V 4. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit. 5. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
- CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
Figure 17. WE#—Controlled Page Buffer Write Timing Waveforms
28F016SV FlashFile™ MEMORY E
5.11 AC Characteristics for CE#—Controlled Page Buffer Write Operations(1)
VCC = 3.3V ± 0.3V, TA = 0°C to +70°C, –40°C to +85°C Temp Commercial/Extended Sym Parameter Speed –75, –100, –120 Unit Notes Min Typ Max tAVEL Address Setup to CE# Going Low 2,3 0 ns VCC = 5V ± 0.5V, 5V ± 0.25V, TA = 0°C to +70°C, –40°C to +85°C Temp Commercial Comm/Ext Speed –65 –70 –80 Sym Parameter V CC 5V ± 5% 5V ± 10% 5V ± 10% Unit Load 30 pF 50 pF 50 pF Notes Min Typ Max Min Typ Max Min Typ Max tAVEL Address Setup to CE# Going Low 2,3 0 0 0 ns NOTES: 1. All other specifications for CE#—Controlled Write Operations can be found in Section 5.9. 2. Address must be valid during the entire WE# low pulse. 3. CE X# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high. 4. Device speeds are defined as: 65/70 ns at VCC = 5V equivalent to 75 ns at VCC = 3.3V 70/80 ns at VCC = 5V equivalent to 120 ns at VCC = 3.3V 5. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit. 6. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
- CEx# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
Figure 18. CE#—Controlled Page Buffer Write Timing Waveforms
28F016SV FlashFile™ MEMORY E
5.12 Erase and Word/Byte Program Performance(3,5)
VCC = 3.3V ± 0.3V, VPP = 5V ± 0.5V, TA = 0°C to +70°C Symbol Parameter Notes Min Typ (1) Max Units Test Conditions Page Buffer Byte Write Time 2,6,7 TBD 8.0 TBD µs Page Buffer Word Write Time 2,6,7 TBD 16.0 TBD µs tWHRH 1A Byte Program Time 2,7 TBD 29.0 TBD µs tWHRH 1B Word Program Time 2,7 TBD 35.0 TBD µs tWHRH 2 Block Program Time 2,7 TBD 1.9 TBD sec Byte Prog. Mode tWHRH 3 Block Program Time 2,7 TBD 1.2 TBD sec Word Prog. Mode Block Erase Time 2,7 TBD 1.4 TBD sec Full Chip Erase Time 2,7 TBD 44.8 TBD sec Erase Suspend Latency Time to Read 4 1.0 12 75 µs Auto Erase Suspend Latency Time to Program 4.0 15 80 µs VCC = 3.3V ± 0.3V, VPP = 12V ± 0.6V, TA = 0°C to +70°C Symbol Parameter Notes Min Typ (1) Max Units Test Conditions Page Buffer Byte Write Time 2,6,7 TBD 2.2 TBD µs Page Buffer Word Write Time 2,6,7 TBD 4.4 TBD µs tWHRH 1 Word/Byte Program Time 2,7 5 9 TBD µs tWHRH 2 Block Program Time 2,7 TBD 0.6 2.1 sec Byte Prog. Mode tWHRH 3 Block Program Time 2,7 TBD 0.3 1.0 sec Word Prog. Mode Block Erase Time 2 0.3 0.8 10 sec Full Chip Erase Time 2,7 TBD 25.6 TBD sec Erase Suspend Latency Time to Read 4 1.0 9 55 µs Auto Erase Suspend Latency Time to Program 4.0 12 60 µs
E 28F016SV FlashFile™ MEMORY
5.12 Erase and Word/Byte Program Performance(3,5) (Continued)
VCC = 5V ± 0.5V, 5V ± 0.25V, VPP = 5V ± 0.5V, TA = 0°C to +70°C Symbol Parameter Notes Min Typ (1) Max Units Test Conditions Page Buffer Byte Write Time 2,6,7 TBD 8.0 TBD µs Page Buffer Word Write Time 2,6,7 TBD 16.0 TBD µs tWHRH 1A Byte Program Time 2,7 TBD 20 TBD µs tWHRH 1B Word Program Time 2,7 TBD 25 TBD µs tWHRH 2 Block Program Time 2,7 TBD 1.4 TBD sec Byte Prog. Mode tWHRH 3 Block Program Time 2,7 TBD 0.85 TBD sec Word Prog. Mode Block Erase Time 2,7 TBD 1.0 TBD sec Full Chip Erase Time 2,7 TBD 32.0 TBD sec Erase Suspend Latency Time to Read 4 1.0 9 55 µs Auto Erase Suspend Latency Time to Program 3.0 12 60 µs VCC = 5V ± 0.5V, 5V ± 0.25V, VPP = 12V ± 0.6V, TA = 0°C to +70°C Symbol Parameter Notes Min Typ (1) Max Units Test Conditions Page Buffer Byte Write Time 2,6,7 TBD 2.1 TBD µs Page Buffer Word Write Time 2,6,7 TBD 4.1 TBD µs tWHRH 1 Word/Byte Program Time 2,7 4.5 6 TBD µs tWHRH 2 Block Program Time 2,7 TBD 0.4 2.1 sec Byte Prog. Mode tWHRH 3 Block Program Time 2,7 TBD 0.2 1.0 sec Word Prog. Mode Block Erase Time 2 0.3 0.6 10 sec Full Chip Erase Time 2,7 TBD 19.2 TBD sec Erase Suspend Latency Time to Read 4 1.0 7 40 µs Auto Erase Suspend Latency Time to Program 3.0 10 45 µs NOTES: 1. +25°C, and nominal voltages. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Specification applies to interrupt latency for single block erase. Suspend latency for erase all unlocked blocks operation extends the maximum latency time to 270 µs. 5. Sampled, but not 100% tested. Guaranteed by design. 6. Assumes using the full Page Buffer to Program to Flash (256 bytes or 128 words). 7. The TBD information will be available in a technical paper. Please contact Intel’s Application Hotline or your local sales office for more information.
6.0 MECHANICAL SPECIFICATIONS
Figure 19. Mechanical Specifications of the 28F016SV 56-Lead TSOP Type I Package
1 Y C A1B e
Figure 20. Mechanical Specifications of the 28F016SV 56-Lead SSOP Type I Package
28F016SV FlashFile™ MEMORY E APPENDIX A DEVICE NOMENCLATURE AND ORDERING INFORMATION Product line designator for all Intel Flash products Package DA = Commercial Temp. 56-Lead SSOP E = Commercial Temp. 56-Lead TSOP T = Extended Temp. 56-Lead SSOP Device Type V = SmartVoltage E2 8F 061 SV - 60 Access Speed (ns) 65 ns (5V, 30 pF), 70 ns (5V), 75 ns (3.3V) 70 ns (5V, 30 pF), 80 ns (5V), 120 ns (3.3V) Product Family S = FlashFile™ MemoryDevice Density 016 = 16 Mbit 0528_21 Valid Combinations Option Order Code V CC = 3.3V ± 0.3V, 50 pF load, 1.5V I/O Levels(1) VCC = 5V ± 10%, 100 pF load TTL I/O Levels(1) VCC = 5V ± 5%, 30 pF load 1.5V I/O Levels(1)
1 E28F016SV 070 E28F016SV-120 E28F016SV-080 E28F016SV-070
2 E28F016SV 065 E28F016SV-075 E28F016SV-070 E28F016SV-065
3 DA28F016SV 070 DA28F016SV-120 DA28F016SV-080 DA28F016SV-070
4 DA28F016SV 065 DA28F016SV-075 DA28F016SV-070 DA28F016SV-065
5 DT28F016SV 080 DT28F016SV-100 DT28F016SV-080 DT28F016SV-080
NOTE: 1. See Section 5.2 for Transient Input/Output Reference Waveforms and Testing Load Circuits.
E 28F016SV FlashFile™ MEMORY APPENDIX B ADDITIONAL INFORMATION (1,2) Order Number Document/Tool 297372 16-Mbit Flash Product Family User’s Manual 290429 28F008SA Datasheet
290490 DD28F032SA 32-Mbit (2 bit x 16, 4 Mbit x 8) FlashFile™ Memory
Datasheet)
292092 AP-357 Power Supply Solutions for Flash Memory
292123 AP-374 Flash Memory Write Protection Techniques
292126 AP-377 16-Mbit Flash Product Family Software Drivers,
28F016SA/28F016SV/28F016XS/28F016XD
292144 AP-393 28F016SV Compatibility with 28F016SA
292159 AP-607 Multi-Site Layout Planning with Intel’s FlashFile™ Components,
292163 AP-610 Flash Memory In-System Code and Data Update Techniques
292165 AB-62 Compiled Code Optimizations for Flash Memories
294016 ER-33 ETOX™ Flash Memory Technology—Insight to Intel’s Fourth
Generation Process Innovation
297508 FLASHBuilder Utility
Contact Intel/Distribution Sales Office Flash Cycling Utility Contact Intel/Distribution Sales Office 28F016SV iBIS Model Contact Intel/Distribution Sales Office 28F016SV VHDL Contact Intel/Distribution Sales Office 28F016SV Timing Designer Library Files Contact Intel/Distribution Sales Office 28F016SV Orcad and ViewLogic Schematic Symbols NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.