28F004SC INTEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 42
Technical content
Datasheet sections
- 1.0 INTRODUCTION
- 1.1 New Features
- 1.2 Product Overview
- 1.3 Pinout and Pin Description
- 2.0 PRINCIPLES OF OPERATION
- 2.1 Data Protection
- 3.0 BUS OPERATION
- 3.1 Read
- 3.2 Output Disable
- 3.3 Standby
- 3.4 Deep Power-Down
- 3.5 Read Identifier Codes Operation
- 3.6 Write
- 4.0 COMMAND DEFINITIONS
- 4.1 Read Array Command
- 4.2 Read Identifier Codes Command
- 4.3 Read Status Register Command
- 4.4 Clear Status Register Command
- 4.5 Block Erase Command
- 4.6 Program Command
- 4.7 Block Erase Suspend Command
- 4.8 Program Suspend Command
- 4.9 Set Block and Master Lock-Bit Commands
- 4.10 Clear Block Lock-Bits Command
- 5.0 DESIGN CONSIDERATIONS
- 5.1 Three-Line Output Control
- 5.2 RY/BY# Hardware Detection
- 5.3 Power Supply Decoupling
- 5.5 VCC , VPP , RP# Transitions
- 5.6 Power-Up/Down Protection
- 6.0 ELECTRICAL SPECIFICATIONS
- 6.1 Absolute Maximum Ratings
- 6.2 Commercial Temperature Operating
- 6.3 Capacitance
- 6.4 DC Characteristics—Commercial
- 6.5 AC Characteristics—Read-Only
- 6.6 AC Characteristics—Write Operations—
- 6.7 Block Erase, Program, and Lock-Bit
- 6.8 Extended Temperature Operating
- 6.9 DC Characteristics—Extended
- 6.10 AC Characteristics—Read-Only Operations
- 7.0 ORDERING INFORMATION
- 8.0 ADDITIONAL INFORMATION
E PRELIMINARY December 1997 Order Number: 290600-003 /c110 SmartVoltage Technology 2.7 V (Read-Only), 3.3 V or 5 V VCC and 3.3 V, 5 V, or 12 V VPP /c110 High-Performance 4, 8 Mbit 85 ns Read Access Time 16 Mbit 95 ns Read Access Time /c110 Enhanced Data Protection Features Absolute Protection with VPP = GND Flexible Block Locking Block Write Lockout during Power Transitions /c110 Enhanced Automated Suspend Options Program Suspend to Read Block Erase Suspend to Program Block Erase Suspend to Read /c110 Industry-Standard Packaging 40-Lead TSOP, 44-Lead PSOP and 40 Bump µBGA* CSP /c110 High-Density 64-Kbyte Symmetrical Erase Block Architecture 4 Mbit: Eight Blocks 8 Mbit: Sixteen Blocks 16 Mbit: Thirty-Two Blocks /c110 Extended Cycling Capability 100,000 Block Erase Cycles /c110 Low Power Management Deep Power-Down Mode Automatic Power Savings Mode Decreases ICC in Static Mode /c110 Automated Program and Block Erase Command User Interface Status Register /c110 SRAM-Compatible Write Interface /c110 ETOX™ V Nonvolatile Flash Technology Intel’s byte-wide SmartVoltage FlashFile™ memory family renders a variety of density offerings in the same package. The 4-, 8-, and 16-Mbit byte-wide FlashFile memories provide high-density, low-cost, nonvolatile, read/write storage solutions for a wide range of applications. Their symmetrically-blocked architecture, flexible voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs, and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the 4-, 8-, and 16-Mbit FlashFile memories offer three levels of protection: absolute protection with V PP at GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They come in industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged 44-lead PSOP. Based on the 28F008SA architecture, the byte-wide SmartVoltage FlashFile memory family enables quick and easy upgrades for designs that demand state-of-the-art technology. BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 4, 8, AND 16 MBIT 28F004SC, 28F008SC, 28F016SC Includes Commercial and Extended Temperature Specifications
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F004SC, 28F008SC, 28F016SC may contain design defects or errors known as errata. Current characterized errata are available on request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel’s Website at http://www.intel.com COPYRIGHT © INTEL CORPORATION 1996, 1997 CG-041493
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E
4 PRELIMINARY
REVISION HISTORY
-001 Original version -002 Table 3 revised to reflect change in abbreviations from “W” for write to “P” for program. Ordering information graphic (Appendix A) corrected: from PB = Ext. Temp. 44-Lead PSOP to TB = Ext. Temp. 44-Lead PSOP. Corrected nomenclature table (Appendix A) to reflect actual Operating Temperature/
Package information
Updated Ordering Information and table Correction to table, Section 6.2.3. Under I LO Test Conditions, previously read VIN = VCC or GND, corrected to VOUT = VCC or GND Section 6.2.7, modified Program and Block Erase Suspend Latency Times -003 Added µBGA* CSP pinout and corrected error in PSOP pinout. Added Design Consideration for VPP Program and Erase Voltages on future sub-0.4µ devices.
1.0 INTRODUCTION
SmartVoltage FlashFile memory specifications. Section 1.0 provides a flash memory overview. design tools which are referenced in Section 8.0.
1.1 New Features
- SmartVoltage Technology
- Enhanced Suspend Capabilities
- In-System Block Locking They share a compatible status register, software commands, and pinouts. These similarities enable a clean upgrade from the 28F008SA and 28F008SA-L to byte-wide SmartVoltage FlashFile products. When upgrading, it is important to note the following differences:
- Because of new feature and density options, the devices have different device identifier codes. This allows for software optimization.
- V PPLK has been lowered from 6.5 V to 1.5 V to support low VPP voltages during block erase, program, and lock-bit configuration operations. Designs that switch V PP off during read operations should transition VPP to GND.
- To take advantage of SmartVoltage tech- nology, allow VPP connection to 3.3 V or 5 V. For more details see application note AP-625, 28F008SC Compatibility with 28F008SA (order number 292180).
1.2 Product Overview
compatibility for the 4-, 8-, and 16-Mbit densities. illustrates the memory organization. program operations at 3.3 V, 5 V, and 12 V VPP . Table 1. SmartVoltage Flash
2.7 V(1)
5 V 5 V, 12 V
- Block erase, program, and lock-bit configuration
operation with VCC , 3.0 V are not supported.
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E
6 PRELIMINARY
A block erase operation erases one of the device’s 64-Kbyte blocks typically within 1 second (5 V V CC , 12 V VPP ), independent of other blocks. Each block can be independently erased 100,000 times (1.6 million block erases per device). A block erase suspend operation allows system software to suspend block erase to read data from or write data to any other block. Data is programmed in byte increments typically within 6 µs (5 V V CC , 12 V V PP ). A program suspend operation permits system software to read data or execute code from any other flash memory array location. To protect programmed data, each block can be locked. This block locking mechanism uses a combination of bits, block lock-bits and a master lock-bit, to lock and unlock individual blocks. The block lock-bits gate block erase and program operations, while the master lock-bit gates block lock-bit configuration operations. Lock-bit config- uration operations (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands) set and clear lock-bits. The status register and RY/BY# output indicate whether or not the device is busy executing or ready for a new command. Polling the status register, system software retrieves WSM feedback. The RY/BY# output gives an additional indicator of WSM activity by providing a hardware status signal. Like the status register, RY/BY#-low indicates that the WSM is performing a block erase, program, or lock-bit configuration operation. RY/BY#-high indicates that the WSM is ready for a new command, block erase is suspended (and program is inactive), program is suspended, or the device is in deep power-down mode. The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical I CCR current is 1 mA at 5 V VCC . When CE# and RP# pins are at V CC , the component enters a CMOS standby mode. Driving RP# to GND enables a deep power-down mode which significantly reduces power consumption, provides write protection, resets the device, and clears the status register. A reset time (t PHQV ) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (t PHEL ) from RP#-high until writes to the CUI are recognized.
1.3 Pinout and Pin Description
The family of devices is available in 40-lead TSOP (Thin Small Outline Package, 1.2 mm thick) and 44-lead PSOP (Plastic Small Outline Package) and 40-bump µBGA* CSP (28F008SC and 28F016SC only). Pinouts are shown in Figures 2, 3 and 4.
Figure 1. Block Diagram Table 2. Pin Descriptions A0–A20 INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle.
4 Mbit → A0–A18
8 Mbit → A0–A19
16 Mbit → A0–A20
outputs data during memory array, status register, and identifier code read cycles. disabled. Data is internally latched during a write cycle. operation. Exit from deep power-down sets the device to read array mode. thereby enabling block erase and program operations to locked memory blocks. spurious results and should not be attempted. OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
8 PRELIMINARY
Table 3. Pin Descriptions (Continued) are latched on the rising edge of the WE# pulse. performing an internal operation (block erase, program, or lock-bit configuration). For erasing array blocks, programming data, or configuring lock-bits. results and should not be attempted. for optimized read performance. Do not float any power pins. CC < 3.0 V are not supported. GND SUPPLY GROUND: Do not float any ground pins. NC NO CONNECT: Lead is not internally connected; it may be driven or floated.
Figure 2. TSOP 40-Lead Pinout
10 PRELIMINARY
Figure 3. PSOP 44-Lead Pinout
This is the view of the package as surface mounted on the board. Note that the signals are mirror images of bottom view.
- Figures are not drawn to scale.
- Address A20 is not included in the 28F008SC.
- More information on µBGA* packages is available by contacting your Intel/Distribution sales office.
**Figure 4. µBGA* CSP 40-Ball Pinout (28F008SC and 28F016SC)**
12 PRELIMINARY
2.0 PRINCIPLES OF OPERATION
overhead with RAM-like interface timings. standby, and output disable operations. block erasure, program, and lock-bit configuration. the identifier codes, or outputs status register data. from any other flash memory array location. Figure 5. Memory Map
E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 13PRELIMINARY
2.1 Data Protection
Depending on the application, the system designer may choose to make the V PP power supply switchable (available only when memory block erases, programs, or lock-bit configurations are required) or hardwired to V PPH1/2/3. The device accommodates either design practice and encourages optimization of the processor-memory interface. When V PP ≤ VPPLK , memory contents cannot be altered. When high voltage is applied to VPP , the two-step block erase, program, or lock-bit configuration command sequences provides pro- tection from unwanted operations. All write functions are disabled when V CC voltage is below the write lockout voltage VLKO or when RP# is at VIL. The device’s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and program operations.
3.0 BUS OPERATION
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
3.1 Read
Block information, identifier codes, or status register can be read independent of the V PP voltage. RP# can be at either VIH or VHH . The first task is to write the appropriate read-mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power- down mode, the device automatically resets to read array mode. Four control pins dictate the data flow in and out of the component: CE#, OE#, WE#, and RP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ 0–DQ 7) control and when active drives the selected memory data onto the I/O bus. WE# must be at V IH and RP# must be at V IH or V HH . Figure 18 illustrates a read cycle.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0–DQ 7 are placed in a high-impedance state.
3.3 Standby
CE# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ 0–DQ 7 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the device continues functioning and consuming active power until the operation completes.
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode. In read mode, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. RP# must be held low for time t PLPH . Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, and the status register is set to 80H. During block erase, program, or lock-bit configuration, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time t PHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
14 PRELIMINARY
Figure 6. Device Identifier Code Memory Map
3.5 Read Identifier Codes
blocks and master lock-bit setting.
3.6 Write
of WE# or CE# (whichever goes high first). Standard microprocessor write timings are used. Figure 18 illustrates a write operation.
4.0 COMMAND DEFINITIONS
Table 3. Bus Operations
- Refer to DC Characteristics. When VPP ≤ VPPLK , memory contents can be read, but not altered.
- X can be VIL or VIH for control and address input pins and VPPLK or VPPH1/2/3 for VPP . See DC Characteristics for VPPLK and
- RY/BY# is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It is VOH
- RP# at GND ± 0.2 V ensures the lowest deep power-down current.
- See Section 4.2 for read identifier code data.
- Command writes involving block erase, write, or lock-bit configuration are reliably executed when V
VCC = VCC2/3 (see Section 6.2 for operating conditions).
- Refer to Table 4 for valid DIN during a write operation.
16 PRELIMINARY
Table 4. Command Definitions(9)
- Bus operations are defined in Table 3.
- X = Any valid address within the device.
IA = Identifier Code Address: see Figure 6. BA = Address within the block being erased or locked. PA = Address of memory location to be programmed.
- SRD = Data read from status register. See Table 7 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID = Data read from identifier codes.
- Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock
codes. See Section 4.2 for read identifier code data.
- If the block is locked, RP# must be at V
program to a locked block while RP# is VIH will fail.
- Either 40H or 10H are recognized by the WSM as the program setup.
- If the master lock-bit is set, RP# must be at V
master lock-bit is not set, a block lock-bit can be set while RP# is VIH.
- If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously
clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is VIH.
- Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
4.1 Read Array Command
voltage and RP# can be VIH or VHH .
4.2 Read Identifier Codes
command, the subsequent information can be read. Table 5. Identifier Codes
4 Mbit 000001 A7
16 Mbit 000001 AA
- Block Is Unlocked DQ 0 = 0
- Block Is Locked DQ 0 = 1
- Reserved for Future Use DQ 1–7 Master Lock Configuration 000003
- Device Is Unlocked DQ 0 = 0
- Device Is Locked DQ 0 = 1
- Reserved for Future Use DQ 1–7 NOTE: 1. X selects the specific block lock configuration code to be read. See Figure 6 for the Device Identifier Code Memory Map.
4.3 Read Status Register
4.4 Clear Status Register
during block erase or program suspend modes.
4.5 Block Erase Command
erased (erase changes all block data to FFH). internally by the WSM (invisible to the system). RY/BY# pin or status register bit SR.7.
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E
18 PRELIMINARY
When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to “1.” Also, reliable block erasure can only occur when V CC = VCC2/3 and VPP = VPPH1/2/3. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while V PP ≤ VPPLK , SR.3 and SR.5 will be set to “1.” Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that RP# = V HH . If block erase is attempted when the corresponding block lock-bit is set and RP# = V IH, the block erase will fail, and SR.1 and SR.5 will be set to “1.” Block erase operations with V IH < RP# < V HH produce spurious results and should not be attempted.
4.6 Program Command
Program is executed by a two-cycle command sequence. Program setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and write verify algorithms internally. After the program sequence is written, the device automatically outputs status register data when read (see Figure 8). The CPU can detect the completion of the program event by analyzing the RY/BY# pin or status register bit SR.7. When program is complete, status register bit SR.4 should be checked. If program error is detected, the status register should be cleared. The internal WSM verify only detects errors for “1”s that do not successfully write to “0”s. The CUI remains in read status register mode until it receives another command. Reliable programs only occurs when V CC = VCC2/3 and VPP = VPPH1/2/3. In the absence of this high voltage, memory contents are protected against programs. If program is attempted while V PP ≤ V PPLK , the operation will fail, and status register bits SR.3 and SR.5 will be set to “1.” Successful program also requires that the corresponding block lock-bit be cleared or, if set, that RP# = V HH . If program is attempted when the corresponding block lock-bit is set and RP# = VIH, program will fail, and SR.1 and SR.4 will be set to “1.” Program operations with V IH < RP# < V HH produce spurious results and should not be attempted.
4.7 Block Erase Suspend
The Block Erase Suspend command allows block-erase interruption to read or write data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to “1”). RY/BY# will also transition to V OH . Specification tWHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Program command sequence can also be issued during erase suspend to program data in other blocks. Using the Program Suspend command (see Section 4.8), a program operation can also be suspended. During a program operation with block erase suspended, status register bit SR.7 will return to “0” and the RY/BY# output will transition to V OL . However, SR.6 will remain “1” to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to V OL . After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 9). V PP must remain at VPPH1/2/3 (the same VPP level used for block erase) while block erase is suspended. RP# must also remain at V IH or VHH (the same RP# level used for block erase). Block erase cannot resume until program operations initiated during block erase suspend have completed.
E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 19PRELIMINARY
4.8 Program Suspend Command
The Program Suspend command allows program interruption to read data in other flash memory locations. Once the program process starts, writing the Program Suspend command requests that the WSM suspend the program sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Program Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the program operation has been suspended (both will be set to “1”). RY/BY# will also transition to V OH . Specification tWHRH1 defines the program suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while program is suspended are Read Status Register and Program Resume. After Program Resume command is written to the flash memory, the WSM will continue the program process. Status register bits SR.2 and SR.7 will automatically clear and RY/BY# will return to V OL . After the Program Resume command is written, the device automatically outputs status register data when read (see Figure 10). V PP must remain at VPPH1/2/3 (the same VPP level used for program) while in program suspend mode. RP# must also remain at V IH or VHH (the same RP# level used for program).
4.9 Set Block and Master Lock-Bit
A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. The block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. With the master lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Master Lock-Bit command, in conjunction with RP# = V HH , sets the master lock-bit. After the master lock-bit is set, subsequent setting of block lock-bits requires both the Set Block Lock-Bit command and V HH on the RP# pin. See Table 6 for a summary of hardware and software write protection options. Set block lock-bit and master lock-bit are initiated using two-cycle command sequence. The set block or master lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set master lock-bit confirm (and any device address). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Figure 11). The CPU can detect the completion of the set lock-bit event by analyzing the RY/BY# pin output or status register bit SR.7. When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of setup followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block or Master Lock-Bit command will result in status register bits SR.4 and SR.5 being set to “1.” Also, reliable operations occur only when V CC = VCC2/3 and VPP = VPPH1/2/3. In the absence of this high voltage, lock-bit contents are protected against alteration. A successful set block lock-bit operation requires that the master lock-bit be cleared or, if the master lock-bit is set, that RP# = V HH . If it is attempted with the master lock-bit set and RP# = VIH, the operation will fail, and SR.1 and SR.4 will be set to “1.” A successful set master lock-bit operation requires that RP# = V HH . If it is attempted with RP# = VIH, the operation will fail, and SR.1 and SR.4 will be set to “1.” Set block and master lock-bit operations with V IH < RP# < V HH produce spurious results and should not be attempted.
20 PRELIMINARY
4.10 Clear Block Lock-Bits
mode until another command is issued. Table 6. Write Protection Alternatives
Table 7. Status Register Definition program, or lock-bit configuration completion. command sequence was entered. masked out when polling the status register.
22 PRELIMINARY
before full status is checked. retry or other error recovery. Repeat for subsequent block erasures. Write FFH after the last operation to place device in read array mode. Figure 7. Automated Block Erase Flowchart
retry or other error recovery. Repeat for subsequent byte writes. sequence of program operations. Figure 8. Automated Program Flowchart
24 PRELIMINARY
Figure 9. Block Erase Suspend/Resume Flowchart
than that being data written. Figure 10. Program Suspend/Resume Flowchart
26 PRELIMINARY
Repeat for subsequent lock-bit set operations. a sequence of lock-bit set operations. Figure 11. Set Block and Master Lock-Bit Flowchart
retry or other error recovery. Figure 12. Clear Block Lock-Bits Flowchart
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E
28 PRELIMINARY
5.0 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
Intel provides three control inputs to accommodate multiple memory connections: CE#, OE#, and RP#. Three-line control provides for: a. Lowest possible memory power dissipation. b. Data bus contention avoidance. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’s READ# control line. This assures that only selected memory devices have active outputs while de- selected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
5.2 RY/BY# Hardware Detection
RY/BY# is a full CMOS output that provides a hardware method of detecting block erase, program and lock-bit configuration completion. This output can be directly connected to an interrupt input of the system CPU. RY/BY# transitions low when the WSM is busy and returns to V OH when it is finished executing the internal algorithm. During suspend and deep power-down modes, RY/BY# remains at V OH .
5.3 Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels, active current levels and transient peaks produced by falling and rising edges of CE# and OE#. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its V CC and GND and between its V PP and GND. These high-frequency, low-inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array’s power supply connection between V CC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance.
5.4 V PP Trace on Printed Circuit
Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for byte writing and block erasing. Use similar trace widths and layout considerations given to the V CC power bus. Adequate V PP supply traces and decoupling will decrease VPP voltage spikes and overshoots.
5.5 V CC , VPP , RP# Transitions
Block erase, program and lock-bit configuration are not guaranteed if V PP or VCC fall outside of a valid voltage range (VCC2/3 and VPPH1/2/3) or RP# ≠ VIH or VHH . If VPP error is detected, status register bit SR.3 is set to “1” along with SR.4 or SR.5, depending on the attempted operation. If RP# transitions to V IL during block erase, program, or lock-bit configuration, RY/BY# will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power- down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restored.
5.6 Power-Up/Down Protection
The device is designed to offer protection against accidental block erasure, byte writing, or lock-bit configuration during power transitions. Upon power- up, the device is indifferent as to which power supply (V PP or V CC ) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for V CC voltages above VLKO when V PP is active. Since both WE# and CE# must be low for a command write, driving either input signal to V IH will inhibit writes. The CUI’s two-step command sequence architecture provides an added level of protection against data alteration. In-system block lock and unlock renders additional protection during power-up by prohibiting block erase and program operations. The device is disabled while RP# = V IL regardless of its control inputs state.
E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 29PRELIMINARY
5.7 V PP Program and Erase
Voltages on Sub-0.4µ SC Memory Family Intel's SmartVoltage FlashFile™ memory family provides in-system program/erase at 3.3 V VPP and 5V VPP as well as faster factory program/erase at 12 V VPP . Future sub-0.4µ lithography SmartVoltage FlashFile memory products will also include a backward- compatible 12 V programming feature. This mode, however, is not intended for extended use. A 12 V program/erase V PP can be applied for 1000 cycles maximum per block or 80 hours maximum per device. To ensure compatibility with future sub-0.4µ SmartVoltage FlashFile memory products, present designs should not permanently connect V PP to 12 V. This will avoid device over-stressing that may cause permanent damage.
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E
30 PRELIMINARY
6.0 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings*
(except V NOTICE: This datasheet contains information on new products in production. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. *WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. NOTES: 1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and –0.2 V on VCC , RP#, and VPP pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on input/output pins and VCC is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 2. Maximum DC voltage on VPP and RP# may overshoot to +14.0 V for periods <20 ns. 3. Output shorted for no more than one seco nd. No more than one output shorted at a time. 4. RP# voltage is normally at VIL or VIH. Connection to supply of VHH is allowed for a maximum cumulative period of 80 hours.
6.2 Commercial Temperature Operating Conditions
Commercial Temperature and VCC Operating Conditions Symbol Parameter Notes Min Max Unit Test Condition TA Operating Temperature 0 +70 °C Ambient Temperature VCC1 VCC Supply Voltage (2.7 V–3.6 V) 1 2.7 3.6 V VCC2 VCC Supply Voltage (3.3 V ± 0.3 V) 3.0 3.6 V VCC3 VCC Supply Voltage (5 V ± 5%) 4.75 5.25 V VCC4 VCC Supply Voltage (5 V ± 10%) 4.5 5.5 V NOTE: 1. Block erase, program, and lock-bit configuration with VCC < 3.0 V should not be attempted.
6.3 Capacitance (1)
TA = +25°C, f = 1 MHz Symbol Parameter Typ Max Unit Condition C IN Input Capacitance 6 8 pF V IN = 0.0 V C OUT Output Capacitance 8 12 pF V OUT = 0.0 V NOTE: 1. Sampled, not 100% tested.
E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 31PRELIMINARY
6.4 DC Characteristics—Commercial Temperature
2.7V VCC 3.3V VCC 5V VCC Test Sym Parameter Notes Typ Max Typ Max Typ Max Unit Conditions ILI Input Load Current 1 ±0.5 ±0.5 ±1 µAV CC = VCC Max, VIN = VCC or GND ILO Output Leakage Current 1 ±0.5 ±0.5 ±10 µAV CC = VCC Max, VOUT = VCC or GND ICCS VCC Standby Current 1,3,6 20 100 20 100 25 100 µA CMOS Inputs VCC = VCC Max CE# = RP# = VCC ± 0.2 V 0.1 2 0.2 2 0.4 2 mA TTL Inputs VCC = VCC Max, CE# = RP# = VIH ICCD VCC Deep Power- Down Current 11 0 1 0 1 0 µA RP# = GND ± 0.2 V IOUT (RY/BY#) = 0 mA ICCR VCC Read Current 1,5,6 6 12 7 12 17 35 mA CMOS Inputs VCC = VCC Max, CE# = GND f = 5 MHz (2.7 V, 3.3 V), 8 MHz (5 V) IOUT = 0 mA 7 18 8 18 20 50 mA TTL Inputs VCC = VCC Max, CE# = GND f = 5 MHz (2.7 V, 3.3 V), 8 MHz (5 V) IOUT = 0 mA ICCW VCC Program or 1,7 17 mA V PP = 3.3 V ± 0.3 V Set Lock-Bit Current 17 35 mA V PP = 5 V ± 10% 12 30 mA V PP = 12 V ± 5% ICCE VCC Block Erase or 1,7 17 mA V PP = 3.3 V ± 0.3 V Clear Block 17 30 mA V PP = 5 V ± 10% Lock-Bits Current 12 25 mA V PP = 12 V ± 5% ICCWS ICCES VCC Program or Block Erase Suspend Current 1,2 1 6 1 10 mA CE# = V IH IPPS VPP Standby Current 1 ±2 ±15 ±2 ±15 ± 2 ±15 µA V PP ≤ VCC IPPR VPP Read Current 1 10 200 10 200 10 200 µA V PP > VCC IPPD VPP Deep Power-Down Current 1 0.1 5 0.1 5 0.1 5 µA RP# = GND ± 0.2 V IPPW VPP Program/ Set 1,7 40 mA V PP = 3.3 V ± 0.3 V Lock-Bit Current 40 40 mA V PP = 5 V ± 10% 15 15 mA V PP = 12 V ± 5% IPPE VPP Block Erase/Clear 1,7 20 mA V PP = 3.3 V ± 0.3 V Block Lock-Bits 20 20 mA V PP = 5 V ± 10% Current 15 15 mA V PP = 12 V ± 5% IPPWS IPPES VPP Program/ Block Erase Suspend Current 1 10 200 10 200 µA V PP = VPPH1/2/3
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E
32 PRELIMINARY
6.4 DC Characteristics—Commercial Temperature (Continued)
2.7 V VCC 3.3 V VCC 5 V VCC Test Sym Parameter Notes Min Max Min Max Min Max Unit Conditions VIH Input High Voltage 7 2.0 V CC + 0.5
2.0 VCC
+ 0.5
2.0 V CC
+ 0.5 V VOL Output Low Voltage 3,7 0.4 0.4 0.45 V V CC = VCC Min IOL = 2 mA (2.7V, 3.3V) 5.8 mA (5V) VOH1 Output High Voltage (TTL) 3,7 2.4 2.4 2.4 V V CC = VCC Min IOH = –2.5 mA VOH2 Output High Voltage (CMOS) 3,7 0.85 VCC 0.85 V CC 0.85 V CC VV CC = VCC Min IOH = –2.5 mA VCC –0.4 VCC –0.4 VCC –0.4 VV CC = VCC Min IOH = –100 µA VPPLK VPP Lockout Voltage 4,7 1.5 1.5 1.5 V VPPH1 VPP Voltage 3.0 3.6 V VPPH2 VPP Voltage 4.5 5.5 4.5 5.5 VPPH3 VPP Voltage 11.4 12.6 11.4 12.6 V VLKO VCC Lockout Voltage 2.0 2.0 2.0 V VHH RP# Unlock Voltage 8,9 11.4 12.6 11.4 12.6 V Set Master Lock-Bit Override Lock-Bit NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25°C. These currents are valid for all product versions (packages and speeds). 2. ICCWS and ICCES are specified with the device de-selected. If read or written while in erase suspend mode, the device’s current is the sum of ICCWS or ICCES and ICCR or ICCW . 3. Includes RY/BY#. 4. Block erases, programs, and lock-bit configurations are inhibited when V PP ≤ VPPLK , and not guaranteed in the range between VPPLK (max) and VPPH1 (min), between VPPH1 (max) and VPPH2 (min), between VPPH2 (max) and VPPH3 (min), and above VPPH3 (max). 5. Automatic Power Savings (APS) reduces typical ICCR to 1 mA at 5 V and 3 mA at 2.7 V and 3.3 V VCC in static operation. 7. Sampled, not 100% tested. 8. Master lock-bit set operations are inhibited when RP# = V IH. Block lock-bit configuration operations are inhibited when the master lock-bit is set and RP# = VIH. Block erases and programs are inhibited when the corresponding block-lock bit is set and RP# = VIH. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be attempted with VIH < RP# < VHH . 9. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
34 PRELIMINARY
Figure 17. AC Waveform for Reset Operation Table 8. Reset Specifications
- These specifications are valid for all product versions (packages and speeds).
- If RP# is asserted when the WSM is not busy (RY/BY# = “1”), the reset will complete within 100 ns.
PHQV , is required from the latter of RY/BY# or RP# going high until outputs are valid.
E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 35PRELIMINARY
6.5 AC Characteristics—Read-Only Operations(1)—Commercial Temperature
TA = 0°C to +70°C Versions(4) 5 V ± 10% VCC -90/-100(6) -120 Unit 3.3 V ± 0.3 V VCC -120 -150 # Sym Parameter Notes Min Max Min Max Min Max Min Max Min Max R1 tAVAV Read Cycle 4, 8 Mbit 85 90 120 150 170 ns Time 16 Mbit 95 100 120 150 170 ns R2 tAVQV Address to 4, 8 Mbit 85 90 120 150 170 ns Output Delay 16 Mbit 95 100 120 150 170 ns R3 tELQV CE# to Output 4, 8 Mbit 2 85 90 120 150 170 ns Delay 16 Mbit 2 95 100 120 150 170 ns R4 tGLQV OE# to Output Delay 2 40 45 50 55 55 ns R5 tPHQV RP# High to Output Delay 400 400 400/ 600(7) 600 600 ns R6 tELQX CE# to Output in Low Z 3 000 00 n s R7 tGLQX OE# to Output in Low Z 3 000 00 n s R8 tEHQZ CE# High to Output in High Z 3 55 55 55 55 55 ns R9 tGHQZ OE# High to Output in High Z 3 10 10 15 20 25 ns R10 tOH Output Hold from Address, CE# or OE# Change, Whichever Occurs First 3 000 00 n s NOTES: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. OE# may be delayed up to t ELQV –tGLQV after the falling edge of CE# without impact on tELQV . 3. Sampled, not 100% tested. 4. See Ordering Information for device speeds (valid operational combinations). 5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed Configuration) for testing characteristics. 6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics. 7. Valid for 3.3 V VCC read operations.
36 PRELIMINARY
Figure 18. AC Waveform for Read Operations
E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 37PRELIMINARY
6.6 AC Characteristics—Write Operations(1,2)—Commercial Temperature
TA = 0°C to +70°C
5 V ± 5%,
5 V ± 10% VCC
3.3 V ± 0.3 V, 2.7 V−3.6 V VCC Valid for All Speeds Unit # Sym Parameter Notes Min Max Min Max W1 t PHWL (tPHEL ) RP# High Recovery to WE# (CE#) Going Low 31 1µ s W2 t ELWL (tWLEL ) CE# (WE#) Setup to WE# (CE#) Going Low 70 0n s W3 t WP Write Pulse Width 7 50 70 ns W4 t DVWH (tDVEH ) Data Setup to WE# (CE#) Going High 4 40 50 ns W5 t AVWH (tAVEH ) Address Setup to WE# (CE#) Going High 4 40 50 ns W6 t WHEH (tEHWH ) CE# (WE#) Hold from WE# (CE#) High 0 0n s W7 t WHDX (tEHDX ) Data Hold from WE# (CE#) High 5 5n s W8 t WHAX (tEHAX ) Address Hold from WE# (CE#) High 5 5n s W9 t WPH Write Pulse Width High 9 25 25 ns W10 t PHHWH (tPHHEH ) RP# V HH Setup to WE# (CE#) Going High 3,8 100 100 ns W11 t VPWH (tVPEH )V PP Setup to WE# (CE#) Going High 3,8 100 100 ns W12 t WHGL (tEHGL ) Write Recovery before Read 0 0n s W13 t WHRL (tEHRL ) WE# (CE#) High to RY/BY# Going Low 8 90 90 ns W14 t QVPH RP# VHH Hold from Valid SRD, RY/BY# High 3,5,8 0 0n s W15 t QVVL VPP Hold from Valid SRD, RY/BY# High 3,5,8 0 0n s NOTES: 1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. A write operation can be initiated and terminated with either CE# or WE#. 3. Sampled, not 100% tested. 4. Refer to Table 4 for valid A IN and DIN for block erase, program, or lock-bit configuration. 5. V PP should be held at VPPH1/2/3 (and if necessary RP# should be held at VHH ) until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0). 6. See Ordering Information for device speeds (valid operational combinations). 7. Write pulse width (t WP ) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH . If CE# is driven low 10 ns before WE# going low, WE# pulse width requirement decreases to tWP – 10 ns for 5 V VCC and tWP – 20 ns for 2.7 V and 3.3 V VCC writes. 8. Block erase, program, and lock-bit configuration with VCC < 3.0 V should not be attempted. 9. Write pulse width high (tWPH ) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL .
38 PRELIMINARY
A. V CC power-up and standby. B. Write block erase or program setup. C. Write block erase confirm or valid address and data.. D. Automated erase or program delay. E. Read status register data. F. Write Read Array command. Figure 19. AC Waveform for Write Operations
E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 39PRELIMINARY
6.7 Block Erase, Program, and Lock-Bit Configuration Performance(3, 4, 5)—
VCC = 3.3 V ± 0.3 V, TA = 0°C to +70°C
3.3 V VPP 5 V VPP 12 V VPP
# Sym Parameter Notes Typ (1) Max Typ (1) Max Typ (1) Max Unit W16 t WHRH1 , tEHRH1 Program Time 2 19 300 10 150 7 125 µs Block Write Time 2 1.2 4 0.7 2 0.5 1.5 sec W16 t WHRH2 , tEHRH2 Block Erase Time 2 0.8 6 0.4 5 0.3 4 sec W16 t WHRH3 , tEHRH3 Set Lock-Bit Time 2 21 TBD 13.3 TBD 11.6 TBD µs W16 t WHRH4 , tEHRH4 Clear Block Lock- Bits Time 2 1.8 TBD 1.2 TBD 1.1 TBD sec W16 t WHRH5 , tEHRH5 Program Suspend Latency Time to Read W16 t WHRH6 , tEHRH6 Erase Suspend Latency Time to Read V
5 V VPP 12 V VPP
# Sym Parameter Notes Typ (1) Max Typ (1) Max Unit W16 t WHRH1 , tEHRH1 Program Time 2 8 150 6 100 µs Block Write Time 2 0.5 1.5 0.4 1 sec W16 t WHRH2 , tEHRH2 Block Erase Time 2 0.4 5 0.3 4 sec W16 t WHRH3 , tEHRH3 Set Lock-Bit Time 2 12 TBD 10 TBD µs W16 t WHRH4 , tEHRH4 Clear Block Lock-Bits Time 2 1.1 TBD 1.0 TBD sec W16 t WHRH5 , tEHRH5 Program Suspend Latency Time to Read 5.6 7 5.2 7.5 µs W16 t WHRH6 , tEHRH6 Erase Suspend Latency Time to Read 9.4 13.1 9.8 12.6 µs NOTES: 1. Typical values measured at TA = +25°C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled, but not 100% tested. 5. Reference the AC Waveform for Write Operations, Figure 19.
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E
40 PRELIMINARY
6.8 Extended Temperature Operating Conditions
Except for the specifications given in this section, all DC and AC characteristics are identical to those give in commercial temperature specifications. See the Section 6.2 for commercial temperature specifications. Extended Temperature and VCC Operating Conditions Symbol Parameter Notes Min Max Unit Test Condition TA Operating Temperature –40 +85 °C Ambient Temperature
6.9 DC Characteristics—Extended Temperature
2.7V VCC 3.3V VCC 5V VCC Test Sym Parameter Notes Typ Max Typ Max Typ Max Unit Conditions ICCD VCC Deep Power-Down Current 1 2 02 02 0 µA RP# = GND ± 0.2 V IOUT (RY/BY#) = 0 mA NOTE: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical specifications.
6.10 AC Characteristics—Read-Only Operations(1) — Extended Temperature
TA = –40°C to +85°C Versions(3) 3.3 V ± 0.3 V VCC -150 Unit # Sym Parameter Notes Min Max Min Max Min Max R1 tAVAV Read Cycle Time 4, 8 Mbit 100 150 170 ns
16 Mbit 110 150 170 ns
R2 tAVQV Address to Output 4, 8 Mbit 100 150 170 ns Delay 16 Mbit 110 150 170 ns R3 tELQV CE# to Output Delay 4, 8 Mbit 2 100 150 170 ns
16 Mbit 2 110 150 170 ns
NOTES: 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. OE# may be delayed up to t ELQV -tGLQV after the falling edge of CE# without impact on tELQV . 3. See Ordering Information for device speeds (valid operational combinations).
E BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY 41PRELIMINARY
7.0 ORDERING INFORMATION
Operating Temperature/Package E = Comm. Temp. 40-Lead TSOP TE = Extended Temp. 40-Lead TSOP PA = Comm. Temp 44-Lead PSOP TB = Ext. Temp 44-Lead PSOP G = Comm. Temp. 40-Ball µBGA* CSP Product line designator for all Intel Flash products Access Speed (ns) 85 ns (5 V, 30 pF), 90 ns (5 V) 120 ns (3.3 V), 150 ns (2.7 V) Product Family S = FlashFile™ Memory Device Density 004 = 4 Mbit 008 = 8 Mbit 016 = 16 Mbit Voltage Options (VCC /VPP ) C = SmartVoltage Flash (2.7 V, 3.3 V and 5 V/3.3 V, 5 V and 12 V) Valid Operational Combinations Order Code by Density 5V V CC 4-Mbit 8-Mbit 16-Mbit 2.7V VCC , 50pF load 3.3V VCC , 50pF load 10% V CC , 100pF load 5% V CC , 30pF load Commercial Temperature E28F004SC-85 E28F008SC-85 E28F016SC-95 -150 -120 -90/-100 (1) -85/95(1) E28F004SC-120 E28F008SC-120 E28F016SC-120 -170 -150 -120 PA28F004SC-85 PA28F008SC-85 PA28F016SC-95 -150 -120 -90/-100 (1) -85/95(1) PA28F004SC-120 PA28F008SC-120 PA28F016SC-120 -170 -150 -120 G28F008SC-120 G28F016SC-120 -170 –150 –120 G28F008SC-150 G28F016SC-150 -170 –150 –120 Extended Temperature TE28F004SC-100 TE28F008SC-100 TE28F016SC-110 -170 -150 -100/-110 (1) TB28F004SC-100 TB28F008SC-100 TB28F016SC-110 -170 -150 -100/-110 (1) NOTE: 1. Valid access time for 16-Mbit byte-wide FlashFile memory.
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY E
42 PRELIMINARY
8.0 ADDITIONAL INFORMATION
Order Number Document/Tool
290598 Byte-Wide Smart3 FlashFile Memory Family Datasheet
290597 Byte-Wide Smart5 FlashFile Memory Family Datasheet
292183 AB-64 4-, 8-, 16-Mbit Byte-Wide FlashFile™ Memory Family Overview
292094 AP-359 28F008SA Hardware Interfacing
292099 AP-364 28F008SA Automation and Algorithms
292123 AP-374 Flash Memory Write Protection Techniques
292180 AP-625 28F008SC Compatibility with 28F008SA
292182 AP-627 Byte-Wide FlashFile™ Memory Family Software Drivers
297729 Byte-Wide SmartVoltage FlashFile™ Memory Family Specification Update
Contact Intel/Distribution Sales Office 4-, 8-, and 16-Mbit Schematic Symbols Contact Intel/Distribution Sales Office 4-, 8-, and 16-Mbit TimingDesigner* Files Contact Intel/Distribution Sales Office 4-, 8-, and 16-Mbit VHDL and Verilog Models Contact Intel/Distribution Sales Office 4-, 8-, and 16-Mbit iBIS Models NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.