28F400BV-TB INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 PRODUCT FAMILY OVERVIEW
- 1.1 New Features in the SmartVoltage
- 1.2 Main Features
- 1.3 Applications
- 1.4 Pinouts
- 1.5 Pin Descriptions
- 2.0 PRODUCT DESCRIPTION
- 2.1 Memory Blocking Organization
- 2.1.1 Boot Block
- 2.1.2 Parameter Blocks
- 2.1.3 Main Blocks
- 3.0 PRODUCT FAMILY PRINCIPLES OF
- 3.1 Bus Operations
- 3.2 Read Operations
- 3.2.1 Read Array
- 3.2.2 Intelligent Identifiers
- 3.3 Write Operations
- 3.3.1 Command User Interface (CUI)
- 3.3.2 Status Register
- 3.3.3 Program Mode
- 3.3.4 Erase Mode
- 3.4 Boot Block Locking
- 3.4.2 WP# = VIL for Boot Block Locking
- 3.4.3 RP# = VHH or WP# = VIH forr Boot Block
- 3.4.4 Upgrade Note for 8-Mbit 44-PSOP
- 3.5 Power Consumption
- 3.5.1 Active Power
- 3.5.2 Automatic Power Savings (APS)
- 3.5.3 Standby Power
- 3.5.4 Deep Power-Down Mode
- 3.6 Power-Up/Down Operation
- 3.6.1 RP# Connected to System Reset
- 3.7 Power Supply Decoupling
- 3.7.1 VPP Trace on Printed Circuit Boards
- 4.0 ABSOLUTE MAXIMUM RATINGS
- 5.1 Applying V
- 5.2 DC Characteristics
- 5.3 AC Characteristics
- 6.0 EXTENDED OPERATING CONDITIONS
- 6.1 Applying V
- 6.2 DC Characteristics
- 6.3 AC Characteristics
E PRELIMINARY July 1997 Order Number: 290530-005 /c110 Intel SmartVoltage Technology 5V or 12V Program/Erase 2.7V, 3.3V or 5V Read Operation Increased Programming Throughput at 12V VPP /c110 Very High-Performance Read 5V: 60/80/120 ns Max. Access Time, 30/40 ns Max. Output Enable Time 3V: 110/150/180 ns Max Access 65/90 ns Max. Output Enable Time 2.7V: 120 ns Max Access 65 ns Max. Output Enable Time /c110 Low Power Consumption Max 60 mA Read Current at 5V Max 30 mA Read Current at 2.7V–3.6V /c110 x8/x16-Selectable Input/Output Bus 28F400 for High Performance 16- or 32-bit CPUs /c110 x8-Only Input/Output Architecture 28F004B for Space-Constrained 8-bit Applications /c110 Optimized Array Blocking Architecture One 16-KB Protected Boot Block Two 8-KB Parameter Blocks One 96-KB Main Block Three 128-KB Main Blocks Top or Bottom Boot Locations /c110 Absolute Hardware-Protection for Boot Block /c110 Software EEPROM Emulation with Parameter Blocks /c110 Extended Temperature Operation –40°C to +85°C /c110 Extended Cycling Capability 100,000 Block Erase Cycles (Commercial Temperature) 10,000 Block Erase Cycles (Extended Temperature) /c110 Automated Word/Byte Program and Block Erase Industry-Standard Command User Interface Status Registers Erase Suspend Capability /c110 SRAM-Compatible Write Interface /c110 Automatic Power Savings Feature 1 mA Typical ICC Active Current in Static Operation /c110 Reset/Deep Power-Down Input 0.2 µA ICC Typical Provides Reset for Boot Operations /c110 Hardware Data Protection Feature Write Lockout during Power Transitions /c110 Industry-Standard Surface Mount Packaging 40-Lead TSOP 44-Lead PSOP: JEDEC ROM Compatible 48-Lead TSOP 56-Lead TSOP /c110 Footprint Upgradeable from 2-Mbit and to 8-Mbit Boot Block Flash Memories /c110 ETOX™ IV Flash Technology 4-MBIT (256K X 16, 512K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY 28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B 28F400CE-T/B, 28F004BE-T/B
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B, 28F400CE-T/B, 28F004BE-T/B may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 or visit Intel’s Website at http:\\\\www.intel.com COPYRIGHT © INTEL CORPORATION, 1997 CG-041493 *Third-party brands and names are the property of their respective owners.
4-MBIT SmartVoltage BOOT BLOCK FAMILY E
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REVISION HISTORY
-001 Initial release of datasheet. -002 Status changed from Product Preview to Preliminary 28F400CV/CE/BE references and information added throughout. 2.7V CE/BE specs added throughout. Note 2 added to Figure 3 to clarify 28F008B pinout vs. 28F008SA. Erroneous arrows leading out of error states deleted from flowcharts in Figs. 9, 10. Sections 5.1, 6.1 changed to “Applying V CC Voltages.” These sections completely changed to clarify VCC ramp requirements. IPPD 3.3V Commercial spec changed from 10 to 5 µA. Capacitance tables added after commercial and extended DC Characteristics tables. Test and slew rate notes added to Figs. 12, 13, 19, 20, 21. Test configuration drawings (Fig. 14, 22) consolidated into one, with component values in table. (Component values also rounded off). t ELFL , tELFH , tAVFL changed from 7 to 5 ns for 3.3V BV-60 commercial and 3.3V TBV-80 extended, 10 to 5 ns for 3.3V BV-80 and BV-120 commercial. tWHAX and tEHAX changed from 10 to 0 ns. tPHWL changed from 1000 ns to 800 ns for 3.3V BV-80, BV-120 commercial. tPHEL changed from 1000 ns to 800 ns for 3.3V BV-60, BV-80, and BV-120 commercial. -003 28F400BE row removed from Table 1 Applying VCC voltages (Sections 5.1 and 6.1) rewritten for clarity. Minor cosmetic changes/edits. -004 Corrections: Spec typographical error “tQWL ” corrected to read “tQVVL .” Intel386™ EX Microprocessor block diagram updated because latest Intel386 CPU specs require less glue logic. Spec t ELFL and tELFH changed from 5 ns (max) to 0 ns (min). New specs tPLPH and tPLQX added from Specification Update document (297595). Specs tEHQZ and tGHQZ improved on most voltage/speed combinations. -005 Correction: Appendix A, Ordering information fixed order numbers from TE27F400BVT80 to TE28F400BVT80 and TE27F400BVB80 to TE28F400BVB80. Updated disclaimer.
1.0 PRODUCT FAMILY OVERVIEW
family’s operating specifications.
1.1 New Features in the
- WP# pin has replaced a DU (Don’t Use) pin. Connect the WP# pin to control signal or to V CC or GND (in this case, a logic-level signal can be placed on DU pin). See Tables 2 and 9 to see how the WP# pin works.
- 5V program/erase operation has been added. If switching VPP for write protection, switch to GND (not 5V) for complete write protection. To take advantage of 5V write-capability, allow for connecting 5V to V PP and disconnecting 12V from VPP line.
- Enhanced circuits optimize low V CC performance, allowing operation down to VCC = 2.7V (using the BE product). If you are using BX/BL 12V V PP boot block products today, you should account for the differences listed above and also allow for connecting 5V to V PP and disconnecting 12V from VPP line, if 5V writes are desired.
1.2 Main Features
CC provides faster read access times. Table 1. SmartVoltage Provides Total Voltage Flexibility
4-MBIT SmartVoltage BOOT BLOCK FAMILY E
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For program and erase operations, 5V V PP operation eliminates the need for in system voltage converters, while 12V VPP operation provides faster program and erase for situations where 12V is available, such as manufacturing or designs where 12V is in-system. For design simplicity, however, just hook up V CC and VPP to the same 5V ± 10% source. The 28F400/28F004B boot block flash memory family is a high-performance, 4-Mbit (4,194,304 bit) flash memory family organized as either
256 Kwords of 16 bits each (28F400 only) or
512 Kbytes of 8 bits each (28F400 and 28F004B). Separately erasable blocks, including a hardware- lockable boot block (16,384 bytes), two parameter blocks (8,192 bytes each) and main blocks (one block of 98,304 bytes and three blocks of 131,072 bytes), define the boot block flash family architecture. See Figures 7 and 8 for memory maps. Each block can be independently erased and programmed 100,000 times at commercial temperature or 10,000 times at extended temperature. The boot block is located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for boot code location. The hardware-lockable boot block provides complete code security for the kernel code required for system initialization. Locking and unlocking of the boot block is controlled by WP# and/or RP# (see Section 3.4 for details). The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the boot block flash memory products. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller of these tasks. The Status Register (SR) indicates the status of the WSM and whether it successfully completed the desired program or erase operation. Program and Erase Automation allows program and erase operations to be executed using an industry- standard two-write command sequence to the CUI. Data writes are performed in word (28F400 family) or byte (28F400 or 28F004B families) increments. Each byte or word in the flash memory can be programmed independently of other memory locations, unlike erases, which erase all locations within a block simultaneously. The 4-Mbit SmartVoltage boot block flash memory family is also designed with an Automatic Power Savings (APS) feature which minimizes system battery current drain, allowing for very low power designs. To provide even greater power savings, the boot block family includes a deep power-down mode which minimizes power consumption by turning most of the flash memory’s circuitry off. This mode is controlled by the RP# pin and its usage is discussed in Section 3.5, along with other power consumption issues. Additionally, the RP# pin provides protection against unwanted command writes due to invalid system bus c onditions that may occur during system reset and power-up/down sequences. For example, when the flash memory powers-up, it automatically defaults to the read array mode, but during a warm system reset, where power continues uninterrupted to the system components, the flash memory could remain in a non-read mode, such as erase. Consequently, the system Reset signal should be tied to RP# to reset the memory to normal read mode upon activation of the Reset signal. See Section 3.6. The 28F400 provides both byte-wide or word-wide input/output, which is controlled by the BYTE# pin. Please see Table 2 and Figure 16 for a detailed description of BYTE# operations, especially the usage of the DQ 15/A–1 pin. The 28F400 products are available in a ROM/EPROM-compatible pinout and housed in the 44-lead PSOP (Plastic Small Outline) package, the 48-lead TSOP (Thin Small Outline, 1.2 mm thick) package and the 56-lead TSOP as shown in Figures 4, 5 and 6, respectively. The 28F004 products are available in the 40-lead TSOP package as shown in Figure 3. Refer to the DC Characteristics Table, Section 5.2 (commercial temperature) and Section 6.2 (extended temperature), for complete current and voltage specifications. Refer to the AC Characteristics Table, Section 5.3 (commercial temperature) and Section 6.3 (extended temperature), for read, write and erase performance specifications.
1.3 Applications
during the production phase. of costly product returns or technician calls. configuration of ISA and PCI add-in cards.
16 Kbytes of hardware-protected boot code, four
numbers, authorization codes).
1.4 Pinouts
Figure 3. The 28F400 44-lead PSOP pinout follows pinouts going outward from the center.
8 PRELIMINARY
A data bus buffer may be needed for processor speeds above 25 MHz. Figure 1. 28F400 Interface to Intel386™ EX Microprocessor Figure 2. 28F004B Interface to Intel80C188EB 8-Bit Embedded Microprocessor
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Figure 5. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation Figure 6. The 56-Lead TSOP Offers Compatibility between 2 and 4 Mbits
1.5 Pin Descriptions
Table 2. 28F400/004 Pin Descriptions don’t care in the signature mode when BYTE# is low. when CE# and WE# are active. Data is internally latched during the write cycle. tri-state when the chip is de-selected or the outputs are disabled. during a Program command. Data is internally latched during the write cycle. 15/A–1 becomes the lowest order address for data output on DQ0–DQ 7. The 28F004B does not include these DQ8–DQ 15 pins. through the CE# and RP# input stages. a read cycle. OE# is active low. WE# INPUT WRITE ENABLE: Controls writes to the Command Register and array blocks. unlocking. It is backwards-compatible with the BX/BL/BV products. transitions from logic-low to logic-high, the device defaults to the read array mode. erased. This overrides any control from the WP# input.
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Table 2. 28F400/004 Pin Descriptions (Continued) HH . See Section 3.4 for details on write protection. read and programmed on DQ0–DQ 15. against Program and Erase commands. GND GROUND: For all internal circuitry. NC NO CONNECT: Pin may be driven or left floating.
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2.0 PRODUCT DESCRIPTION
2.1 Memory Blocking Organization
This product family features an asymmetrically- blocked architecture providing system memory integration. Each erase block can be erased independently of the others up to 100,000 times for commercial temperature or up to 10,000 times for extended temperature. The block sizes have been chosen to optimize their functionality for common applications of nonvolatile storage. The combination of block sizes in the boot block architecture allow the integration of several memories into a single chip. For the address locations of the blocks, see the memory maps in Figures 4 and 5.
2.1.1 ONE 16-KB BOOT BLOCK
The boot block is intended to replace a dedicated boot PROM in a microprocessor or microcontroller- based system. The 16-Kbyte (16,384 bytes) boot block is located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map to accommodate different microprocessor protocols for boot code location. This boot block features hardware controllable write-protection to protect the crucial microprocessor boot code from accidental modification. The protection of the boot block is controlled using a combination of the V PP , RP#, and WP# pins, as is detailed in Section 3.4.
2.1.2 TWO 8-KB PARAMETER BLOCKS
The boot block architecture includes parameter blocks to facilitate storage of frequently updated small parameters that would normally require an EEPROM. By using software techniques, the byte- rewrite functionality of EEPROMs can be emulated. These techniques are detailed in Intel’s application note, AP-604 Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM. Each boot block component contains two parameter blocks of 8 Kbytes (8,192 bytes) each. The parameter blocks are not write-protectable.
2.1.3 ONE 96-KB + THREE 128-KB
After the allocation of address space to the boot and parameter blocks, the remainder is divided into main blocks for data or code storage. Each 4-Mbit device contains one 96-Kbyte (98,304 byte) block and three 128-Kbyte (131,072 byte) blocks. See the memory maps for each device for more information.
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Figure 7. Word-Wide x16-Mode Memory Maps NOTE: Address = A[18:0]. These memory maps apply to the 28F004B or the 28F400 in x8 mode. Figure 8. Byte-Wide x8-Mode Memory Maps
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3.0 PRODUCT FAMILY PRINCIPLES
Flash memory combines EPROM functionality with in-circuit electrical write and erase. The boot block flash family utilizes a Command User Interface (CUI) and automated algorithms to simplify write and erase operations. The CUI allows for 100% TTL-level control inputs, fixed power supplies during erasure and programming, and maximum EPROM compatibility. When V PP < VPPLK , the device will only successfully execute the following commands: Read Array, Read Status Register, Clear Status Register and intelligent identifier mode. The device provides standard EPROM read, standby and output disable operations. Manufacturer identification and device identification data can be accessed through the CUI or through the standard EPROM A 9 high voltage access (VID) for PROM programming equipment. The same EPROM read, standby and output disable functions are available when 5V or 12V is applied to the V PP pin. In addition, 5V or 12V on VPP allows write and erase of the device. All functions associated with altering memory contents: Program and Erase, Intelligent Identifier Read, and Read Status are accessed via the CUI. The internal Write State Machine (WSM) completely automates program and erase, beginning operation signaled by the CUI and reporting status through the Status Register. The CUI handles the WE# interface to the data and address latches, as well as system status requests during WSM operation.
3.1 Bus Operations
Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. These bus operations are summarized in Tables 3 and 4.
3.2 Read Operations
3.2.1 READ ARRAY
When RP# transitions from VIL (reset) to VIH, the device will be in the read array mode and will respond to the read control inputs (CE#, address inputs, and OE#) without any commands being written to the CUI. When the device is in the read array mode, five control signals must be controlled to obtain data at the outputs.
- RP# must be logic high (V IH)
- WE# must be logic high (VIH)
- BYTE# must be logic high or logic low
- CE# must be logic low (VIL)
- OE must be logic low (VIL) In addition, the address of the desired location must be applied to the address pins. Refer to Figures 15 and 16 for the exact sequence and timing of these signals. If the device is not in read array mode, as would be the case after a program or erase operation, the Read Mode command (FFH) must be written to the CUI before reads can take place. During system design, consideration should be taken to ensure address and control inputs meet required input slew rates of <10 ns as defined in Figures 12 and 13.
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Table 3. Bus Operations for Word-Wide Mode (BYTE# = VIH) Table 4. Bus Operations for Byte-Wide Mode (BYTE# = VIL)
- Refer to DC Characteristics.
IL, VIH for control pins and addresses, VPPLK or VPPH for VPP .
- See DC Characteristics for VPPLK , VPPH1 , VPPH2 , VHH , VID voltages.
- Manufacturer and device codes may also be accessed via a CUI write sequence, A1–A17 = X, A1–A18 = X.
- See Table 5 for device IDs.
- Refer to Table 7 for valid D
IN during a write operation.
- Command writes for block erase or word/byte program are only executed when VPP = VPPH1 or VPPH2 .
- To write or erase the boot block, hold RP# at VHH or WP# at VIH. See Section 3.4.
- RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.
3.2.2 INTELLIGENT IDENTIFIERS
Table 5. Intelligent Identifier Table
3.3 Write Operations
3.3.1 COMMAND USER INTERFACE (CUI)
3.3.1.1 Command Function Description
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Table 6. Command Codes and Descriptions
00 Invalid/
these codes for future functions.
40 Program
when OE# is enabled. To read the array, issue a Read Array command.
10 Alternate
20 Erase
this can not cancel that operation in progress. address and data, and begin erasing the block indicated on the address pins. Suspend commands and will output Status Register data when OE# is toggled low. Status Register data is updated by toggling either OE# or CE# low.
70 Read Status
outputs Status Register data, regardless of the address presented to the device. The device automatically enters this mode after program or erase has completed. This is one of the two commands that is executable while the WSM is operating.
Table 6. Command Codes and Descriptions (Continued)
50 Clear Status
90 Intelligent
A0 = 1 for device, all other address inputs are ignored). See Section 3.2.2. Table 7. Command Bus Definitions
- Bus operations are defined in Tables 3 and 4.
- IA = Identifier Address: A0 = 0 for manufacturer code, A0 = 1 for device code.
- SRD - Data read from Status Register.
- IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and
- BA = Address within the block being erased.
- PA = Address to be programmed. PD = Data to be programmed at location PA.
- Either 40H or 10H commands is valid.
- When writing commands to the device, the upper data bus [DQ
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Table 8. Status Register Bit Definition before checking Program or Erase Status bits. still unable to verify successful block erasure. but failed to program a byte or word. be masked out when polling the Status Register.
3.3.2 STATUS REGISTER
DQ 15/A–1 retains the low order address function. Status Register contents change while being read. completion of a program or erase operation. successful in performing the desired operation.
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3.3.2.1 Clearing the Status Register
The WSM sets status bits 3 through 7 to “1,” and clears bits 6 and 7 to “0,” but cannot clear status bits 3 through 5 to “0.” Bits 3 through 5 can only be cleared by the controlling CPU through the use of the Clear Status Register (50H) command, because these bits indicate various error conditions. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence) before reading the Status Register to determine if an error occurred during that series. Clear the Status Register before beginning another command or sequence. Note, again, that a Read Array command must be issued before data can be read from the memory or intelligent identifier.
3.3.3 PROGRAM MODE
Programming is executed using a two-write sequence. The Program Setup command is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute a sequence of internally timed events to: 1. Program the desired bits of the addressed memory word or byte. 2. Verify that the desired bits are sufficiently programmed. Programming of the memory results in specific bits within a byte or word being changed to a “0.” If the user attempts to program “1”s, there will be no change of the memory cell content and no error occurs. The Status Register indicates programming status: while the program sequence is executing, bit 7 of the Status Register is a “0.” The Status Register can be polled by toggling either CE# or OE#. While programming, the only valid command is Read Status Register. When programming is complete, the Program Status bits should be checked. If the programming operation was unsuccessful, bit 4 of the Status Register is set to a “1” to indicate a Program Failure. If bit 3 is set to a “1,” then V PP was not within acceptable limits, and the WSM did not execute the programming sequence. The Status Register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, reads from the Memory Array or Intelligent Identifier cannot be accomplished until the CUI is given the appropriate command.
3.3.4 ERASE MODE
To erase a block, write the Erase Set-Up and Erase Confirm commands to the CUI, along with the addresses identifying the block to be erased. These addresses are latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only one block can be erased at a time. The WSM will execute a sequence of internally timed events to: 1. Program all bits within the block to “0.” 2. Verify that all bits within the block are sufficiently programmed to “0.” 3. Erase all bits within the block to “1.” 4. Verify that all bits within the block are sufficiently erased. While the erase sequence is executing, bit 7 of the Status Register is a “0.” When the Status Register indicates that erasure is complete, check the Erase Status bit to verify that the erase operation was successful. If the Erase operation was unsuccessful, bit 5 of the Status Register will be set to a “1,” indicating an Erase Failure. If V PP was not within acceptable limits after the Erase Confirm command is issued, the WSM will not execute an erase sequence; instead, bit 5 of the Status Register is set to a “1” to indicate an Erase Failure, and bit 3 is set to a “1” to identify that V PP supply voltage was not within acceptable limits. Clear the Status Register before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, reads from the Memory Array, Status Register, or Intelligent Identifier cannot be accomplished until the CUI is given the Read Array command.
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3.3.4.1 Suspending and Resuming Erase
operation has been suspended. command or Read Status Register command. reduces active current draw.
3.4 Boot Block Locking
3.4.2 WP# = V
3.4.3 RP# = V HH OR WP# = VIH FOR BOOT
3.4.4 UPGRADE NOTE FOR 8-MBIT
density-package combinations have WP# pins. Table 9. Write Protection Truth Table
before further attempts are allowed by the Write State Machine. retry or other error recovery. Repeat for subsequent word/byte program operations. or after a sequence of word/byte programs. Figure 9. Automated Word/Byte Programming Flowchart
24 PRELIMINARY
attempts are allowed by the Write State Machine. cases where multiple blocks are erase before full status is checked. retry or other error recovery. Repeat for subsequent block erasures. Write FFH after the last operation to reset device to read array mode. Figure 10. Automated Block Erase Flowchart
Figure 11. Erase Suspend/Resume Flowchart
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3.5 Power Consumption
3.5.1 ACTIVE POWER
With CE# at a logic-low level and RP# at a logic- high level, the device is placed in the active mode. Refer to the DC Characteristics table for I CC current values.
3.5.2 AUTOMATIC POWER SAVINGS (APS)
Automatic Power Savings (APS) provides low- power operation during active mode. Power Reduction Control (PRC) circuitry allows the device to put itself into a low current state when not being accessed. After data is read from the memory array, PRC logic controls the device’s power consumption by entering the APS mode where typical I CC current is less than 1 mA. The device stays in this static state with outputs valid until a new location is read.
3.5.3 STANDBY POWER
With CE# at a logic-high level (V IH), and the CUI in read mode, the memory is placed in standby mode, which disables much of the device’s circuitry and substantially reduces power consumption. Outputs (DQ 0–DQ 15 or DQ 0–DQ 7) are placed in a high- impedance state independent of the status of the OE# signal. When CE# is at logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed.
3.5.4 DEEP POWER-DOWN MODE
The SmartVoltage boot block family supports a low typical I CC in deep power-down mode, which turns off all circuits to save power. This mode is activated by the RP# pin when it is at a logic-low (GND ± 0.2V). Note: BYTE# pin must be at CMOS levels to meet the I CCD specification. During read modes, the RP# pin going low de- selects the memory and places the output drivers in a high impedance state. Recovery from the deep power-down state, requires a minimum access time of t PHQV (see AC Characteristics table). During erase or program modes, RP# low will abort either erase or program operations, but the memory contents are no longer valid as the data has been corrupted by the RP# function. As in the read mode above, all internal circuitry is turned off to achieve the power savings. RP# transitions to V IL, or turning power off to the device will clear the Status Register.
3.6 Power-Up/Down Operation
The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, V PP or VCC , powers-up first. The CUI is reset to the read mode after power-up, but the system must drop CE# low or present a new address to ensure valid data at the outputs. A system designer must guard against spurious writes when V CC voltages are above VLKO and VPP is active. Since both WE# and CE# must be low for a command write, driving either signal to V IH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RP# is brought to V IH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.
3.6.1 RP# CONNECTED TO SYSTEM
The use of RP# during system reset is important with automated write/erase devices because the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization would not occur because the flash memory may be providing status information instead of array data. Intel’s Flash memories allow proper CPU initialization following a system reset by connecting the RP# pin to the same RESET# signal that resets the system CPU.
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3.6.2 V CC , VPP AND RP# TRANSITIONS
The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from deep power-down mode, or after V CC transitions above VLKO (Lockout voltage), is read array mode. After any word/byte write or block erase operation is complete and even after VPP transitions down to VPPLK , the CUI must be reset to read array mode via the Read Array command if accesses to the flash memory are desired. Please refer to Intel’s application note AP-617 Additional Flash Data Protection Using VPP , RP#, and WP#, for a circuit-level discription of how to implement the protection discussed in Section 3.6.
3.7 Power Supply Decoupling
Flash memory’s power switching characteristics require careful device decoupling methods. System designers should consider three supply current issues: 1. Standby current levels (I CCS ) 2. Active current levels (ICCR ) 3. Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each V CC and GND, and between its VPP and GND. These high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 3.7.1 V PP TRACE ON PRINTED CIRCUIT BOARDS Designing for in-system writes to the flash memory requires special consideration of the VPP power supply trace by the printed circuit board designer. The V PP pin supplies the flash memory cells current for programming and erasing. One should use similar trace widths and layout considerations given to the V CC power supply trace. Adequate VPP supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots. NOTE: Table headings in Sections 5 and 6 (i.e., BV-60, BV-80, BV-120, TBV-80, TBE-120) refer to the specific products listed below. See Appendix A for more information on product naming and line items. Abbreviation Applicable Product Names BV-60 E28F004BV-T60, E28F004BV-B60, PA28F400BV-T60, PA28F400BV-B60, E28F400CV-T60, E28F400CV-B60, E28F400BV-T60, E28F400BV-B60 BV-80 E28F004BV-T80, E28F004BV-B80, PA28F400BV-T80, PA28F400BV-B80, E28F400CV-T80, E28F400CV-B80, E28F400BV-T80, E28F400BV-B80 BV-120 E28F004BV-T120, E28F004BV-B120, PA28F400BV-T120, PA28F400BV-B120 TBV-80 TE28F004BV-T80, TE28F004BV-B80, TB28F400BV-T80, TB28F400BV-B80, TE28F400CV-T80, TE28F400CV-B80, TE28F400BV-T80, TE28F400BV-B80 TBE-120 TE28F004BE-T120, TE28F004BE-B120, TE28F400CE-T120, TE28F400CE-B120
4-MBIT SmartVoltage BOOT BLOCK FAMILY E
28 PRELIMINARY
4.0 ABSOLUTE MAXIMUM
RATINGS* Commercial Operating Temperature During Block Erase Extended Operating Temperature During Block Erase Voltage on Any Pin (except V CC , VPP , A9 and RP#) Voltage on Pin RP# or Pin A9 VPP Program Voltage with Respect to GND during Block Erase VCC Supply Voltage NOTICE: This datasheet contains preliminary information on new products in production. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. * WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may effect device reliability. NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is –0.5V on input/output pins. During transitions, this level may undershoot to –2.0V for periods <20 ns. Maximum DC voltage on input/output pins is V CC + 0.5V which, during transitions, may overshoot to VCC + 2.0V for periods <20 ns. 3. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns. Maximum DC voltage on RP# or A9 may overshoot to 13.5V for periods <20 ns. 4. Output shorted for no more than one second. No more than one output shorted at a time.
5.0 COMMERCIAL OPERATING CONDITIONS
Table 10. Commercial Temperature and VCC Operating Conditions
- 10% VCC specifications apply to the 60 ns, 80 ns and 120 ns product versions in their standard test configuration.
- 5% VCC specifications apply to the 60 ns version in its high-speed test configuration.
5.1 Applying V CC Voltages
≤ 1V/100 µs No delay required.
- These requirements must be strictly followed to guarantee all other read and write specifications.
- To switch between 3.3V and 5V operation, the system should first transition V
- These guidelines must be followed for any VCC transition from GND.
30 PRELIMINARY
5.2 DC Characteristics
Table 11. DC Characteristics (Commercial)
Table 11. DC Characteristics (Commercial) (Continued)
32 PRELIMINARY
2.0 VCC +
Table 12. Capacitance (TA = 25°C, f = 1 MHz)
- All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T = +25°C. These currents are valid for all
product versions (packages and speeds).
- ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of
- Block erases and word/byte writes are inhibited when VPP = VPPLK , and not guaranteed in the range between VPPH 1 and
- Sampled, not 100% tested.
- Automatic Power Savings (APS) reduces I
CCR to less than 1 mA typical, in static operation.
- For the 28F004B, address pin A10 follows the COUT capacitance numbers.
- For all BV/CV parts, VLKO = 2.0V for both 3.3V and 5V operations.
34 PRELIMINARY
5.3 AC Characteristics
Table 13. AC Characteristics: Read Only Operations (Commercial)
Table 13. AC Characteristics: Read Only Operations (Commercial) (Continued)
- See AC Input/Output Reference Waveform for timing measurements.
- OE# may be delayed up to t
CE –tOE after the falling edge of CE# without impact on tCE .
- Sampled, but not 100% tested.
FLQV , BYTE# switching low to valid output delay will be equal to tAVQV , measured from the time DQ15/A–1 becomes valid.
- See Test Configurations (Figure 14), 3.3V Standard Test component values.
- See Test Configurations (Figure 14), 5V High-Speed Test component values.
- See Test Configurations (Figure 14), 5V Standard Test component values.
PLPH is the minimum time RP# must be held low to produce a valid reset of the device.
36 PRELIMINARY
Figure 15. AC Waveforms for Read Operations Figure 16. BYTE# Timing Diagram for Read Operations
Table 14. AC Characteristics: WE#–Controlled Write Operations (1) (Commercial)
38 PRELIMINARY
Table 14. AC Characteristics: WE#–Controlled Write Operations (1) (Commercial) (Continued)
- Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during read mode.
- The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.
- Refer to command definition table for valid AIN. (Table 7)
- Refer to command definition table for valid DIN. (Table 7)
- Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
- For boot block program/erase, RP# should be held at V
- Time tPHBR is required for successful locking of the boot block.
- Sampled, but not 100% tested.
- See Test Configurations (Figure 14), 3.3V Standard Test component values.
- See Test Configurations (Figure 14), 5V High-Speed Test component values.
- See Test Configurations (Figure 14), 5V Standard Test component values.
- VCC Power-Up and Standby.
- Write Program or Erase Setup Command.
- Write Valid Address and Data (Program) or Erase Confirm Command.
- Automated Program or Erase Delay.
- Read Status Register Data.
- Write Read Array Command.
Figure 17. AC Waveforms for Write Operations (WE#–Controlled Writes)
40 PRELIMINARY
Table 15. AC Characteristics: CE#–Controlled Write Operations (1,12) (Commercial)
Table 15. AC Characteristics: CE#–Controlled Write Operations (1,12) (Commercial) (Continued)
42 PRELIMINARY
See WE# Controlled Write Operations for notes 1 through 11.
- Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where
be measured relative to the CE# waveform.
- VCC Power-Up and Standby.
- Write Program or Erase Setup Command.
- Write Valid Address and Data (Program) or Erase Confirm Command.
- Automated Program or Erase Delay.
- Read Status Register Data.
- Write Read Array Command.
Figure 18. Alternate AC Waveforms for Write Operations (CE#–Controlled Writes)
Table 16. Erase and Program Timings (Commercial TA = 0°C to +70°C)
- All numbers are sampled, not 100% tested.
- Max erase times are specified under worst case conditions. The max erase times are tested at the same value
CC and VPP . See Note 3 for typical conditions.
- Typical conditions are +25°C with VCC and VPP at the center of the specifed voltage range. Production programming using
VCC = 5.0V, VPP = 12.0V typically results in a 60% reduction in programming time.
- Contact your Intel field representative for more information.
44 PRELIMINARY
6.0 EXTENDED OPERATING CONDITIONS
Table 17. Extended Temperature and VCC Operating Conditions
- AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
- 10% VCC specifications apply to 80 ns and 120 ns versions in their standard test configuration.
6.1 Applying V CC Voltages
≤ 1V/100 µs No delay required.
- These requirements must be strictly followed to guarantee all other read and write specifications.
- To switch between 3.3V and 5V operation, the system should first transition V
- These guidelines must be followed for any VCC transition from GND.
6.2 DC Characteristics
Table 18. DC Characteristics: Extended Temperature Operation
46 PRELIMINARY
Table 18. DC Characteristics: Extended Temperature Operation (Continued)
48 PRELIMINARY
2.0 VCC
Table 19. Capacitance (TA = 25 °C, f = 1 MHz)
- All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T = +25°C. These currents are valid for all
product versions (packages and speeds).
- ICCES is specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR .
- Block erases and word/byte programs inhibited when VPP = VPPLK , and not guaranteed in the range between VPPH 1 and
- Sampled, not 100% tested.
- Automatic Power Savings (APS) reduces I
CCR to less than 1 mA typical, in static operation.
- For the 28F004B address pin A10 follows the COUT capacitance numbers.
50 PRELIMINARY
Input rise and fall times (10% to 90%) <10 ns. Figure 19. 2.7V–3.6V Input Range and Measurement Points Input rise and fall times (10% to 90%) <10 ns. Figure 20. 3.3V Input Range and Measurement Points and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns. Figure 21. 5V Input Range and Measurement Points NOTE: See table for component values. Figure 22. Test Configuration NOTE: CL includes jig capacitance.
6.3 AC Characteristics
Table 20. AC Characteristics: Read Only Operations(1) (Extended Temperature)
- See AC Input/Output Reference Waveform for timing measurements.
- OE# may be delayed up to t
CE –tOE after the falling edge of CE# without impact on tCE .
- Sampled, but not 100% tested.
FLQV , BYTE# switching low to valid output delay will be equal to tAVQV , measured from the time DQ15/A–1 becomes valid.
- See Test Configurations (Figure 22), 5V Standard Test component values.
PLPH is the minimum time RP# must be held low to produce a valid reset of the device.
52 PRELIMINARY
Table 21. AC Characteristics: WE#-Controlled Write Operations(1) (Extended Temperature)
E 4-MBIT SmartVoltage BOOT BLOCK FAMILY 53PRELIMINARY NOTES: 1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to AC Characteristics during read mode. 2. The on-chip WSM completely automates program/e rase operations; program/erase algorithms are now controlled internally which includes verify and margining operations. 3. Refer to command definition table for valid AIN. (Table 7) 4. Refer to command definition table for valid DIN. (Table 7) 5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1) 6. For boot block program/erase, RP# should be held at V HH or WP# should be held at VIH until operation completes successfully. 7. Time tPHBR is required for successful locking of the boot block. 8. Sampled, but not 100% tested. 10. See Test Configurations (Figure 22), 5V Standard Test component values.
54 PRELIMINARY
Table 22. AC Characteristics: CE#–Controlled Write Operations (1,11) (Extended Temperature) See WE# Controlled Write Operations for notes 1 through 10.
- Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE#
measured relative to the CE# waveform.
Table 23. Erase and Program Timings (Extended TA = –40°C to +85°C)
- All numbers are sampled, not 100% tested.
- Max erase times are specified under worst case conditions. The max erase times are tested at the same value
CC and VPP . See Note 3 for typical conditions.
- Typical conditions are +25°C with VCC and VPP at the center of the specifed voltage range. Production programming using
VCC = 5.0V, VPP = 12.0V typically results in a 60% reduction in programming time.
- Contact your Intel field representative for more information.
4-MBIT SmartVoltage BOOT BLOCK FAMILY E
56 PRELIMINARY
ORDERING INFORMATION
for all Intel Flash products Density / Organization X00 = x8/x16 Selectable (X = 2, 4, 8) Access Speed(ns) BV/CV: VCC = 5V BE/CE: VCC = 2.7V Architecture B = Boot Block C = Compact 48-Lead TSOP Boot Block Operating Temperature T = Extended Temp Blank = Commercial Temp Package E = TSOP PA = 44-Lead PSOP TB = Ext. Temp 44-Lead PSOP E28F4 00 CV - T 08 T = Top Boot B = Bottom Boot Voltage Options (VPP /VCC ) V = (5 or 12 / 3.3 or 5) E = (5 or 12 / 2.7 or 5) T 0530_23 VALID COMBINATIONS: 40-Lead TSOP 44-Lead PSOP 48-Lead TSOP 56-Lead TSOP Commercial E28F004BVT60 PA28F400BVT60 E28F400CVT60 E28F400BVT60 E28F004BVB60 PA28F400BVB60 E28F400CVB60 E28F400BVB60 E28F004BVT80 PA28F400BVT80 E28F400CVT80 E28F400BVT80 E28F004BVB80 PA28F400BVB80 E28F400CVB80 E28F400BVB80 E28F004BVT120 PA28F400BVT120 E28F004BVB120 PA28F400BVB120 Extended TE28F004BVT80 TB28F400BVT80 TE28F400CVT80 TE28F400BVT80 TE28F004BVB80 TB28F400BVB80 TE28F400CVB80 TE28F400BVB80 TE28F004BET120 TE28F400CET120 TE28F004BEB120 TE28F400CEB120 Table 24. Summary of Line Items
E 4-MBIT SmartVoltage BOOT BLOCK FAMILY 57PRELIMINARY APPENDIX B ADDITIONAL INFORMATION RELATED INTEL INFORMATION (1,2) Order Number Document
290599 Smart 5 Boot Block Flash Memory Family 2, 4, 8 Mbit Datasheet
292194 AB-65 Migrating Designs from SmartVoltage Boot Block to Smart 5 Flash
292154 AB-60 2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family
290531 2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet 290539 8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
292164 AP-611 2/4M Boot Block Compatibility with 2/4/8-M SmartVoltage Boot Block Flash
290448 28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet 290449 28F002/200BL-T/B 2-Mbit Low Power Boot Block Flash Memory Datasheet 290451 28F004/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet 290450 28F004/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory Datasheet
292148 AP-604 Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM
292172 AP-617 Additional Flash Data Protection Using VPP , RP#, and WP#
292130 AB-57 Boot Block Architecture for Safe Firmware Updates
NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.