E28F002BL-T150

28F200BL-TB INTEL | Alldatasheet

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Technical content

*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. December 1995COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 290449-006 2-MBIT (128K x 16, 256K x 8) LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY 28F200BL-T/B, 28F002BL-T/B Y Low Voltage Operation for Very Low Power Portable Applications ÐV CC e 3.0V–3.6V Y Expanded Temperature Range Ð b20§Ct o a70§C Y x8/x16 Input/Output Architecture Ð 28F200BL-T, 28F200BL-B Ð For High Performance and High Integration 16-bit and 32-bit CPUs Y x8-only Input/Output Architecture Ð 28F002BL-T, 28F002BL-B Ð For Space Constrained 8-bit

Applications

Y Upgradeable to Intel’s SmartVoltage Products Y Optimized High-Density Blocked Architecture Ð One 16-KB Protected Boot Block Ð Two 8-KB Parameter Blocks Ð One 96-KB Main Block Ð One 128-KB Main Block Ð Top or Bottom Boot Locations Y Extended Cycling Capability Ð 10,000 Block Erase Cycles Y Automated Word/Byte Write and Block Erase Ð Command User Interface Ð Status Registers Ð Erase Suspend Capability Y SRAM-Compatible Write Interface Y Automatic Power Savings Feature Ð 0.8 mA Typical I CC Active Current in Static Operation Y Very High-Performance Read Ð 150 ns Maximum Access Time Ð 65 ns Maximum Output Enable Time Y Low Power Consumption Ð 15 mA Typical Active Read Current Y Reset/Deep Power-Down Input Ð 0.2 mAI CC Typical Ð Acts as Reset for Boot Operations Y Write Protection for Boot Block Y Hardware Data Protection Feature Ð Erase/Write Lockout during Power Transitions Y Industry Standard Surface Mount Packaging Ð 28F200BL: JEDEC ROM Compatible 44-Lead PSOP 56-Lead TSOP Ð 28F002BL: 40-Lead TSOP Y 12V Word/Byte Write and Block Erase ÐV PP e 12V g5% Standard Y ETOXTM III Flash Technology Ð 3.3V Read Y Independent Software Vendor Support

28F200BL-T/B, 28F002BL-T/B Intel’s 2-Mbit Low Power Flash Memory Family is an extension of the Boot Block Architecture which includes block-selective erasure, automated write and erase operations and standard microprocessor interface. The 2-Mbit Flash Memory Family enhances the Boot Block Architecture by adding more density and blocks, x8/x16 input/output control, very low power, very high speed, an industry standard ROM compatible pinout and surface mount packaging. The 2-Mbit Low Power Flash Family opens a new capability for 3V battery-oper- ated portable systems and allows for an easy upgrade to Intel’s 4-Mbit Low Power Boot Block Flash Memory Family. The Intel 28F200BL-T/B are 16-bit wide flash memory offerings. These high density flash memories provide user selectable bus operation for either 8-bit or 16-bit applications. The 28F200BL-T and 28F200BL-B are 2,097,152-bit non-volatile memories organized as either 262,144 bytes or 131,072 words of information. They are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the industry standard ROM/EPROM pinout. The Intel 28F002BL-T/B are 8-bit wide flash memories with 2,097,152 bits organized as 262,144 bytes of information. They are offered in a 40-Lead TSOP package, which is ideal for space-constrained portable systems. These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified word/byte write and block erasure. The 28F200BL-T/28F002BL-T provide block locations compatible with Intel’s low voltage MCS-186 family, i386 TM, i486 TM microprocessors. The 28F200BL-B/28F002BL-B provide compatibility with Intel’s 80960KX and 80960SX families as well as other low voltage embedded microproces- sors. The boot block includes a data protection feature to protect the boot code in critical applications. With a maximum access time of 150 ns, these 2-Mbit flash devices are very high performance low power memories which interface to a wide range of low power microprocessors and microcontrollers. A deep power-down mode lowers the total V CC power consumption to 0.66 mW. This is critical in handheld battery powered systems such as Handy Phones. For very high speed applications using a 5V supply, refer to the Intel 28F200BX-T/B, 28F002BX-T/B 2-Mbit Boot Block Flash Memory Family datasheet. Manufactured on Intel’s 0.8 micron ETOX III process, the 2-Mbit low power flash memory family provides world class quality, reliability and cost-effectiveness at the 2-Mbit density level.

28F200BL-T/B, 28F002BL-T/B

1.0 PRODUCT FAMILY OVERVIEW

Throughout this datasheet 28F200BL refers to both the 28F200BL-T and 28F200BL-B devices and 28F002BL refers to both the 28F002BL-T and 28F002BL-B devices. The 2-Mbit flash family refers to both the 28F200BL and 28F002BL products. This datasheet comprises the specifications for four sep- arate products in the 2-Mbit flash memory family. Section 1 provides an overview of the 2-Mbit flash memory family including applications, pinouts and pin descriptions. Sections 2 and 3 describe in detail the specific memory organizations for the 28F200BL and 28F002BL products respectively. Section 4 combines a description of the family’s principles of operations. Finally, section 5 describes the family’s operating specifications. PRODUCT FAMILY x8/x16 Products x8-Only Products 28F200BL-T 28F002BL-T 28F200BL-B 28F002BL-B

1.1 Designing for Upgrade to

Today’s high volume boot block products are up- gradable to Intel’s SmartVoltage boot block prod- ucts that provide program and erase operation at 5V or 12V V PP and read operation at 3V or 5V V CC. Intel’s SmartVoltage boot block products provide the following enhancements to the boot block products described in this data sheet: 1. DU pin is replaced by WP Ý to provide a means to lock and unlock the boot block with logic sig- nals. 2. 5V Program/Erase operation uses proven pro- gram and erase techniques with 5V g10% ap- plied to V PP. 3. Enhanced circuits optimize performance at 3.3V VCC. Refer to the 2, 4 or 8 Mbit SmartVoltage Boot Block Flash Memory Data Sheets for complete specifica- tions. When you design with 12V V PP boot block products you should provide the capability in your board de- sign to upgrade to SmartVoltage products. Follow these guidelines to ensure compatibility: 1. Connect DU (WP Ý on SmartVoltage products) to a control signal or to V CC or GND. 2. If adding a switch on V PP for write protection, switch to GND for complete write protection. 3. Allow for connecting 5V to V PP and disconnect 12V from line V PP line, if desired.

1.2 Main Features

The 28F200BL/28F002BL low power boot block flash memory family is a very low power and very high performance 2-Mbit (2,097,152 bit) memory family organized as either 128 Kwords (131,072 words) of 16 bits each or 256 Kbytes (262,144 bytes) of 8 bits each. Five Separately Erasable Blocks including a Hard- ware-Lockable boot block (16,384 Bytes), two pa- rameter blocks (8,192 Bytes each) and two main blocks (1 block of 98,304 Bytes and 1 block of 131,072 Bytes) are included on the 2-Mbit family. An erase operation erases one of the 5 blocks in typi- cally 3.4 seconds and the boot or parameter blocks in typically 2.0 seconds, independent of the remain- ing blocks. Each block can be independently erased and programmed 10,000 times. The Boot Block is located at either the top (28F200BL-T, 28F002BL-T) or the bottom (28F200BL-B, 28F002BL-B) of the address map in order to accommodate different microprocessor pro- tocols for boot code location. The hardware locka- ble boot block provides the most secure code stor- age. The boot block is intended to store the kernel code required for booting-up a system. When the RP Ý pin is between 11.4V and 12.6V the boot block is unlocked and program and erase operations can be performed. When the RP Ý pin is at or below 4.1V the boot block is locked and program and erase op- erations to the boot block are ignored. The 28F200BL products are available in the ROM/EPROM compatible pinout and housed in the 44-Lead PSOP (Plastic Small Outline) package and the 56-Lead TSOP (Thin Small Outline, 1.2 mm thick) package as shown in Figures 3 and 4. The 28F002BL products are available in the 40-Lead TSOP (1.2 mm thick) package as shown in Figure 5. The Command User Interface (CUI) serves as the interface between the microprocessor or microcon- troller and the internal operation of the 28F200BL and 28F002BL flash memory products.

28F200BL-T/B, 28F002BL-T/B Program and Erase Automation allow program and erase operations to be executed using a two- write command sequence to the CUI. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verifications, there- by unburdening the microprocessor or microcontrol- ler. Writing of memory data is performed in word or byte increments for the 28F200BL family and in byte increments for the 28F002BL family typically within 11 ms. The Status Register (SR) indicates the status of the WSM and whether the WSM successfully completed the desired program or erase operation. Maximum Access Time of 150 ns (t ACC) is achieved over the commercial temperature range (0 §Ct o a70§C), over V CC supply voltage range (3.0V to 3.6V, 4.5V to 5.5V) and 50 pF output load. IPP Program current is 40 mA for x16 operation and 30 mA for x8 operation. I PP Erase current is 30 mA maximum. V PP erase and programming voltage is 11.4V to 12.6V (V PP e 12V g5%) un- der all operating conditions. Typical I CC Active Current of 15 mA is achieved for the x16 products and the x8 products. The 2-Mbit flash family is also designed with an Au- tomatic Power Savings (APS) feature to minimize system battery current drain and allow for extremely low power designs. Once the device is accessed to read the array data, APS mode will immediately put the memory in static mode of operation where I CC active current is typically 0.8 mA until the next read is initiated. When the CE Ý and RP Ý pins are at V CC and the BYTEÝ pin (28F200BL-only) is at either V CC or GND the CMOS Standby mode is enabled where ICC is typically 40 mA. A Deep Power-down Mode is enabled when the RPÝ pin is at ground minimizing power consumption and providing write protection during power-up con- ditions. I CC current during deep power-down mode is 0.20 mA typical . An initial maximum access time or Reset Time of 600 ns is required from RP Ý switching until outputs are valid. Equivalently, the device has a maximum wake-up time of 1 ms until writes to the Command User Interface are recog- nized. When RP Ý is at ground the WSM is reset, the Status Register is cleared and the entire device is protected from being written to. This feature pre- vents data corruption and protects the code stored in the device during system reset. The system Reset pin can be tied to RP Ý to reset the memory to nor- mal read mode upon activation of the Reset pin. When the CPU enters reset mode, it expects to read the contents of a memory location. Furthermore, with on-chip program/erase automation in the 2-Mbit family and the RP Ý functionality for data pro- tection, after the CPU is reset and even if a program or erase command is issued, the device will not rec- ognize any operation until RP Ý returns to its normal state. For the 28F200BL, Byte-wide or Word-wide In- put/Output Control is possible by controlling the BYTEÝ pin. When the BYTE Ý pin is at a logic low the device is in the byte-wide mode (x8) and data is read and written through DQ [0:7]. During the byte- wide mode, DQ [8:14] are tri-stated and DQ 15/Ab1 becomes the lowest order address pin. When the BYTEÝ pin is at a logic high the device is in the word-wide mode (x16) and data is read and written through DQ [0:15].

1.3 Applications

The 2-Mbit low power boot block flash memory fami- ly combines high density, 3V operation, high per- formance, cost-effective flash memories with block- ing and hardware protection capabilities. Its flexibility and versatility will reduce costs throughout the prod- uct life cycle. Flash memory is ideal for Just-In-Time production flow, reducing system inventory and costs, and eliminating component handling during the production phase. During the product life cycle, when code updates or feature enhancements be- come necessary, flash memory will reduce the up- date costs by allowing either a user-performed code change via floppy disk or a remote code change via a serial link. The 2-Mbit boot block flash memory family provides full function, blocked flash memories suitable for a wide range of applications. These ap- plications include Extended PC BIOS, Handy Digi- tal Cellular Phone program and data storage and various other portable embedded applications where both program and data storage are required. Reprogrammable systems such as Notebook and Palmtop computers, are ideal applications for the 2-Mbit low power flash products. Portable and han- dheld personal computer applications are becoming more complex with the addition of power manage- ment software to take advantage of the latest micro- processor technology, the availability of ROM-based application software, pen tablet code for electronic handwriting, and diagnostic code. Figure 1 shows an example of a 28F200BL-T application. This increase in software sophistication augments the probability that a code update will be required after the PC is shipped. The 2-Mbit low power flash memory products provide an inexpensive update so-

quire operation at extremely low power levels.

16 Kbytes of Hardware-Protected Boot code, 2 Main

8 Kbytes each for frequently updatable data storage

application with the 28F002BL-T. ers to achieve the best possible product design. a versatile low power product family. Figure 1. 28F200BL-T Interface to Intel386 TM EX Embedded Processor Figure 2. 28F002BL-T Interface to INTEL 80L188EB, Low Voltage 8-Bit Embedded Microprocessor

1.4 Pinouts

and to future higher density boot block memories. Figure 3. PSOP Lead Configuration for x8/x16 28F200BL

28F200BL-T/B, 28F002BL-T/B

1.5 Pin Descriptions for x8/x16 28F200BL

Symbol Type Name and Function A0 –A16 I ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle. A9 I ADDRESS INPUT: When A 9 is at 12V the signature mode is accessed. During this mode A 0 decodes between the manufacturer and device ID’s. When BYTE Ý is at a logic low only the lower byte of the signatures are read. DQ 15/Ab1 is a don’t care in the signature mode when BYTE Ý is low. DQ0 –DQ7 I/O DATA INPUTS/OUTPUTS: Inputs array data on the second CE Ý and WE Ý cycle during a program command. Inputs commands to the command user interface when CE Ý and WE Ý are active. Data is internally latched during the write and program cycles. Outputs array, Intelligent Identifier and Status Register data. The data pins float to tri-state when the chip is deselected or the outputs are disabled. DQ8 –DQ15 I/O DATA INPUT/OUTPUTS: Inputs array data on the second CE Ý and WE Ý cycle during a program command. Data is internally latched during the write and program cycles. Outputs array data. The data pins float to tri-state when the chip is deselected or the outputs are disabled as in the byte-wide mode (BYTE Ý e ‘‘0’’). In the byte-wide mode DQ 15/Ab1 becomes the lowest order address for data output on DQ 0-DQ7. CEÝ I CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers. CE Ý is active low; CE Ý high deselects the memory device and reduces power consumption to standby levels. If CE Ý and RP Ý are high, but not at a CMOS high level, the standby current will increase due to current flow through the CE Ý and RP Ý input stages. RPÝ I RESET/DEEP POWER-DOWN: Provides Three-State control. Puts the device in deep power-down mode. Locks the boot block from program/erase. When RP Ý is at logic high level and equals 4.1V maximum the boot block is locked and cannot be programmed or erased. When RP Ý e 11.4V minimum the boot block is unlocked and can be programmed or erased. When RP Ý is at a logic low level the boot block is locked, the deep power-down mode is enabled and the WSM is reset preventing any blocks from being programmed or erased, therefore providing data protection during power transitions. When RP Ý transitions from logic low to logic high, the flash memory enters the read-array mode. OEÝ I OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a read cycle. OE Ý is active low. WEÝ I WRITE ENABLE: Controls writes to the Command Register and array blocks. WEÝ is active low. Addresses and data are latched on the rising edge of the WE Ý pulse.

28F200BL-T/B, 28F002BL-T/B

1.5 Pin Descriptions for x8/x16 28F200BL (Continued)

Symbol Type Name and Function BYTEÝ I BYTEÝ ENABLE: Controls whether the device operates in the byte-wide mode (x8) or the word-wide mode (x16). BYTE Ý e ‘‘0’’ enables the byte-wide mode, where data is read and programmed on DQ 0 –DQ7 and DQ 15/Ab1 becomes the lowest order address that decodes between the upper and lower byte. DQ 8 –DQ14 are tri-stated during the byte-wide mode. BYTE Ý e ‘‘1’’ enables the word-wide mode where data is read and programmed on DQ 0 –DQ15. VPP PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming data in each block. Note: VPP k VPPLMAX memory contents cannot be altered. VCC DEVICE POWER SUPPLY (3.3V g0.3V, 5V g10%) GND GROUND: For all internal circuitry. NC NO CONNECT: Pin may be driven or left floating. DU DON’T USE PIN: Pin should not be connected to anything.

28F200BL-T/B, 28F002BL-T/B

1.6 Pin Descriptions for x8 28F002BL

Symbol Type Name and Function A0 –A17 I ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle. A9 I ADDRESS INPUT: When A 9 is at 12V the signature mode is accessed. During this mode A 0 decodes between the manufacturer and device ID’s. DQ0 –DQ7 I/O DATA INPUTS/OUTPUTS: Inputs array data on the second CE Ý and WE Ý cycle during a program command. Inputs commands to the command user interface when CE Ý and WE Ý are active. Data is internally latched during the write and program cycles. Outputs array Intelligent Identifier and status register data. The data pins float to tri-state when the chip is deselected or the outputs are disabled. CEÝ I CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers. CE Ý is active low; CE Ý high deselects the memory device and reduces power consumption to standby levels. RPÝ I RESET/DEEP POWER-DOWN: Provides Three-State control. Puts the device in deep power-down mode. Locks the Boot Block from program/erase. When RP Ý is at logic high level and equals 4.1V maximum the Boot Block is locked and cannot be programmed or erased. When RP Ý e 11.4V minimum the Boot Block is unlocked and can be programmed or erased. When RP Ý is at a logic low level the Boot Block is locked, the deep power-down mode is enabled and the WSM is reset preventing any blocks from being programmed or erased, therefore providing data protection during power transitions. When RP Ý transitions from logic low to logic high, the flash memory enters the read-array mode. OEÝ I OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a read cycle. OE Ý is active low. WEÝ I WRITE ENABLE: Controls writes to the Command Register and array blocks. WE Ý is active low. Addresses and data are latched on the rising edge of the WE Ý pulse. VPP PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming data in each block. Note: VPP k VPPLMAX memory contents cannot be altered. VCC DEVICE POWER SUPPLY (3.3V g0.3V, 5V g10%) GND GROUND: For all internal circuitry NC NO CONNECT: Pin may be driven or left floating DU DON’T USE PIN: Pin should not be connected to anything

Figure 6. 28F200BL Word/Byte-Wide Block Diagram

2.1.1 BLOCKlNG

2.1.1.1 Boot Block Operation and Data

er failure or other disruption during code update. necessary while providing security when needed.

2.1.1.2 Parameter Block Operation

2.1.1.3 Main Block Operation

2.1.2 BLOCK MEMORY MAP

sides in memory space from 02000H to 02FFFH. (word locations). See Figure 7. Figure 7. 28F200BL-B Memory Map

sides in memory space from 10000H to 1BFFFH. Figure 8. 28F200BL-T Memory Map

Figure 9. 28F002BL Byte-Wide Block Diagram

3.1.1 BLOCKING

3.1.1.1 Boot Block Operation and Data

er failure or other disruption during code update.

3.1.1.2 Parameter Block Operation

for the 28F002BL-T and 28F002BL-B.

3.1.1.3 Main Block Operation

(1 x 128-Kbyte block and 1 x 96-Kbyte block).

3.1.2 BLOCK MEMORY MAP

ory space from 20000H to 3FFFFH. See Figure 10. Figure 10. 28F002BL-B Memory Map

sides in memory space from 20000H to 37FFFH. Figure 11. 28F002BL-T Memory Map

4.0 PRODUCT FAMILY PRINCIPLES

Table 1. Bus Operations for WORD-WIDE Mode (BYTE Ý e VIH) Table 2. Bus Operations for BYTE-WIDE Mode (BYTE Ý e VIL)

1. Refer to DC Characteristics.

IL or V IH for control pins and addresses, V PPL or V PPH for V PP.

1. See DC characteristics for V PPL,V PPH,V HH,V ID voltages.
2. Manufacturer and Device codes may also be accessed via a CPU write sequence. A 1 –A16 e VIL.
3. Device ID e 2274H for 28F200BL-T and 2275H for 28F200BL-B.
4. Refer to Table 4 for valid D IN during a write operation.
5. Command writes for Block Erase or Word/Byte Write are only executed when V PP e VPPH.
6. To write or erase the boot block, hold RP Ý at V HH.
7. RP Ý must be at GND g0.2V to meet the 1.2 mA maximum deep power-down current.
8. The device ID codes are identical to those of the 28F200BX 5V versions and SmartVoltage equivalents.

Table 3. Bus Operations

1. Refer to DC Characteristics.

IL or V IH for control pins and addresses, V PPL or V PPH for V PP.

1. See DC characteristics for V PPL,V PPH,V HH,V ID voltages.
2. Manufacturer and Device codes may also be accessed via a CUI write sequence. A 1 –A17 e VIL.
3. Device ID e 7CH for 28F002BL-T and 7DH for 28F002BL-B.
4. Refer to Table 4 for valid D IN during a write operation.
5. Command writes for Block erase or byte program are only executed when V PP e VPPH.
6. Program or erase the Boot block by holding RP Ý at V HH.
7. RP Ý must be at GND g0.2V to meet the 1.2 mA maximum deep power-down current.
8. The device ID codes are identical to those of the 28F002BX 5V versions and SmartVoltage equivalents.

4.3 Read Operations

Array, Intelligent Identifier, and Status Register. in the ‘‘Write Operations’’ section. mum to obtain valid data on the outputs.

4.3.1 READ ARRAY

from the selected memory on to the I/O bus.

4.3.1.1 Output Control

4.3.1.2 Input Control

or DQ [0:7]) are controlled by OEÝ.

4.3.2 INTELLIGENT lDENTlFlERS

28F200BL-T/B, 28F002BL-T/B 28F002BL Products The manufacturer and device codes are also read via the CUI or by taking the A 9 pin to 12V. Writing 90H to the CUI places the device into Intelligent Identifier read mode. A read of location 00000 H outputs the manufacturer’s identification code, 89H, and location 00001 H outputs the device code; 7CH for 28F002BL-T, 7DH for 28F002BL-B.

4.4 Write Operations

Commands are written to the CUI using standard mi- croprocessor write timings. The CUI serves as the interface between the microprocessor and the inter- nal chip operation. The CUI can decipher Read Ar- ray, Read Intelligent Identifier, Read Status Register, Clear Status Register, Erase and Program com- mands. In the event of a read command, the CUI simply points the read path at either the array, the Intelligent Identifier, or the status register depending on the specific read command given. For a program or erase cycle, the CUI informs the write state ma- chine that a write or erase has been requested. Dur- ing a program cycle, the Write State Machine will control the program sequences and the CUI will only respond to status reads. During an erase cycle, the CUI will respond to status reads and erase suspend. After the Write State Machine has completed its task, it will allow the CUI to respond to its full com- mand set. The CUI will stay in the current command state until the microprocessor issues another com- mand. The CUI will successfully initiate an erase or write operation only when V PP is within its voltage range. Depending upon the application, the system design- er may choose to make the V PP power supply switchable, available only when memory updates are desired. The system designer can also choose to ‘‘hard-wire’’ V PP to 12V. The 2-Mbit flash family is designed to accommodate either design practice. It is recommended that RP Ý be tied to logical Reset for data protection during unstable CPU reset func- tion as described in the ‘‘Product Family Overview’’ section.

4.4.1 BOOT BLOCK WRITE OPERATIONS

In the case of Boot Block modifications (write and erase), RP Ý is set to V HH e 12V typically, in addi- tion to V PP at high voltage. However, if RP Ý is not at VHH when a program or erase operation of the boot block is attempted, the corresponding status register bit (Bit 4 for Program and Bit 5 for Erase, refer to Table 5 for Status Register Definitions) is set to indi- cate the failure to complete the operation.

4.4.2 COMMAND USER INTERFACE (CUI)

The Command User Interface (CUI) serves as the interface to the microprocessor. The CUI points the read/write path to the appropriate circuit block as described in the previous section. After the WSM has completed its task, it will set the WSM Status bit to a ‘‘1’’, which will also allow the CUI to respond to its full command set. Note that after the WSM has returned control to the CUI, the CUI will remain in its current state.

4.4.2.1 Command Set

00 Invalid/Reserved

10 Alternate Program Setup

20 Erase Setup

40 Program Setup

50 Clear Status Register

70 Read Status Register

90 Intelligent Identifier

D0 Erase Resume/Erase Confirm FF Read Array

4.4.2.2 Command Function Descriptions

Device operations are selected by writing specific commands into the CUI. Table 4 defines the 2-Mbit flash family commands.

Table 4. Command Definitions

8 Operation Address Data Operation Address Data

1. Bus operations are defined in Tables 1, 2, 3.

e Identifier Address: 00H for manufacturer code, 01H for device code.

1. SRD e Data read from Status Register.
2. IID e Intelligent Identifier Data.

Following the Intelligent Identifier Command, two read operations access manufacturer and device codes. e Address within the block being erased.

1. WA e Address to be written.

WD e Data to be written at location WA.

1. Either 40H or 10H commands is valid.
2. When writing commands to the device, the upper data bus [DQ

to avoid burning additional current. other address inputs are ignored). dress presented to the device. gram or erase has completed. the accumulated error status.

28F200BL-T/B, 28F002BL-T/B Program Setup (40H or 10H) This command simply sets the CUI into a state such that the next write will load the address and data registers. Either 40H or 10H can be used for Pro- gram Setup. Both commands are included to ac- commodate efforts to achieve an industry standard command code set. Program The second write after the program setup command, will latch addresses and data. Also, the CUI initiates the WSM to begin execution of the program algo- rithm. While the WSM finishes the algorithm, the de- vice will output Status Register contents. Note that the WSM cannot be suspended during program- ming. Erase Setup (20H) Prepares the CUI for the Erase Confirm command. No other action is taken. If the next command is not an Erase Confirm command then the CUI will set both the Program Status and Erase Status bits of the Status Register to a ‘‘1’’, place the device into the Read Status Register state, and wait for another command. Erase Confirm (D0H) If the previous command was an Erase Setup com- mand, then the CUI will enable the WSM to erase, at the same time closing the address and data latches, and respond only to the Read Status Register and Erase Suspend commands. While the WSM is exe- cuting, the device will output Status Register data when OE Ý is toggled low. Status Register data can only be updated by toggling either OE Ý or CE Ý low. Erase Suspend (B0H) This command only has meaning while the WSM is executing an Erase operation, and therefore will only be responded to during an erase operation. After this command has been executed, the CUI will initi- ate the WSM to suspend Erase operations, and then return to responding to only Read Status Register or to the Erase Resume commands. Once the WSM has reached the Suspend state, it will set an output into the CUI which allows the CUI to respond to the Read Array, Read Status Register, and Erase Re- sume commands. In this mode, the CUI will not re- spond to any other commands. The WSM will also set the WSM Status bit to a ‘‘1’’. The WSM will con- tinue to run, idling in the SUSPEND state, regardless of the state of all input control pins, with the exclu- sion of RP Ý.R P Ý low will immediately shut down the WSM and the remainder of the chip. Erase Resume (D0H) This command will cause the CUI to clear the Sus- pend state and set the WSM Status bit to a ‘‘0’’, but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect in all other conditions.

4.4.3 STATUS REGlSTER

The 2-Mbit flash family contains a status register which may be read to determine when a program or erase operation is complete, and whether that oper- ation completed successfully. The status register may be read at any time by writing the Read Status command to the CUI. After writing this command, all subsequent Read operations output data from the status register until another command is written to the CUI. A Read Array command must be written to the CUI to return to the Read Array mode. The status register bits are output on DQ [0:7] whether the device is in the byte-wide (x8) or word- wide (x16) mode for the 28F200BL. In the word-wide mode the upper byte, DQ [8:15] is set to 00H during a Read Status command. In the byte-wide mode, DQ[8:14] are tri-stated and DQ 15/Ab1 retains the low order address function. It should be noted that the contents of the status register are latched on the falling edge of OE Ý or CEÝ whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the contents of the status register change while reading the status register. CE Ý or OE Ý must be toggled with each subsequent status read, or the completion of a program or erase operation will not be evident. The Status Register is the interface between the mi- croprocessor and the Write State Machine (WSM). When the WSM is active, this register will indicate the status of the WSM, and will also hold the bits indicating whether or not the WSM was successful in performing the desired operation. The WSM sets status bits ‘‘Three’’ through ‘‘Seven’’ and clears bits ‘‘Six’’ and ‘‘Seven’’, but cannot clear status bits ‘‘Three’’ through ‘‘Five’’. These bits can only be cleared by the controlling CPU through the use of the Clear Status Register command.

4.4.3.1 Status Register Bit Definition

Table 5. Status Register Definitions able to successfully perform an erase verify. back between V PPL and V PPH. These bits are reserved for future use and should be masked out when polling the Status Register.

4.4.3.2 Clearing the Status Register

status register, or Intelligent Identifier.

4.4.4 PROGRAM MODE

1. program the desired bits of the addressed memo-
2. verify that the desired bits are sufficiently pro-

within a byte or word being changed to a ‘‘0’’.

28F200BL-T/B, 28F002BL-T/B Similar to erasure, the status register indicates whether programming is complete. While the pro- gram sequence is executing, bit 7 of the status regis- ter is a ‘‘0’’. The status register can be polled by toggling either CE Ý or OE Ý to determine when the program sequence is complete. Only the Read Status Register command is valid while program- ming is active. When programming is complete, the status bits, which indicate whether the program operation was successful, should be checked. If the programming operation was unsuccessful, Bit 4 of the status regis- ter is set to a ‘‘1’’ to indicate a Program Failure. If Bit 3 is set then V PP was not within acceptable limits, and the WSM will not execute the programming se- quence. The status register should be cleared before at- tempting the next operation. Any CUI instruction can follow after programming is completed; however, it must be recognized that reads from the memory, status register, or Intelligent Identifier cannot be ac- complished until the CUI is given the appropriate command. A Read Array command must first be giv- en before memory contents can be read. Figure 12 shows a system software flowchart for de- vice byte programming operation. Figure 13 shows a similar flowchart for device word programming oper- ation (28F200BL-only).

4.4.5 ERASE MODE

Erasure of a single block is initiated by writing the Erase Setup and Erase Confirm commands to the CUI, along with the addresses, A [12:16] for the 28F200BL or A [12:17] for the 28F002BL, identifying the block to be erased. These addresses are latched internally when the Erase Confirm command is is- sued. Block erasure results in all bits within the block being set to ‘‘1’’. The WSM will execute a sequence of internally timed events to: 1. program all bits within the block 2. verify that all bits within the block are sufficiently programmed 3. erase all bits within the block and 4. verify that all bits within the block are sufficiently erased While the erase sequence is executing, Bit 7 of the status register is a ‘‘0’’. When the status register indicates that erasure is complete, the status bits, which indicate whether the erase operation was successful, should be checked. If the erasure operation was unsuccessful, Bit 5 of the status register is set to a ‘‘1’’ to indicate an Erase Failure. If V PP was not within acceptable limits after the Erase Confirm command is issued, the WSM will not execute an erase sequence; instead, Bit 5 of the status register is set to a ‘‘1’’ to indicate an Erase Failure, and Bit 3 is set to a ‘‘1’’ to identify that V PP supply voltage was not within acceptable limits. The status register should be cleared before at- tempting the next operation. Any CUI instruction can follow after erasure is completed; however, it must be recognized that reads from the memory array, status register, or Intelligent Identifier can not be ac- complished until the CUI is given the appropriate command. A Read Array command must first be giv- en before memory contents can be read. Figure 14 shows a system software flowchart for Block Erase operation.

4.4.5.1 Suspending and Resuming Erase

Since an erase operation typically requires 2 to 5 seconds to complete, an Erase Suspend command is provided. This allows erase-sequence interruption in order to read data from another block of the mem- ory. Once the erase sequence is started, writing the Erase Suspend command to the CUI requests that the Write State Machine (WSM) pause the erase se- quence at a predetermined point in the erase algo- rithm. The status register must be read to determine when the erase operation has been suspended. At this point, a Read Array command can be written to the CUI in order to read data from blocks other than that which is being suspended. The only other valid command at this time is the Erase Resume command or Read Status Register operation. Figure 15 shows a system software flowchart detail- ing the operation. During Erase Suspend mode, the chip can go into a pseudo-standby mode by taking CE Ý to V IH and the active current is now a maximum of 6 mA. If the chip is enabled while in this mode by taking CE Ý to V IL, the Erase Resume command can be issued to re- sume the erase operation. Upon completion of reads from any block other than the block being erased, the Erase Resume com- mand must be issued. When the Erase Resume command is given, the WSM will continue with the erase sequence and complete erasing the block. As with the end of erase, the status register must be read, cleared, and the next instruction issued in or- der to continue.

4.4.6 EXTENDED CYCLlNG

very high cycling capability. Repeat for subsequent bytes. reset the device to Read Array Mode. before full status is checked. attempting retry or other error recovery. Figure 12. Automated Byte Programming Flowchart

Repeat for subsequent words. reset the device to Read Array Mode. before full status is checked. attempting retry or other error recovery. Figure 13. Automated Word Programming Flowchart

Repeat for subsequent blocks. before full status is checked. attempting retry or other error recovery. Figure 14. Automated Block Erase Flowchart

Figure 15. Erase Suspend/Resume Flowchart

4.5 Power Consumption

4.5.1 ACTlVE POWER

high level, the device is placed in the active mode.

4.5.2 AUTOMATlC POWER SAVlNGS

outputs valid until a new memory location is read.

4.5.3 STANDBY POWER

28F200BL-T/B, 28F002BL-T/B continue to perform the erase or program function and consume program or erase active power until program or erase is completed.

4.5.4 RESET/DEEP POWER-DOWN

The 2-Mbit flash family supports a typical I CC of 0.2 mA in deep power-down mode. One of the target markets for these devices is in portable equipment where the power consumption of the machine is of prime importance. The 2-Mbit flash family has a RP Ý pin which places the device in the deep power- down mode. When RP Ý is at a logic-low (GND g0.2V), all circuits are turned off and the device typ- ically draws 0.2 mAo fV CC current. During read modes, the RP Ý pin going low dese- lects the memory and places the output drivers in a high impedance state. Recovery from the deep pow- er-down state, requires a maximum of 600 ns to ac- cess valid data (t PHQV). During erase or program modes, RP Ý low will abort either erase or program operation. The contents of the memory are no longer valid as the data has been corrupted by the RP Ý function. As in the read mode above, all internal circuitry is turned off to achieve the 0.2 mA current level. RP Ý transitions to V IL or turning power off to the device will clear the status register. The use of RP Ý during system reset is important with automated write/erase devices. When the sys- tem comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during write/ erase modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization would not occur because the flash memory would be providing the status information instead of array data. Intel’s Flash Memories allow proper CPU initialization fol- lowing a system reset through the use of RP Ý input. In this application, RP Ý is controlled by the same RESETÝ signal that resets the system CPU.

4.6 Power-Up Operation

The 2-Mbit flash family is designed to offer protec- tion against accidental block erasure or program- ming during power transitions. Upon power-up the 2-Mbit flash family is indifferent as to which power supply, V PP or V CC, powers-up first. Power supply sequencing is not required. The 2-Mbit flash family ensures the CUI is reset to the read mode on power-up. In addition, on power-up the user must either drop CEÝ low or present a new address to ensure valid data at the outputs. A system designer must guard against spurious writes for V CC voltages above V LKO when V PP is active. Since both WE Ý and CE Ý must be low for a command write, driving either signal to V IH will inhibit writes to the device. The CUI architecture provides an added level of protection since alteration of mem- ory contents can only occur after successful com- pletion of the two-step command sequences. Finally the device is disabled until RP Ý is brought to V IH, regardless of the state of its control inputs. This fea- ture provides yet another level of memory protec- tion.

4.7 Power Supply Decoupling

Flash memory’s power switching characteristics re- quire careful device decoupling methods. System designers are interested in 3 supply current issues: # Standby current levels (I CCS) # Active current levels (I CCR) # Transient peaks produced by falling and rising edges of CE Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 mF ceramic capacitor connected between each V CC and GND, and be- tween its V PP and GND. These high frequency, low- inherent inductance capacitors should be placed as close as possible to the package leads. 4.7.1 V PP TRACE ON PRINTED CIRCUIT BOARDS Writing to flash memories while they reside in the target system, requires special consideration of the V PP power supply trace by the printed circuit board designer. The V PP pin supplies the flash memory cell’s current for programming and erasing. One should use similar trace widths and layout consider- ations given to the V CC power supply trace. Ade- quate V PP supply traces and decoupling will de- crease spikes and overshoots.

4.7.2 V CC,V PP AND RP Ý TRANSITIONS

The CUI latches commands as issued by system software and is not altered by V PP or CE Ý tran- sitions or WSM actions. Its state upon power-up, af- ter exit from deep power-down mode or after V CC transitions below V LKO (Lockout voltage), is Read Array mode. After any word/byte write or block erase operation is complete and even after V PP transitions down to VPPL, the CUI must be reset to Read Array mode via the Read Array command when accesses to the flash memory are desired.

28F200BL-T/B, 28F002BL-T/B

5.0 OPERATING SPECIFICATIONS

During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b20§Ct o a70§C(1) During Block Erase and Word/Byte WriteÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0 §Ct o7 0 §C Temperature Under Bias ÀÀÀÀÀÀÀÀÀ b20§Ct o a80§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a125§C Voltage on Any Pin (except V CC,V PP,A 9 and RP Ý) with Respect to GND ÀÀÀÀÀÀÀÀ b2.0V to a7.0V(2) Voltage on Pin RP Ý or Pin A 9 with Respect to GND ÀÀÀÀÀÀÀ b2.0V to 13.5V (2, 3) VPP Program Voltage with Respect to GND during Block Erase and Word/Byte Write ÀÀÀÀÀ b2.0V to a14.0V(2, 3) VCC Supply Voltage with Respect to GND ÀÀÀÀÀÀÀÀ b2.0V to a7.0V(2) Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA (4) NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. OPERATING CONDITIONS Symbol Parameter Notes Min Max Unit TA Operating Temperature b20 a70 §C VCC VCC Supply Voltage 3.00 3.60 V VCC VCC Supply Voltage 5 4.50 5.50 V NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is b0.5V on input/output pins. During transitions, this level may undershoot to b2.0V for periods k20 ns. Maximum DC voltage on input/output pins is V CC a 0.5V which, during transitions, may overshoot to V CC a 2.0V for periods k20 ns. 3. Maximum DC voltage on V PP may overshoot to a14.0V for periods k20 ns. Maximum DC voltage on RP Ý or A 9 may overshoot to 13.5V for periods k20 ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. AC Specifications are valid at both voltage ranges. See DC Characteristics table for voltage range-specific specifications. DC CHARACTERISTICS VCC e 3.3V g0.3V Symbol Parameter Notes Min Typ Max Unit Test Condition ILI Input Load Current 1 g1.0 mAV CC e VCC Max VIN e VCC or GND ILO Output Leakage Current 1 g10 mAV CC e VCC Max VOUT e VCC or GND ICCS VCC Standby Current 1, 3 45 120 mAV CC e VCC Max CEÝ e RPÝ e VCC g0.2V 45 120 mAV CC e VCC Max CEÝ e RPÝ e VIH ICCD VCC Deep Power-down Current 1 0.20 1.2 mAR P Ý e GND g0.2V ICCR VCC Read Current for 1, 5, 15 25 mA V CC e VCC Max, CE Ý e GND 28F200BL Word-Wide and 6f e 5 MHz, I OUT e 0m A Byte-Wide Mode and CMOS Inputs 28F002BL Byte-Wide Mode 15 25 mA V CC e VCC Max, CE Ý e VIL f e 5 MHz, I OUT e 0m A TTL Inputs

28F200BL-T/B, 28F002BL-T/B DC CHARACTERISTICS (Continued) VCC e 3.3V g0.3V Symbol Parameter Notes Min Typ Max Unit Test Condition ICCW VCC Word/Byte Write Current 1, 4 30 mA Word/Byte Write in Progress ICCE VCC Block Erase Current 1, 4 20 mA Block Erase in Progress ICCES VCC Erase Suspend Current 1, 2 3 6 mA CE Ý e VIH Block Erase Suspended IPPS VPP Standby Current 1 g15 mAV PP s VCC IPPD VPP Deep 1 5.0 mAR P Ý e GND g0.2V Power-down Current IPPR VPP Read Current 1 200 mAV PP l VCC IPPW VPP Word Write Current 1, 4 40 mA V PP e VPPH Word Write in Progress IPPW VPP Byte Write Current 1, 4 30 mA V PP e VPPH Byte Write in Progress IPPE VPP Block Erase Current 1, 4 30 mA V PP e VPPH Block Erase in Progress IPPES VPP Erase Suspend Current 1 200 mAV PP e VPPH Block Erase Suspended IRPÝ RPÝ Boot Block 1, 4 500 mAR P Ý e VHH Unlock Current IID A9 Intelligent Identifier Current 1, 4 500 mAA 9 e VID VID A9 Intelligent Identifier Voltage 11.4 12.0 13.0 V VIL Input Low Voltage b0.5 0.6 V VIH Input High Voltage 2.0 V CCa0.5 V VOL Output Low Voltage 0.4 V V CC e VCC Min IOL e 2m A VOH1 Output High Voltage (TTL) 2.4 V V CC e VCC Min IOH eb 2m A VOH2 Output High Voltage 0.85 V CC VV CC e VCC Min (CMOS) I OH eb 2.5 mA VCCb0.4 V CC e VCC Min IOH eb 2.5 mA VPPL VPP during Normal Operations 3 0.0 4.1 V VPPH VPP during Erase/Write 11.4 12.0 12.6 V Operations VLKO VCC Erase/Write Lock Voltage 1.7 V VHH RPÝ Unlock Voltage 11.4 12.0 13.0 V Boot Block Write/Erase NOTES: are valid for all product versions (packages and speeds). 2. I CCES is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum of I CCES and I CCR. 3. Block Erases and Word/Byte Writes are inhibited when V PP e VPPL and not guaranteed in the range between V PPH and VPPL. 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces I CCR to less than 1 mA in static operation.

28F200BL-T/B, 28F002BL-T/B CAPACITANCE(1) TA e 25§C, f e 1 MHz Symbol Parameter Typ Max Unit Condition CIN Input Capacitance 6 8 pF V IN e 0V COUT Output Capacitance 10 12 pF V OUT e 0V NOTE: 1. Sampled, not 100% tested. DC CHARACTERISTICS VCC e 5.0V g10%(4) Symbol Parameter Notes Min Typ Max Unit Test Condition ILI Input Load Current 1 g1.0 mAV CC e VCC Max VIN e VCC or GND ILO Output Leakage Current 1 g10 mAV CC e VCC Max VOUT e VCC or GND ICCS VCC Standby Current 1.5 mA V CC e VCC Max CEÝ e RPÝ e VIH 100 mAV CC e VCC Max CEÝ e RPÝ e VCC g0.2V ICCD VCC Deep Power-down 1 1.2 mAR P Ý e GND g0.2V Current ICCR VCC Read Current for 1 40 mA V CC e VCC Max, CE Ý e GND 28F200BL Word-Wide and f e 5 MHz, I OUT e 0m A Byte-Wide Mode and CMOS Inputs 28F002BL 40 mA V CC e VCC Max, CE Ý e VIL f e 5 MHz, I OUT e 0m A TTL Inputs ICCW VCC Word-Byte Write Current 1, 4 70 mA Word or Byte Write in Progress ICCE VCC Block Erase Current 1, 4 30 mA Block Erase in Progress ICCES VCC Erase Suspend Current 1, 2 10 mA CE Ý e VIH Block Erase Suspended IPPS VPP Standby Current 1 g15 mAV PP s VCC IPPD VPP Deep Power-down 1 5.0 mAR P Ý e GND g0.2V Current

28F200BL-T/B, 28F002BL-T/B DC CHARACTERISTICS (Continued) VCC e 5.0V g10% Symbol Parameter Notes Min Typ Max Unit Test Condition IPPR VPP Read Current 1 200 mAV PP l VCC IPPW VPP Word Write Current 1, 4 40 mA V PP e VPPH Word Write in Progress IPPW VPP Byte Write Current 1, 4 30 mA V PP e VPPH Byte Write in Progress IPPE VPP Block Erase Current 1, 4 30 mA V PP e VPPH Block Erase in Progress IPPES VPP Erase Suspend Current 1 200 mAV PP e VPPH Block Erase Suspended IRPÝ RPÝ Boot Block Unlock Current 1, 4 500 mAR P Ý e VHH IID A9 Intelligent Identifier Current 1, 4 500 mAA 9 e VID VID A9 Intelligent Identifier Voltage 11.4 12.0 13.0 V VIL Input Low Voltage b0.5 0.8 V VIH Input High Voltage 2.0 V CCa0.5 V VOL Output Low Voltage 0.45 V V CC e VCC Min IOL e 5.8 mA VOH1 Output High Voltage (TTL) 2.4 V V CC e VCC Min IOH eb 2.5 mA VOH2 Output High Voltage 0.85 V CC VV CC e VCC Min (CMOS) I OH eb 2.5 mA VCCb0.4 V CC e VCC Min IOH eb 100 mA VPPL VPP during Normal Operations 3 0.0 6.5 V VPPH VPP during Erase/Write 11.4 12.0 12.6 V Operations VLKO VCC Erase/Write Lock Voltage 2.2 V VHH RPÝ Unlock Voltage 11.4 12.0 13.0 V Boot Block Write/Erase NOTES: are valid for all product versions (packages and speeds). 2. I CCES is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum of I CCES and I CCR. 3. Block Erase/Byte Writes are inhibited when V PP e VPPL and not guaranteed in the range between V PPH and V PPL. 4. All parameters are sampled, not 100% tested.

28F200BL-T/B, 28F002BL-T/B AC INPUT/OUTPUT REFERENCE WAVEFORM 290449–15 AC test inputs are driven at 3.0V for a Logic ‘‘1’’ and 0.0V for a logic ‘‘0’’. Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) k 10 ns. AC TESTING LOAD CIRCUIT 290449–16 CL e 50 pF CL Includes Jig Capacitance RL e 3.3 K X AC CHARACTERISTICSÐRead-Only Operations (1) VCC e 3.3V g0.3V, 5.0V g10%(3) Versions 28F200BL-150 Unit28F002BL-150 Symbol Parameter Notes Min Max tAVAV tRC Read Cycle Time 150 ns tAVQV tACC Address to Output Delay 150 ns tELQV tCE CEÝ to Output Delay 2 150 ns tPHQV tPWH RPÝ High to Output Delay 600 ns tGLQV tOE OEÝ to Output Delay 2 65 ns tELQX tLZ CEÝ to Output Low Z 3 0 ns tEHQZ tHZ CEÝ High to Output High Z 3 55 ns tGLQX tOLZ OEÝ to Output Low Z 3 0 ns tGHQZ tDF OEÝ High to Output High Z 3 45 ns tOH Output Hold from Addresses, 3 0 ns CEÝ or OE Ý Change, Whichever is First tIR Input Rise Time 10 ns tIF Input Fall Time 10 ns tELFL CEÝ to BYTE Ý Switching 3 5 ns tELFH Low to High tFHQV BYTEÝ Switching High 3, 4 150 ns to Valid Output Delay tFLQZ BYTEÝ Switching Low 3 45 ns to Output High Z NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE Ý may be delayed up to t CE –tOE after the falling edge of CE Ý without impact on t CE. 3. Sampled, not 100% tested. 4. t FLQV, BYTE Ý switching low to valid output delay will be equal to t AVQV, measured from the time DQ 15/Ab1 becomes valid.

Figure 16. AC Waveforms for Read Operations

Figure 17. BYTE Ý Timing Diagram for Both Read and Write Operations for 28F200BL

28F200BL-T/B, 28F002BL-T/B AC CHARACTERISTICS FOR WE Ý CONTROLLED WRITE OPERATIONS (1) VCC e 3.0V–3.6V, 5.0V g10% Versions(4) 28F200BL-150 Unit28F002BL-150 Symbol Parameter Notes Min Max tAVAV tWC Write Cycle Time 150 ns tPHWL tPS RPÝ High Recovery to WE Ý Going Low 1 ms tELWL tCS CEÝ Setup to WE Ý Going Low 0 ns tPHHWH tPHS RPÝ VHH Setup to WE Ý Going High 6, 8 200 ns tVPWH tVPS VPP Setup to WE Ý Going High 5, 8 200 ns tAVWH tAS Address Setup to WE Ý Going High 3 95 ns tDVWH tDS Data Setup to WE Ý Going High 4 100 ns tWLWH tWP WEÝ Pulse Width 100 ns tWHDX tDH Data Hold from WE Ý High 4 0 ns tWHAX tAH Address Hold from WE Ý High 3 10 ns tWHEH tCH CEÝ Hold from WE Ý High 10 ns tWHWL tWPH WEÝ Pulse Width High 50 ns tWHQV1 Duration of Programming Operation (Boot) 2, 5, 6 6 ms tWHQV2 Duration of Word/Byte 2, 5, 6 0.3 s Programming Operation tWHQV3 Duration of Erase Operation 2, 5, 6 0.3 s (Parameter) tWHQV4 Duration of Erase Operation (Main) 2, 5, 6 0.6 s tQVVL tVPH VPP Hold from Valid SRD 5, 8 0 ns tQVPH tPHH RPÝ VHH Hold from Valid SRD 6, 8 0 ns tPHBR Boot-Block Relock Delay 7, 8 200 ns tIR Input Rise Time 10 ns tIF Input Fall Time 10 ns NOTES: 1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC characteristics during Read Mode. 2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled inter- nally which includes verify and margining operations. 3. Refer to command definition table for valid A IN. 4. Refer to command definition table for valid D IN. 5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7 e1). 6. For Boot Block Program/Erase, RP Ý should be held at V HH until operation completes successfully. 7. Time t PHBR is required for successful relocking of the Boot Block. 8. Sampled but not 100% tested.

28F200BL-T/B, 28F002BL-T/B BLOCK ERASE AND BYTE/WORD WRITE PERFORMANCE VCC e 3.0V–3.6V, 5.0V g10% Parameter Notes 28F200BL-150 Unit28F002BL-150 Min Typ (1) Max Boot/Parameter Block Erase Time 2 2.0 8.6 s Main Block Erase Time 2 3.4 17.0 s Main Block Byte Program Time 2 1.4 5.3 s Main Block Word Program Time 2 0.7 2.7 s NOTES: 1. 25 §C, 12.0V V PP. 2. Excludes System-Level Overhead.

Figure 18. AC Waveforms for a Write and Erase Operations (WE Ý-Controlled Writes)

28F200BL-T/B, 28F002BL-T/B AC CHARACTERISTICS FOR CE Ý-CONTROLLED WRITE OPERATIONS VCC e 3.0V–3.6V, 5.0V g10% Versions 28F200BL-150 Unit28F002BL-150 Symbol Parameter Notes Min Max tAVAV tWC Write Cycle Time 150 ns tPHEL tPS RPÝ High Recovery to CE Ý Going Low 1 ms tWLEL tWS WEÝ Setup to CE Ý Going Low 0 ns tPHHEH tPHS RPÝ VHH Setup to CE Ý Going High 6, 8 200 ns tVPEH tVPS VPP Setup to CE Ý Going High 5, 8 200 ns tAVEH tAS Address Setup to CE Ý Going High 3 95 ns tDVEH tDS Data Setup to CE Ý Going High 4 100 ns tELEH tCP CEÝ Pulse Width 100 ns tEHDX tDH Data Hold from CE Ý High 4 0 ns tEHAX tAH Address Hold from CE Ý High 3 10 ns tEHWH tWH WEÝ Hold from CE Ý High 10 ns tEHEL tCPH CEÝ Pulse Width High 50 ns tEHQV1 Duration of Word/Byte Programming 2, 5, 6 6 ms Operation (Boot) tEHQV2 Duration of Erase Operation (Boot) 2, 5, 6 0.3 s tEHQV3 Duration of Erase Operation (Parameter) 2, 5, 6 0.3 s tEHQV4 Duration of Erase Operation (Main) 2, 5, 6 0.6 s tQVVL tVPH VPP Hold from Valid SRD 5, 8 0 ns tQVPH tPPH RPÝ VHH Hold from Valid SRD 6, 8 0 ns tPHBR Boot-Block Relock Delay 7 200 ns tIR Input Rise Time 10 ns tIF Input Fall Time 10 ns NOTES: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE Ý and WE Ý in systems where CEÝ defines the write pulse-width (within a longer WE Ý timing waveform), all set-up, hold and inactive WE Ý time should be measured relative to the CE Ý waveforms. 2, 3, 4, 5, 6, 7, 8: Refer to AC characteristics for WE Ý-controlled write operations. 9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC characteristics during read mode.

Figure 19. Alternate AC Waveforms for Write and Erase Operations (CE Ý-Controlled Writes)

28F200BL-T/B, 28F002BL-T/B

ORDERING INFORMATION

290449–20 VALID COMBINATIONS: E28F200BL-T150 PA28F200BL-T150 E28F200BL-B150 PA28F200BL-B150 290449–21 VALID COMBINATIONS: E28F002BL-T150 E28F002BL-B150 References Order DocumentNumber 290448 28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet 290450 28F004/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory Datasheet 290451 28F004/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet 290531 2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet 290530 4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet 290539 8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet

292098 AP-363 ‘‘Extended Flash BIOS Concepts for Portable Computers’’

292148 AP-604 ‘‘Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM’’

292161 AP-608 ‘‘Implementing a Plug and Play BIOS Using Intel’s Boot Block Flash Memory’’

292163 AP-610 Flash Memory In-System Code and Data Update Technique

292169 AP-615 Accommodating Industry Trends in Boot Code Flash Memory

292178 AP-623 ‘‘Multi-Site Layout Planning Using Intel’s Boot Block Flash Memory’’

292130 AB-57 ‘‘Boot Block Architecture for Safe Firmware Updates’’

292154 AB-60 ‘‘2/4/8- Mbit SmartVoltage Boot Block Flash Memory Family’’

28F200BL-T/B, 28F002BL-T/B

Revision History

-001 Original Version -002 Modified BYTE Ý AC Timings Modified t DVWH parameter for AC Characteristics for Write Operations -003 PWD renamed to RP Ý for JEDEC standardization compatibility. Combined V CC Read Current for 28F200BX-L Word-Wide and Byte-Wide Mode and 28F002BX-L Byte-Wide Mode in DC Characteristics tables. Changed I PPS current spec from g10 mAt o g15 mA in DC Characteristics table. Added Boot Block Unlock current spec in DC Characteristics tables. Improved t PWH spec to 600 ns (was 700 ns) Changed I CCR current spec from 20 mA maximum to 25 mA maximum and added typical spec to DC Characteristics table. -004 Added I OH CMOS Specification. Expanded temperature operating range, from 0 §C–70 §Ct o b20§ – a70§C. Product naming changed: 28F200BX-TL/BL changed to 28F200BL-T/B 28F002BX-TL/BL changed to 28F002BL-T/B Typographical errors corrected. Added 28F400BX interface to Intel386 TM EX Embedded Processor Block Diagram. Added upgrade considerations for SmartVoltage Boot Block products. Previously specified V CC tolerance of 3.0V to 3.6V for Read, Program and Erase has been changed to 3.15V to 3.6V for Program and Erase operation, while the Read operation remains 3.0V to 3.6V. -005 Typographical errors corrected. VCC Lockout voltage changed from 2.0V to 1.7V. -006 Added input rise/fall time specifications.