28F002BC INTEL | Alldatasheet
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Technical content
Datasheet sections
- 1.0 INTRODUCTION
- 1.1 Designing for Density Upgradeability
- 1.2 Main Features
- 1.3 Applications
- 1.4 Pinouts
- 1.5 Pin Descriptions
- 2.0 PRODUCT DESCRIPTION
- 2.1 Memory Organization
- 2.1.1 Blocking
- 3.0 PRINCIPLES OF OPERATION
- 3.1 Bus Operations
- 3.2 Read Operations
- 3.2.1 Read Array
- 3.2.2 Intelligent Identifiers
- 3.3 Write Operations
- 3.3.1 Command User Interface (CUI)
- 3.3.2 Status Register
- 3.3.3 Program Mode
- 3.3.4 Erase Mode
- 3.3.5 Extended Cycling
- 3.4 Boot Block Locking
- 3.4.2 RP# = VHH for Boot Block Unlocking
- 3.5 Power Consumption
- 3.5.1 Active Power
- 3.5.2 Standby Power
- 3.5.3 Deep Power-Down
- 3.6 Power-Up/Down Operation
- 3.6.1 RP# Connected to System Reset
- 3.7 Power Supply Decoupling
- 3.7.1 VPP Trace on Printed Circuit Boards
- 4.0 ELECTRICAL SPECIFICATIONS
- 4.1 Absolute Maximum Ratings
- 4.2 Operating Conditions
- 4.2.1 Capacitance
- 4.2.2 Input/Output Test Conditions
- 4.2.3 DC Characteristics
- 4.2.4 AC Characteristics
E PRELIMINARY October 1996 Order Number: 290578-003 /c110 High Performance Read 80/120 ns Max Access Time 40 ns Max. Output Enable Time /c110 Low Power Consumption 20 mA Typical Read Current /c110 x8-Only Input/Output Architecture Space-Constrained 8-bit
Applications
/c110 Optimized Array Blocking Architecture One 16-KB Protected Boot Block Two 8-KB Parameter Blocks One 96-KB Main Block One 128-KB Main Block Top Boot Location /c110 Hardware Data Protection Feature Erase/Write Lockout during Power Transitions Absolute Hardware Protection for Boot Block /c110 Software EEPROM Emulation with Parameter Blocks /c110 Extended Cycling Capability 100,000 Block Erase Cycles /c110 Automated Byte Write and Block Erase /c110 Industry-Standard Command User Interface Status Registers Erase Suspend Capability /c110 SRAM-Compatible Write Interface /c110 Reset/Deep Power-Down Input 0.2 µA ICC Typical Provides Reset for Boot Operations /c110 Industry-Standard Surface Mount Packaging 40-Lead TSOP 44-Lead PSOP 40-Lead PDIP /c110 ETOX™ IV Flash Technology 5V Read /c110 12V Write and Block Erase VPP = 12V ±5% Standard VPP = 12V ±10% Option /c110 Independent Software Vendor Support Intel’s 2-Mbit flash memory is an extension of the Boot Block architecture which includes block-selective erasure, automated write and erase operations, and a standard microprocessor interface. The 2-Mbit flash memory enhances the Boot Block architecture by adding more density and blocks, x8 input/output control, very high-speed, low-power, and industry-standard ROM-compatible pinout and surface mount packaging. The Intel 28F002BC is an 8-bit wide flash memory offering. This high-density flash memory provides user- selectable bus operation for 8-bit applications. The 28F002BC is a 2,097,152-bit nonvolatile memory organized as 262,144 bytes of information. It is offered in 44-lead PSOP, 40- lead PDIP and 40-lead TSOP package, which is ideal for space-constrained portable systems or any application with board space limitations. This device uses an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified byte write and block erasure. The 28F002BC provides block locations compatible with Intel’s MCS®-186 family, 80286, 90860CA, and the Intel386™, Intel486™, Pentium®, and Pentium Pro microprocessors. The boot block includes a data protection feature to protect the boot code in critical applications. With a maximum access time of 80 ns, this high-performance 2-Mbit flash memory interfaces at zero wait-state to a wide range of microprocessors and microcontrollers. A deep power-down mode lowers the total V CC power consumption to 1 µW typical. This power savings is critical in hand-held battery powered systems. For very low-power applications using a 3.3V supply, refer to the Intel 28F002BV-T/B 2-Mbit SmartVoltage Boot Block Flash Memory datasheet. Manufactured on Intel’s 0.6 micron ETOX™ IV process technology, the 28F002BC flash memory provides world-class quality, reliability, and cost-effectiveness at the 2-Mbit density. 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F002BC may contain design defects or errors known as errata. Current characterized errata are available on request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 COPYRIGHT © INTEL CORPORATION, 1996 CG-041493
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY E
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REVISION HISTORY
-001 Original version -002 Pin 2 of 44-Lead PSOP changed from DU to NC Alternate program command (10H) removed WSM transition table added -003 40-Lead PDIP package added
E 28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY 5PRELIMINARY
1.0 INTRODUCTION
This datasheet comprises the specifications for the 28F002BC 2-Mbit flash memory. Section 1 provides an overview of the 2-Mbit flash memory, including applications, pinouts, and pin descriptions. Section 2 describes the memory organization in detail. Section 3 defines a description of the memory’s principles of operation. Finally, Section 4 details the memory’s operating specifications.
1.1 Designing for Density
The 28F002BC has been optimized to meet market requirements. Applications currently using the 28F001BX and 28F002BX can migrate to this product. Of course, both the 28F001BX and the 28F002BX devices use an 8-bit wide bus. Those applications needing a 16-bit wide bus or lower voltage can convert to the Smart 5 or SmartVoltage family of flash memory products. SmartVoltage is also the natural migration path to the 4-Mbit density. Both the 28F002BC and the 4-Mbit SmartVoltage are offered in identical packages to make upgrade seamless. A few simple considerations can smooth the migration path significantly: 1. Connect the NC pin of the 28F002BC to GND (this will retain boot block locking when a 4-Mbit SmartVoltage is inserted). 2. Design a switchable V PP to take advantage of the 5V VPP option on SmartVoltage devices. 3. If anticipating to use the 5V VPP option, switch VPP to GND for complete write protection. Previous designs with Intel’s 28F002BX devices on occasion had to use a NOR gate (or some other scheme) to prevent issues with floating addresses latching incorrect data. The 28F002BC has corrected this issue and does not need the NOR gate. When migrating a design using the 28F002BX to the 28F002BC, the NOR gate can be removed. When considering upgrading, packaging is of paramount importance. Current and future market trends indicate TSOP and PSOP as the packages that will enable designs into the next century.
1.2 Main Features
The 28F002BC Boot Block flash memory is a high- performance, 2-Mbit (2,097,152 bit) flash memory organized as 256 Kbytes (262,144 bytes) of 8 bits each. The 28F002BC has separately erasable blocks, including a hardware-lockable boot block (16,384 bytes), two parameter blocks (8,192 bytes each) and two main blocks (one block of 98,304 bytes and one block of 131,072 bytes). An erase operation typically erases one of the main blocks in 2.4 seconds and the boot or parameter blocks in 1.0 second. Each block can be independently erased and programmed 100,000 times. The boot block is located at the top of the address map to match the protocol of many systems, including Intel’s MCS-186 family, 80960CA, i860™ microprocessors as well as Pentium and Pentium Pro microprocessors. The hardware-lockable boot block provides the most secure code storage. The boot block is intended to store the kernel code required for booting-up a system. When the RP# pin is between 11.4V and 12.6V, the boot block is unlocked and program and erase operations can be performed. When the RP# pin is at or below 6.5V, the boot block is locked and program and erase operations to the boot block are ignored. The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the 28F002BC. Program and Erase Automation allows program and erase operations to be executed using an industry standard two-write command sequence to the CUI. Data writes are performed in byte increments. Each byte in the flash memory can be programmed independently of other memory locations but is erased simultaneously with all other locations within the block. The status register (SR) indicates the status of the internal Write State Machine (WSM), which reports critical information on program and/or erase sequences. The maximum access time of 80 ns (t ACC ) is guaranteed over the commercial temperature range (0°C to +70°C), 10% V CC supply voltage range (4.5V to 5.5V) and 100 pF output load.
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Figure 1. 28F002BC-T Interface to a Pentium® Microprocessor System conditions. Typical ICC active current is 20 mA. is enabled and ICC drops to about 50 µA. until writes to the CUI are recognized.
1.3 Applications
via floppy disk or remote link. where both program and data storage are required.
an example 28F002BC application.
1.4 Pinouts
PDIP package diagram is shown in Figure 3. Figure 2. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained Applications
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Figure 3. The 40-Lead PDIP Offers the Lowest Cost Package Solution
Figure 4. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM Standards
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1.5 Pin Descriptions
Table 1. 28F002BC Pin Descriptions this mode, A0 decodes between the manufacturer and device IDs. through the CE# and RP# input stages. during a read cycle. OE# is active low. WE# INPUT WRITE ENABLE: Controls writes to the Command Register and array blocks. deep power-down mode, locks, and unlocks the boot block from program/erase. cannot be programmed or erased. flash memory enters the read array mode. memory contents cannot be altered. GND GROUND: For all internal circuitry. NC NO CONNECT: Pin may be driven or left floating.
2.0 PRODUCT DESCRIPTION
Figure 5. 28F002BC Internal Block Diagram
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2.1 Memory Organization
2.1.1 BLOCKING
2.1.1.1 Boot Block - 16 KB
necessary while providing security at other times. Figure 6. 28F002BC-T Memory Map
2.1.1.2 Parameter Blocks - 8 KB (each)
2.1.1.3 Main Block - 96 KB and 128 KB
3.0 PRINCIPLES OF OPERATION
maximum EPROM compatibility. (VID) access for PROM programming equipment.
status while the WSM is in operation.
3.1 Bus Operations
3.2 Read Operations
is available at the outputs.
3.2.1 READ ARRAY
- WE# must be logic high (V IH)
- CE# must be logic low (VIL)
- OE# must be logic low (VIL)
- RP# must be logic high (VIH) In addition, the address of the desired location must be applied to the address pins. Refer to AC Characteristics for the exact sequence and timing of these signals. If the device is not in read array mode, as would be the case after a program or erase operation, the Read Mode command (FFH) must be written to the CUI before array reads can take place.
Table 2. 28F002BC Bus Operations
9 A 0 VPP DQ 0–7
- Refer to DC Characteristics.
IL, VIH for control pins and addresses, VPPLK or VPPH for VPP .
- See DC Characteristics for VPPLK , VPPH , VHH , VID voltages.
- Manufacturer and device codes may also be accessed via a CUI write sequence, A1-A17 = X.
- Refer to Table 3 for valid DIN during a write operation.
- Command writes for program or block erase are only executed when VPP = VPPH .
- To write or erase the boot block, hold RP# at VHH .
- RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.
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3.2.2 INTELLIGENT IDENTIFIERS
outputs the manufacturer’s identification code, 89H. necessary. The 40-lead PDIP device ID is 7CH.
3.3 Write Operations
contents: Program Setup and Erase Setup/Confirm. is to a block other than the one being erased). operations that modify the status register. to Table 5 for status register definitions).
3.3.1 COMMAND USER INTERFACE (CUI)
Table 3. Command Set Codes and
00 Invalid/Reserved
20 Erase Setup
40 Program Setup
50 Clear Status Register
70 Read Status Register
90 Intelligent Identifier
Table 4. Command Bus Definitions
- Bus operations are defined in Table 2.
- Following the Intelligent Identifier command, two read operations access manufacturer and device codes respectively.
3.3.1.1 Command Function Description
current operation and resets to read array mode. Confirm at this point would be ignored by the CUI). data path at the array (see Appendix B). other address inputs are ignored).
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY E
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Read Status Register (70H) This is one of three commands that is executable while the WSM is operating. After this command is written, a read of the device will output the contents of the status register, regardless of the address presented to the device. The device automatically enters this mode after program or erase has completed. Clear Status Register (50H) The WSM can set the Program Status and Erase Status bits in the status register to “1,” but it cannot clear them to “0.” The status register is operated in this fashion for two reasons, the first is synchronization. Since the WSM does not know when the host CPU has read the status register, it would not know when to clear the status bits. Second, if the CPU is programming a string of bytes, it may be more efficient to query the status register after programming the string. Thus, if any errors exist while programming the string, the status register will return the accumulated error status. The Clear Status Register command clears the Program, Erase, and V PP Status bits to “0.” Program Setup (40H) This command simply sets the CUI into a state such that the next write will load the Address and Data registers. After this command is executed, the outputs default to the status register. Two consecutive Read Array commands (FFH) are required to reset to Read Array after the Program Setup command. Program The write following the Program Setup command will latch address and data. Also, the CUI initiates the WSM to begin execution of the program algorithm. The device outputs status register data when OE# is enabled. To read array data after the program operation is completed, a Read Array command is required. Erase Setup (20H) The Erase Setup command prepares the CUI for the Erase Confirm command. No other action is taken. If the next command is not an Erase Confirm command, then the CUI will set both the Program Status and Erase Status bits of the status register to a “1,” place the device into read status register mode, and wait for another command. Erase Confirm (D0H) If the previous command was an Erase Setup command, then the CUI will enable the WSM to erase, at the same time closing the address and data latches, and respond only to the Read Status Register and Erase Suspend commands. While the WSM is executing, the device will output status register data when OE# is toggled low. Status register data can only be updated by toggling either OE# or CE#. If the previous command was not the Erase Setup command (20H), the Erase Confirm command is ignored. Status Register bits 4 and 5 are both set to indicate an invalid command sequence. Erase Suspend (B0H) This command is only valid while the WSM is executing an erase operation. At all other times, this command is ignored. After this command has been executed, the CUI will set a signal that directs the WSM to suspend erase operations. While waiting for the erase to be suspended, the CUI responds only to the Read Status Register command or to the Erase Resume command. Once the WSM has reached the Suspend state, it will set an output in the CUI that allows the CUI to respond to the Read Array, Read Status Register, and Erase Resume commands. In this mode, the CUI will not respond to any other commands. The WSM will also set the WSM and Erase Suspend status bits to a “1.” The WSM will continue to run, idling in the Suspend state, regardless of the state of all input control pins except V PP and RP#. If VPP is taken below VPPLK , the VPP low status bit (SR.3) will be set and the WSM will abort the suspended erase operation. If active, RP# will immediately shut down the WSM and the remainder of the chip. During a suspend operation, the data and address latches will remain closed, but the address pads are able to drive the address into the read path.
E 28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY 17PRELIMINARY Erase Resume (D0H) This command will cause the CUI to clear the Suspend state and clear the WSM Status Bit to a “0,” but only if an Erase Suspend command was previously issued. Erase Resume will not have any effect under any other conditions.
3.3.2 STATUS REGISTER
The 28F002BC contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. The status register may be read at any time by writing the Read Status Register command to the CUI. After writing this command, all subsequent read operations output data from the status register until another command is written to the CUI. A Read Array command must be written to the CUI to return to read array mode. The status register bits are output on DQ[0:7]. The contents of the status register are latched on the falling edge of OE# or CE#, whichever occurs last in the read cycle. This prevents possible bus errors that might occur if the contents of the status register change while reading the status register. CE# or OE# must be toggled with each subsequent status read to insure the status register is updated; otherwise, the completion of a program or erase operation will not be evident from the status register. When the WSM is active, the status register will indicate the status of the WSM and upon command completion, it will indicate success or failure of the operation (see Table 5 for definition of status register bits).
3.3.2.1 Clearing the Status Register
The WSM sets status bits “3” through “7” to “1,” and clears bits “6” and “7” to “0,” but cannot clear status bits “3” through “5” to “0.” Bits 3 through 5 can only be cleared by the controlling CPU through the use of the Clear Status Register command. These bits can indicate various error conditions. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence). The status register may then be read to determine if an error occurred during that programming or erasure series. This feature adds flexibility to the way the device may be programmed or erased. To clear the status register, the Clear Status Register command is written to the CUI. Then, any other command may be issued to the CUI. Note, again, that before a read cycle can be initiated, a valid read command must be written to the CUI to specify whether the read data is to come from the memory array, status register, or intelligent identifier.
3.3.3 PROGRAM MODE
Programming is executed using a two-write sequence. The Program Setup command is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM then executes a sequence of internally- timed events to: 1. Program the desired bits of the addressed memory byte. 2. Verify that the desired bits are sufficiently programmed. Programming of the memory results in specific bits within a byte being changed to a “0.” If the user attempts to program “1”s, there will be no change in memory contents and no error is reported by the status register. Similar to erasure, the status register indicates whether programming is complete. While the program sequence is executing, bit 7 of the status register is a “0.” The status register can be polled by toggling either CE# or OE# to determine when the program sequence is complete. Only the Read Status Register command is valid while programming is active. When programming is complete, the status bits, which indicate whether the program operation was successful, should be checked. If the programming operation was unsuccessful, bit 4 of the status register is set to a “1” to indicate a program failure. If bit 3 is set to a “1,” then V PP was not within acceptable limits, and the WSM did not execute the programming sequence. If the program operation fails, bit 4 of the status register will be set within 1.5 ms, as determined by the timeout of the WSM. The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, reads from the memory array cannot be accomplished until the CUI is given the Read Array command. Figure 7 shows the Automated Programming Flowchart.
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Table 5. Status Register Bit Definition still unable to successfully verify block erasure. but failed to program a byte. PP has not been switched on. masked out when polling the status register.
3.3.4 ERASE MODE
returns to read status register mode.
- Program all bits within the block to “0.”
- Verify that all bits within the block are
- Erase all bits within the block (set all bits to “1”).
- Verify that all bits within the block are
E 28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY 19PRELIMINARY When the status register indicates that erasure is complete, the status bits, which indicate whether the erase operation was successful, should be checked. If the erase operation was unsuccessful, bit 5 of the status register will be set (within 1.5 ms) to “1,” indicating an erase failure. If V PP is not within acceptable during the suspended period, the WSM does not execute the erase sequence; instead, bit 5 of the status register is set to a “1” to indicate an Erase Failure, and bit 3 is set to a “1” to indicate that the V PP supply voltage was outside acceptable limits. The status register should be cleared before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, reads from the memory array cannot be accomplished until the CUI is given the Read Array command. Figure 8 details the Automated Block Erase Flowchart.
3.3.4.1 Suspending and Resuming Erase
Since an erase operation may take a few seconds to complete, an Erase Suspend command is provided. This allows erase-sequence interruption in order to read data from another block of the memory array. Once the erase sequence is started, writing the Erase Suspend command to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase algorithm. The status register must then be read to determine if the erase operation has been suspended. Taking V PP below VPPLK latches the VPP low status and aborts the operation in progress. VPP should be main- tained at valid levels, even during Erase Suspend. At this point, a Read Array command can be written to the CUI in order to read data from blocks other than that being erased. The only other valid commands at this time are Erase Resume and Read Status Register. During erase suspend mode, the chip can go into a pseudo-standby mode by taking CE# to V IH, which reduces active current draw. To resume the erase operation, the chip must be enabled by taking CE# to VIL, then issuing the Erase Resume command. When the Erase Resume command is given, the WSM will continue with the erase sequence and finish erasing the block. As with the end of a standard erase operation, the status register must be read, cleared, and the next instruction issued in order to continue. Figure 9 highlights the Erase Suspend/Resume Flowchart.
3.3.5 EXTENDED CYCLING
Intel has designed extended cycling capability into its ETOX IV flash memory technology. The 28F002BC flash memory is designed for 100,000 program/erase cycles on each of the five blocks. At 10% V PP , the parameter blocks are capable of 10,000 program/erase cycles. The combination of low electric fields, clean oxide processing and minimized oxide area per memory cell subjected to the tunneling electric field results in very high cycling capability.
3.4 Boot Block Locking
The Boot Block memory architecture features a hardware-lockable boot block so that the kernel code for the system can be kept secure while the parameter and main blocks are programmed and erased independently as necessary. Only the boot block can be locked independently from the other blocks. 3.4.1 V PP = VIL FOR COMPLETE PROTECTION For complete write protection of all blocks in the flash device, the VPP programming voltage can be held low. When VPP is below VPPLK , any program or erase operation will cause the device to set an error bit in the status register.
3.4.2 RP# = V
In the case of boot block modifications (write and erase), RP# and V PP are set to V HH (12V). However, if RP# is not at VHH when a program or erase operation of the boot block is attempted, the corresponding status register bit (Bit 4 for Program and Bit 5 for Erase, refer to Table 5 for status register definitions) is set to indicate the failure to complete the specified operation.
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attempts are allowed by the Write State Machine. where multiple bytes are programmed before full status is checked. Toggle CE# or OE# to Update SRD. Repeat for subsequent writes. Figure 7. Automated Programming Flowchart
attempts are allowed by the Write State Machine. cases where multiple blocks are erase before full status is checked. retry or other error recovery. Repeat for subsequent block erasures. Write FFH after the last operation to reset device to read array mode. Figure 8. Automated Block Erase Flowchart
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Figure 9. Erase Suspend/Resume Flowchart
E 28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY 23PRELIMINARY
3.5 Power Consumption
3.5.1 ACTIVE POWER
With CE# at a logic-low level and RP# at a logic- high level, the device is placed in the active mode. The device I CC current is a maximum of 60 mA at 10 MHz with TTL input signals.
3.5.2 STANDBY POWER
With CE# at a logic-high level (VIH), the memory is placed in standby mode, where the maximum ICC standby current is 100 µA. The standby operation disables much of the device’s circuitry and substantially reduces device power consumption. The outputs (DQ[0:7]) are placed in a high- impedance state independent of the status of the OE# signal. When CE# is at a logic-high level during erase or program, the device will continue to perform the erase or program function and consume erase or program active power until erase or program is completed.
3.5.3 DEEP POWER-DOWN
The 28F002BC flash memory supports a typical I CC of 0.2 µA in deep power-down mode. This mode is activated by the RP# pin when it is at a logic-low (GND ± 0.2V); in this mode, all internal circuits are turned off to save power. Setting the RP# pin low de-selects the memory and places the output drivers in a high impedance state. Recovery from the deep power-down state requires a minimum access time of 300 ns (see AC Characteristics table, t PHQV parameter). During erase or program modes, RP# low will abort either erase or program operations, but the memory contents are no longer valid as the data has been corrupted. RP# transitions to V IL or turning power off to the device will clear the status register.
3.6 Power-Up/Down Operation
The 28F002BC offers protection against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, V PP or VCC , powers-up first. The CUI is reset to the read mode after power-up, but the system must drop CE# low or present a new address to ensure valid data at the outputs. A system designer must guard against spurious writes when V CC voltages are above VLKO and VPP = VHH . Since both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RP# is brought to V IH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system PowerGood/Reset) during power up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.
3.6.1 RP# CONNECTED TO SYSTEM
The use of RP# during system reset is important with automated write/erase devices because the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization would not occur because the flash memory may be providing status information instead of array data. Intel’s Flash memories allow proper CPU initialization following a system reset by connecting the RP# pin to the same RESET# signal that resets the system CPU. 3.6.2 V CC , VPP AND RP# TRANSITIONS The CUI latches commands as issued by system software and is not altered by VPP , CE# transitions, or WSM actions. Its default state upon power-up, after exit from deep power-down mode, or after V CC transitions above VLKO , is read array mode. After any program or block erase operation is complete, and even after VPP transitions down to VPPLK , the CUI must be reset to read array mode via the Read Array command if access to the flash memory is desired.
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY E
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3.7 Power Supply Decoupling
Flash memory’s power switching characteristics require careful device decoupling methods. System designers should consider three supply current issues: 1. Standby current levels (I CCS ) 2. Active current levels (ICCR ) 3. Transient peaks produced by falling and rising edges of CE# Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each V CC and GND, and between its VPP and GND. These high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 3.7.1 V PP TRACE ON PRINTED CIRCUIT BOARDS Designing for in-system writes to the flash memory requires special consideration of the VPP power supply trace by the printed circuit board designer. The V PP pin supplies the flash memory cells current for programming and erasing. One should use similar trace widths and layout considerations given to the V CC power supply trace. Adequate VPP supply traces and decoupling capacitors placed adjacent to the component will decrease spikes and overshoots.
4.0 ELECTRICAL SPECIFICATIONS
4.1 Absolute Maximum Ratings
- Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20
- Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns. Maximum DC voltage on RP# or A9 may
overshoot to 13.5V for periods <20 ns.
- Output shorted for no more than one second. No more than one output shorted at a time.
4.2 Operating Conditions
Table 6. Temperature and VCC Operating Conditions
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4.2.1 CAPACITANCE
- Sampled, not 100% tested.
- For the 28F002BC, address pin A
10 follows the COUT capacitance numbers.
4.2.2 INPUT/OUTPUT TEST CONDITIONS
and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Figure 10. Inputs and Measurement Points Figure 11. Standard Test Configuration
4.2.3 DC CHARACTERISTICS
Table 7. DC Characteristics
28 PRELIMINARY
Table 7. DC Characteristics (Continued)
2.4 V VCC = VCC Min
valid for all product versions (packages and speeds).
- ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of
- Block erases and byte writes are inhibited when VPP = VPPLK , and not guaranteed in the range between VPPH and VPPLK .
- Sampled, not 100% tested.
CC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.
- VCC = 12.0V ± 10% for applications requiring 100,000 block erase cycles.
- VPP = 12.0V ± 5% for applications requiring 100,000 block erase cycles.
- V PP = 12.0V ± 10% for applications requiring wider VPP tolerances: Parameter blocks can sustain 10,000 block erase
4.2.4 AC CHARACTERISTICS
Table 8. AC Characteristics: Read Only Operations
- See AC Input/Output Reference Waveform for timing measurements.
- OE# may be delayed up to t
CE —t OE after the falling edge of CE# without impact on tCE .
- Sampled, but not 100% tested.
- See Standard Test Configuration (Figure 11).
30 PRELIMINARY
Figure 12. AC Waveforms for Read Operations Table 9. AC Characteristics: WE#—Controlled Write Operations(1)
Table 9. AC Characteristics: WE#—Controlled Write Operations(1) (Continued)
- Read timing characteristics during write and erase opera tions are the same as during read-only operations. Refer to AC
characteristics during read mode.
- The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify and margining operations.
- Refer to command definition table for valid AIN.
- Refer to command definition table for valid DIN.
- Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
- For boot block program/erase, RP# should be hel d at V
HH until operation completes successfully.
- Time tPHBR is required for successful relocking of the boot block.
- Sampled, but not 100% tested.
32 PRELIMINARY
- V CC Power-Up and Standby
- Write Program Setup or Erase Setup Command
- Write Valid Address and Data (Program or Erase Confirm Command
- Automated Program or Erase Delay
- Read Status Register Data
Figure 13. AC Waveforms for Write and Erase Operations (WE#—Controlled Writes)
Table 10. AC Characteristics: CE#—Controlled Write Operations(1,9) See WE# Controlled Write Operations for notes 1 through 8.
- Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where
be measured relative to the CE# waveform.
34 PRELIMINARY
- V CC Power-Up and Standby
- Write Program Setup or Erase Setup Command
- Write Valid Address and Data (Program or Erase Confirm Command
- Automated Program or Erase Delay
- Read Status Register Data
Figure 14. Alternate AC Waveforms for Write and Erase Operations (CE#—Controlled Writes) Table 11. Erase and Program Timings (TA = +25°C)
- All numbers are sampled, not 100% tested.
- Erase times near max limits when the 10% V
E 28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY 35PRELIMINARY APPENDIX A
ORDERING INFORMATION
E = 40-Lead TSOP P = 40-Lead PDIP PA = 44-Lead PSOP Product Line Designator for all Intel Flash products Density/Organization 00X = x8-only (X = 2) Access Speed (ns) 80, 120 T = Top Boot Architecture B = Boot Block 0578_14 VALID COMBINATIONS: 40-Lead TSOP 40-Lead PDIP 44-Lead PSOP Commercial 2 M E28F002BC-T80 P28F002BC-T80 PA28F002BC-T80 E28F002BC-T120 P28F002BC-T120 PA28F002BC-T120
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY E
36 PRELIMINARY
Write State Machine Current/Next States Command Input (and Next State) Current State SR.7 Data When Read Read Array (FFH) Program Setup (40H) Erase Setup (20H) Erase Confirm (D0H) Erase Susp. (B0H) Erase Resume (D0H) Read Status (70H) Clear Status (50H) Read ID (90H) Read Array “1” Array Read Array Program Setup Erase Setup Read Array Read Status Read Array Read ID Program Setup “1” Status Program (Command Input = Byte Program Data) Program* (Not Comp.) “0” Status Program Program (Comp.) “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read ID Erase Setup “1” Status Erase Command Error Erase Erase Cmd. Error Erase Erase Command Error Erase Cmd. Error “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read ID Erase (Not Comp.) “0” Status Erase Erase Susp. to Status Erase Erase (Comp.) “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read ID Erase Suspend to Status “1” Status Erase Susp. to Array Erase Susp. to Array Erase Susp. to Array Erase Erase Susp. to Array Erase Erase Susp. to Status Erase Susp. to Array Erase Susp. to Array Erase Suspend to Array “1” Array Erase Susp. to Array Erase Susp. to Array Erase Susp. to Array Erase Erase Susp. to Array Erase Erase Susp. to Status Erase Susp. to Array Erase Susp. to Array Read Status “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read ID Read Identifier “1” ID Read Array Program Setup Erase Setup Read Array Read Status Read Array Read ID NOTE: You cannot program “1”s to the flash. Writing FFH after the Program Setup command will initiate the program algorithm of the WSM machine. The WSM will attempt the program, realize you are trying to program “1”s, and exit to read status mode without changing memory contents. No error is returned. Writing another FFH while in read status mode will return the flash to Read Array.
E 28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY 37PRELIMINARY APPENDIX C ADDITIONAL INFORMATION RELATED INTEL INFORMATION (1,2) Order Number Document
292130 AB-57 Boot Block Architecture for Safe Firmware Updates
292098 AP-363 Extended Flash BIOS Concepts for Portable Computers
292148 AP-604 Using Intel’s Boot Block Flash Memory Parameter Blocks to Replace EEPROM
292161 AP-608 Implementing a Plug and Play BIOS Using Intel’s Boot Block Flash Memory
292163 AP-610 Flash Memory In-System Code and Data Update Techniques
290448 28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet 290451 28F004/400BX-T/B 4-Mbit Boot Block Flash Memory Datasheet 290531 28F002/200BV-T/B 2-Mbit SmartVoltage Flash Memory Datasheet 290530 28F004/400BV-T/B 4-Mbit SmartVoltage Flash Memory Datasheet NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.