28F160S3 INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 INTRODUCTION
- 1.1 New Features
- 1.2 Product Overview
- 1.3 Pinout and Pin Description
- 2.0 PRINCIPLES OF OPERATION
- 2.1 Data Protection
- 3.0 BUS OPERATION
- 3.1 Read
- 3.2 Output Disable
- 3.3 Standby
- 3.4 Deep Power-Down
- 3.5 Read Query Operation
- 3.6 Read Identifier Codes Operation
- 3.7 Write
- 4.0 COMMAND DEFINITIONS
- 4.1 Read Array Command
- 4.2 Read Query Mode Command
- 4.2.1 Query Structure Output
- 4.2.2 Query Structure Overview
- 4.2.3 Block Status Register
- 4.2.4 CFI Query Identification String
- 4.2.5 System Interface Information
- 4.2.6 Device Geometry Definition
- 4.2.7 Intel-Specific Extended Query Table
- 4.3 Read Identifier Codes Command
- 4.4 Read Status Register Command
- 4.5 Clear Status Register Command
- 4.6 Block Erase Command
- 4.7 Full Chip Erase Command
- 4.8 Write to Buffer Command
- 4.9 Byte/Word Write Command
- 4.10 STS Configuration Command
- 4.11 Block Erase Suspend Command
- 4.12 Program Suspend Command
- 4.13 Set Block Lock-Bit Commands
- 4.14 Clear Block Lock-Bits Command
- 5.0 DESIGN CONSIDERATIONS
- 5.1 Three-Line Output Control
- 5.2 STS and WSM Polling
- 5.3 Power Supply Decoupling
- 5.5 VCC , VPP , RP# Transitions
- 5.6 Power-Up/Down Protection
- 6.0 ELECTRICAL SPECIFICATIONS
- 6.1 Absolute Maximum Ratings
- 6.2 Operating Conditions
- 6.2.1 Capacitance
- 6.2.2 AC Input/Output Test Conditions
- 6.2.3 DC Characteristics
- 6.2.4 AC Characteristics - Read-Only
- 6.2.6 Reset Operations
- 6.2.7 Erase, Program, And Lock-Bit
E ADVANCE INFORMATION June 1997 Order Number: 290608-001 /c110 Two 32-Byte Write Buffers 2.7 µs per Byte Effective Programming Time /c110 Low Voltage Operation 2.7V or 3.3V VCC 2.7V, 3.3V or 5V VPP /c110 100 ns Read Access Time (16 Mbit) 110 ns Read Access Time (32 Mbit) /c110 High-Density Symmetrically-Blocked Architecture 32 64-Kbyte Erase Blocks (16 Mbit) 64 64-Kbyte Erase Blocks (32 Mbit) /c110 System Performance Enhancements STS Status Output /c110 Industry-Standard Packaging µBGA* package, SSOP, and TSOP (16 Mbit) µBGA* package and SSOP (32 Mbit) /c110 Cross-Compatible Command Support Intel Standard Command Set Common Flash Interface (CFI) Scaleable Command Set (SCS) /c110 100,000 Block Erase Cycles /c110 Enhanced Data Protection Features Absolute Protection with VPP = GND Flexible Block Locking Block Erase/Program Lockout during Power Transitions /c110 Configurable x8 or x16 I/O /c110 Automation Suspend Options Program Suspend to Read Block Erase Suspend to Program Block Erase Suspend to Read /c110 ETOX™ V Nonvolatile Flash Technology Intel’s Word-Wide FlashFile™ memory family provides high-density, low-cost, non-volatile, read/write storage solutions for a wide range of applications. The Word-Wide FlashFile memories are available at various densities in the same package type. Their symmetrically-blocked architecture, flexible voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs, and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the Word-Wide FlashFile memories offer three levels of protection: absolute protection with V PP at GND, selective block locking, and program/erase lockout during power transitions. These alternatives give designers ultimate control of their code security needs. This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. It comes in the industry-standard 56-lead SSOP and µBGA packages. In addition, the 16-Mb device is available in the industry-standard 56-lead TSOP package. WORD-WIDE FlashFile™ MEMORY FAMILY 28F160S3, 28F320S3 Includes Extended Temperature Specifications
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F160S3 and 28F320S3 may contain design defects or errors known as errata. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 or visit Intel’s website at http:\\\\www.intel.com COPYRIGHT © INTEL CORPORATION, 1997 CG-041493 *Third-party brands and names are the property of their respective owners.
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REVISION HISTORY
-001 Original version
E 28F160S3, 28F320S3 5ADVANCE INFORMATION
1.0 INTRODUCTION
This datasheet contains 16- and 32-Mbit Word- Wide FlashFileTM memory (28F160S3 and 28F320S3) specifications. Section 1 provides a flash memory overview. Sections 2, 3, 4, and 5 describe the memory organization and functionality. Section 6 covers electrical specifications for extended temperature product offerings.
1.1 New Features
The Word-Wide FlashFile memory family maintains basic compatibility with Intel’s 28F016SA and 28F016SV. Key enhancements include:
- Common Flash Interface (CFI) Support
- Scaleable Command Set (SCS) Support
- Low Voltage Technology
- Enhanced Suspend Capabilities They share a compatible Status Register, basic software commands, and pinout. These similarities enable a clean migration from the 28F016SA or 28F016SV. When upgrading, it is important to note the following differences:
- Because of new feature and density options, the devices have different manufacturer and device identifier codes. This allows for software optimization.
- New software commands.
- To take advantage of low voltage on the 28F160S3 and 28F320S3, allow V PP connection to V CC . The 28F160S3 and 28F320S3 do not support a 12V VPP option.
1.2 Product Overview
The Word-Wide FlashFile memory family provides density upgrades with pinout compatibility for the 16- and 32-Mbit densities. They are high- performance memories arranged as 1 Mword and
2 Mwords of 16 bits or 2 Mbyte and 4 Mbyte of
8 bits. This data is grouped in thirty-two and sixty- four 64-Kbyte blocks that can be erased, locked and unlocked in-system. Figure 1 shows the block diagram, and Figure 5 illustrates the memory organization. This family of products are optimized for fast factory programming and low power designs. Specifically designed for 3V systems, the 28F160S3 and 28F320S3 support read operations at 2.7V–3.6V Vcc with block erase and program operations at 2.7V–3.6V and 5V V PP . High programming performance is achieved through highly-optimized write buffers. A 5V V PP option is available for even faster factory programming. For a simple low power design, V CC and V PP can be tied to 2.7V. Additionally, the dedicated VPP pin gives complete data protection when VPP ≤ VPPLK . Internal VPP detection circuitry automatically configures the device for optimized write operations. A Common Flash Interface (CFI) permits OEM- specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scaleable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal device operation. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device’s 64-Kbyte blocks typically within t WHQV2/EHQV2 independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. Data is programmed in byte, word or page increments. Program suspend mode enables the system to read data or execute code from any other flash memory array location.
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over non-buffer programming. Lock-Bits commands) set and clear lock-bits. device is in static mode (addresses not switching).
1.3 Pinout and Pin Description
Figure 1. Block Diagram
Table 1. Pin Descriptions latched during a write cycle. A0 selects high or low byte when operating in x8 mode. In x16 mode, A0 is not used; input buffer is off. are disabled. Data is internally latched during a write cycle. first rising edge of CE0# or CE1# disables the device. operation. Exit from deep power-down sets the device to read array mode. OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle. are latched on the rising edge of the WE# pulse. cannot be erased or programmed, and block lock-bits cannot be set or cleared. BYTE# INPUT BYTE ENABLE: Configures x8 mode (low) or x16 mode (high). operations. Do not float any power pins. erase, program, or block-lock configuration with invalid VCC values. GND SUPPLY GROUND: Do not float any ground pins. NC NO CONNECT: Lead is not internally connected; it may be driven or floated.
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Figure 2. TSOP 56-Lead Pinout
Figure 3. SSOP 56-Lead Pinout
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the board. Note that the signals are mirror imaged.
- Figures are not drawn to scale.
- Address A21 is not included in the 28F160S3.
- More information on µBGA* packages is available by contacting your Intel/Distribution sales office.
**Figure 4. µBGA* Package Pinout**
2.0 PRINCIPLES OF OPERATION
standby, and output disable operations. and verified through the Status Register.
erase, programming, and lock-bit configuration. other flash memory array location.
2.1 Data Protection
Figure 5. Memory Map
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3.0 BUS OPERATION
The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
3.1 Read
Block information, query information, identifier codes and Status Registers can be read independent of the V PP voltage. The first task is to place the device into the desired read mode by writing the appropriate read-mode command (Read Array, Query, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. Control pins dictate the data flow in and out of the component. CE 0#, CE1# and OE# must be driven active to obtain data at the outputs. CE0# and CE 1# are the device selection controls, and, when both are active, enable the selected memory device. OE# is the data output (DQ DQ 15) control: When active it drives the selected memory data onto the I/O bus. WE# must be at V IH and RP# must be at VIH. Figure 17 illustrates a read cycle.
3.2 Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0–DQ 15 are placed in a high-impedance state.
3.3 Standby
CE 0# or CE1# at a logic-high level (VIH) places the device in standby mode, substantially reducing device power consumption. DQ 0–DQ 15 (or DQ0– DQ 7 in x8 mode) outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, programming, or lock-bit configuration, the device continues functioning and consuming active power until the operation completes.
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode. In read mode, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. RP# must be held low for time t PLPH . Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, and the Status Register is set to 80H. During block erase, programming, or lock-bit configuration modes, RP#-low will abort the operation. STS in RY/BY# mode remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after programming or partially altered after an erase or lock-bit configuration. Time t PHWL is required after RP# goes to logic-high (VIH) before another command can be written. It is important in any automated system to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, programming, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel’s Flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.5 Read Query Operation
The read query operation outputs block status, Common Flash Interface (CFI) ID string, system interface, device geometry, and Intel-specific extended query information.
3.6 Read Identifier Codes
identify each block’s lock-bit setting. Figure 6. Device Identifier Code Memory Map
3.7 Write
and lock-bit configuration can also be performed. an address within the device. (CE0#, CE 1#), whichever goes high first. Standard microprocessor write timings are used. Figure 18 illustrates a write operation.
4.0 COMMAND DEFINITIONS
bit configuration operations.
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Table 2. Bus Operations
10 V IL X X X X X X High Z High Z (9)
- Refer to Table 19. When VPP ≤ VPPLK , memory contents can be read, but not altered.
- X can be VIL or VIH for control and address input pins and VPPLK or VPPH1/2 for VPP . See Table 19, for VPPLK and VPPH1/2
- STS in level RY/BY# mode (default) is VOL when the WSM is executing internal block erase, programming, or lock-bit
program suspend mode, or deep power-down mode.
- See Section 4.3 for read identifier code data.
- See Section 4.2 for read query data.
- Command writes involving block erase, write, or lock-bit configuration are reliably executed when V
VCC = VCC1/2 (see Section 6.2).
- Refer to Table 3 for valid DIN during a write operation.
- DQ refers to DQ0–7 if BYTE# is low and DQ0–15 if BYTE# is high.
- High Z will be VOH with an external pull-up resistor.
- RP# at GND ± 0.2V ensures the lowest deep power-down current.
- OE# = VIL and WE# = VIL concurrently is an undefined state and should not be attempted.
Table 3. Word-Wide FlashFile™ Memory Command Set Definitions(13)
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NOTES: 1. Bus operations are defined in Table 2. 2. X = Any valid address within the device. BA = Address within the block being erased or locked. IA = Identifier Code Address: see Table 12. QA = Query database Address. PA = Address of memory location to be programmed. 3. ID = Data read from Query database. SRD = Data read from Status Register. See Table 15 for a description of the Status Register bits. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#. CC = Configuration Code. (See Table 14.) 4. The upper byte of the data bus (DQ 8–15) during command writes is a “Don’t Care” in x16 operation. 5. Following the Read Identifier Codes command, read operations access manufacturer, device, and block-lock codes. See Section 4.3 for read identifier code data. 6. If a block is locked (i.e., the block’s lock-bit is set to 0), WP# must be at VIH in order to perform block erase, program and suspend operations. Attempts to issue a block erase, program and suspend operation to a locked block while WP# is VIL will fail. 7. Either 40H or 10H are recognized by the WSM as the byte/word program setup. 8. After the Write to Buffer command is issued, check the XSR to make sure a Write Buffer is available. 9. N = byte/word count argument such that the number of bytes/words to be written to the input buffer = N + 1. N = 0 is 1 byte/word length, and so on. Write to Buffer is a multi-cycle operation, where a byte/word count of N + 1 is written to the correct memory address (WA) with the proper data (WD). The Confirm command (D0h) is expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the buffered write. Writing a byte/word count outside the buffer boundary causes unexpected results and should be avoided. 10. The write to buffer, block erase, or full chip erase operation does not begin until a Confirm command (D0h) is issued. Confirm also reactivates suspended operations. 11. A block lock-bit can be set only while WP# is V IH. 12. WP# must be at VIH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. 13. Commands other than those shown above are reserved for future use and should not be used. 14. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.
E 28F160S3, 28F320S3 17ADVANCE INFORMATION
4.1 Read Array Command
Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started block erase, program, or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation—unless the WSM is suspended via an Erase-Suspend or Program- Suspend command. The Read Array command functions independently of the V PP voltage.
4.2 Read Query Mode Command
This section defines the data structure or “database” returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI.
4.2.1 QUERY STRUCTURE OUTPUT
The Query “database” allows system software to gain critical information for controlling the flash component. This section describes the device’s CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest- order data outputs (DQ 0-7) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this device, the Query table device starting address is a 10h word address, since the maximum bus width is x16. For this word-wide (x16) device, the first two bytes of the Query structure, “Q” and ”R” in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII “Q” in the low byte (DQ 0-7) and 00h in the high byte (DQ 8-15). Since the device is x8/x16 capable, the x8 data is still presented in word-relative (16-bit) addresses. However, the “fill data” (00h) is not the same as driven by the upper bytes in the x16 mode. As in x16 mode, the byte address (A 0) is ignored for Query output so that the “odd byte address” (A0 high) repeats the “even byte address” data (A0 low). Therefore, in x8 mode using byte addressing, the device will output the sequence “Q”, “Q”, “R”, “R”, “Y”, “Y”, and so on, beginning at byte-relative address 20h (which is equivalent to word offset 10h in x16 mode). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address.
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Table 4. Summary of Query Structure Output as a Function of Device and Mode
- The system must drive the lowest order addresses to access all the device’s array data when the device is configured in x8
Table 5. Example of Query Structure Output of a x16- and x8-Capable Device
4.2.2 QUERY STRUCTURE OVERVIEW
and address locations are summarized in Table 8. Table 6. Query Structure
- Refer to Section 4.2.1 and Table 4 for the detailed definition of offset address as a function of device word width and mode.
- BA = The beginning location of a Block Address (i.e., 08000h is the beginning location of block 1 when the block size is
- Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
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4.2.3 BLOCK STATUS REGISTER
word address 02h within each block. Table 7. Block Status Register
- BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in word mode.)
4.2.4 CFI QUERY IDENTIFICATION STRING
Table 8. CFI Identification
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4.2.5 SYSTEM INTERFACE INFORMATION
optimizing system interface software. Table 9. System Interface Information
4.2.6 DEVICE GEOMETRY DEFINITION
Table 10. Device Geometry Definition
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4.2.7 INTEL-SPECIFIC EXTENDED QUERY
Certain flash features and commands are optional. The Intel-Specific Extended Query table specifies this and other similar types of information. Table 11. Primary-Vendor Specific Extended Query
Description
(P)h 03h Primary Extended Query Table Unique ASCII String “PRI“ 31: 0050h 32: 0052h 33: 0049h (P+3)h 01h Major Version Number, ASCII 34: 0031h (P+4)h 01h Minor Version Number, ASCII 35: 0030h (P+5)h 04h Optional Feature & Command Support bit 0 Chip Erase Supported ( 1=yes, 0=no) bit 1 Suspend Erase Supported (1=yes, 0=no) bit 2 Suspend Program Supported (1=yes, 0=no) bit 3 Lock/Unlock Supported ( 1=yes, 0=no) bit 4 Queued Erase Supported (1=yes, 0=no) bits 5–31 Reserved for future use; undefined bits are “0” 36: 000Fh 37: 0000h 38: 0000h 39: 0000h (P+9)h 01h Supported Functions after Suspend Read Array, Status, and Query are always supported during suspended Erase or Program operation. This field defines other operations supported. bit 0 Program Supported after Erase Suspend (1=yes, 0=no) bits 1-7 Reserved for future use; undefined bits are “0” 3A: 0001h (P+A)h 02h Block Status Register Mask Defines which bits in the Block Status Register section of Query are implemented. bit 0 Block Status Register Lock-Bit [BSR.0] active (1=yes, 0=no) bit 1 Block Erase Status Bit [BSR.1] active (1=yes, 0=no) bits 2-15 Reserved for future use; undefined bits are “0” 3B: 0003h 3C: 0000h NOTES: 1. The variable P is a pointer which is defined at offset 15h in Table 8.
E 28F160S3, 28F320S3 25ADVANCE INFORMATION Table 11. Primary-Vendor Specific Extended Query (Continued) (P+C)h 01h V CC Logic Supply Optimum Program/Erase voltage (highest performance) bits 7–4 BCD value in volts bits 3–0 BCD value in 100 mv 3D: 0050h (P+D)h 01h V PP [Programming] Supply Optimum Program/Erase voltage bits 7–4 HEX value in volts bits 3–0 BCD value in 100 mv 3E: 0050h (P+E)h reserved Reserved for future use Table 12. Identifier Codes
32 Mbit 000001 D4
- Block is Unlocked DQ 0 = 0
- Block is Locked DQ 0 = 1
- Reserved for Future Use DQ 2-7 Block Erase Status x0002 (1)
- Last erase completed successfully DQ 1 = 0
- Last erase did not complete successfully DQ 1 = 1
- Reserved for Future Use DQ 2-7 NOTES: 1. X selects the specific block lock configuration code. See Figure 6 for the device identifier code memory map. 2. A 0 should be ignored in this address. The lowest order address line is A1 in both word and byte mode.
4.3 Read Identifier Codes
4.4 Read Status Register
by writing the Read Status Register command.
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Following a program, block erase, set block lock-bit, or clear block lock-bits command sequence, only SR.7 is valid until the Write State Machine completes or suspends the operation. Device I/O pins DQ 0-6 and DQ 8-15 are invalid. When the operation completes or suspends (SR.7 = 1), all contents of the Status Register are valid when read. The eXtended Status Register (XSR) may be read to determine Write Buffer availability (see Table 16). The XSR may be read at any time by writing the Write to Buffer command. After writing this command, all subsequent read operations output data from the XSR, until another valid command is written. The contents of the XSR are latched on the falling edge of OE# or CE X# whichever occurs last in the read cycle. Write to buffer command must be re-issued to update the XSR latch.
4.5 Clear Status Register
Status Register bits SR.5, SR.4, SR.3, and SR.1 are set to “1”s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 15). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or programming several bytes/words in sequence) may be performed. The Status Register may be polled to determine if an error occurred during the sequence. To clear the Status Register, the Clear Status Register command is written. It functions independently of the applied V PP voltage. This command is not functional during block erase or program suspend modes.
4.6 Block Erase Command
Block Erase is executed one block at a time and initiated by a two-cycle command. A Block Erase Setup command is written first, followed by a Confirm command. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs Status Register data when read (see Figure 10). The CPU can detect block erase completion by analyzing STS in level RY/BY# mode or Status Register bit SR.7. Toggle OE#, CE 0#, or CE1# to update the Status Register. When the block erase is complete, Status Register bit SR.5 should be checked. If a block erase error is detected, the Status Register should be cleared before system software attempts corrective actions. The CUI remains in read Status Register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both Status Register bits SR.4 and SR.5 being set to “1.” Also, reliable block erasure can only occur when V CC = VCC1/2 and VPP = VPPH1/2. In the absence of these voltages, block contents are protected against erasure. If block erase is attempted while V PP ≤ VPPLK , SR.3 and SR.5 will be set to “1.” Successful block erase requires that the corresponding block lock-bit be cleared, or WP# = V IH. If block erase is attempted when the corresponding block lock-bit is set and WP# = VIL, the block erase will fail and SR.1 and SR.5 will be set to “1.”
4.7 Full Chip Erase Command
The Full Chip Erase command followed by a Confirm command erases all unlocked blocks. After the Confirm command is written, the device erases all unlocked blocks from block 0 to block 31 (or 63) sequentially. Block preconditioning, erase, and verify are handled internally by the WSM. After the Full Chip Erase command sequence is written to the CUI, the device automatically outputs the Status Register data when read. The CPU can detect full chip erase completion by polling the STS pin in level RY/BY# mode or Status Register bit SR.7. When the full chip erase is complete, Status Register bit SR.5 should be checked to see if the operation completed successfully. If an erase error occurred, the Status Register should be cleared before issuing the next command. The CUI remains in read Status Register mode until a new command is issued. If an error is detected while erasing a block during a full chip erase operation, the WSM skips the remaining cells in that block and proceeds to erase the next block. Reading the block valid status code by issuing the Read Identifier Codes command or Query command informs the user of which block(s) failed to erase.
E 28F160S3, 28F320S3 27ADVANCE INFORMATION This two-step command sequence of setup followed by execution ensures that block contents are not accidentally erased. An invalid Full Chip Erase command sequence will result in both Status Register bits SR.4 and SR.5 being set to 1. Also, reliable full chip erasure can only occur when V CC = VCC1/2 and VPP = VPPH1/2. In the absence of these voltages, block contents are protected against erasure. If full chip erase is attempted while VPP ≤ VPPLK , SR.3 and SR.5 will be set to 1. When WP# = V IL, only unlocked blocks are erased. Full chip erase cannot be suspended.
4.8 Write to Buffer Command
To program the flash device via the write buffers, a Write to Buffer command sequence is initiated. A variable number of bytes or words, up to the buffer size, can be written into the buffer and programmed to the flash device. First, the Write to Buffer setup command is issued along with the Block Address. At this point, the eXtended Status Register information is loaded and XSR.7 reverts to the “buffer available” status. If XSR.7 = 0, no write buffer is available. To retry, continue monitoring XSR.7 by issuing the Write to Buffer setup command with the Block Address until XSR.7 = 1. When XSR.7 transitions to a “1,” the buffer is ready for loading. Now a Word/Byte count is issued at an address within the block. On the next write, a device start address is given along with the write buffer data. For maximum programming performance and lower power, align the start address at the beginning of a Write Buffer boundary. Subsequent writes must supply additional device addresses and data, depending on the count. All subsequent addresses must lie within the start address plus the count. After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM to begin copying the buffer data to the flash memory. If a command other than Write Confirm is written to the device, an “Invalid Command/Sequence” error will be generated and Status Register bits SR.5 and SR.4 will be set to “1.” For additional buffer writes, issue another Write to Buffer setup command and check XSR.7. The write buffers can be loaded while the WSM is busy as long as XSR.7 indicates that a buffer is available. Refer to Figure 7 for the Write to Buffer flowchart. If an error occurs while writing, the device will stop programming, and Status Register bit SR.4 will be set to a “1” to indicate a program failure. Any time a media failure occurs during a program or an erase (SR.4 or SR.5 is set), the device will not accept any more Write to Buffer commands. Additionally, if the user attempts to write past an erase block boundary with a Write to Buffer command, the device will abort programming. This will generate an “Invalid Command/Sequence” error and Status Register bits SR.5 and SR.4 will be set to “1.” To clear SR.4 and/or SR.5, issue a Clear Status Register command. Reliable buffered programming can only occur when V CC = V CC1/2 and V PP = V PPH1/2. If programming is attempted while VPP ≤ V PPLK , Status Register bits SR.4 and SR.5 will be set to “1.” Programming attempts with invalid V CC and VPP voltages produce spurious results and should not be attempted. Finally, successful programming requires that the corresponding Block Lock-Bit be cleared, or WP# = V IH. If a buffered write is attempted when the corresponding Block Lock-Bit is set and WP# = V IL, SR.1 and SR.4 will be set to “1.”
4.9 Byte/Word Program Commands
Byte/Word programming is executed by a two-cycle command sequence. Byte/Word Program setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and verify algorithms internally. After the write sequence is written, the device automatically outputs Status Register data when read. The CPU can detect the completion of the program event by analyzing STS in level RY/BY# mode or Status Register bit SR.7. When programming is complete, Status Register bit SR.4 should be checked. If a programming error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for “1”s that do not successfully program to “0”s. The CUI remains in read Status Register mode until it receives another command. Refer to Figure 8 for the Word/Byte Program flowchart. Also, Reliable byte/word programming can only occur when V CC = VCC1/2 and VPP = VPPH1/2. In the absence of this high voltage, contents are protected against programming. If a byte/word program is
28F160S3, 28F320S3 E
28 ADVANCE INFORMATION
attempted while VPP ≤ VPPLK , Status Register bits SR.4 and SR.3 will be set to “1.” Successful byte/word programming requires that the corresponding block lock-bit be cleared. If a byte/word program is attempted when the corresponding block lock-bit is set and WP# = V IL, SR.1 and SR.4 will be set to “1.”
4.10 STS Configuration Command
The Status (STS) pin can be configured to different states using the STS pin Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued or RP# is low. Initially, the STS pin defaults to level RY/BY# operation where STS low indicates that the state machine is busy. STS high indicates that the state machine is ready for a new operation or suspended. To reconfigure the Status (STS) pin to other modes, the STS pin Configuration command is issued followed by the desired configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described in Table 14. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Write Complete interrupt pulse. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns. Supplying the 00h configuration code with the Configuration command resets the STS pin to the default RY/BY# level mode. Refer to Table 14 for configuration coding definitions. The Configuration command may only be given when the device is not busy or suspended. Check SR.7 for device status. An invalid configuration code will result in both Status Register bits SR.4 and SR.5 being set to “1.”
4.11 Block Erase Suspend
The Block Erase Suspend command allows block-erase interruption to read or program data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs Status Register data when read after the Block Erase Suspend command is written. Polling Status Register bit SR.7 can determine when the block erase operation has been suspended. When SR.7 = 1, SR.6 should also be set to “1,” indicating that the device is in the erase suspend mode. STS in level RY/BY# mode will also transition to V OH . Specification tWHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Program command sequence can also be issued during erase suspend to program data in other blocks. Using the Program Suspend command (see Section 4.12), a program operation can also be suspended. During a program operation with block erase suspended, Status Register bit SR.7 will return to “0” and STS in RY/BY# mode will transition to V OL . However, SR.6 will remain “1” to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and STS in RY/BY# mode will return to V OL . After the Erase Resume command is written, the device automatically outputs Status Register data when read (see Figure 11). V PP must remain at VPPH1/2 and VCC must remain at VCC1/2 (the same VPP and VCC levels used for block erase) while block erase is suspended. RP# must also remain at VIH (the same RP# level used for block erase). Block erase cannot resume until program operations initiated during block erase suspend have completed.
4.12 Program Suspend Command
The Program Suspend command allows program interruption to read data in other flash memory locations. Once the programming process starts, writing the Program Suspend command requests that the WSM suspend the program sequence at a predetermined point in the algorithm. The device continues to output Status Register data when read after the Program Suspend command is written. Polling Status Register bits SR.7 can determine when the programming operation has been suspended. When SR.7 = 1, SR.2 should also be set to “1”, indicating that the device is in the program suspend mode. STS in level RY/BY# mode will also transition to V OH . Specification tWHRH1 defines the program suspend latency.
E 28F160S3, 28F320S3 29ADVANCE INFORMATION At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while programming is suspended are Read Status Register and Program Resume. After a Program Resume command is written, the WSM will continue the programming process. Status Register bits SR.2 and SR.7 will automatically clear and STS in RY/BY# mode will return to V OL . After the Program Resume command is written, the device automatically outputs Status Register data when read. V PP must remain at VPPH1/2 and VCC must remain at VCC1/2 (the same VPP and VCC levels used for programming) while in program suspend mode. RP# must also remain at V IH (the same RP# level used for programming). Refer to Figure 9 for the Program Suspend/Resume flowchart.
4.13 Set Block Lock-Bit Command
A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits. The block lock-bits gate program and erase operations. With WP# = V IH, individual block lock-bits can be set using the Set Block Lock-Bit command. Set block lock-bit is initiated using a two-cycle command sequence. The Set Block Lock-Bit setup along with appropriate block or device address is written followed by the Set Block Lock-Bit Confirm and an address within the block to be locked. The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs Status Register data when read. The CPU can detect the completion of the set lock-bit event by analyzing STS in level RY/BY# mode or Status Register bit SR.7. When the set lock-bit operation is complete, Status Register bit SR.4 should be checked. If an error is detected, the Status Register should be cleared. The CUI will remain in read Status Register mode until a new command is issued. This two-step sequence of setup followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block Lock-Bit command will result in Status Register bits SR.4 and SR.5 being set to “1.” Also, reliable operations occur only when V CC = VCC1/2 and VPP = VPPH1/2. In the absence of these voltages, lock-bit contents are protected against alteration. A successful set block lock-bit operation requires that WP# = V IH. If it is attempted with WP# = VIL, the operation will fail and SR.1 and SR.4 will be set to “1.” See Table 13 for write protection alternatives. Refer to Figure 12 for the Set Block Lock-Bit flowchart.
4.14 Clear Block Lock-Bits
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. This command is valid only when WP# = V IH. The clear block lock-bits operation is initiated using a two-cycle command sequence. A Clear Block Lock-Bits setup command is written followed by a Confirm command. Then, the device automatically outputs Status Register data when read (see Figure 13). The CPU can detect completion of the clear block lock-bits event by analyzing STS in level RY/BY# mode or Status Register bit SR.7. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in Status Register bits SR.4 and SR.5 being set to “1.” Also, a reliable clear block lock-bits operation can only occur when V CC = VCC1/2 and VPP = VPPH1/2. If a clear block lock-bits operation is attempted while V PP ≤ VPPLK , SR.3 and SR.5 will be set to “1.” In the absence of these voltages, the block lock-bits contents are protected against alteration. A successful clear block lock-bits operation requires that WP# = V IH. If a clear block lock-bits operation is aborted due to VPP or VCC transitioning out of valid range or RP# or WP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. When the operation is complete, Status Register bit SR.5 should be checked. If a clear block lock-bit error is detected, the Status Register should be cleared. The CUI will remain in read Status Register mode until another command is issued.
30 ADVANCE INFORMATION
Table 13. Write Protection Alternatives Table 14. Configuration Coding Definitions DQ7–DQ2 are reserved for future use. any flash device's WSM is busy. for servicing continuous buffer write operations. interrupt service routine is desired.
- When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
Table 15. Status Register Definition command sequence was entered. operation, if the block lock-bit is set. masked when polling the Status Register. Table 16. Extended Status Register Definition that another Write to buffer command is possible.
32 ADVANCE INFORMATION
- Byte- or word-count values on DQ0-7 are loaded into
- The device now outputs the Status Register when
read (XSR is no longer available).
- Write Buffer contents will be programmed at the
device start address or destination flash address.
- Align the start address on a Write Buffer boundary for
maximum programming performance.
- The device aborts the Write to Buffer command if the
- The Status Register indicates an “improper command
sequence” if the Write to Buffer command is aborted. Follow this with a Clear Status Register command. operation to reset the device to Read Array mode. Figure 7. Write to Buffer Flowchart
Figure 8. Single Byte/Word Program Flowchart
34 ADVANCE INFORMATION
Figure 9. Program Suspend/Resume Flowchart
- The Erase Confirm byte must follow Erase Setup when
the Erase Queue status (XSR.7)=0. operation to reset the device to Read Array mode. Figure 10. Block Erase Flowchart
36 ADVANCE INFORMATION
Figure 11. Block Erase Suspend/Resume Flowchart
before full status is checked. Repeat for subsequent lock-bit set operations. or after a sequence of lock-bit set operations. Figure 12. Set Block Lock-Bit Flowchart
38 ADVANCE INFORMATION
retry or other error recovery. Figure 13. Clear Block Lock-Bits Flowchart
E 28F160S3, 28F320S3 39ADVANCE INFORMATION
5.0 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
Intel provides three control inputs to accommodate multiple memory connections: CEX# (CE0#, CE1#), OE#, and RP#. Three-line control provides for: a. Lowest possible memory power dissipation; b. Data bus contention avoidance. To use these control inputs efficiently, an address decoder should enable CEx# while OE# should be connected to all memory devices and the system’s READ# control line. This assures that only selected memory devices have active outputs, while de- selected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
5.2 STS and WSM Polling
STS is an open drain output that should be connected to V CC by a pull-up resistor to provide a hardware form of detecting block erase, program, and lock-bit configuration completion. In default mode, it transitions low during execution of these commands and returns to V OH when the WSM has finished executing the internal algorithm. For alternate STS pin configurations, see Section 4.10. STS can be connected to an interrupt input of the system CPU or controller. It is active at all times. STS, in default mode, is also V OH when the device is in block erase suspend (with programming inactive) or in reset/power-down mode.
5.3 Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. Standby current levels, active current levels and transient peaks produced by falling and rising edges of CE X# and OE# are areas of interest. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its V CC and GND and V PP and GND. These high- frequency, low-inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array’s power supply connection between V CC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance.
5.4 V PP Trace on Printed Circuit
Updating target-system resident flash memories requires that the printed circuit board designer pay attention to V PP power supply traces. The VPP pin supplies the memory cell current for programming and block erasing. Use similar trace widths and layout considerations given to the V CC power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots.
5.5 V CC , VPP , RP# Transitions
Block erase, program, and lock-bit configuration are not guaranteed if RP# ≠ V IH, or if VPP or VCC fall outside of a valid voltage range (VCC1/2 and VPPH1/2). If VPP error is detected, Status Register bit SR.3 and SR.4 or SR.5 are set to “1.” If RP# transitions to V IL during block erase, program, or lock-bit configuration, STS in level RY/BY# mode will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. Because the aborted operation may leave data partially altered, the command sequence must be repeated after normal operation is restored.
5.6 Power-Up/Down Protection
The device offers protection against accidental block erase, programming, or lock-bit configuration during power transitions. A system designer must guard against spurious writes for V CC voltages above VLKO when V PP is active. Since both WE# and CEX# must be low for a command write, driving either input signal to VIH will inhibit writes. The CUI’s two-step command sequence architecture provides an added level of protection against data alteration. In-system block lock and unlock renders additional protection during power-up by prohibiting block erase and program operations. RP# = V IL disables the device regardless of its control inputs states.
40 ADVANCE INFORMATION
6.0 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings
- All specified voltages are with respect to GND. Minimum
- Maximum DC voltage on VPP may overshoot to +7.0V
- Output shorted for no more than one second. No more
than one output shorted at a time.
- Operating temperature is for extended product defined
6.2 Operating Conditions
Table 17. Temperature and VCC Operating Conditions(1)
- Device operations in the VCC voltage ranges not covered in the table produce spurious results and should not be
6.2.1 CAPACITANCE
Table 18. Capacitance(1), TA = +25°C, f = 1 MHz
- Sampled, not 100% tested.
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
Input rise and fall times (10% to 90%) <10 ns. Figure 14. Transient Input/Output Reference Waveform for VCC = 2.7V–3.6V Input rise and fall times (10% to 90%) <10 ns. Figure 15. Transient Input/Output Reference Waveform for VCC = 3.3V ± 0.3V Figure 16. Transient Equivalent Testing
42 ADVANCE INFORMATION
6.2.3 DC CHARACTERISTICS
Table 19. DC Characteristics, TA = –40
Table 19. DC Characteristics (Continued)
- All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25°C. These currents are
valid for all product versions (packages and speeds).
- ICCWS and ICCES are specified with the device de-selected. If read or programmed while in erase suspend mode, the
device’s current is the sum of ICCWS or ICCES and ICCR or ICCW .
- Includes STS in level RY/BY# mode.
- Block erase, program, and lock-bit configurations are inhibited when V
between VPPLK (max) and VPPH1 (min), between VPPH1 (max) and VPPH2 (min), and above VPPH2 (max).
- Automatic Power Savings (APS) reduces typical ICCR to 3 mA at 2.7V and 3.3V VCC static operation.
- Sampled, not 100% tested.
With VCC ≤ VLKO flash memory writes are inhibited.
44 ADVANCE INFORMATION
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS
Table 20. AC Read Characteristics (1,5), TA = –40
32 Mbit 1 110 130 140 160
32 Mbit 2 110 130 140 160
32 Mbit 3 110 130 140 160
- See AC Input/Output Reference Waveform for maximum allowable input slew rate.
- OE# may be delayed up to t
ELQV -tGLQV after the falling edge of CEX# without impact on tELQV .
- Sampled, not 100% tested.
- See Ordering Information for device speeds (valid operational combinations).
- See Figures 14 through 16 for testing characteristics.
Note: CEX# is the latter of CE0# and CE1# low or the first of CE0# or CE1# high. Figure 17. AC Waveform for Read Operations
46 ADVANCE INFORMATION
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS
Table 21. Write Operations(1,5,6), TA = –40°C to +85°C
- Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics for read-only operations.
- Sampled, not 100% tested.
- Refer to Table 3 for valid A
IN and DIN for block erase, program, or lock-bit configuration.
- V PP should be at VPPH1/2 until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0).
- See Ordering Information for device speeds (valid operational combinations).
- See Figures 14 through 16 for testing characteristics.
A. V CC power-up and standby. B. Write block erase or program setup. C. Write block erase confirm or valid address and data.. D. Automated erase or program delay. E. Read Status Register data. F. Write Read Array command. CE X# is the latter of CE0# and CE1# low or the first of CE0# or CE1# high. Figure 18. AC Waveform for Write Operations
48 ADVANCE INFORMATION
6.2.6 RESET OPERATIONS
Figure 19. AC Waveform for Reset Operation Table 22. Reset AC Specifications(1)
- These specifications are valid for all product versions (packages and speeds).
- If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing, the reset will
- A reset time, tPHQV , is required from the latter of STS in RY/BY# mode or RP# going high until outputs are valid.
6.2.7 ERASE, PROGRAM, AND LOCK-BIT CONFIGURATION PERFORMANCE
Table 23. Erase/Write/Lock Performance(3,4)
- Typical values measured at TA = +25°C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to
change based on device characterization.
- Excludes system-level overhead.
- These performance numbers are valid for all speed versions.
- Sampled but not 100% tested.
50 ADVANCE INFORMATION
Table 24. Erase/Write/Lock Performance(3,4)
- Typical values measured at TA = +25°C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to
change based on device characterization.
- Excludes system-level overhead.
- These performance numbers are valid for all speed versions.
- Sampled but not 100% tested.
E 28F160S3, 28F320S3 51ADVANCE INFORMATION APPENDIX A DEVICE NOMENCLATURE AND ORDERING INFORMATION Product line designator for all Intel Flash products Package DT = Extended Temp. 56-Lead SSOP TE = Extended Temp. 56-Lead TSOP GT = Extended Temp. Device Type 3 = 2.7V / 3.3V VCC 2.7V/3.3V / 5V VPP E28F1 06 S3 -1 Access Speed (ns) Product Family S = FlashFile™ Memory 56-Bump µBGA* package Device Density 160 = 16-Mbit 320 = 32-Mbit T Order Code by Density Valid Operational Combinations
16 Mb 32 Mb
2.7V-3.6V VCC 50 pF load (16 Mb / 32 Mb) 3.3V ± 0.3V VCC 50 pF load (16 Mb / 32 Mb) 56-lead TSOP S3-100 56-lead TSOP S3-110 -120 / -130 -100 / -110 56-lead TSOP S3-130 56-lead TSOP S3-140 -150 / -160 -130 / -140 56-lead SSOP S3-100 56-lead SSOP S3-110 -120 / -130 -100 / -110 56-lead SSOP S3-130 56-lead SSOP S3-140 -150 / -160 -130 / -140 56-bump µBGA S3-100 56-bump µBGA S3-110 -120 / -130 -100 / -110 56-bump µBGA S3-130 56-bump µBGA S3-140 -150 / -160 -130 / -140
28F160S3, 28F320S3 E
52 ADVANCE INFORMATION
ADDITIONAL INFORMATION (1,2) Order Number Document/Tool
290609 Word-Wide FlashFile MemoryTM Family 28F160S5, 28F320S5 Datasheet
292203 AP-645 28F160S3/S5 Compatibility with 28F016SA/SV
292204 AP-646 Common Flash Interface (CFI) and Command Sets
www.mcif.com Common Flash Interface Specification 290528 28F016SV 16-Mb (1Mbit x 16, 2 Mbit x 8) FlashFile™ Memory Datasheet 290489 28F016SA 16-Mb (1Mbit x 16, 2 Mbit x 8) FlashFile™ Memory Datasheet 297372 16-Mbit Flash Product Family User’s Manual
292123 AP-374 Flash Memory Write Protection Techniques
292144 AP-393 28F016SV Compatibility with 28F016SA
292159 AP-607 Multi-Site Layout Planning with Intel’s FlashFile™ Components,
292163 AP-610 Flash Memory In-System Code and Data Update Techniques
Contact Intel/Distribution Sales Office Mechanical Specification µBGA* Package Preliminary Guide Contact Intel/Distribution Sales Office Surface Mount and PCB Guidelines for µBGA* Packaging Contact Intel/Distribution Sales Office Multi-Site Layouts: 56-lead TSOP to 56-bump µBGA* package 56-lead SSOP to 56-bump µBGA package Contact Intel/Distribution Sales Office CFI - Common Flash Interface Reference Code NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.