DEI3283-SAB-G | DigiCamel IC Datasheet

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Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 11

Technical content

FEATURES

x Two separate analog receiver channels x Converts ARINC 429 levels to serial data x ARINC 429 inputs withstand +/-200V x TTL inputs to test complete analog/digital RX function x TTL and CMOS compatible outputs x Low power dissipation x Internal band gap voltage reference x MIL-STD-883B burn-in screening available x Package Options: 20 Lead ceramic DIP, 20 Terminal ceramic LCC, and 20 Lead SOIC x Direct replacement for Fairchild/Raytheon RM3283 and RM3183 and Holt HI-8482 Function Diagram

385 East Alamo Drive

Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com DEI3283 DUAL ARINC 429 LINE RECEIVER Device Engineering Incorporated

©2012 Device Engineering Inc Page 2 of 11 DS-MW-03283-01 Rev L 12/12/2012 General Description The DEI3283 consists of two analog ARINC 429 receivers which take differentially encoded ARINC level data and convert it to serial TTL level data. The DEI3283 provides two complete analog ARINC receivers with no external components required. Input level shifting thin film resistors and bipolar technology allow ARINC input voltage transients up to r200V without damage to the DEI3283. Each channel is identical, featuring symmetrical propagation delays for better high speed performance. Input common mode rejection is excellent and threshold voltage is stable, independent of supply voltage. Data outputs are TTL and CMOS compatible. Two TTL compatible test inputs used to test the ARINC channels are available. They can be used to override the ARINC input data and set the channel outputs to a known state. The DEI ARINC line driver family IC’s are companion chips to the DEI3283 line receiver. Together they provide the analog functions needed for the ARINC 429 interface. Functional Description The DEI3283 contains two discrete ARINC 429 receiver channels. Each channel contains three main sections: a resistor input network, a window comparator, and a logic output buffer stage. The first stage provides over voltage protection and biases the signal using voltage dividers and current sources, providing excellent input common mode rejection. The test inputs are provided to set the outputs to a predetermined state for built-in channel test capability. If the test inputs are not used, they should be grounded. The window comparator section detects data from the resistor input network. A LOGIC 1 corresponds to ARINC “High” state (OUTA) and a LOGIC 0, to ARINC “Low” state (OUTB). An ARINC “Null” state at the inputs forces both outputs to LOGIC 0. Threshold and hysteresis voltages are generated by a band gap voltage reference to maintain stable switching characteristics over temperature and power supply variations. The output stage generates a TTL compatible logic output capable of driving 3mA of load. Pin Assignments PIN NAME DESCRIPTION 1 -Vs Supply Voltage (-15V) 2 TEST A Logic Input, see functional characteristics.

3 CAP2B A429 INPUT, Ch 2, B Capacitor node

4 IN2B A429 INPUT, Ch 2, B input

5 OUT2B Logic Output, Ch 2, B’s output

6 IN2A A429 INPUT, Ch 2, A input

7 CAP2A A429 INPUT, Ch 2, A Capacitor node

8 OUT2A Logic Output, Ch 2, A’s output

9 +VL Supply Voltage (+5V) 10 NC 11 +VS Supply Voltage (+15V)

12 OUT1B Logic Output, Ch 1, B’s output

14 GND Supply Return

15 OUT1A Logic Output, Ch 1, A’s output

16 IN1B A429 INPUT, Ch 1, B input

17 CAP1B A429 INPUT, Ch 1, B Capacitor node

18 IN1A A429 INPUT, Ch 1, A input

19 CAP1A A429 INPUT, Ch 1, A Capacitor node

20 TESTB Logic Input, see functional characteristics. Absolute Maximum Ratings Parameter Min. Max. Units Supply Voltage: +VS to -VS +VS to GND -Vs to GND -20 +36 +20 V V V +VL Voltage +7 V Logic Input Voltage -0.3 +VL + 0.3 V ARINC 429 Input Voltage -200 +200 V Storage -65 +150 °C Temperature Range Operating -55 +125 °C Junction Temperature Ceramic Plastic -55 -55 +175 +145 Lead Soldering Temperature (60 sec., DIP, LCC) +300 °C Peak Body Temperature, J-STD-020 (SOIC) Non-G Package -G Package +240 +260 Recommended Operating Conditions Symbol Parameters Min. Max. Units +Vs Positive Supply Voltage 13.5 16.5 V -Vs Negative Supply Voltage -16.5 -13.5 V +VL +VL Supply Voltage 4.5 5.5 V Top Case Temperature Ceramic Plastic: -SA -SE -55 -40 -55 +125 +125 +85

Electrical Characteristics

Symbol Parameter Conditions (1,2) Min. Max. Units POWER SUPPLIES ICC +VS (+15V) Supply Current Supply = +/- 16.5V, Vl = 5.0V, Test Inputs = 0V Test Inputs = 5V 3.5 3.5 6.0 6.0 mA IEE -Vs (-15V) Supply Current Supply = +/- 16.5V, Vl = 5.0V, Test Inputs = 0V Test Inputs = 5V 7.5 11.0 12.0 18.5 mA IL +VL (+5V) Supply Current Supply = +/- 16.5V, Vl = 5.0V, Test Inputs = 0V Test Inputs = 5V 4.5 10.8 9.0 17.6 mA A429 INPUTS VHH NULL to 1 transition, V(INA) – V(INB) Supply = +/-15.0V, Vl = 5.00V Test inputs = 0V VINB = -2.50V 5.70 6.30 V VHL 1 to NULL transition, V(INA) – V(INB) Supply = +/-15.0V, Vl = 5.00V Test inputs = 0V VINB = -2.50V 4.50 5.50 V VHHYS 1 to NULL transition hysteresis VHH-VHL 0.8 1.2 V VLL NULL to 0 transition, V(INA) – V(INB) Supply = +/-15.0V, Vl = 5.00V Test inputs = 0V VINB = +2.50V -6.30 -5.70 V VHL 0 to NULL transition, V(INA) – V(INB) Supply = +/-15.0V, Vl = 5.00V Test inputs = 0V VINB = +2.50V -5.50 -4.50 V VLHYS 0 to NULL transition hysteresis VLL-VLH -1.2 -0.8 V VCM Input common mode voltage range -13 +13 V RINGND Input resistance, Input to GND Unpowered, INA to GND, INB to GND 20 30 Nȍ RIN Input resistor, INA to CAPA, INB to CAPB Unpowered INA to CAPA, INB to CAPB 8.5 11.5 Nȍ CIN Input capacitance, INA to GND, INB to GND (3) 10 pF TEST LOGIC INPUTS VIH LOGIC 1 input voltage Functional Test 2.0 V VIL LOGIC 0 input voltage Functional Test 0.9 V IIH LOGIC 1 input current VIH = 5V Supply = +/-15.0V, Vl = 5.00V 0 600 µA IIL LOGIC 0 input current VIL = 0.8V Supply = +/-15.0V, Vl = 5.00V 0 50 µA LOGIC OUTPUTS VOH LOGIC 1 output voltage Vsupply = +/-15.0V, Vl = 5.0V IOH = -100uA (Room Temp) IOH = -2.8mA 4.0 3.5 V V VOL LOGIC 0 output voltage Vsupply = +/-15.0V, Vl = 5.0V IOL = 100uA (Room Temp) IOL = 2.0mA 0.1 0.8 V V

©2012 Device Engineering Inc Page 5 of 11 DS-MW-03283-01 Rev L 12/12/2012 Symbol Parameter Conditions (1,2) Min. Max. Units Tr Output rise time CL = 60 pF (4) 10 70 ns Tf Output Fall Time CL = 60 pF (4) 10 70 ns TPLH Prop delay, A429 to LH output A429 In = 0 to 10V (4) CAPA, CAPB, OUT CL = 60 pF 1500 ns TPHL Prop delay, A429 to HL output A429 In = 0 to 10V (4) CAPA, CAPB, OUT CL = 60 pF 1500 ns DTP Matching of TPLH and TPHL |TPLH-TPHL| (4) 500 ns TPTLH Prop delay, TESTA/B to LH output CL = 60 pF, VIN = 0.8V/2.0V (4) 400 600 ns TPTHL Prop delay, TESTA/B to HL output CL = 60 pF, VIN = 0.8V/2.0V (4) 800 1300 ns Notes: 1. Unless otherwise noted, currents flowing in to DUT are positive, Currents flowing out of DUT are negative, Voltages are referenced to Ground. 2. Unless otherwise noted, Tcase = -55°C to +125°C for -xMx, -40°C to +125°C for -xAx, and -55°C to +85°C for –xEx versions; 3. Guaranteed by design. Not production tested. 4. Sample tested. AC Test Waveforms

©2012 Device Engineering Inc Page 6 of 11 DS-MW-03283-01 Rev L 12/12/2012 Functional Characteristics Test Inputs Outputs ARINC Inputs V(A) – V(B) TEST A TEST B OUT_A OUT_B Output State Null 0 0 0 0 Null Low 0 0 0 1 Low High 0 0 1 0 High X 0 1 0 1 Low X 1 0 1 0 High X 1 1 0 0 Null V[INA – INB] V[OUT_A] V[OUT_B] Parameter Characteristics (100KBS) min max units Time Y 9.75 10.25 us Time X 4.87 5.13 us Pulse rise time 0.5 2 us Pulse fall time 0.5 2 us Vhigh +7.25 11 V diff Vhh +6.5 V diff Vhl +2.5 V diff Vnull -0.5 +0.5 V diff Vll -2.5 V diff Vlh -6.5 V diff Vlow -11 -7.25 V diff

©2012 Device Engineering Inc Page 7 of 11 DS-MW-03283-01 Rev L 12/12/2012 Applications Discussion The standard connections for the DEI3283 are shown in the figure below. Dual ±15VDC supplies are recommended for the +VS/-VS supplies. Decoupling of all supplies should be done near the IC to avoid propagation of noise spikes due to switching transients. The ground connection should be sturdy and isolated from large switching currents to provide as quiet a ground reference as possible. The noise filter capacitors are optional and are added to provide extra noise immunity by limiting bandwidth of the input signal before it reaches the window comparator stage. Two capacitors are used for each channel and they must be the same value. The suggested capacitor value for a 100 kHz operation is 39 pF. For lower data rates, larger values of capacitance may be used to yield better noise performance. To get optimum performance, the following equation can be used to calculate capacitor value for a specific data rate: Where CFILTER is the capacitor value in pF, and FO is the input frequency (10 kHz dFO d150 kHz).

Applications

ARINC Receiver Standard Connections

©2012 Device Engineering Inc Page 8 of 11 DS-MW-03283-01 Rev L 12/12/2012 Process Flow Process Step Plastic Standard Ceramic Standard Plastic Burn-In Ceramic Burn-In THERMAL CYCLE MIL-STD-883B M1010.4 Condition B NO 10 Cycles NO 10 Cycles CONSTANT ACCELERATION MIL-STD-883B M2001, Method D. N/A YES N/A YES GROSS & FINE LEAK MIL-STD-883B M1014.10 N/A YES N/A YES BURN IN MIL-STD-883B M1015 Condition A N/A N/A 160hrs @ +125 °C 160hrs @ +125 °C FINAL ELECTRICAL TEST, Room Temperature 100% 100% 100% 100% FINAL ELECTRICAL TEST, High Temperature 100% @ 100% @ FINAL ELECTRICAL TEST, Low Temperature 0.65% AQL -55 or -40°C 0.65% AQL @ -55°C 0.65% AQL -55 or -40°C 0.65% AQL @ -55°C Burn-In Circuit

©2012 Device Engineering Inc Page 9 of 11 DS-MW-03283-01 Rev L 12/12/2012 Package Characteristics Package Characteristics PACKAGE TYPE 20L Ceramic LCC 20L CERDIP 20L CERDIP GREEN 20L SOIC 20L SOIC GREEN Reference (see ordering info)

20 CLCC 20 CERDIP 20 CERDIP

G

20 SOIC 20 SOIC G

JEDEC MO Reference MO-047 MS-030-A- AE MS-030-A- AE MS-013-AE MS-013-AE THERMAL RESISTANCE: TJA (4 layer PCB) TJC 85 °C/W 30 °C/W 70 °C/W 28 °C/W 70 °C/W 28 °C/W 85 °C/W 30 °C/W 85 °C/W 30 °C/W JEDEC Moisture Sensitivity Level (MSL) Hermetic Hermetic Hermetic MSL 1 / 250°C MSL 1 / 250°C Lead Finish Material / JEDEC Pb-free code SnPb solder dip na SnPb solder dip na SnAgCu solder dip SnPb plate na Matte Sn Pb-Free DESIGNATION Not Pb-free Not Pb-free Pb free Not Pb-free RoHS Compliant 20L SOIC ( – G and non - G ) Package

Ordering Information

Part Number Marking Package Operating Temperature Range Burn In DEI3283-CMB DEI3283-CMB 20 CERDIP -55qC to +125qC Y DEI3283-CMB-G DEI3283-CMB E1 20 CERDIP G -55qC to +125qC Y DEI3283-CMS DEI3283-CMS 20 CERDIP -55qC to +125qC N DEI3283-CMS-G DEI3283-CMS E1 20 CERDIP G -55qC to +125qC N DEI3283-EMB DEI3283-EMB 20 CLCC -55qC to +125qC Y DEI3283-EMS DEI3283-EMS 20 CLCC -55qC to +125qC N DEI3283-SAB DEI3283-SAB 20 SOIC -40qC to +125qC Y DEI3283-SAB-G DEI3283-SAB E3 20 SOIC G -40qC to +125qC Y DEI3283-SAS DEI3283-SAS 20 SOIC -40qC to +125qC N DEI3283-SAS-G DEI3283-SAS E3 20 SOIC G -40qC to +125qC N DEI3283-SEB DEI3283-SEB 20 SOIC -55qC to +85qC Y DEI3283-SEB-G DEI3283-SEB E3 20 SOIC G -55qC to +85qC Y DEI3283-SES DEI3283-SES 20 SOIC -55qC to +85qC N DEI3283-SES-G DEI3283-SES E3 20 SOIC G -55qC to +85qC N DEI3283-SMB DEI3283-SMB 20 SOIC -55qC to +125qC Y DEI3283-SMB-G DEI3283-SMB E3 20 SOIC G -55qC to +125qC Y DEI3283-SMS DEI3283-SMS 20 SOIC -55qC to +125qC N DEI3283-SMS-G DEI3283-SMS E3 20 SOIC G -55qC to +125qC N Notes: 1. All packages marked with Lot Code and Date Code. “E1” or “E3” after Date Code denotes Pb Free category. 2. The –CMB/-EMB/-SAB/-SEB/-SMB parts may be marked as – CMS/-EMS/-SAS/-SES/-SMS with a “B” stamp to denote burn-in. DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose.

Product Information

DEI3283-SAB-G specifications and overview.

Summary

DUAL ARINC 429 LINE RECEIVER

Description

DUAL ARINC 429 LINE RECEIVER

Source title DEI3283-SAB-G Datasheet(PDF) - Device Engineering Incorporated

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