DEI1116-QES-G

DEI1116 DEIAZ | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 14

Technical content

Features

• Two Receivers and One Transmitter
• 3.3V or 5V supply operation
• Pin compatible with DEI1016, HI3282 and HI8282A
• Wraparound Self-Test mode
• Word length can be configured for 25 bit or 32 bits operation
• Parity Status and generation of Receive and Transmit Words
• 8 Word Transmitter buffer
• Low Power CMOS
• Supports multiple ARINC protocols: 429, 571, 575, 706
• Temperature range options: -55/+85°C and -55/+125°C
• Package options: 44L MQFP and 44L PLCC
• Lightning Protection options: DEI1117 operates with 10K Ohm series resistor on A429 inputs.
• Pin and software compatible with the DEI1016 ARINC

429 Transceiver

The DEI1116/DEI1117 provides an interface between a standard avionics type serial digital data bus and a 16-bit- wide digital data bus. The interface circuit consists of a single channel transmitter with an 8X32 bit buffer, two independent receive channels, and a host programmable control register to select oper ating options. The two receiver channels operate identically , each providing a direct electrical interface to an ARINC data bus. The transmitter circuit contains an 8 word by 32 bit buffer memory and control logic which allows the host to write a block of data into the transmitter. The block of data is transmitted automatically by enabling the transmitter with no further attention by the host computer. Data is transmitted in TTL format on the DO(A)/DO(B ) output pins. The signal format is compatible with DEI’s extensive line of ARINC 429 Line drivers for easy connection to the ARINC data bus. The DEI1116 and DEI1117 differ in their A429 RX input characteristics. The DEI1116 interfaces directly to the A429 bus signals; the DEI1117 operates with 10K ohm series resistors. The series resistors support implementation of lightning transient protection. Figure 1: Block Diagram DEI1116 / DEI1117 ARINC 429 Transceiver Family

385 East Alamo Drive

Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: info@deiaz.com Device Engineering Incorporated Control Register TX FIFO

8 Words X 32 Bits

/DR1, /DR2 TXR /OE1, /OE2 /LD1, /LD2 ENTX /LDCW /DBCEN /MR

© 2012 Device Engineering Inc. DS-MW-01117-01 Rev B Page 2 of 14 02/09/2012 Table 1: Pin Definitions SYMBOL DEFINITION VDD Power Input. +5VDC ±10% GND Power Return and Signal Ground. DI1(A) ARINC 429 Input. R eceiver Channel 1, “A” input DI1(B) ARINC 429 Input. R eceiver Channel 1, “B” input DI2(A) ARINC 429 Input. R eceiver Channel 2, “A” input DI2(B) ARINC 429 Input. R eceiver Channel 2, “B” input /LDCW Logic Input. Load Control Register. A Low input pulse loads the Control Register from D[15:0]. SEL Logic Input. Receiver word select. A Low input se lects receiver Word 1; Hi selects Word 2 to be read on D [15:0] port. /LD1 Logic Input. Load Transmitter Word 1. A Lo w input pulse loads Word 1 into the Transmitter FIFO from D [15:0]. /LD2 Logic Input. Load Transmitter Word 2. A Lo w input pulse loads Word 2 into the Transmitter FIFO from D [15:0]. ENTX Logic Input. Enable Transmitter. A Hi input en ables the Transmitter to send data from the Transmitter FIFO. This must be Low while writing data into Transmitter FIFO. Transmitter memory is cleared by high-to-low transition. D[15:0] Logic Input / Tri-state Output. This 16-bit bi-directional data port is the uP data interface. Receiver data is read from this port. Control Register and Transmitter FIFO data is written into this port. /OE1 Logic Input. Receiver 1 Output Enable. A Low input enables the D [15:0] port to output Receiver 1 data. Word 1 or Word 2 will be output as determined by the SEL input. /OE2 Logic Input. Receiver 2 Output Enable. A Low input enables the D [15:0] port to output Receiver 2 data. Word 1 or Word 2 will be output as determined by the SEL input. /DR1 Logic Output. Data Ready, Receiver 1. A Low output indicates valid data in receiver 1. /DR2 Logic Output. Data Ready, Receiver 2. A Low output indicates valid data in receiver 2. TXR Logic Output. Transmitter Ready. A Hi output i ndicates the Transmitter FIFO is empty and ready to accept new data. DO(A), DO(B) Logic Outputs. Transmitter serial data outputs. This is a return-to-zero format signal which will normally feed an ARINC 429 Line Driver IC. A Hi output on DO(A) indicates the Transmitter data bit is a 1. A Hi output on DO(B) indicates the Transmitter data bit is a 0. The signal returns to zero for second half of bit time. TXCK Logic Output. Transmitter Clock. This outputs a clock frequency equal to the transmit data rate. The clock is always enabled and in phase with the data. The output is Hi during the first half of the data bit time. 1MCK Logic Input. External Clock. Master clock us ed by both the Receivers and Transmitter. The 1MHz rate is an X10 clock for the HI data rate (100 kbps), and a X80 clock for LO data rate (12.5 kbps). /MR Logic Input. Master Reset. A Lo input resets the Transmitter FIFO, bit counters, word counter, gap timers, /DRx, and TXR. The Control Register is not affected. Used on power up and system reset. /DBCEN Logic Input with internal pull up to V DD. Data Bit Control Enable. A Low input enables the transmitter parity bit control function as defined by control register bit 4 (PAREN). A Hi input forces transmitter parity bit insertion regardless of PAREN value. The pin is normally left open or tied to ground.

© 2012 Device Engineering Inc. DS-MW-01117-01 Rev B Page 3 of 14 02/09/2012 Figure 2: Terminal Connections Table 2: DC Electrical Characteristics Conditions: Ta = -55 to +125 ºC, Vdd = 3.3V ± 10% or Vdd = 5V ± 10% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT ARINC INPUTS: DI[1A/1B/2A/2B] (DEI1116) or DI[1A/1B/2A/2B]E with external 10K Ohm resistors (DEI1117) Differential Input Voltage ONE ZERO NULL Vil Vil Vnull 6.5 -13.0 -2.5 10.0 -10.0 13.0 -6.5 2.5 V V V Common Mode Input Voltage Vcm -10 10 V Input Resistance: Differential To GND To VDD RI RG RH 132 7500 200 100 KOhm KOhm KOhm Input Capacitance CI 20 pF LOGIC INPUTS Input Voltage: HI VIH Vdd = 3.0V to 5.5V 0.7*Vdd Vdd+0.5 V Input Voltage: LO VIL Vdd = 3.0V to 5.5V -0.5 0.8 V Hi-Z Input Current: Iin 0V to Vdd -10 10 µA Input Pull-up Current, /DBCEN IPU 0V -100 µA LOGIC OUTPUTS Output Voltage: TTL Logic 1 Output Voltage: CMOS Logic 1 Output Voltage: TTL Logic 0 Output Voltage: CMOS Logic 0 VOH-T VOH-C VOL-T VOL-C IOH = -4ma IOH = -100ua IOL = 4ma IOL = 100ua Vdd -0.5 Vdd -0.1 0.4 0.1 V V V V Output Capacitance: Cout 10 pF OPERATING SUPPLY CURRENT Supply Current at VDD = 3.3V or 5V IDD Fck = 1MHZ IDD ~ 4*(VDD-2.7) 12 mA Supply Voltage VDD 3.0 5.5 V

© 2012 Device Engineering Inc. DS-MW-01117-01 Rev B Page 4 of 14 02/09/2012 Table 3: Absolute Maximum Ratings PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VDD -0.5 +7.0 V DC Input Voltage, Logic inputs VIN-logic -0.6 VCC+0.6 V DC Input Voltage, RX pins: DI[1A/1B/2A/2B] DEI1116 DEI1117 with external 10K ohm series resistors DO160 Sect 22 Lightning Immunity pin injection WF4 & WF5A WF3 VIN-rx VIN-rxe ±40 ±40 ±300 ±600 V Clamp diode current, any pin except RX inputs ±25 mA DC Output Current per pin ±25 mA Storage Temperature Tstg -65 +150 °C Junction Temperature, operating TJmax +145 °C Table 4: AC Electrical Characteristics PARAMETER SYMBOL Data Rate 100kbps Data Rate 12.5kbps MIN MAX MIN MAX UNITS 1MCK Frequency f 1MCK 0.99 1.01 0.99 1.01 MHz 1MCK Duty Cycle CK DC 40 60 40 60 % 1MCK Rise/Fall Time T CRF 10 10 ns Master Reset Pulse Width T MR 200 200 ns Transmitter Data Rate (1MCK = 1MHz) T DR 99 101 12.4 12.6 kbps Receiver Data Rate (1MCK = 1MHz), (DATA = 50% BIT/ 50% NULL TIME) RDR 95 105 8.0 14.5 kbps Functional Description: The DEI1116/1117 supports a number of various options which are selected by data written into the control register. Data is written into the control register from the 16-bit data bus when the /LDCW signal is pulsed to a logic “0”. The twelve control bits control the following functions: 1) Word Length (32 or 25 bits) 2) Transmitter bit 32 (Parity or Data) 3) Wrap around self test. 4) Source Destination code checking of received data. 5) Transmitter parity (even or odd) 6) Transmitter and Receiver data rate (100 or 12.5 kbps) Table 5: Control Register Format BIT SYMBOL BIT SYMBOL D15 (MSB) WLSEL D7 X1 D14 RCVSEL D6 SDENB1 D13 TXSEL D5 /SLFTST D12 PARCK D4 PAREN D11 Y2 D3 NOT USED D10 X2 D2 NOT USED D9 SDENB2 D1 NOT USED D8 Y1 D0 NOT USED

© 2012 Device Engineering Inc. DS-MW-01117-01 Rev B Page 5 of 14 02/09/2012 Table 6: Control Word NAME DATA BIT DESCRIPTION PAREN D4 Transmitter Parity Enable. Enables parity bit insertion into transmitter data bit 32. Parity is always inserted if /DBCEN is open or HI. If /DBCEN is LO, Logic “0” on PAREN inserts data on bit 32, and Logic “1” on PAREN inserts parity on bit 32. /SLFTST1 D5 Self Test Enable. Logic “0” enables a “wrap around” test mode which internally connects the transmitter outputs to both receiver inputs, bypassing the receiver front end. The test data is inverted before going into receiver 2 so that its data is the complement of that received by receiver 1. The transmitter output is active during test mode. SDEN12 D6 S/D Code Check Enable for receiver 1. Logic “1” enables the Source/Destination Decoder for receiver 1. X1, Y12 D7, D8 S/D compare code RX1. If the receiver 1 S/D code check is enabled (SDEN1=1), then incoming receiver data S/D fields will be compared to X1, Y1. If they match, the word will be accepted by receiver 1; if not, it will be ignored. X1 (D7) is compared to serial data bit 9, Y1 (D8) is compared to serial data bit 10. SDEN22 D9 S/D Code Check Enable for receiver 2. Logic “1” enables the Source/Destination Decoder for receiver 2. X2, Y22 D10, D11 S/D compare code RX2. If the receiver 2 S/D code check is enabled (SDEN2=1), then incoming receiver data S/D fields will be compared to X2, Y2. If they match, the word will be accepted by receiver 2; if not, it will be ignored. X2 (D10) is compared to serial data bit 9, Y2 (D11) is compared to serial data bit 10. PARCK D12 Parity Check Enable. Logic “1” inverts the transmitter parity bit for test of parity circuits. Logic “0” selects normal odd parity; logic “1” selects even parity. TXSEL3 D13 Transmitter Data Rate Select. Logic “0” sets the transmitter to the HI data rate. HI rate is equal to the clock rate divided 10. Logic “1” sets the transmitter to the LO data rate. LO rate is equal to the clock rate divided by 80. RCVSEL4 D14 Receiver Data Rate Select. Logic “0” sets both receivers to accept the HI data rate. The nominal HI data rate is the input clock divided by 10. Logic “1” sets both receivers to the LO data rate. The nominal LO data rate is the input clock divided by 80. WLSEL5 D15 Word Length Select. Logic “0” sets the transmitter and receivers to a 32 bit word format. Logic “1” sets them to a 25 bit word format. NOT USED D0-D3 When writing to the control register, the four “not used bits” are “don’t care” bits. These four bits will not be used on the chip. NOTES 1) The test mode should always conclude with ten null’s. This step prevents both receivers from accepting invalid data. 2) SDENn, Xn & Yn should be changed within 20 bit times after /DRn goes low and the bit stream has been read, or within 30 bit times after a master reset has been removed. 3) TXSEL should only be changed during the time that TXR is high or Master Reset is low. 4) RCVSEL should be changed only during a Master Reset pulse. If changed at any other time, then the next bit stream from both Receiver 1 and Receiver 2 should be ignored. 5) When the control word is written the effect of the WLSEL bit will take effect immediately on the first complete ARINC word received or transmitted following the control word write operation.

© 2012 Device Engineering Inc. DS-MW-01117-01 Rev B Page 6 of 14 02/09/2012 Data Format: The ARINC serial data is shuffled and formatted into two 16 bit words (WORD1 and WORD2) used by the bi-directional data bus interface. Figure 3a shows the mapping between the 32 bit ARINC serial data and the two data words. Figure 3b describes the mapping for the 25 bit serial word used when control register bit WLSEL is set to logic “1”. Figure 3a: Mapping of Serial Data to/from Word 1 and Word 2 in 32 bit format. Figure 3b: Mapping of Serial Data to/from Word 1 and Word 2 in 25 bit format. 29 262728 123432 31 30 22 19202125 24 23 15 12131418 17 16 8 56711 10 9 123415 121314 08 56711 10 9 123415 121314 08 56711 10 9 PARITY SSM SIGN DATA MSB LSB S/D or DATA LABEL LSB MSB SIGN DATA MSB DATA LSB S/D or DATA SSM PARITY LABEL LSB MSB Word 2 Format Word 1 Format BIT FUNCTION BIT FUNCTION

32 Bit ARINC Serial Data Format (Bit 1 is Transmitted First)

123422 19202125 24 23 15 12131418 17 16 8 56711 10 9 123415 121314 08 56711 10 9 123415 121314 08 56711 10 9 PARITY DATA MSB LSB LABEL LSB MSB DATA MSB NOT USED PARITY LABEL LSB MSB Word 2 Format Word 1 Format BIT FUNCTION BIT FUNCTION

25 Bit ARINC Serial Data Format (Bit 1 is Transmitted First)

© 2012 Device Engineering Inc. DS-MW-01117-01 Rev B Page 7 of 14 02/09/2012 Receiver Operation: Since the receivers function identically, only one will be discussed in detail. The recei ver consists of the following circuits. Line Receiver The front end of the Line Receiver functions as a voltage level translator. It transforms the ±10 volt differential ARINC data signals into 5 Volt internal logi c levels. The line receivers are protected against shorts to ±40 Volts and provide common mode voltage rejection. The DEI1116 and 1117 differ in their A429 RX input characteristics. The DEI1116 interfaces directly to the A429 bus signals. DEI1117 version bypasses some of the on-chip resistance and thus operates with 10K ohm series resistors. The series resistors support implementation of lightning transient protection. The 1117 withstands Level 3 pin injection levels with only the resistors. Higher levels are achieved with a TVS shunt placed between the series resistor and 1117 DIxx pin. The outputs of the Line Receiver are one of two inputs to the Self-Test Data Selector. The other input to the Data Selector is the self-test signal from the transmitter section. The self- test signals are inverted goi ng into Receiver 2. The data selector is controled by Control Register bit D5 (/SLFTST). Self-Test Data Selector SLFTST DO(A) DI1(A) DI1(B) Comparator To Receive Decoder Figure 4: Line Receiver Block Diagram Incoming Data The incoming data (either self test or ARINC) is triple sampled by the word gap timer to generate a data clock. The start of each bit is first detected and then verified two receive- clock cycles later. The receiv e clock is 1MHz for HI speed and 125 KHz for LO speed operation and is generated by the Receiver/Transmitter timing circu it. The receive clock is ten times the normal data rate to ensure no data ambiguity. Parity Control The parity of the incoming messa ge is checked when either word of the receiver is read. Logic “0” indicates the received word has an odd number of 1’s (no error). Logic “1” indicates the received word has an even number of 1’s (error condition). If the data format has data in bit 32 instead of parity, the user software must calculate the value of the 32nd bit. If Word 1 and Word 2 together have an even number of 1’s, then data bit 32 is a logic “1”. Otherwise, it is a logic “0”.

© 2012 Device Engineering Inc. DS-MW-01117-01 Rev B Page 8 of 14 02/09/2012 S/D Decoder The Source/Destination decoder compares the user set code (X and Y) with bits 9 and 10 of the data word. The decoder can be enabled and disabled by the SDENn bits of the Control Register. If the two codes are matched, a signal is generated to latch in the received data into the receiver buffer. Otherwise the data word is ignored and not latched into the receive buffer. If the data is latched, the data ready flag (/DRn) is set to indicate to the user that a valid data word is ready to be read. Data Clock The derived data clock then shifts the data down a 32 bit long Data Shift Register. The data word length is selectable for either 25 or 32 bits long by Control Register Bit WLSEL. As soon as the data word is completely received, an internal signal is generated by the word gap timer circuit to enable loading data into the 32 bit receive buffer latch. Data Access To access the receiver data, the user sets the receiver data select input (SEL) to a logic “0 ” and pulses the output enable (/OEn) line with a logic “0”. This causes Data Word 1 to be placed on the 16 bit data bus. To read Word 2, the user sets the data select input (SEL) to a logic “1” and pulses the output enable (/OEn) low to place Word 2 on the data bus. When both Word 1 and Word 2 have been read, DRn will be reset. This reset is triggered by the leading edge of the final /OEn pulse. If a new data word is received before the previous data has been read from the receiver bu ffer (as indicated by the /DRn signal flip-flop), the receive buff er will not be over written by the new data. The new data will remain in the shift register until either the /DRn signal is reset and it can be written into the receive buffer or it is overw ritten by the next incoming data word. Data in the shift register will be overwritten by new incoming data, while data that has been latched into the receive buffer can not be overwritten. Data Error Conditions If the receiver input data word string is broken before the entire data word is received, th e receiver will reset and ignore the partially received data word. If the receiver input data word st ring is not properly framed with at least 1 null bit before the word and 1 null bit after the word, the receiver will reset and ignore the improperly framed data word. Transmitter Operation: The transmitter section consists of an 8 word by 32 bit FIFO, parity generator, transmitter word gap timer, and a TTL output circuit. FIFO Buffer The 8x32 buffer memory allows the user to load up to 8 words into the transmitter, enable it, and then ignore it while the transmitter ships out the data without further attention. Data is loaded into the buffer by pulsing /LD1 to load the first 16 bits (WORD 1) from the data bus, and pulsing /LD2 to load WORD 2. /LD1 must always precede /LD2. The transmitter must always be disabled while loading the buffer (ENTX = logic "0"). If the buffer is full and new data is pulsed with /LD1 and /LD2, the last 32 bit word in the buffer will be overwritten. Data will remain in the buffer until ENTX is pulsed to a logic “1”, which will activate the FIFO clock and data is shifted out serially to the transmitter driver. The buffer data is transmitted until the last word in the buffer is shifted out. At this time a transmitter ready signal (TXR) is set to a logic “1” indicating that the buffer is empty and ready to receive up to eight more data words. Writing into the buffer memory is disabled when ENTX is set to logic “1”. Transmitter Ready Signal (TXR) The transmitter ready flag (TXR) is set to logic “0” with the first occurrence of an /LD2 pulse to indicate that the buffer is not empty. Output Register The output register is designed such that it can shift out a word of 25 bits or 32 bits. The length is controlled by control register bit "WLSEL". Parity Generator The parity generator calculates either odd or even parity as specified by control register bit "PARCK". Odd parity is normally used; even parity is available to test the receiver parity check circuit. Odd parity means that there is an odd number of 1's in the 25 or 32 bit serial word. Bit 8 of word one is replaced with a parity bit if parity is selected by the control register bit "PAREN" and the /DBCEN pin. Otherwise, bit 8 is passed through as data. Transmitter Output The transmitter driver outputs three TTL compatible signals: 1) DO(A), 2) DO(B), and 3) TXCLK. DO(A) and DO(B) are the transmitter data in two rail, return-to-zero format. DO(A) indicates a logic "1" data bit by going to a "1" for the 1st half of a bit time, then returning to "0" for the 2nd half; DO(B) remains at "0" for the whole bit time. In the same fashion, DO(B) indicates a logic "0" data bit by pulsing HI while DO(A) remains LO. A null bit is indicated when both signals remain LO. It is illegal for both signals to be logic "1". The TXCLK is a free running clock signal of 50% duty cycle and in phase with transmitter data. The clock will always be logic "1" during the first half of a bit time.

© 2012 Device Engineering Inc. DS-MW-01117-01 Rev B Page 13 of 14 02/09/2012 Table 8: DEI1116/DEI1117 Ordering Information DEI PART NUMBER (2) MARKING (1) REQUIRES EXT DIxx 10K RES PACKAGE TEMP RANGE PROCESSING (3) DEI1116-QES-G DEI1116-QES e3 No 44 PQFP G -55 / +85 °C PLASTIC STANDARD DEI1116-QMS-G DEI1116-QMS e3 No 44 PQFP G -55 / +125 °C PLASTIC STANDARD DEI1116-PMS-G DEI1116-PMS e3 No 44 PLCC G -55 / +125 °C PLASTIC STANDARD DEI1116-PES-G DEI1116-PES e3 No 44 PLCC G -55 / +85 °C PLASTIC STANDARD DEI1117-QES-G DEI1117-QES e3 Yes 44 PQFP G -55 / +85 °C PLASTIC STANDARD DEI1117-QMS-G DEI1117-QMS e3 Yes 44 PQFP G -55 / +125 °C PLASTIC STANDARD DEI1117-PMS-G DEI1117-PMS e3 Yes 44 PLCC G -55 / +125 °C PLASTIC STANDARD DEI1117-PES-G DEI1117-PES e3 Yes 44 PLCC G -55 / +85 °C PLASTIC STANDARD Notes: 1. All packages marked with Lot Code and Date Code. “e3” or “e4” after Date Code denotes Pb Free category. 2. Suffix legend: -XYZ-G: X = package code, Y = temperature range code, Z = process flow code, -G = Green (Pb Free) 3. Contact factory for screening method of other packages Table 9: Screening Process PLASTIC STANDARD -xxS Other Packages WAFER PROBE Room Temp THERMAL CYCLE -MIL-STD-883B M1010.4 Condition B NO GROSS & FINE LEAK NO BURN IN -MIL-STD-883B M1015 Condition A NO ELECTRICAL TEST ROOM TEMPERATURE 100% ELECTRICAL TEST HIGH TEMPERATURE 100% +125°C (-xMx) 100% +85°C (-xEx) ELECTRICAL TEST LOW TEMPERATURE 0.65% AOQL @-55°C Note: AOQL samples use a Zero Acceptance Number sampling plan per AS9100 Table 10: Package Characteristics PACKAGE TYPE PACKAGE REF THERMAL RESIST θJC / θJA (ºC/W) JEDEC MOISTURE SENSITIVITY LEVEL & PEAK BODY TEMP LEAD FINISH MATERIAL / JEDEC Pb-Free CODE Pb Free DESIGNATION JEDEC MO 44L PLASTIC QUAD FLAT PACK, GREEN 44 PQFP G 21/65 MSL 3 260ºC Matte Sn e3 RoHS Compliant M0-112-AA-1 44L PLASTIC CHIP CARRIER, GREEN 44 PLCC G 21/46 MSL 3 245ºC Matte Sn e3 RoHS Compliant MS-018-AC