DEI1282

DEI1282 DEIAZ | Alldatasheet

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Technical content

©2018 Device Engineering Inc. 1 of 17 DS-MW-01282-01 Rev. L 05/18/2018

FEATURES

• Eight discrete inputs o Individually configurable as either GND/OPEN or 28V/OPEN(GND) inputs. o Input threshold and hysteresis per AirBus ABD0100H specification. § GND/OPEN mode: 4.5V/10.5V threshold, 3V hysteresis § 28V/OPEN mode: 6V/12V threshold, 3V hysteresis o 1mA input current to prevent dry relay contacts. o Internal isolation diodes o Inputs protected from Lightning Induced Transients per DO160F, Section 22, Cat A3 and B3 o 1284 version supports higher lightning levels and input filtering via use of off-chip input resistors o Withstands inadvertent application of 115VAC/400Hz power o Built-in Test (BIT) to test internal circuits including input comparator
• Serial I/O interface to read data register and write configuration register o Direct interface to Serial Peripheral Interface (SPI) port. o TTL/CMOS compatible inputs and Tristate output o 8.6MHz Max Data Rate o Serial input to expand Shift Register
• Logic Supply Voltage (VCC): 3.3V +/-5%
• Analog Supply Voltage (VDD): 12V to 16.5V
• 16L SOIC EP package PIN ASSIGNMENTS DEI 1282 1284 1DIN1 DIN2 DIN3 DIN4 VDD GND VCC SEL DIN5 DIN6 DIN7 DIN8 SDI /CS SDO SCLK Figure 1 DEI1282, 1284 Pin Assignment (16 Lead SOIC)

385 East Alamo Drive

Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com DEI1282, 1284 8CH BIT PROGRAMMABLE GND/OPN & 28V/OPN DISCRETE INTERFACE IC Device Engineering Incorporated

©2018 Device Engineering Inc. 2 of 17 DS-MW-01282-01 Rev. L 05/18/2018 FUNCTIONAL DESCRIPTION DEI1282 and DEI1284 are eight-channel discrete-to-digital interface ICs implemented in a High Voltage Dielectric Isolated technology. They sense eight discrete signals of the type commonly found in avionic systems and convert them to serial logic data. Each input can be individually configured as either GND/OPEN or 28V/OPEN format input via a serial data input. The discrete data is read from the device via an eight-bit serial shift register with 3-state output. This serial interface is compatible with the industry standard Serial Peripheral Interface (SPI) bus. The discrete inputs are implemented with a high voltage technology to provide immunity to lightning induced transients. The DEI1282 tolerates DO160F Level 3 (600V) stress directly to the input pins without the need for additional protection components. The DEI1284 version operates with 3K Ohm off-chip series resistors on the inputs. These are used in combination with Transient Voltage Suppressor (TVS) devices to achieve Level 4 (1500V) and Level 5 (3200V) immunity. The resistors act to limit surge current, thus allowing small TVS devices. The resistors are also used to implement low pass filtering by adding capacitors on the inputs. The filtering provides noise rejection and anti-aliasing of the sampled signal. The on-chip Built-in Test (BIT) feature provides a Test Mode which provides a means to inject a test signal into each input comparator without interfering with the discrete input signals. The test coverage includes each DIN comparator as well as the digital logic and IO. Table 1 Pin Descriptions PINS NAME DESCRIPTION 1-8 DIN[1:8] Discrete Inputs. Eight discrete signals which can be individually configured as either GND/OPEN or 28V/OPEN format inputs. 9 SDO Logic Output. Serial Data Output. This pin is the output from MSB (Bit 8) of the selected shift register (Data/Configuration). It is clocked by the rising edge of SCLK. This is a 3-state output enabled by /CS. 10 SCLK Logic Input. Serial Shift Clock. A low-to-high transition on this input shifts data on the serial data input into Bit 0 of the selected shift register. The selected shift register is shifted from Bit 1 to Bit 8. Bit 8 of the selected shift register is driven on SDO. 11 /CS Logic Input. Chip Select. A low level on this input enables the SDO 3- state output and the selected shift register. A high level on this input forces SDO to the high impedance state and disables the shift registers so SCLK transitions have no effect. When the Data Register is selected, a high-to-low transition causes the Discrete Input data to be loaded into the Data Register. When the Configuration Register is selected, a low-to- high transition causes the Serial Configuration Register data to be loaded into the parallel configuration outputs. 12 SDI Logic Input. Serial Data Input. Data on this input is shifted into the LSB (Bit 1) of the selected shift register on the rising edge of the SCLK when /CS input is low. 13 SEL Logic Input. Selects between the Data Register and Configuration Register. H = DATA, L = CONF. 14 VCC Logic Supply Voltage. 3.3V+/-5%

15 GND Logic/Signal Ground

16 VDD Analog Supply Voltage. 12V to 16.5V

©2018 Device Engineering Inc. 4 of 17 DS-MW-01282-01 Rev. L 05/18/2018 Table 2 Truth Table Serial Interface Operation SEL /CS SCLK SDI DIN[1:8] SDO Description X H X X X HI Z Not Selected H ↓ L X Valid DIN[8] DR[1:8]← DIN[1:8] H L ↑ DR[1] X DR[8] DR[n+1] ← DR[n], DR[1] ← SDI L L ↑ CR[1] X CR[8] CR[n+1] ← CR[n], CR[1] ← SDI L ↑ L X X HI Z CL[1:8]← CR[1:8] Legend: DR = Data Register CR = Configuration Register CL = Configuration Latch X = Don’t Care DIN [1:8] Discrete AFE The Discrete Input Analog Front End circuit function is represented in Figure 3. Each DINn signal is conditioned by the resistor / diode network and presented to a comparator with hysteresis. When the input is configured for GND/OPEN operation, the pull-up resistor and diode are enabled and comparator threshold voltage is selected. When the input is configured for 28V/OPEN operation, the pull-down resistor is enabled and the comparator is appropriately configured. Prior to configuration (after power up) and during BIT, neither pull-up nor pull-down is enabled and the AFE presents a high impedance (Hi-Z). Some notable features are:

• Input voltage levels and hysteresis: o 28V/OPEN
• High level input voltage: 12.0 to 49 V
• Low level input voltage: -4 to 6.0 V
• Hysteresis: > 3 V o GND/OPEN
• High level input voltage: 10.5 to 49 V
• Low level input voltage: -4 to 4.5 V
• Hysteresis: > 3 V
• The input current is ~ 1mA. This current will prevent a “dry” relay contact.
• Input noise immunity is maximized with a combination of voltage hysteresis and use of a slow input voltage comparator.
• The inputs can withstand continuous input voltages of 49V, lightning transient voltages per DO160 Level 3 pin injection tests, and survive inadvertent application of 115VAC/400Hz. Data Register The 8-bit Data Register is a “parallel-input, serial-output” register that samples the input channels and reads-out the data to the Serial Data Output. The register is read via the SDO output as described in Figure 4 and Figure 5. A low DIN input level results in a Logic 0, and a high input level results in a Logic 1. Configuration Register The 9-bit Configuration Register (CR) is a “serial-input, parallel-output with data latch” register that individually configures each AFE input as either GND/OPEN or 28V/OPEN format. (CR[n]: 0 sets DIN[n] to 28V/OPEN mode (pull-down); CR[n]: 1 sets DIN[n] to GND/OPEN mode (pull-up). The register is reset to 0’s at Power Up and the AFE inputs are forced into high impedance mode until the CR is programmed (see Power Up Initialization). Bit 9 is used to enable or disable Built-in Test (see BIT Operation). The register is programmed via the serial data input as described in Figures 6– 8. Serial Interface The DEI1282/1284 incorporates a serial IO interface for programming the Discrete Input configuration and for reading the Discrete Input status. Refer to Figure 2. The interface is SPI Mode 0 compatible and consists of /CS, SEL, SCLK, SDO, and SDI signals. Figures 4 – 5 depict the Data Read sequence and Configuration Write sequence for both a single device and dual “daisy chained” devices; refer to Figure 16 for connection details.

©2018 Device Engineering Inc. 6 of 17 DS-MW-01282-01 Rev. L 05/18/2018 /CS SCLK SDO SDI X DIN1DIN2DIN3DIN4DIN5DIN6DIN7DIN8 SI1 SI2SI3SI4SI5SI6SI7SI8 X X SEL SDI data shifted to SDO after 8 bit delay X VALID X SI 8 SI 7 SI 6 SI 5 SI 4 SI 3 SI 2 SI 1 X Figure 5 Read Data Register, 16 Bit Daisy Chain (See Figure 18) Figure 6 Write Configuration Register (9-bit cycle) /CS SCLK SDO SDI PCD PCD PCD PCD PCD PCD PCD PCD

9 XXXXXXX NCD

XDIN[1:8] SEL X X X X X X NCD 9XX NCD NCD NCD NCD NCD NCD NCD 1 X DCDn = Daisy Chain Data Bits NCDn = New Configuration Data Bits PCDn = Present Configuration Bits PDO[1:8] Internal Config Latch Present Configuration New Configuration NCD PCD X NCD 9 latched into Config S-Reg at SCLK Figure 7 Write Configuration Register (16-bit cycle) /CS SCLK SDO SDI XX PCD PCD PCD PCD PCD PCD PCD PCD DIN[1:8] SEL X NCD NCD NCD NCD NCD NCD NCD NCD 9X X PCD PDO[1:9] Internal Config Latch Present Configuration New Configuration NCDn = New Configuration Data Bits PCDn = Present Configuration Data Bits NCD NCD

©2018 Device Engineering Inc. 7 of 17 DS-MW-01282-01 Rev. L 05/18/2018 Figure 8 Write Configuration Register, 18 bit Daisy Chain (See Figure 18) /CS SCLK SDO SDI XX PCD PCD PCD PCD PCD PCD PCD PCD DCD DCD DCD DCD DCD DCD DCD DCD XDIN[1:8] SEL DCD DCD DCD DCD DCD DCD DCD DCD 9X NCD NCD NCD NCD NCD NCD NCD 3 X DCDn= Daisy Chain Data Bits NCDn= New Configuration Data Bits PCDn= Present Configuration Data Bits PDO[1:8] Internal Config Latch Present Configuration New DCD PCD NCD NCD DCD NCD Config

©2018 Device Engineering Inc. 9 of 17 DS-MW-01282-01 Rev. L 05/18/2018 ELECTRICAL DESCRIPTION Table 3 Absolute Maximum Ratings PARAMETER MIN MAX UNITS VCC Supply Voltage -0.3 +5.0 V VDD Supply Voltage -0.3 18 V Operating Temperature Exposed pad soldered to heat sink -55 +125 °C Storage Temperature Plastic Package -55 +150 °C Input Voltage DIN[1:8] Continuous (3) DO160F, Waveform 3, Level 3 (3) DO160F, Waveform 4 and 5, Level 3 (3) DO160F, Abnormal Surge Voltage, 100ms (3) Logic Inputs DOUT -10 -600 -300 -1.5 -0.5 +49 +600 +300 VCC + 1.5 VCC + 0.5 Vdc Vpk Vpk Vpk V V Power Dissipation @ 125°C, Steady state 16L SOIC 0.63 W Junction Temperature: Tjmax, Plastic Packages 150 °C ESD per JEDEC A114-A Human Body Model Logic and Supply pins DIN pins 2000 1000 V V Peak Body Temperature (10 sec duration) 260 °C Notes: 1. Stresses above absolute maximum ratings may cause permanent damage to the device. 2. Voltages referenced to Ground. 3. Stress applied to external 3K Ohm series resistor in series with DINn pin. Applies to DEI1284 only. Table 4 Recommended Operating Conditions PARAMETER SYMBOL CONDITIONS Supply Voltage VCC VDD 3.3V±5% 12V to 16.5V Logic Inputs and Outputs 0 to VCC Discrete Inputs DIN[1:8] 0 to 49V Operating Temperature Plastic Ta -55ºC to 125ºC

©2018 Device Engineering Inc. 10 of 17 DS-MW-01282-01 Rev. L 05/18/2018 Table 5 DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS (1) MIN LIMIT NOM MAX LIMIT UNIT Logic Inputs/Outputs VIH HI level input voltage VCC = 3.3V 2.0 V VIL LO level input voltage VCC = 3.3V 0.8 V VIhst Input hysteresis voltage, SCLK input (3) 50 mV VOH HI level output voltage IOUT = -20uA VCC – 0.1 V IOUT = -4mA, VCC = 3V 2.4 V VOL LO level output voltage IOUT = 20uA 0.1 V IOUT = 4mA, VCC = 3V 0.4 V IIN Input leakage, except SEL VIN = VCC or GND -10 10 uA IIN-SEL Input leakage, SEL VIN = VCC VIN = GND -10 -50 uA IOZ 3-state leakage current Output in Hi Impedance state. VOUT = VIHmin, VILmax -10 10 uA Discrete Inputs, Configured as Ground/Open (internal pull-up) (4) VIH HI level input voltage 10.5 49 V RIH HI level DIN-to-GND resistance Resistor from DIN to GND to guarantee HI input condition. 50K W IIH HI level input current VIN = 28V, VDD = 15V VIN = 49V, VDD = 15V 100 250 uA uA VIL LO level input voltage -4.0 4.5 V RIL LO level DIN-to-GND resistance Resistor from DIN to GND to guarantee LO input condition. 500 W IIL LO level input current VIN = 0V, VDD = 15V -0.8 -1.0 -1.8 mA VIhst Input hysteresis voltage 3 V Discrete Inputs, Configured as 28V/Open (internal pull-down) (4) VIH HI level input voltage 12.0 49 V IIH HI level input current VIN = 28V, VDD = 15V 0.6 0.8 1.35 mA VIL LO level input voltage -4 6.0 V IIL LO level input current VIN = 1V, VDD = 15V 50 uA VIhst Input hysteresis voltage 3 V Power Supply ICC Max quiescent logic supply current VIN(logic) = VCC or GND VIN[1:8] = open 1.8 3 mA IDD Max quiescent analog supply current VIN(logic) = VCC or GND Ground/Open Mode, VIN[1:8] = Open VIN[1:8] = GND mA Notes: 2. Current flowing into device is ‘+’. Current flowing out of device is ‘-‘. Voltages are referenced to Ground. 3. Guaranteed by design. Not production tested. 4. With 3K Ohm, 2% resistor in series with DIN input pin. Applies to DEI1284 only.

©2018 Device Engineering Inc. 11 of 17 DS-MW-01282-01 Rev. L 05/18/2018 Table 6 AC Electrical Characteristics SYMBOL PARAMETER CONDITIONS (5,6,7) MIN LIMIT MAX LIMIT UNIT fMAX SCLK frequency. 50% duty cycle 0.1 8.6 MHz tW SCLK pulse width. 50 ns tsu1 Setup time, SCLK to /CS↓. 30 ns th1 Hold time, /CS↓ to SCLK. 25 ns tsu2 Setup time, DIN valid to /CS↓. 15 us th2 Hold time, /CS↓ to DIN not valid. 500 ns tsu3 Setup time, SDIN valid to SCLK↑. 25 ns th3 Hold time, SCLK↑ to SDIN not valid. 25 ns tsu4 Setup time, SEL valid to /CS↓. 30 ns th4 Hold time, SEL valid to /CS↑. 25 ns tp1 Propagation delay, /CS↓ to DOUT valid. (1) 105 ns tp2 Propagation delay, SCLK↑ to DOUT valid. (1) 90 ns tp3 Propagation delay, /CS↑ to DOUT HI-Z. (1) (2) (3) 80 ns tp4 Delay time between /CS active. 20 ns th5 Hold time, SCLK↑ to DOUT (1) 10 ns Cin Maximum logic input pin Capacitance. 10 pF Cout Maximum SDO pin capacitance, output in HI-Z state. 15 pF Notes: 1. SDO loaded with 50pF to GND. 2. SDO loaded with 1KW to GND for Hi output, 1KW to VCC for Low output. 3. Timing measured at 25%VCC for “0” to Hi-Z, 75%VCC for “1” to Hi-Z. 4. Sample tested on lot basis. 5. Guaranteed by design. Not production tested. 6. Ta = -55ºC to 85 or 125ºC, VCC = 3V, VDD = 15V, VIL = 0V, VIH = VCC unless otherwise noted. 7. Measurements made at 50%VCC. /CS SCLK SDO SDI DIN[1:8] tsu1 th1 tW 1/fmax tsu2 th2 X X valid tsu3 th3 X X D/C0 D/C1 tp1 tp2 tp3 tp4 valid SEL tsu4 th4 th5 Figure 12 Switching Waveforms

©2018 Device Engineering Inc. 14 of 17 DS-MW-01282-01 Rev. L 05/18/2018 Daisy Chain Connection Multiple DEI1282/1284 ICs can be connected as daisy chain. Figure 16 shows three devices connected in SPI series mode. The critical timing is Tsu3 (see Fig 12), minimum SDIN valid to SCLK setup time. Figure 18 Example connection of three DEI128X’s connected as daisy chain

©2018 Device Engineering Inc. 15 of 17 DS-MW-01282-01 Rev. L 05/18/2018 Package Power Dissipation The DEI1282/84 power dissipation varies with channel configuration and operating conditions. Figure 18 shows the device package power dissipation for various conditions. This includes the contributions from Supply currents and Input currents. The four curves are as follows: Table 7 Legend for Power Dissipation Curves CURVE ID SUPPLY VOLTAGE, TEMPERATURE, IC VARIATION +28V/OPEN-Nom 3.3V, 12V / 27ºC / typical IC parameters +28V/OPEN-Wst 3.3V, 16.5V / 125ºC / Worst case IC parameters GND/OPEN-Nom 3.3V, 12V / 27ºC / typical IC parameters GND/OPEN-Wst 3.3V, 16.5V / 125ºC / Worst case IC parameters DEI1282 Power Dissipation Graph 100 200 300 400 500 600 700 800 0 1 2 3 4 5 6 7 8 Number Channels Active Power Dissipation (mW) +28V/OPN-Nom +28V/OPN-Wst GND/OPN-Nom GND/OPN-Wst Notes: 1. The active channels are forced to Ground for GND/OPEN type and forced to 28V for 28V/OPEN type. 2. The DEI1284 package power dissipation is lower than the DEI1282 because a portion of the power is shifted to the external resistors. The DEI1284 incremental Pd is ~20% lower for GND/OPEN and ~15% lower for 28V/OPEN. Figure 19 Power Dissipation for Various Conditions

©2018 Device Engineering Inc. 16 of 17 DS-MW-01282-01 Rev. L 05/18/2018 PACKAGE DESCRIPTION - 16L Narrow Body, Exposed Pad SOIC Table 8 Package Information Package Type Package Ref Θjc/ Θja (°C/W) JEDEC Moisture Sensitivity Level Lead Finish / JEDEC Pb-Free Code Pb Free Designation JEDEC MO 16L SOIC NB SnPb 16 EP SOICN ~10 / ~40 MSL 1 / 260°C 85/15 SnPb plate na Not Pb-free MS- 012-AC 16L SOIC NB Matte Sn RoHS 16 EP SOICN G ~10 / ~40 MSL 1 / 260°C 100% Matte Sn e3 RoHS MS- 012-AC Notes: 1. Mounted on 4 layer PCB with exposed pad soldered to PCB land with thermal VIAs to internal GND plane The PCB design and layout is a significant factor in determining thermal resistance ( Θja) of the IC package . Use maximum trace width on all power and signal connections at the IC; these traces serve as heat spreaders which improve heat flow from the IC leads. The exposed pad on the bottom of the SOIC package must be soldered to a heat-spreader land pattern on the PCB. The IC exposed pad is electrically isolated, but must be connected to some potential on the PCB, typically Ground or Vcc. Maximize the PCB land size by extending it beyond the IC outline if possible. A grid of thermal VIAs, which drop down and connect to the buried copper plane(s), should be placed under the heat-spreader land. A typical VIA grid is 12mil plated holes on a 50mil pitch. Use as many VIAs as space allows. VIAs should be plugged to prevent voids being formed between the exposed pad and PCB heat-spreader land due to solder escaping by the capillary effect. Wicking can be avoided by tenting the VIAs with solder mask.

©2018 Device Engineering Inc. 17 of 17 DS-MW-01282-01 Rev. L 05/18/2018 Note: The bottom thermal contact (exposed pad) is electrically isolated. Figure 20 16 Lead Narrow Body EP SOIC Outline

ORDERING INFORMATION

Table 9 Ordering Information Part Number Marking Package (1) Requires 3KΩ Resistor on DIN Temperature DEI1282-SES DEI1282-SES 16 EP SOIC No -55ºC / 85ºC DEI1282-SMS DEI1282-SMS 16 EP SOIC No -55ºC / 125ºC DEI1282-SES-G DEI1282-SES-G / e3 16 EP SOIC G No -55ºC / 85ºC DEI1282-SMS-G DEI1282-SMS-G / e3 16 EP SOIC G No -55ºC / 125ºC DEI1284-SES-G DEI1284-SES-G / e3 16 EP SOIC G Yes -55ºC / 85ºC DEI1284-SMS-G DEI1284-SMS-G / e3 16 EP SOIC G Yes -55ºC / 125ºC Notes: 1. Refer to Table 8 DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose.