DEI1167-TMS-G

DEI1167 DEIAZ | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 8

Technical content

©2015 Device Engineering Inc Page 1 of 8 DS-MW-01167-01 Rev B 02/17/2015

FEATURES

x Eight GND/OPEN discrete inputs o Meet electrical requirements for ABD0100 GND/OPEN discrete input. o Hysteresis provides noise immunity. o Internal pull up resistor o Internal isolation diode o Inputs protected from Lightning Induced Transients per DO160D, Section 22, Cat A3 and B3. x 3.3V or 5V TTL/CMOS compatible digital IO o 8 tri-state outputs o /CS & /OE control inputs x Logic Supply: 3.3V or 5V x Analog Supply: 12V x 24L TSSOP package PIN ASSIGNMENTS Figure 1 DEI1167 Pin Assignment (24 Lead TSSOP) Table 1 Pin Descriptions Pins Name Description 8-1 DIN[8:1] Discrete Inputs. Eight Ground/Open format discrete signals. These have an internal pull- up to VDD. The threshold and hysteresis characteristics are determined by the applied VDD voltage. 9-10 NC Not Connected. 11 /CS Chip Select Logic Input. Low input selects the device. Internal pull-up to VCC. 12 /OE Output Enable Logic Input. Low input when /CS is low will enable the tri-state outputs. Internal pull-up to VCC. 13 VDD Analog Supply. +12V 14 GND Analog Ground. 19 VCC Logic Supply. +3.3V or +5V 22 GND Logic Ground. 15-18,20,21,23,24 DO[8:1] Logic Outputs. Eight tri-state data outputs. 385 E. Alamo Dr. Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com DEI1167 OCTAL GND/OPEN INPUT, PARALLEL OUTPUT INTERFACE IC Device Engineering Incorporated

1 DIN1

20 DIN5

/CS /OE DO7 DO8 VDD GND DEI1167 17 8 15 10 14 11 13 12

©2015 Device Engineering Inc Page 2 of 8 DS-MW-01167-01 Rev B 02/17/2015 FUNCTIONAL DESCRIPTION The DEI1167 is an eight-channel parallel-output discrete-to-digital interface BICMOS device. It senses eight Ground/Open discrete signals of the type commonly found in avionic systems. The data is read from the device via a parallel 3-state output. 12K 12K 12K 12K 12K 12K DO1 DO2 DO3 DO4 DO5 DO6 DI N1 V DD CE OE VCC 12K DO7 DO8- GND DI N2 DI N3 DI N4 DI N5 DI N6 DI N7 DI N8 12K THRESHO LD AND HYSTERESIS THRESHOLD AND HYSTERESI S THRESHOLD AND HYSTERESI S THRESHOLD AND HYSTERESI S THRESHOLD AND HYSTERESI S THRESHOLD AND HYSTERESI S THRESHOLD AND HYSTERESI S THRESHOLD AND HYSTERESI S Figure 2 DEI1167 Function Diagram Table 2 Truth Table /CE /OE DIN[8:1] DO[8:1] L L Open L L L Ground H H X X High Z X H X High Z

©2015 Device Engineering Inc Page 5 of 8 DS-MW-01167-01 Rev B 02/17/2015 ELECTRICAL DESCRIPTION Table 3 Absolute Maximum Ratings PARAMETER MIN MAX UNITS Vcc Supply Voltage -0.3 +7.0 V Vdd Supply Voltage -0.3 20 V Operating Temperature Plastic Package -55 +125 Storage Temperature Plastic Package -55 +150 Input Voltage DIN[8:1] Continuous DO160D, Waveform 3, Level 3 DO160D, Waveform 4 and 5, Level 3 Logic Inputs DO[8:1] -600 -300 -1.5 -0.5 +40 +600 +300 VCC + 1.5 VCC + 0.5 V Power Dissipation @ 85 °C: (> 10 Sec) 24L TSSOP 0.8 W Junction Temperature: Tjmax, Plastic Packages 145 ESD per JEDEC A114-A Human Body Model Logic and Supply pins DIN pins 2000 1000 V Peak Body Soldering Temperature (10 sec duration) 260 °C Notes: 1. Stresses above absolute maximum ratings may cause permanent damage to the device. 2. Voltages referenced to Ground Table 4 Recommended Operating Conditions PARAMETER SYMBOL CONDITIONS Supply Voltage VCC VDD 5.0V±10%, 3.3V±10% 12V±10% Logic Inputs /CS, /OE 0 to VCC Discrete Inputs DIN[8:1] 0 to 40V Operating Temperature -TES -TMS -55 to +85 ºC -55 to +125 ºC

©2015 Device Engineering Inc Page 6 of 8 DS-MW-01167-01 Rev B 02/17/2015 Table 5 DC Electrical Characteristics LIMITS Symbol Parameter Test Conditions VCC (V) MIN MAX Unit LOGIC INPUTS AND OUTPUTS VIH High level input voltage 3.6 5.5 2.0 V VIL Low level input voltage 3.0 4.5 0.8 V IOH = -20uA 3.0 4.5 VCC –

0.1 V VOH High level output voltage

IOH = -4.5mA 4.5 3.0 V IOL = 20uA 3.0 4.5

0.1 V VOL Low level output voltage

IOL = 4.5mA 4.5 0.40 V IOZ 3-state leakage current Output in Hi Impedance state. Vout = 0V and 5V 5.5 -10 +10 uA IIIL Low level input current VIN = 0V 5.5 -300 -50 uA DISCRETE INPUTS VDD = +12V VIH High level input voltage 3.0 to 5.5 7.5 V RIH High level Din-to-GND resistance Resistor from Din to GND to guarantee HI input condition 3.0 to 5.5 50K Ohm VIL Low level input voltage 3.0 to 5.5 3.5 V RIL Low level Din-to-GND resistance Resistor from Din to GND to guarantee LO input condition 3.0 to 5.5 500 Ohm VIhst Input hysteresis voltage 3.0 to 5.5 1.3 V IIH High level input current Vin =7.5V 3.0 to 5.5 -420 -190 uA IIL Low level input current Vin = 0V 3.0 to 5.5 -1.2 -0.6 mA SUPPLY VOLTAGES VDD = +12V ICC Quiescent logic supply current Vin(logic) = Vcc or GND VIN[8:1] = open 5.5 800 uA IDD Quiescent analog supply current Vin(logic) = Vcc or GND DIN[8:1] = Open DIN[8:1] = GND 5.5 5.5 mA Notes: 1. Current flowing into DUT is positive. Current flowing out of DUT is negative. Voltages are referenced to GND.

©2015 Device Engineering Inc Page 7 of 8 DS-MW-01167-01 Rev B 02/17/2015 Table 6 AC Electrical Characteristics Limits Symbol Parameter VCC (V) -55 to 85ÛC -55 to 125ÛC Unit tZLmax tZHmax Maximum propagation delay, /CSĻ and /OEĻ to DO. (1) (3) 3.0 4.5 5.5 166 183 ns tHZmax tLZmax Maximum propagation delay, /CSĹ or / OEĹ to DO HI-Z. from D0 Low or high. (1) (2) (3) 3.0 4.5 5.5 166 118 108 183 130 120 ns tHLmin tLHmin Minimum data propagation delay, Din to DO (4) (5) 5.0 0.4 0.4 us tHlmax tLHmax Maximum data propagation delay, Din to DO (4) (5) 5.0 420 630 us Cin-max Maximum logic input Capacitance. (6) 10 10 pF Cout-max Maximum DO pin capacitance, output in HI-Z state. (6) 15 15 pF Notes: 1. DO is loaded with 50pF to GND. 2. DO is loaded with 1K Ohms to GND for High output, 1K Ohms to VCC for Low output. 3. Timing measured from VIN=1.5V to 'VOUT=200mV. See Figure 4 4. See Figure 3 5. The delay is due to both the on chip filter circuits and VDD. 6. Guaranteed by design. 7. All measurements at VDD = 12V

ORDERING INFORMATION

Part Number Marking Package Temperature DEI1167-TES-G DEI1167-TES 24 TSSOP -55 / +85 ºC DEI1167-TMS-G DEI1167-TMS 24 TSSOP -55 / +125 ºC Note: Part is marked with “E4” after date code to denote lead free category DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose.

©2015 Device Engineering Inc Page 8 of 8 DS-MW-01167-01 Rev B 02/17/2015 PACKAGE DESCRIPTION 24L TSSOP Moisture Sensitivity: Level 2 /260ÛC per JEDEC J-STD-020A (1yr floor life) Ĭj a : 84ÛC/W (Mounted on 4 layer PCB) Ĭj c : 16ÛC/W Lead Finish: NiPdAu plated Materials: RoHS compliant Figure 8 24 Lead TSSOP Outline Drawing