DEI1049-TMS-G

DEI1049 DEIAZ | Alldatasheet

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Technical content

©2019 Device Engineering Inc. Page 1 of 8 DS-MW-01049-01 Rev B 01/08/2019

385 East Alamo Drive

Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com

FEATURES

• Octal ARINC 429 to TTL/CMOS logic line receivers
• Operates from single +5 V ± 10% or 3.3 V ± 10% power supply
• Operates in high noise environment o Input Common Voltage Range: ± 20 V o 2 V minimum Input hysteresis
• DEI1049 operates with external 40 kΩ resistors on inputs o Lightning protection beyond Level 3 o Fault isolation
• Package: 38L TSSOP, 4.4 mm body
• Withstands inadvertent short to 115 Vac on inputs DEI1049 PINOUT Table 1 DEI1049 Pin Description FUNCTIONAL DESCRIPTION The DEI1049 is a BiCMOS device which contains eight differential line receivers. Each receiver channel translates incoming ARINC 429 data bus signals (tri-level RZ bipolar differential modulation) to a pair of TTL/CMOS logic outputs. Each channel operates independently and meets the requirements of the ARINC 429 Digital Information Transfer Standard. Refer to Figure 1 DEI1049 Block Diagram and Truth Table. PIN NAME DESCRIPTION 15, 13, 11, 9, 7, 5, 3, 1 IN[8:1]A 429 INPUTS. ARINC 429 format serial digital data “A” inputs. 16, 14, 12, 10, 8, 6, 4, 2 IN[8:1]B 429 INPUTS. ARINC 429 format serial digital data “B” inputs. 17 NC Not connected.

18 TESTA LOGIC INPUT, Test input A

19 TESTB LOGIC INPUT, Test input B

21, 23, 25, 27, 32, 34, 36, 38 OUT[8:1]A LOGIC OUTPUTS. CMOS/TTL format serial digital data “A” outputs. 20, 22, 24, 26, 31, 33, 35, 37 OUT[8:1]B LOGIC OUTPUTS. CMOS/TTL format serial digital data “B” outputs. 29 VDD POWER INPUT. 5 VDC or 3.3 VDC. 28, 30 VSS POWER INPUT. Ground. Device Engineering Incorporated DEI1049 OCTAL ARINC 429 LINE RECEIVER

©2019 Device Engineering Inc. Page 2 of 8 DS-MW-01049-01 Rev B 01/08/2019 The device is designed to operate in a high noise environment. Inputs are accepted over a +/- 20 V common mode voltage range and the receivers provide over 2 Volts of hysteresis. Circuit speed is optimized to reject high frequency transients. The DEI1049 device provides logic level TEST inputs for built in system test. They force the outputs of all eight receivers to the specified ZERO, ONE or NULL state. The ARINC inputs are ignored when the device is in test mode. The DEI1049 has a single test port which controls all 8 channels. The DEI1049 is equivalent to the DEI1046A product, but with 40 k Ω of the input resistors removed so the part will operate with external 40 kΩ resistors. The DEI1049 ARINC inputs must be connected to the ARINC bus through 40 kΩ series resistors for correct operation. The external resistors provide fault isolation in the event of IC damage that might otherwise cause excessive loading of the ARINC signals. The ARINC inputs incorporate on-chip lightning protection by use of high value resistors on the inputs to minimize IR heating. The resistors have dielectric isolation to withstand the voltage transients. The inputs withstand lighting induced transients up to and including DO160 Level 3 pin injection levels. Higher levels can be achieved with the addition of external transient voltage suppressor (TVS) devices between the inputs and ground. The 40 kΩ resistors limit surge current and thus minimize the power requirement and size of the TVS. The ARINC inputs withstand inadvertent short to 115 Vac aircraft power without sustaining damage. Figure 1 DEI1049 Block Diagram and Truth Table

©2019 Device Engineering Inc. Page 3 of 8 DS-MW-01049-01 Rev B 01/08/2019 ELECTRICAL DESCRIPTION Table 2: Absolute Maximum Rating PARAMETER MIN MAX UNITS Supply Voltage (with respect to VSS) -0.3 7.0 V Storage Temperature -65 +150 °C Input Voltage, continuous (ARINC Inputs) 115 Vac Power Dissipation @ 85 °C 800 mW Junction Temperature, Tjmax (limited by molding compound Tg) 145 °C Peak Body Temperature 260 °C Lightning Protection (ARINC 429 Channel Inputs) Waveform 3 (2) Waveform 4, & 5A (2) (3) -720 -360 +720 +360 V V ESD JS-001-2017 HBM 1B Class Notes: 1. Stresses above these limits can cause permanent damage. 2. Per DO160, Sect 22 Level 3 pin injection. See Figures 4, 5 and 6. 3. Inputs can be protected to withstand higher stress by adding shunt TVS on inputs. Inputs withstand 1500 V Waveform 5A when clipped ≤ 600 V. Table 3: Recommended Operating Conditions PARAMETER SYMBOL CONDITIONS Supply Voltage VDD +5 V ±10% +3.3 V ±10% Logic Input Levels TESTA, B 0 to VDD Operating Temperature -TES -TMS Ta -55 to +85 °C -55 to +125 °C

©2019 Device Engineering Inc. Page 4 of 8 DS-MW-01049-01 Rev B 01/08/2019 Table 4: Electrical Characteristics Conditions: Temperature: -55 °C to +85 °C (-TES); -55 °C to +125 °C (-TMS) VDD = +5 V ±10% or 3.3 V ±10% INA/B inputs have 40kΩ resistors installed between the IC pins and A429 signal. PARAMETER TEST CONDITION SYMBOL MIN MAX UNITS ARINC INPUTS VA – VB = Logic +1 OUTA = 1 V +1 6.5 13 V VA – VB = Logic -1 OUTB = 1 V -1 -6.5 -13 V VA – VB = Logic Null OUTA = 0 OUTB = 0 VNULL -2.5 2.5 V Input Hysteresis V HY 2.0 4.0 V Input Common Mode Voltage Range Logic +1, Null, Logic -1 V CM -20 +20 V Input Resistance INA to INB VDD open, Shorted to VSS or +5 V (1) RIN 280 k Ω Input Resistance INA or INB to VSS VDD open, Shorted to VSS or +5 V RS 140 k Ω Input Capacitance INA to INB VDD open, Shorted to VSS or +5 V (1) CIN 10 pF Input Capacitance INA or INB to VSS VDD open, Shorted to VSS or +5 V (1) CS 10 pF LOGIC INPUTS Logic 0 Voltage V IL 0.8 V Logic 1 Voltage V IH 2.0 V Logic 0 Current V IL = 0.8 I IL 25 µA Logic 1 Current V IH = 2.0 I IH 50 µA LOGIC OUTPUTS OUTPUT HIGH VOLTAGE TTL IOH = -5 mA (VDD = 5.0 V) IOH = -5 mA (VDD = 3.3 V) TTL Compatible VOH 2.4 V OUTPUT LOW VOLTAGE TTL IOL= 5 mA (VDD = 5.0 V) V OL 0.4 V OUTPUT HIGH VOLTAGE CMOS IOH = 100µA CMOS Compatible VOH VDD – 50 mV V OUTPUT LOW VOLTAGE CMOS IOL= 100 µA CMOS Compatible VOL VSS+ 50 mV V SUPPLY CURRENT VDDCurrent Data Rate = 0MHZ, INA/B = open, OUTA/B = open, VDD = 5.5 V or 3.63 V IDD 1.5 8.5 mA Notes: 1. Guaranteed by design, not production tested. 2. Current flowing into device is positive. Current flowing out of device is negative. All voltages are with respect to VSS unless otherwise noted.

©2019 Device Engineering Inc. Page 5 of 8 DS-MW-01049-01 Rev B 01/08/2019 Table 5: Switching Characteristics PARAMETER TEST CONDITION (1, 2) SYMBOL MAX VDD 3.3 V MAX VDD 5 V UNITS INA/B to OUTA/B Prop Delay TESTA = TESTB = 0 CL = 50 pF tLH 1000 900 ns INA/B to OUTA/B Prop Delay TESTA = TESTB = 0 CL = 50 pF tHL 1000 900 ns OUTA/B rise time 10% to 90%, C L = 50 pF t r 50 25 ns OUTA/B fall time 10% to 90%, C L = 50 pF t f 50 25 ns TESTA/B to OUTA/B Prop delay CL = 50 pF t TOH 100 60 ns TESTA/B to OUTA/B Prop delay CL = 50 pF t TOL 100 60 ns Notes: 1. Sample tested. 2. Refer to Figures 2 – 3.

©2019 Device Engineering Inc. Page 7 of 8 DS-MW-01049-01 Rev B 01/08/2019

ORDERING INFORMATION

Table 6: Ordering Information DEI PN MARKING (1) TEST INPUTS TEMPERATURE RANGE PACKAGE SCREENING DEI1049-TES-G DEI1049-TES (e4) YES -55/+85 °C 38L TSSOP G Standard DEI1049-TMS-G DEI1049-TMS (e4) YES -55/+125 °C 38L TSSOP G Standard Notes: 1. All packages marked with Lot Code and Date Code. (e4) after Date Code denotes Pb Free category. Table 7: Screening Process SCREENING STANDARD ELECTRICAL TEST: ROOM TEMPERATURE 100% HIGH TEMPERATURE 100% @ 85 °C or 125 °C LOW TEMPERATURE 0.65% AQL@-55 °C

©2019 Device Engineering Inc. Page 8 of 8 DS-MW-01049-01 Rev B 01/08/2019 PACKAGE DESCRIPTION Table 8: Package Characteristics CHARACTERISTIC VALUE REFERENCE 38L TSSOP G QJA (4 layer PCB with Power Planes) 75 °C/W QJC 15 °C/W JEDEC MOISTURE SENSITIVITY LEVEL (MSL) MSL 2 / 260 °C LEAD FINISH MATERIAL / JEDEC Pb-free CODE NiPdAu Pb-Free DESIGNATION RoHS Compliant JEDEC REFERENCE MO-153-BD-1 Figure 6 38L TSSOP Mechanical Outline DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose.