DEI1041-SMB-G

DEI1041 DEIAZ | Alldatasheet

Document overview

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• PDF pages: 8

Technical content

Printed copies are uncontrolled reference documents Page 1 of 8 DS-MW-01041-01 Rev R 5/7/2019

385 East Alamo Drive

Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com

FEATURES

• ARINC 429 to TTL/CMOS logic line receiver
• Drop-in replacement for HI-8588 and HI-8588-10
• Operates from single 5 V ±10% or 3.3 V ±10% power supply
• ARINC inputs internally protected to lightning requirements of DO-160 Level 3 pin injection
• ARINC inputs withstand inadvertent short to 115 Vac on inputs
• Operates in high noise environment o Input Common Voltage Range: ± 20 V o 2 V minimum Input hysteresis
• Logic level TEST inputs bypass analog inputs.
• High input resistance allows use of external series resistors to support: o Lightning protection beyond Level 3 o Fault isolation
• Package: 8L SOIC TERMINAL DESCRIPTION Table 1 Terminal Description Device Engineering Incorporated DEI1041 ARINC 429 LINE RECEIVER PIN NAME DESCRIPTION 4 INA 429 INPUT. ARINC 429 format serial digital data “A” input 3 INB 429 INPUT. ARINC 429 format serial digital data “B” input 2 TESTA LOGIC INPUT. Test input A 8 TESTB LOGIC INPUT. Test input B 6 OUTA LOGIC OUTPUT. CMOS/TTL format serial digital data “A” output 7 OUTB LOGIC OUTPUT. CMOS/TTL format serial digital data “B” output 1 VDD POWER INPUT. 5 V OR 3.3V 5 GND POWER INPUT. Ground

Printed copies are uncontrolled reference documents Page 2 of 8 DS-MW-01041-01 Rev R 5/7/2019 FUNCTIONAL DESCRIPTION The DEI1041 is a BiCMOS device which contains one ARINC 429 differential line receiver. It translates incoming ARINC 429 data bus signals (tri-level RZ bipolar differential modulation) to a pair of TTL/CMOS logic outputs. It meets the requirements of the ARINC 429 Digital Information Transfer Standard. Refer to Figure 1 “DEI1041 Block Diagram and Truth Table”. The device is designed to operate in a high noise environment. Inputs are accepted over a ±20 V common mode voltage range and the receivers provide over 2 V of hysteresis. Circuit speed is optimized to reject high frequency transients. All ARINC input pins are designed with internal protection from damage due to transients meeting the lightning induced transient requirements of DO-160 Level 3 pin injection. The ARINC inputs may optionally be connected to ARINC bus through external 10 kΩ series resistors. These resistors may be added in combination with transient voltage suppressors to achieve lighting protection beyond the Level A3 limits due to high input impedance. The ARINC input pins are designed with internal protection from damage due to lighting induced transients of DO-160 Level 3 pin injection. The protection incorporates on-chip high value resistors to minimize IR heating and high-voltage dielectric isolation to withstand the voltage transients. Higher protection levels can be achieved with the addition of external TVS devices between the inputs and ground, or alternately, TVS devices in combination with series current limiting resistors between the ARINC bus and the IC/TVS node. The series resistors reduce the power requirement and size of the TVS. Resistor values up to 10 kΩ are feasible. The ARINC inputs withstand inadvertent short to 115 Vac aircraft power without sustaining damage. The DEI1041 provides logic level TEST inputs for built in system test. They force the receiver outputs to the specified ZERO, ONE or NULL state. The ARINC inputs are ignored when the device is in test mode. Figure 1 DEI1041 Block Diagram and Truth Table

Printed copies are uncontrolled reference documents Page 3 of 8 DS-MW-01041-01 Rev R 5/7/2019 ELECTRICAL DESCRIPTION Table 2 Recommended Operating Conditions PARAMETER SYMBOL CONDITIONS Supply Voltage VDD 5 V ±10%

3.3 V ±10%

Logic Input Levels TESTA,B 0 to VDD Operating Temperature -SES -SMS Ta -55 to 85 °C -55 to 125 °C Table 3 Absolute Maximum Rating PARAMETER MIN MAX UNIT Supply Voltage (with respect to GND) -0.3 7.0 V Input Voltage, continuous (ARINC Inputs) -40 40 V Logic Input and Outputs –0.3 VDD + 0.3 V Lightning Protection (ARINC 429 Channel Inputs) Waveform 3 (2) Waveform 4, 5A (2) (3) -600 -300 600 300 V Power Dissipation @ 85 °C 500 mW ESD per JEDEC JS-001 Human Body Model (HBM) 1C Class Storage Temperature -65 150 °C Junction Temperature, Tjmax 145 °C Peak Body Temperature 260 °C Notes: 1. Stresses above these limits can cause permanent damage. 2. Per DO160, Sect 22 Level 3 pin injection. See Figures 4-6. 3. Inputs can be protected to withstand higher stress by adding series resistors and shunt TVS on inputs. Inputs withstand 1500 V Waveform 5A when clipped ≤ 600 V.

Printed copies are uncontrolled reference documents Page 4 of 8 DS-MW-01041-01 Rev R 5/7/2019 Table 4 Electrical Characteristics Conditions: Temperature: -55 °C to 85°C (SES), 55 °C to 125°C (SMS) VDD = 5 V ±10% or 3.3 V ±10% PARAMETER TEST CONDITION SYMBOL MIN NOM MAX UNIT ARINC INPUTS ARINC ONE Input Voltage V(INA – INB) For OUTA = 1, OUTB = 0 VONE 6.5 10 13 V ARINC NULL Input Voltage V(INA – INB) For OUTA = OUTB = 0 VNULL -2.5 0 2.5 V ARINC ZERO Input Voltage V(INA – INB) For OUTA = 0, OUTB = 1 VZERO -6.5 -10 -13 V Input Hysteresis VHY 2 V Input Common Mode Voltage Range ONE, NULL, ZERO VCM -20 20 V Input Resistance INA to INB VDD open, shorted to GND or 5 V (1) RIN 280 780 kΩ Input Resistance INA or INB to GND VDD open, shorted to GND or 5 V RS 140 390 kΩ Input Capacitance INA to INB VDD open, shorted to GND or 5 V (1) CIN 10 pF Input Capacitance INA or INB to GND VDD open, shorted to GND or 5 V (1) CS 10 pF TEST INPUTS Logic 0 Voltage VIL 0.8 V Logic 1 Voltage VIH 2.0 V Logic 0 Current VIL = 0.8 V IIL 20 µA Logic 1 Current VIH = 2.0 V IIH 25 µA LOGIC OUTPUTS OUTPUT HIGH VOLTAGE TTL IOH = -5 mA (VDD = 5.0 V) IOH = -5 mA (VDD = 3.3 V) TTL Compatible VOH 2.4 V OUTPUT LOW VOLTAGE TTL IOL = 5 mA (VDD = 5.0 V) VOL 0.4 V

Printed copies are uncontrolled reference documents Page 5 of 8 DS-MW-01041-01 Rev R 5/7/2019 Conditions: Temperature: -55 °C to 85 °C (SES), 55 °C to 125 °C (SMS) VDD = 5 V ±10% or 3.3 V ±10% PARAMETER TEST CONDITION SYMBOL MIN NOM MAX UNIT OUTPUT HIGH VOLTAGE CMOS IOH = 100 µA CMOS Compatible VOH VDD – .05 V OUTPUT LOW VOLTAGE CMOS IOL = 100 µA CMOS Compatible VOL .05 V SUPPLY CURRENT VDD Current Data Rate = 0 MHZ INA/B = open, OUTA/B = open, VDD = 5.5 V or 3.63 V IDD 0.4 5 mA Notes: 1. Guaranteed by design, not production tested. 2. Current flowing into device is positive. Current flowing out of device is negative. All voltages are with respect to GND unless otherwise noted. Table 5 Switching Characteristics PARAMETER TEST CONDITION (1) SYMBOL MAX MAX UNIT VDD 3.3 V VDD 5 V INA/B to OUT A/B Prop Delay TESTA = TESTB = 0 CL = 50 pF tLH 1000 900 ns INA/B to OUT A/B Prop Delay TESTA = TESTB = 0 CL = 50 pF tHL 1000 900 ns Matching of tLH and tHL Dtp 500 500 ns OUTA/B rise time 10% to 90%, CL = 50 pF tr 50 25 ns OUTA/B fall time 10% to 90%, CL = 50 pF tf 50 25 ns TESTA/B to OUTA/B Prop delay CL = 50 pF tTOH 100 60 ns TESTA/B to OUTA/B Prop delay CL = 50 pF tTOL 100 60 ns Notes: 1. Sample tested.

Printed copies are uncontrolled reference documents Page 7 of 8 DS-MW-01041-01 Rev R 5/7/2019 PACKAGE DESCRIPTION Table 6 Package Characteristics CHARACTERISTIC VALUE REFERENCE 8L NB SOIC G QJA (4 layer PCB with Power Planes) 55 °C/W QJC 24 °C/W JEDEC MOISTURE SENSITIVITY LEVEL MSL 1 / 260 °C LEAD FINISH MATERIAL / JEDEC Pb-free CODE NiPdAu Pb-Free DESIGNATION RoHS Compliant JEDEC REFERENCE MS-012-AC Figure 7 Mechanical Outline, 8L NB SOIC G

Printed copies are uncontrolled reference documents Page 8 of 8 DS-MW-01041-01 Rev R 5/7/2019 PROCESS FLOW Table 7 Process Flow PROCESS STEP PLASTIC STANDARD PLASTIC BURN-IN BURN IN (1) N/A 96 h @ 125 °C FINAL ELECTRICAL TEST, Room Temperature 100% 100% FINAL ELECTRICAL TEST, High Temperature 100% @ 85 or 125 °C 100% @ 85 or 125 °C FINAL ELECTRICAL TEST, Low Temperature 0.65% AQL @ -55 °C 0.65% AQL @ -55 °C NOTES: 1. Burn-in conditions: 125 °C, 96 h, VDD = 5.0 V, Inputs = 0 V, Outputs open.

ORDERING INFORMATION

Table 8 Ordering Information DEI PN PART MARKING (1) TEMPERATURE RANGE BURN-IN PACKAGE TYPE DEI1041-SES-G DEI1041 YYWWE4 SES -55/+85 °C NO 8L NB SOIC G DEI1041-SMS-G DEI1041 YYWWE4 SMS -55/+125 °C NO 8L NB SOIC G DEI1041-SMB-G DEI1041 YYWWE4 SMB -55/+125 °C YES 8L NB SOIC G NOTES: 1. Lot code marked on bottom. (e4) after Date Code denotes Pb Free category. DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose.