DEI1198

DEI1198 DEIAZ | Alldatasheet

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Technical content

©2019 Device Engineering Inc. 1 of 12 DS-MW-01198-01 Rev. E 5/10/2019

FEATURES

• Eight discrete inputs o Senses GND/OPEN discrete signals. o Meets input threshold and hysteresis requirements specified per AirBus ABD0100H specification. § Thresholds: 4.5 V / 10.5 V, Hysteresis: 3 V o ~1 mA DIN source/sink current to prevent dry relay contacts. o Internal isolation diode. o Uses an external 3 kΩ resistor on the inputs to implement lightning transient immunity of 1600 V and higher. i.e.: DO160E, Section 22, Levels 4 and 5. o Inputs protected from Lightning Induced Transients per DO160, Section 22, Cat A3 and B3 plus waveform 5A to 500 V.
• Parallel I/O interface o TTL/CMOS compatible inputs and Tristate outputs o CLK & /OE control inputs and outputs
• Logic Supply Voltage (VCC): 3.3 V ±%
• Analog Supply Voltage (VDD): 12.0 V to 16.5 V
• Package Options o 24 Lead TSSOP o 24 Lead TSSOP EP Thermally Enhanced
• Pin compatible with DEI1166/67 PIN ASSIGNMENTS Figure 1 DEI1198 Pin Assignment (24 Lead TSSOP) DEI1198 8CH GND/OPEN PARALLEL OUTPUT DISCRETE INTERFACE IC

6031 South Maple Avenue

Tempe, AZ 85283 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com Device Engineering Incorporated

©2019 Device Engineering Inc. 2 of 12 DS-MW-01198-01 Rev. E 5/10/2019 FUNCTIONAL DESCRIPTION DEI1198 is an eight-channel parallel discrete-to-digital interface IC implemented in an HV DIMOS technology. It senses eight GND/OPEN discrete signals of the type commonly found in avionic systems and converts them to logic data. The discrete data is read from the device via a parallel tri-state bus. The discrete input circuits are designed to achieve a high level of lightning transient immunity. The application design requires a series 3 kΩ resistor on each discrete input to achieve DO160 Level 3 and WF5A 500 V pin injection immunity. Higher immunity levels can be achieved (i.e. Level 5) with the addition of a TVS between the resistor and the input pin. Table 1 Pin Description PINS NAME DESCRIPTION 1-8 DIN[1:8] Discrete Inputs. Eight GND/OPEN discrete input signals. 9-10 NC Not Connected. 11 CLK Latch Clock Logic Input. A low level on this input enables transparent mode. A high level on this input enables latch mode. 12 /OE Output Enable Logic Input. Low input will enable the tri-state outputs 13 VDD Analog Supply Voltage. 12 V to 16.5 V

14 GND Logic/Signal Ground

19 VCC Logic Supply Voltage. 3.3V+/-5%

22 GND Logic Ground

15-18,20-21,23- DO[1:8] Logic Outputs. Eight tri-state data outputs DIN[1:8] Discrete AFE The Discrete Input Analog Front End circuit function is represented in Figure 3. Each DINn signal is conditioned by the resistor / diode network and presented to a comparator with hysteresis. The external 3 k Ω resistor is part of the front end circuitry for achieving threshold and hysteresis requirements while protecting the chip from Lightning Induced Transients. Some notable features are: l The DIN source/sink current is ~1 mA. This current will prevent a “dry” relay contact. l The input voltage and hysteresis: o Low Level: -4.0 to +4.5 V o High Level: 10.5 to 49 V o Hysteresis: > 3 V l Input noise immunity is maximized with a combination of voltage hysteresis and use of a slow input voltage comparator l The inputs can withstand continuous input voltages of 49 V. The isolation diode breakdown voltage is greater than 45 V. The 10 k Ω input resistance (consists of a 7 k Ω On-Chip resistor and a 3 k Ω Off-Chip resistor) is designed to limit diode breakdown current to safe levels during transient events.

©2019 Device Engineering Inc. 3 of 12 DS-MW-01198-01 Rev. E 5/10/2019 Table 2 Truth Table CLK /OE DIN[1:8] LATCH[1:8] DO[1:8] DESCRIPTION 1 1 X Hold HiZ Output = HiZ, Latch = Hold mode 1 X Open 0 X Latch[1:8] <= DIN [1:8] Ground 1 1 0 X Hold Latch[1:8] Output = Latched data

0 X X DIN[1:8] X Latch = Transparent mode

Output = Live data Open 1 1 Legend: X = don’t care input or undefined output HiZ = Hi Impedance Figure 2 Function Block Diagram (two channels shown) Figure 3 Analog Front End Detail

©2019 Device Engineering Inc. 5 of 12 DS-MW-01198-01 Rev. E 5/10/2019 ELECTRICAL DESCRIPTION Table 3 Absolute Maximum Ratings PARAMETER MIN MAX UNITS VCC Supply Voltage -0.3 +5.0 V VDD Supply Voltage -0.3 18 V Operating Temperature 1198-TES-G 1198-TMS-G -55 -55 +85 +125 Storage Temperature Plastic Package -55 +150 °C Input Voltage (3)(4) DIN[1:8] Continuous DO160, Waveform 3, Level 3 DO160, Waveform 4 and 5, Level 3 DO160, Waveform 4 and 5 DO160, Abnormal Surge Voltage, 100ms Logic Inputs DOUT -10 -600 -300 -500 -1.5 -0.5 +49 +600 +300 +500 VCC + 1.5 VCC + 0.5 V V V V V V V Power Dissipation @ 85 °C steady state, 1198-TES-G Power Dissipation @ 125 °C steady state, 1198-TMS-G 0.8 0.8 W W Junction Temperature: Tjmax 145 °C ESD per JEDEC A114 Human Body Model Logic and Supply pins DIN pins 2000 1000 V Peak Body Temperature (10 sec duration) 260 °C Notes: 1. Stresses above absolute maximum ratings may cause permanent damage to the device. 2. Voltages referenced to Ground 3. Stress applied to external 3 kΩ series resistor in series with DINn pin. 4. Discrete input voltage amplitude tolerance for WF3, 4 and 5 are +20% / -0%

©2019 Device Engineering Inc. 6 of 12 DS-MW-01198-01 Rev. E 5/10/2019 Table 4 Recommended Operating Conditions PARAMETER SYMBOL CONDITIONS Supply Voltage VCC VDD

3.3 V ±5%

12.0 V to 16.5 V Logic Inputs and Outputs 0 to VCC Discrete Inputs DIN[1:8] 0 to 49 V Operating Temperature 1198-TES-G 1198-TMS-G Ta -55 to +85 °C -55 to +125 °C Table 5 DC Electrical Characteristics SYMOBL PARAMETER CONDITIONS (1)(2) LIMITS UNIT MIN NOM MAX Logic Inputs/Outputs V1IH HI level input voltage VCC = 3.3 V 2.0 V V1IL LO level input voltage 0.8 V VOH HI level output voltage I_DOUT = -20 uA VCC – 0.1 V I_DOUT = -4 mA, VCC = 3V 2.4 V VOL LO level output voltage I_DOUT = 20 uA 0.1 V I_DOUT = 4 mA, VCC = 3 V 0.4 V IIN Input leakage VIN = VCC VIN = GND -10 -35 0 uA IOZ 3-state leakage current Output in Hi Impedance state. DOUT = VIHmin, VILmax -10 10 uA Discrete Inputs (4) V2IH HI level input voltage 10.5 49 V RIH HI level DIN-to-GND resistance Resistor from DIN to GND to guarantee HI input condition. 50 kΩ IIH HI level input current DIN = 28 V, VDD = 15 V DIN = 49 V, VDD = 15 V 240 uA mA V2IL LO level input voltage -4.0 4.5 V RIL LO level DIN-to-GND resistance Resistor from DIN to GND to guarantee LO input condition. 500 Ω IIL LO level input current DIN = 0V, VDD = 15V -0.8 -1.3 -1.8 mA VIhst Input hysteresis voltage 3 V Power Supply ICC Max quiescent logic supply current VIN(logic) = VCC or GND DIN[1:8]= open 1.8 3 mA

©2019 Device Engineering Inc. 7 of 12 DS-MW-01198-01 Rev. E 5/10/2019 SYMOBL PARAMETER CONDITIONS (1)(2) LIMITS UNIT MIN NOM MAX IDD Max quiescent analog supply current VIN(logic) = VCC or GND DIN[1:8]= Open DIN[1:8]= GND mA Notes: 2. Current flowing into device is ‘+’. Current flowing out of device is ‘- ‘. Voltages are referenced to Ground 3. Guaranteed by design. Not production tested 4. With 3 kΩ, 2% resistor in series with DIN input pin

©2019 Device Engineering Inc. 8 of 12 DS-MW-01198-01 Rev. E 5/10/2019 Table 6 AC Electrical Characteristics SYMOBL PARAMETER CONDITIONS (1,2) LIMITS UNITMIN MAX tHL tLH Propagation delay, DIN to DO. (3) CLK = /OE = 0 550 ns tHZ tLZ Output disable delay, /OE↑ to DO HI-Z. (4)(5) 50 ns tZH tZL Output Enable delay, /OE↓ to DO active. (4)(5) 50 ns tSU DIN setup time, DIN to CLK↓ (6) 550 ns tH DIN hold time, DIN to CLK↑ (6) 10 ns Cin Logic input pin Capacitance. (7) 10 pf Cout DOUT pin capacitance, output in HI-Z state. (7) 15 pf Notes: 1. DOUT loaded with 50 pF to GND. 2. Ta = -55 to +85/+125 °C. VDD = 12 V, VCC = 3 V. VIL = 0 V, VIH = VCC unless otherwise noted. 4. DOUT loaded with 1 k Ω to GND for Hi output, 1 kΩ to VCC for Low output. 5. Timing measured from /OE=1.5 V to DO=200 mV. See Figure 7. 7. Not production tested. Guaranteed by design. 8. AC characteristics are sample tested on lot basis. TIMING DIAGRAMS Figure 7 Switching Waveforms 3.0 DO DIN HIGH Z DO HIGH Z HI 1.5 tSU tH CLK DIN 4.5 HI 1.5 4.5 tLH tHL LO HI 1.5 1.3 tZL tLZ 0.2 HIGH Z HIGH Z 1.5 1.3 tZH tHZ 0.2 3.0 3.0 0 0 OE DO 1.5OE

©2019 Device Engineering Inc. 9 of 12 DS-MW-01198-01 Rev. E 5/10/2019

APPLICATION INFORMATION

The DEI1198 Analog Front End provides a moderate level of noise immunity via a combination of hysteresis and limited bandwidth. The Hysteresis is 3 V minimum, and the comparator bandwidth is approximately 10 MHZ. Many applications provide additional noise immunity by means of debounce/filtering in software or in digital circuitry (i.e. FPGA). Common input debounce techniques are readily found with a web search of the term “software debounce” and range from simple detectors of two or more sequential stable readings to FIR filters emulating RC time constants. Input Current Characteristics The DIN Input Current vs. Voltage characteristics are shown in Figure 8. Figure 8 Input IV Characteristics (VDD = 15 V)

©2019 Device Engineering Inc. 10 of 12 DS-MW-01198-01 Rev. E 5/10/2019 Package Power Dissipation The DEI1198 power dissipation varies with operating conditions. Figure 9 shows the device package power dissipation for various operating conditions. This includes the contributions from Supply currents and DIN Input currents. The curves are as follows: Table 7 Legend for Power Dissipation Curves CURVE ID SUPPLY VOLTAGE, TEMPERATURE, IC VARIATION GND/OPEN-Nom 3.3 V, 12 V / 27 °C / typical IC parameters GND/OPEN-Wst 3.3 V, 16.5 V / 85 °C / Worst case IC parameters Figure 9 DEI1198 Power Dissipation vs Active Channels

ORDERING INFORMATION

Table 8 Ordering Information PART NUMBER MARKING PACKAGE TEMPERATURE DEI1198-TES-G DEI1198-TES 24 TSSOP G -55 / +85 °C DEI1198-TMS-G DEI1198-TMS 24 TSSOP EP G -55 / +125 °C 100 200 300 400 500 600 700 800 0 1 2 3 4 5 6 7 8 Number CH Active Power Dissipation (mW) GND/OPN-Nom GND/OPN-Wst DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose. Number of Active Channels

©2019 Device Engineering Inc. 11 of 12 DS-MW-01198-01 Rev. E 5/10/2019 PACKAGE DESCRIPTIONS Table 9 Package Information CHARACTERISTIC 25TSSOP G 24TSSOP EP G Moisture Sensitivity MSL 1 / 260 °C MSL 3 / 260 °C Lead Finish NiPdAu 100% Matte Sn Materials RoHS Compliant RoHS Compliant JEDEC Reference MO-153-AD MO-153-AD Thermal Resistance (°C/W) Θja: Θjc: ~84 ~16 ~29 The PCB design and layout are a significant factor in determining thermal resistance ( Θja) of the IC package . Use maximum trace width on all power and signal connections at the IC. These traces serve as heat spreaders which improve heat flow from the IC leads. The exposed thermal pad of the 24TSSOP EP G package must be soldered to a heat spreader land pattern on the PCB to achieve required thermal performance.

• Connect the exposed thermal pad to electrical Ground.
• Use large and multi-layer PCB boards, at least 4 layers 3” x 3”, with internal solid GND and Power planes.
• Maximize the thermal pad land size by extending it beyond the IC to form a dog-bone pattern on the top layer and a similar sized heat spreader copper pattern on the bottom layer.
• Use thermal VIAs to connect the thermal pad land pattern on the top layer, inter GND(s) and bottom GND layer. Place as many thermal VIA’s in the land pattern as space allows to conduct heat from the thermal pad to the internal ground plane and bottom heat spreader. Figure 10 24 TSSOP G Outline

©2019 Device Engineering Inc. 12 of 12 DS-MW-01198-01 Rev. E 5/10/2019 SYMBOLS MIN NOM MAX -- -- 1.20 A1 0.00 -- 0.15 A2 0.80 1.00 1.05 b 0.19 -- 0.30 D 7.70 7.80 7.90 E1 4.30 4.40 4.50 E 6.40 BSC

0.65 BSC

L1 1.00 REF L 0.45 0.60 0.75 S 0.20 -- -- 0 ° -- 8 ° E2 2.28 -- 3.00 D1 3.70 -- 4.75 Figure 11 24 TSSOP EP G Outline Thermal Pad