DEI1160A DEIAZ | Alldatasheet

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©2014 Device Engineering Inc. 1 of 13 DS-MW-01160-02 Rev A 03/21/2014

FEATURES

x The DEI1160A is an improved version of the DEI1160 with greater transient voltage immunity, which simplifies the equipment design for lightning and RF immunity requirements. x Eight discrete inputs o Individually configurable to sense either GND/OPEN or 28V/OPEN(or 28V/GND) discrete signals o Hysteresis provides noise immunity o 1mA input current to prevent dry relay contacts. o Internal isolation diode o Inputs protected from Lightning Induced Transients per DO160E, Section 22, Cat A3 and B3. o Inputs protected from Power Input Abnormal Surge per DO160E, Section 16, Cat Z. x Serial I/O interface to read data register and write configuration register o Direct interface to Serial Peripheral Interface (SPI) port. o TTL/CMOS compatible inputs and Tristate output o 10MHz Data Rate o Serial input to expand Shift Register x Logic Supply Voltage (VCC): 3.3V or 5V x Analog Supply Voltage (VDD): 15V +/-10% x 16L SOIC EP package PIN ASSIGNMENTS DEI1160A

1 DIN1

/CS SDO SCLK Figure 1 DEI1160A Pin Assignment (16 Lead SOIC)

385 East Alamo Drive

Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com DEI1160A PROGRAMMABLE GND/OPN & 28V/OPN DISCRETE INPUT INTERFACE IC Device Engineering Incorporated

©2014 Device Engineering Inc. 2 of 13 DS-MW-01160-02 Rev A 03/21/2014 FUNCTIONAL DESCRIPTION The DEI1160A is an eight-channel discrete-to-digital interface IC implemented in an HV DMOS technology. It senses eight discrete signals of the type commonly found in avionic systems and converts them to serial logic data. Each input can be individually configured as either GND/OPEN or 28V/OPEN format input via a serial data input command. The discrete data is read from the device via an eight-bit serial shift register with 3-state output. This serial interface is compatible with the industry standard Serial Peripheral Interface (SPI) bus. Table 1 Pin Descriptions PINS NAME DESCRIPTION 1-8 DIN[1:8] Discrete Inputs. Eight discrete signals which can be individually configured as either GND/OPEN or 28V/OPEN format inputs. 9 SDO Logic Output. Serial Data Output. This pin is the output from MSB (Bit 8) of the selected shift register (Data/Configuration). It is clocked by the rising edge of SCLK. This is a 3-state output enabled by /CS. 10 SCLK Logic Input. Serial Shift Clock. A low-to-high transition on this input shifts data on the serial data input into Bit 0 of the selected shift register. The selected shift register is shifted from Bit 0 to Bit 7. Bit 7 of the selected shift register is driven on DOUT. 11 /CS Logic Input. Chip Select. A low level on this input enables the SDO 3- state output and the selected shift register. A high level on this input forces DOUT to the high impedance state and disables the shift registers so SCLK transitions have no effect. When the Data register is selected, a high-to-low transition causes the Discrete Input data to be loaded into the Data register. When the Configuration Register is selected, a low-to-high transition causes the Serial Configuration register data to be loaded into the parallel configuration outputs. 12 SDI Logic Input. Serial Data Input. Data on this input is shifted into the LSB (Bit 1) of the selected shift register on the rising edge of the SCLK when /CS input is low. 13 SEL Logic Input. Selects between the Serial DATA and CONFIGURATION registers. H = DATA, L = CONF. 14 VCC Logic Supply Voltage. 3.3V or 5V

15 GND Logic/Signal Ground

16 VDD Analog Supply Voltage. +15V+/-10%

©2014 Device Engineering Inc. 4 of 13 DS-MW-01160-02 Rev A 03/21/2014 Table 2 Truth Table SEL /CS SCLK SDI DIN[1:8] SDO DESCRIPTION X H X X X HI Z Not Selected H Ļ L X Valid DIN[8] DR[1:8]ĸ DIN[1:8] H L Ĺ DR[1] X DR[8] DR[n+1] ĸ DR[n], DR[1] ĸ SDI L L Ĺ CR[1] X CR[8] CR[n+1] ĸ CR[n], CR[1] ĸ SDI L Ĺ L X X HI Z CL[1:8]ĸ CR[1:8] Legend: DR = Data Register CR = Configuration Register CL = Configuration Latch DIN[1:8] Discrete AFE The Discrete Input Analog Front End circuit function is represented in Figure 3. Each DINn signal is conditioned by the resistor / diode network and presented to an amplifier followed by a comparator with hysteresis. When the input is configured for GND/OPEN operation, the pull-up resistor & diode is enabled and the appropriate amplifier offset voltage and comparator threshold voltage are selected. When configured for 28V/OPEN, the pull-down resistor is enabled and the amp/comparator is appropriately configured. Some notable features are: x The input current is ~1mA. This current will prevent a “dry” relay contact. x The input threshold voltage and hysteresis: o The falling Vth > 3.5V. o The rising Vth < 14V. o Hysteresis is maximum practical to meet the threshold requirements. x Input noise immunity is maximized with a combination of voltage hysteresis and use of a slow input voltage comparator x The inputs can withstand continuous input voltages of 40V minimum. The isolation diode breakdown voltage is greater than 45V. The 10K Ohm input resistor is designed to limit diode breakdown current to safe levels during transient events. Data Register The 8-bit Data Register is a “parallel-input, serial-output” register that samples the input channels and reads-out the data to the Serial Data Output. The register is read via the SDO output as described in Figure 4 and Figure 5. A low input level results in a Logic 0, and a high input level results in a Logic 1. Configuration Register The 8-bit Configuration Register is a “serial-input, parallel-output with data latch” register that individually configures each AFE input as eithe r GND/OPEN o r 28V/OPEN format. The registe r is programmed via the se rial data input as described in Figure 6 and Figure 7. Logic 0 sets the respective input to 28V/OPEN mode (pull-down); Logic 1 sets the respective input to GND/OPEN mode (pull-up). The register is Reset to 0’s when the Vcc Logic Supply voltage transitions from low to hi, thus initializing the AFE inputs to a pull-down state.

©2014 Device Engineering Inc. 8 of 13 DS-MW-01160-02 Rev A 03/21/2014 ELECTRICAL DESCRIPTION Table 3 Absolute Maximum Ratings PARAMETER MIN MAX UNITS Vcc Supply Voltage -0.3 +7.0 V Vdd Supply Voltage -0.3 18 V Operating Temperature Plastic Package -55 +125 Storage Temperature Plastic Package -55 +150 Input Voltage DIN[1:8] Continuous DO160E, Waveform 3, Level 3 DO160E, Waveform 4 and 5, Level 3+ DO160E, Abnormal Surge Voltage, 100ms Logic Inputs DOUT -10 -720 -600 -1.5 -0.5 +49 +720 +600 VCC + 1.5 VCC + 0.5 V V V V V V Power Dissipation @ 125 °C: (> 10 Sec) 16L SOIC 0.3 W Junction Temperature: Tjmax, Plastic Packages 145 ESD per JEDEC A114-A Human Body Model Logic and Supply pins DIN pins 2000 1000 V Peak Body Temperature (10 sec duration) 235 °C Notes: 1. Stresses above absolute maximum ratings may cause permanent damage to the device. 2. Voltages referenced to Ground Table 4 Recommended Operating Conditions PARAMETER SYMBOL CONDITIONS Supply Voltage VCC VDD 5.0V±10%, 3.3V±10% 15V±10% Logic Inputs and Outputs 0 to VCC Discrete Inputs DIN[1:8] 0 to 40V Operating Temperature Plastic Ta -55 to +125 ºC

©2014 Device Engineering Inc. 9 of 13 DS-MW-01160-02 Rev A 03/21/2014 Table 5 DC Electrical Characteristics SYMBOL PARAMETER CONDITIONS (1) LIMITS UNIT MIN NOM MAX Logic Inputs/Outputs VIH HI level input voltage VCC = 5V VCC = 3.3V 3.1 2.0 V VIL LO level input voltage 0.8 V VIhst Input hysteresis voltage, SCLK input (3) 50 mV IOUT = -20uA VCC – 0.1 VCC V VOH HI level output voltage IOUT = -4mA, Vcc = 3V 2.4 3 V IOUT = 20uA 0.1 V VOL LO level output voltage IOUT = 4mA, Vcc = 3V 0.4 V IIN Input leakage Vin = Vcc or GND -10 10 uA IOZ 3-state leakage current Output in Hi Impedance state. VOUT = VIHmin, VILmax -10 10 uA Discrete Inputs, Configured as Ground/Open (internal pull-up) VIH HI level input voltage 14 49 V RIH HI level Din-to-GND resistance Resistor from Din to GND to guarantee HI input condition. 50K Ohm IIH HI level input current Vin = 28V, VDD = 15V Vin = 49V, VDD = 15V 1.7 240 uA mA VIL LO level input voltage -3 3.5 V RIL LO level Din-to-GND resistance Resistor from Din to GND to guarantee LO input condition.

500 Ohm

IIL LO level input current Vin = 0V, VDD = 15V -0.9 -1.1 -1.25 mA VIhst Input hysteresis voltage 1 V Discrete Inputs, Configured as 28V/Open (internal pull-down) VIH HI level input voltage 14 49 V IIH HI level input current Vin = 28V, VDD = 15V 1.1 1.3 1.75 mA VIL LO level input voltage -3 3.5 V IIL LO level input current Vin = 1V, VDD = 15V 48 100 uA VIhst Input hysteresis voltage 1 V Power Supply ICC Max quiescent logic supply current Vin(logic) = Vcc or GND VIN[1:8]= open 1 13.5 mA IDD Max quiescent analog supply current Vin(logic) = Vcc or GND VIN[1:8]= Open VIN[1:8]= GND, All configured as Ground/Open mA Notes: 2. Current flowing into device is positive. Current flowing out of device is negative. Voltages are referenced to Ground. 3. Guaranteed by design. Not production tested.

©2014 Device Engineering Inc. 10 of 13 DS-MW-01160-02 Rev A 03/21/2014 Table 6 AC Electrical Characteristics (4) LIMITS SYMBOL PARAMETER CONDITIONS (6, 7) Min Max UNIT fMAX SCLK frequency. (50% duty cycle) (5) VCC = 3.0V VCC = 4.5V 8.6 MHz tW SCLK pulse width. (5) VCC = 3.0V VCC = 4.5V ns tsu1 Setup time, SCLK low to /CSĻ. VCC = 3.0V VCC = 4.5V ns th1 Hold time, /CSĻ to SCLKĹ. VCC = 3.0V VCC = 4.5V ns tsu2 Setup time, DIN valid to /CSĻ. 2 us th2 Hold time, /CSĻ to DIN not valid. 15 ns tsu3 Setup time, SDIN valid to SCLKĹ. VCC = 3.0V VCC = 4.5V ns th3 Hold time, SCLKĹ to SDIN not valid. VCC = 3.0V VCC = 4.5V ns tsu4 Setup time, SEL valid to /CSĻ. VCC = 3.0V VCC = 4.5V ns th4 Hold time, SEL valid to /CSĹ. VCC = 3.0V VCC = 4.5V ns tp1 Propagation delay, /CSĻ to DOUT valid. (1) VCC = 3.0V VCC = 4.5V 105 ns tp2 Propagation delay, SCLKĹ to DOUT valid. (1) VCC = 3.0V VCC = 4.5V ns tp3 Propagation delay, /CSĹ to DOUT HI- Z. (1) (2) (3) VCC = 3.0V VCC = 4.5V ns tp4 Delay time between /CS active. (5) VCC = 3.0V VCC = 4.5V ns Cin Maximum logic input pin Capacitance. (5) 10 pf Cout Maximum DOUT pin capacitance, output in HI-Z state. (5) 15 pf Notes: 1. DOUT loaded with 50pF to GND. 2. DOUT loaded with 1K Ohms to GND for Hi output, 1K Ohms to VCC for Low output. 3. Timing measured at 25%VCC for “0” to Hi-Z, 75%VCC for “1” to Hi-Z. 4. Sample tested on lot basis. 5. Not tested 6. Ta = -55 to +125ºC. VDD = +15V, VIL = 0V, VIH = VCC unless otherwise noted. 7. Measurements made at 50%VCC.

©2014 Device Engineering Inc. 11 of 13 DS-MW-01160-02 Rev A 03/21/2014 /CS SCLK SDO SDI DIN[1:8] tsu1 th1 tW 1/fmax tsu2 th2 X Xvalid tsu3 th3 X X D/C0 D/C1 tp1 tp2 tp3 tp4 valid SEL tsu4 th4 Figure 11 Switching Waveforms

ORDERING INFORMATION

Part Number Marking Package Burn In Temperature DEI1160A-SES DEI1160A SES 16 EP SOIC No -55 / +85 ºC DEI1160A-SMS DEI1160A SMS 16 EP SOIC No -55 / +125 ºC DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose.

©2014 Device Engineering Inc. 12 of 13 DS-MW-01160-02 Rev A 03/21/2014

APPLICATION INFORMATION

The DEI1160A power dissipation varies with channel configuration and operating conditions. Figure 12 shows the device package power dissipation for various conditions. This includes the contributions from Supply currents and Input currents. The four curves are as follows: Table 7 Legend for Power Dissipation Curves CURVE ID CONFIGURATION SUPPLY VOLTAGE / TEMPERATURE PROCESS CONDITION ACTIVE CHANNEL +28V/OPN-Nom All channels = 28V/OPN 3.3V, 15V / 27ºC Typical 28V +28V/OPN-Wst All channels = 28V/OPN 5.5V, 16.5V/ 125ºC Worst case (Low resistance and fast transistors) 28V GND/OPN-Nom All channels = GND/OPN 3.3V, 15V / 27ºC Typical GND GND/OPN-Wst All channels = GND/OPN 5.5V, 16.5V / 125ºC Worst case (Low resistance and fast transistors) GND Figure 12 Power Dissipation for Various Conditions DEI1160 Pwr Dissipation Graph 100 200 300 400 500 600 700 800 0 1 2 3 4 5 6 7 8 Number CH Active Pwr Dissipation (mW) +28V/OPN-Nom +28V/OPN-Wst GND/OPN-Nom GND/OPN-Wst

©2014 Device Engineering Inc. 13 of 13 DS-MW-01160-02 Rev A 03/21/2014 PACKAGE DESCRIPTION - 16L Narrow Body EP SOIC Moisture Sensitivity: MSL 1 / 260ÛC Ĭj a : ~40ÛC/W (Mounted on 4 layer PCB with exposed pad soldered to PCB land with thermal vias to internal GND plane) Ĭj c : ~10ÛC/W Lead Finish: SnPb plated Exposed Pad: Electrically Isolated from IC terminals. The PCB design and layout is a significant factor in determining thermal resistance ( Ĭja) of the IC package . Use maximum trace width on all power and signal connections at the IC. These traces serve as heat spreaders which improve heat flow from the IC leads. The exposed heat sink pad of the SOIC package should be soldered to a heat-spreader land pattern on the PCB. T he IC e xpo se d pad is e le c t ric a lly iso late d, so t he PCB l a nd m ay be at a ny po te nti al , ty pic ally GND, f o r t he b e st he at si nk . Maximize the PCB land size by extending it beyond the IC outline if possible. A grid of thermal VIAs, which drop down and connect to the buried copper plane(s), should be placed under the heat-spreader land. A typical VIA grid is 12mil holes on a 50mil pitch. The barrel is plated to about 1.0 ounce copper. Use as many VIAs as space allows. VIAs should be plugged to prevent voids being formed between the exposed pad and PCB heat-spreader land due to solder escaping by the capillary effect. This can be avoided by tenting the VIAs with solder mask. Figure 13 16 Lead Narrow Body EP SOIC Outline