DEI1085-QMS-G

DEI1084 DEIAZ | Alldatasheet

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Technical content

©2015 Device Engineering Inc. 1 of 15 DS-MW-01084-02 Rev. H 11/24/2015

FEATURES

x ARINC specification 429 compatible x 3.3V/5.5V supply operation x Dual receiver and single transmitter interface x 32nd transmit bit can be data or parity x Self test mode x Pin compatible with HI3584 & HI8584 x Programmable label recognition x On-chip 16 label memory for each receiver x 32 x 32 FIFO for transmitter and each receiver x Independent data rate selection for transmitter and each receiver x Status register x Data scramble control x Package Options: 52L QFP, 52L CQFJ, & 64L MLPQ GENERAL DESCRIPTION The DEI1084 is a CMOS ARINC 429 Transceiver IC. It is pin compatible with the Holt HI-3584 and HI-8584 products. The DEI2084/85-Mxx versions are alternate package pin- outs of the DEI1084/85-Mxx to provide access to the /TXSEL output in the MLPQ package. The enhancements relative to the DEI1016 transceiver include: 32x32 bit FIFO for transmitter, 32x32 bit FIFO for each receiver, a status register, label recognition capability, bit timing feature and choice of scrambled or unscrambled ARINC data output. The DEI1085 version requires external serial 10KOhm resistors on the receiver inputs. This simplifies the implementation of external lightning protection networks. The DEI1084 version has on-chip 10KOhm resistors and do not require external resistors on the inputs.

ORDERING INFORMATION

Part Number Marking Package Burn In 10K Resistors Temperature DEI1084-QES-G DEI1084-QES 52L MQFP G No internal -55 / +85 ºC DEI1084-QMS-G DEI1084-QMS 52L MQFP G No internal -55 / +125 ºC DEI1084-MES-G DEI1084-MES 64L MLPQ G No internal -55 / +85 ºC DEI1084-UMS DEI1084-UMS 52L CQFJ No internal -55 / +125 ºC DEI1085-QES-G DEI1085-QES 52L MQFP G No external -55 / +85 ºC DEI1085-QMS-G DEI1085-QMS 52L MQFP G No external -55 / +125 ºC DEI1085-MES-G DEI1085-MES 64L MLPQ G No external -55 / +85 ºC DEI1085-UMS DEI1085-UMS 52L CQFJ No external -55 / +125 ºC DEI2084-MES-G DEI2084-MES 64L MLPQ G No internal -55 / +85 ºC DEI2085-MES-G DEI2085-MES 64L MLPQ G No external -55 / +85 ºC DEI2084-MMS-G DEI2084-MMS 64L MLPQ G No internal -55 / +125 ºC DEI2085-MMS-G DEI2085-MMS 64L MLPQ G No external -55 / +125 ºC DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose.

385 East Alamo Drive

Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com DEI1084/1085 ARINC 429 ENHANCED TRANSCEIVER Device Engineering Incorporated

©2015 Device Engineering Inc. 2 of 15 DS-MW-01084-02 Rev. H 11/24/2015 PIN ASSIGNMENTS

©2015 Device Engineering Inc. 3 of 15 DS-MW-01084-02 Rev. H 11/24/2015 FUNCTIONAL DESCRIPTION ANALOG FRONT END (AFE) WITH LIGHTNING PROTECTION. The AFE implements the analog detection portion of the receiver circuit. The ARINC 429 characteristic describes RX detection levels as follows. STATE DIFFERENTIAL VOLTAGE ONE +6.5V to +13V NULL +2.5V to -2.5V ZERO -6.5V to -13V The AFE detects the received ARINC line signal and converts it into a stream of digital logic levels. It consists of a pair of differential comparators per receiver capable of ±10V of common mode rejection. The AFE is powered by an on chip 2.5V voltage regulator. This makes the part capable of operating from a supply voltage ranging from 2.97V to 5.5V. The DEI1085 version parts bypass 10K ohms of the input resistors, facilitating the use of 10K external series resistors to provide lightning immunity without impacting the input resistance specifications. Lightning transient protection is provided at the receiver input pins. The receiver input pins, in combination with external 10K Ohm resistors, provide immunity to DO160 Level 3 Lightning Induced Transients. (These include the 600V peak damped sinusoid and 300V/150µs pulse). This immunity is provided by the external 10K resistors combined with the on-chip Zener diodes located within the r e c e i v e r i n p u t n e t w o r k . D u r i n g a v o l t a g e t r a n s i e n t , t h e diodes shunt current to ground and drop most of the transient voltage across the external resistors, thus protecting the chip’s input pins. When the internal resistor wire bond option is used, the application must provide Transient Voltage Suppressor (TVS) devices to limit transient voltage to ±120V.

16 BIT DATA BUS

A 16 Bit parallel bi-directional tri-state data bus provides communication to the host. SERIAL INTERFACE The DEI1084 consists of two receive channels and one transmit channel. Each receive channel operates independently of each other and the transmitter. The receive data is asynchronous to the transmitter data and can also be at a different data rate than the transmitter. TRANSMITTER The transmitter clock is free running and in phase with the transmitter data. The transmitter data (DO(A) and DO(B)) are TTL level signals. There are always at least 4 null bits between data words. An external ARINC line driver is required to interface the transmitter to the ARINC serial data bus. RECEIVER The receiver signals (DI(A) and DI(B)) are differential, bipolar, return-to-zero logic signals. The ARINC channels can be connected directly to the receiver with no external components. Table 1: DEI1084 Pin Description SIGNAL FUNCTION DESCRIPTION VDD POWER Power Input: +3V or +5V . RIN1A INPUT ARINC receiver 1 positive input. RIN1B INPUT ARINC receiver 1 negative input. RIN2A INPUT ARINC receiver 2 positive input. RIN1B INPUT ARINC receiver 2 negative input. /DR1 OUTPUT Receiver 1 data flag ready. /FF1 OUTPUT Receiver 1 FIFO full. /HF1 OUTPUT Receiver 1 FIFO half full. /DR2 OUTPUT Receiver 2 data flag ready. /FF2 OUTPUT Receiver 2 FIFO full. /HF2 OUTPUT Receiver 2 FIFO half full. SEL INPUT Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2). /EN1 INPUT Data Bus control, enables receiver 1 data to output. /EN2 INPUT Data Bus control, enables receiver 2 data to output. BD[15:0] I/O Data Bus. GND POWER Power and signal ground. /NFD INPUT No frequency discrimination if low (pull up) /PL1 INPUT Latch enable for byte 1 entered from data bus to transmitter FIFO. /PL2 INPUT Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow /PL1. TX/R OUTPUT Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. /HFT OUTPUT Transmitter FIFO half full. /FFT OUTPUT Transmitter FIFO full. 429DO OUTPUT “ONES” data output from transmitter. /429DO OUTPUT “ZEROS” data output from transmitter. /TXSEL OUTPUT Transmitter Speed Select Status. Hi = High speed, Lo = Low speed. Inverted control word “TXSEL”. ENTX INPUT Enable transmission. /CWSTR INPUT Clock for control word register. /RSR INPUT R e a d s t a t u s r e g i s t e r i f S E L = 0 , r e a d control register if SEL = 1 (pull up) CLK INPUT Master clock input. TX CLK OUTPUT Transmitter clock equal to master clock (CLK), divided by either 10 or 80. /MR INPUT Master reset.

©2015 Device Engineering Inc. 4 of 15 DS-MW-01084-02 Rev. H 11/24/2015 CONTROL REGISTER A 16-bit control register is used to configure the device. The control register bits CR0 – CR15 are loaded from BD00 – BD15 when /CWSTR is pulsed low. The control register contents are output on the data bus when SEL = 1 and /RSR is pulsed low. Each bit of the control register has the following function: Table 2: Control Register Bit definition CR Bit FUNCTION STATE DESCRIPTION

0 Data rate HI = CLK/10 CR0 Receiver 1

1 Data rate LO= CLK/80

0 Normal operation CR1 Label

1 Load 16 labels using /PL1,/PL2

Read 16 labels using /EN1, /EN2 Disable label recognition CR2 Enable Label Recognition (Receiver 1) 1 Enable label recognition

0 Disable label recognition CR3 Enable Label

(Receiver 2)

1 Enable label recognition

0 Transmitter 32nd bit is data CR4 Enable 32nd

bit as parity 1 Transmitter 32nd bit is parity

0 The 429DO and /429DO digital

outputs are internally connected to the Rx logic inputs CR5 Self Test

1 Normal operation

0 Receiver 1 decoder disabled CR6 Receiver 1

decoder 1 ARINC bits 9 and 10 must match CR7 and CR8 - - CR7 If receiver 1 decoder is enabled, the ARINC bit 9 must match this bit - - CR8 If receiver 1 decoder is enabled, the ARINC bit 10 must match this bit

0 Receiver 2 decoder disabled CR9 Receiver 2

decoder 1 ARINC bits 9 and 10 must match CR10 and CR11 - - CR10 If receiver 2 decoder is enabled, the ARINC bit 9 must match this bit - - CR11 If receiver 2 decoder is enabled, the ARINC bit 10 must match this bit

0 Transmitter 32nd bit is Odd parity CR12 Invert

1 Transmitter 32nd bit is Even parity

0 Data rate = HI = CLK/10 CR13 Transmitter

1 Data rate = LO = CLK/80

0 Data rate = HI = CLK/10 CR14 Receiver 2

0 Scramble ARINC data CR15 Data format

1 Unscramble ARINC data

The device contains a 9-bit status register which can be interrogated to determine the status of the ARINC receivers, data FIFOs and transmitter. The contents of the status register are output on BD0 - BD08 when the /RSR pin is take n low and SEL = 0. Unused bits are output as zeros. The following table defines the status register bits. Table 3: Status Register Bit Definition SR Bit FUNCTION STATE DESCRIPTION

0 Receiver 1 FIFO empty SR0 Data ready

(Receiver 1) 1 Receiver 1 FIFO contains valid data. Resets to zero when all data has been read. /DR1 pin is the inverse of this bit Receiver 1 FIFO holds less than 16 words SR1 FIFO half full (Receiver 1) 1 Receiver 1 FIFO holds at least 16 words. /HF1 pin is the inverse of this bit

0 Receiver 1 FIFO not full SR2 FIFO full

(Receiver 1) 1 Receiver 1 FIFO full. To avoid data loss, the FIFO must be read within one ARINC word period. /FF1 pin is the inverse of this bit.

0 Receiver 2 FIFO empty SR3 Data ready

(Receiver 2) 1 Receiver 2 FIFO contains valid data. Resets to zero when all data has been read. /DR2 pin is the inverse of this bit

0 Receiver 2 FIFO holds less than

(Receiver 2) 1 Receiver 2 FIFO holds at least 16 words. /HF2 pin is the inverse of this bit

0 Receiver 2 FIFO not full SR5 FIFO full

(Receiver 2) 1 Receiver 2 FIFO full. To avoid data loss, the FIFO must be read within one ARINC word period. /FF2 pin is the inverse of this bit.

0 Transmitter FIFO not empty SR6 Transmitter

FIFO empty 1 Transmitter FIFO empty

0 Transmitter FIFO not full SR7 Transmitter

FIFO full 1 Transmitter FIFO full. /FFT pin is the inverse of this bit Transmitter FIFO contains less than 16 words SR8 Transmitter FIFO half full 1 Transmitter FIFO contains at least 16 words. /HFT pin is the inverse of this bit

©2015 Device Engineering Inc. 5 of 15 DS-MW-01084-02 Rev. H 11/24/2015 DATA FORMAT Control register bit CR15 is used to control how individual bits in the received or transmitted ARINC word are mapped to the data bus during data read or write operations. Table 4 describes this mapping: Table 4: Parallel Data Bus Format, Scrambled & Not Scrambled ARINC BIT CR15 = 0 ARINC BIT CR15 = 1 DATA BUS WORD1 WORD2 WORD1 WORD2 BD00 8 Label 14 1 Label 17 BD01 7 Label 15 2 Label 18 BD02 6 Label 16 3 Label 19 BD03 5 Label 17 4 Label 20 BD04 4 Label 18 5 Label 21 BD05 3 Label 19 6 Label 22 BD06 2 Label 20 7 Label 23 BD07 1 Label 21 8 Label 24 BD08 32 Parity 22 9 SDI 25 BD09 30 23 10 SDI 26 BD10 31 24 11 27 BD11 9 SDI 25 12 28 BD12 10 SDI 26 13 29 BD13 11 27 14 30 BD14 12 28 15 31 BD15 13 29 16 32 Parity BIT TIMING The ARINC 429 characteristic describes the RX acceptance timing as follows. HIGH SPEED LOW SPEED BIT RATE 100K BPS ± 1% 12K to 14.4K BPS RISE TIME 1.5 ± 0.5 µs 10 ± 5 µs FALL TIME 1.5 ± 0.5 µs 10 ± 5 µs PULSE WIDTH 5µs ± 5% 34.5 to 41.7 µs 1. Key to the performance of timing checking logic is an a c c u r a t e 1 M H z c l o c k s o u r c e . L e s s t h a n 0 . 1 % e r r o r i s recommended. 2. The sampling shift registers are 10 bits long and must show three consecutive Ones, Zeros or Nulls to be considered valid data. Additionally, for data bits, the One or Zero in the upper bits of the sampling shift registers must be followed by a Null in the lower bits within the d a t a b i t t i m e . F o r a N u l l i n t h e w o r d g a p , t h r e e consecutive Nulls must be found in both the upper and lower bits of the sampling shift register. In this manner the minimum pulse width is guaranteed. 3. The Word Gap timer samples the Null shift register every 10 input clocks (80 for low speed) after the last data bit of a valid reception. If the Null is present, the Word Gap counter is inc remented. A count of 3 will e nable the next reception. 4 . E a c h d a t a b i t m u s t f o l l o w i t s p re d e c e s so r b y no t l e s s t h a n 8 s a m p l e s a n d n o m o r e t h a n 1 2 s a m p l e s . I n t h i s manner the bit rate is checked. With exactly 1 MHz clock frequency, the acceptable data bit rates are as follows: If the /NFD pin is HI, the device accepts signals that meet these specifications and rejects signals outside the tolerances. The way this is achieved is described below: /NFD=HI /NFD=LO LO Speed HI Speed Data Bit Rate Min 10.4KBPS 83KBPS 0.1KBPS Data Bit Rate Max 15.6KBPS 125KBPS 500KBPS If /NFD pin is held low, frequency discrimination is disabled and any data stream totaling 32 bits is accepted even with gaps between bits. The protocol still requires a word gap as defined in 4 above. RECEIVER PARITY The receiver parity circuit counts Ones received, including the parity bit. If the result is odd, then “0” will appear in the 32nd bit. RETRIEVING DATA Once ARINC 32-bit word is recognized, the receiver logic check for correct decoding and label matching prior to loading the word into (or reject the word from) the 32 x 32 re c e iv e r FIFO. If CR 2 o r CR 3 is/a re ONE, t he n AR INC words with have matching labels will be accepted into Receiver FIFO. If CR6 or CR9 is/are ONE, then ARINC words with matching decoder value (CR7, CR8 for RX1) and (CR10, CR11 for RX2) will be accepted into Receiver FIFO. The following table describes this operation: Table 5: RX Data Filter Logic CR2(3) ARINC word matches label CR6(9) ARINC word bits 9&10 match CR7&8 (10&11) FIFO

0 X 0 X Load FIFO

1 No 0 X Ignore data

1 Yes 0 X Load FIFO

0 X 1 No Ignore data

0 X 1 Yes Load FIFO

1 Yes 1 No Ignore data

1 No 1 Yes Ignore data

1 No 1 No Ignore data

1 Yes 1 Yes Load FIFO

O n c e a v a l i d A R I N C w o r d i s l o a d e d i n t o t h e F I F O , t h e DATA READY FLAG will be turned on ; /DR1 or /DR2 (or both) will go low. The data flag for a receiver will r e m a i n l o w u n t i l a l l A R I N C w o r d s a r e r e t r i e v e d a n d t h e Receiver FIFO is empty. When data ready in Receiver FIFO, data can be retrieved by activating (/EN1, SEL) or (/EN2, SEL) to output the receiver data to the 16 bit parallel bus (see table 1). Example to retrieve Receiver 1 data, first set (SEL = 0, t h e n / E N 1 = 0 ) t o p l a c e W O R D 1 o n t h e 1 6 - b i t b u s . Release the 16-bit bus with (/EN1 = 1). Next set (SEL =1, t he n / E N 1 = 0 ) f o r W O R D 2 . L a s t , re l e a s e t he 1 6 - b i t b u s with (/EN1 = 1). Use (/EN2) for Receiver 2 data retrieval. Up to 32 ARINC words may be loaded into each receiver’s FIFO. The /FF1 (/FF2) pin will go low when the receiver 1 (2) FIFO is full. Failure to retrieve data from a full FIFO

©2015 Device Engineering Inc. 6 of 15 DS-MW-01084-02 Rev. H 11/24/2015 will cause the next valid ARINC word received to overwrite the existing data in FIFO location 32. A FIFO half full flag /HF1 (/HF2) goes low if the FIFO contains 16 or more received ARINC words. The /HF1 (/HF2) pin is intended to act as an interrupt flag to the systems external microprocessor, allowing a 16 word data retrieval routine to be performed, without the user needing to continually poll the status register bits. RECEIVERS Figure 1 Receiver Function Diagram LABEL RECOGNITION The chip compares the incoming label to the stored labels i f l a b e l r e c o g n i t i o n i s e n a b l e d . I f a m a t c h i s f o u n d , t h e data is processed. If a match is not found, no indicators of receiving ARINC data are presented. Note that 00 (Hex) is treated in the same way as any other label value. Label bit significance is not changed by the status of control register bit CR15. Label bits BD00 – BD07 are always compared to receive ARINC bits 1- 8 respectively. LOADING LABELS When writing to, or reading from the label memory, SEL must be set HIGH. Write to control register with Enable Label Read/Write (set CR1 = 1) and Disable Label recognition (set CR2,3 = 0) during the label write sequence. Then the next 16 writes of data (/PL pulsed low) load the label data into each location of the label memory from the BD00 – BD07 pins. The /PL1 pin is used to write lab e l data f o r re c e iv e r 1 and /PL 2 f o r re c e ive r 2. Alw ay s write to all 16 location of label memory to ensure that no previous unwanted label memory residual affect the label recognition. Note that ARINC word reception is suspended during the label memory write sequence. Therefore, CR1 of control register has to be written with zero before returning to normal operation. READING LABELS When writing to, or reading from the label memory, SEL must be set HIGH. Write to control register with Enable Label Read/Write (set CR1 = 1) and Disable Label recognition (set CR2,3 = 0) during the label read sequence. Then the next 16 data reads of the selected receiver (/EN t a k e n l o w ) a r e l a b e l s . / E N 1 i s u s e d t o r e a d l a b e l s f o r receiver 1, and /EN2 to read labels for receiver 2. Label data is presented on BD00 – BD07. All 16 locations should be accessed, and CR1 must be written to zero before returning to normal operation.

©2015 Device Engineering Inc. 7 of 15 DS-MW-01084-02 Rev. H 11/24/2015 TRANSMITTER Figure 2 Transmitter Function Diagram FIFO OPERATION Prior to loading FIFO (TX Buffer), do these (sequence does not matter): 1) Hold ENTX at Low to stop enable transmission 2) Check if TX/R is low (which means TX Buffer is empty). Whe n the FIFO is empty and ENTX low, the n proceed to load FIFO with /PL1 and /PL2. Otherwise asserting /PL1 and /PL2 has not data loading effect to the FIFO. The FIFO is loaded sequentially by first pulsing /PL1 to load byte 1 and then /PL2 to load byte 2. The control logic automatically loads the 31 bit word (or 32 bit word if CR4 = 0) in the next available position of the FIFO. If TX/R, the transmitter ready flag is high (FIFO empty), then up to 32 words, each 31 or 32 bits long, may be loaded. If TX/R is low, then only the available positions may be loaded. If all 32 positions are full, the /FFT flag is asserted and the FIFO ignores further attempts to load data. A transmitter FIFO half-full flag /HFT is provided. When t h e t r a n s m i t F I F O c o n t a i n s l e s s t h a n 1 6 w o r d s , / H F T i s high, indicating to the system microprocessor that a 16 ARINC word block write sequence can be initiated. In normal operation (CR4 = 1), the 32nd bit transmitted is a parity bit. Odd or even parity is selected by programming control register bit CR12 to a zero or one. If CR4 is programmed to a 0, the all 32 bits of data loaded into the transmitter FIFO are treated as data and are transmitted. DATA TRANSMISSION Set ENTX to high to enable transmission, the FIFO positions are incremented with the top register loading into the data transmission shift register. Within 2.5 data clocks t h e f i r s t d a t a b i t a p p e a r s a t 4 2 9 D O a n d / 4 2 9 D O . T h e 3 2 bits in the data transmission shift register (or 31 bits plus parity bit) are presented sequentially to the outputs in the ARINC 429 format with the following timing: HI Speed LO Speed ARINC Data Bit Time 10 Clocks 80 Clocks Data Bit Time 5 Clocks 40 Clocks Null Bit Time 5 Clocks 40 Clocks Word Gap Time 40 Clocks 320 Clocks The word counter detects when all loaded positions have been transmitted and sets the transmitter ready flag, TX/R, high. Once the transmission start it will continue till the TX FIFO is empty. Setting ENTX to low at the mid point of transmission does not stop the transmission. TRANSMITTER PARITY The parity generator counts the Ones in the 31 bit word. If control register bit CR12 is set low, the 32nd bit transmitted will make parity odd. If the control bit is high, t h e p a r i t y i s e v e n . S e t t i n g C R 4 t o a z e r o b y p a s s e s t h e p a r i t y g e n e r a t o r , a n d a l l o w s 3 2 b i t s o f d a t a t o b e transmitted. MASTER RESET On a Master Reset data transmission and reception are immediately terminated, all three FIFOs cleared as are the F I F O f l a g s a t t he d e v i c e p i ns a n d i n t he S t a t u s R e g i s t e r. The Control Register is not affected by a Master Reset.

©2015 Device Engineering Inc. 11 of 15 DS-MW-01084-02 Rev. H 11/24/2015

ELECTRICAL CHARACTERISTICS

Table 6: DC Characteristics Conditions: Ta = -55 to +125 ºC, Vdd = 3.3V ± 10% and 5V ± 10% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT ARINC INPUTS: RIN[1A/1B/2A/2B] aka DI[1A/1B/2A/2B] or RIN[1A/1B/2A/2B]E aka DI[1A/1B/2A/2B]E with external 10K Ohm resistors Differential Input Voltage ONE ZERO NULL Vil Vil Vnull 6.5 -13.0 -2.5 10.0 -10.0 -13.0 -6.5 2.5 V V V Common Mode Input Voltage Vcm -10 10 V Input Resistance: Differential To GND To VDD RI RG RH 132 7500 200 100 KOhm KOhm KOhm Input Capacitance CI 20 pF LOGIC INPUTS Input Voltage HI VIH Vdd = 3.0V to 5.5V 0.7*Vdd Vdd+0.5 V Input Voltage LO VIL Vdd = 3.0V to 5.5V -0.5 0.8 V Input Pull-up Current, /NFD. /RSR pins IPU -100 µA Input Currents, all others pins IIN -10 10 µA LOGIC OUTPUTS Output Voltage: TTL Logic 1 Output Voltage: CMOS Logic 1 Output Voltage: TTL Logic 0 Output Voltage: CMOS Logic 0 VOH-T VOH-C VOL-T VOL-C IOH = -4ma IOH = -100ua IOL = 4ma IOL = 100ua Vdd -0.5 Vdd -0.1 0.4 0.1 V V V V Output Capacitance: Cout 10 pF OPERATING SUPPLY CURRENT VDD = 3.3V or 5V IDD Fck = 1MHZ IDD ~ 4*(VDD-2.7) 10 mA Supply Voltage VDD 3.0 5.5 V

©2015 Device Engineering Inc. 12 of 15 DS-MW-01084-02 Rev. H 11/24/2015 AC CHARACTERISTICS Table 7: General AC Characteristics Data Rate 100kbps Data Rate 12.5kbps PARAMETER SYMBOL MIN MAX MIN MAX UNITS 1MCK Frequency f1MCK 0.99 1.01 0.99 1.01 MHz 1MCK Duty Cycle CKDC 40 60 40 60 % 1MCK Rise/Fall Time TCRF 10 10 ns Transmitter Data Rate (1MCK = 1MHz) TDR 99 101 12.4 12.6 kbps Receiver Data Rate (1MCK = 1MHz) (DATA = 50% BIT/ 50% NULL TIME) RDR 83.3 125 10.2 15.6 kbps Receiver Data Rate No Frequency Discrimination (/NFD=0) /NFD 71.4 166 8.77 19.2 kbps AC TIMING CHARACTERISTICS Table 8: 3V AC Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS CONTROL WORD TIMING Pulse Width: /CWSTR Setup: DATA BUS Valid to /CWSTR Hi Hold: /CWSTR Hi to DATA BUS Hi-Z tCWSTR tCWSET tCWHLD ns ns ns RECEIVER FIFO AND LABEL READ TIMING Delay: Start ARINC 32nd bit to /DR Lo: High Speed Low Speed tD/R tD/R 128 µs µs Delay: /DR Lo to /EN Lo Delay: /EN Hi to /DR Hi tD/REN tEND/R 150 ns ns Setup: SEL to /EN Lo Hold: SEL to /EN Hi tSELEN tENSEL ns ns Delay: /EN Lo to DATA BUS Valid Delay: /EN Hi to DATA BUS Hi-Z tENDATA tDATAEN 80 140 100 ns ns Pulse Width: /EN1 or /EN2 Spacing: /EN Hi to next /EN Lo (Same ARINC Word) Spacing: /EN Hi to next /EN Lo (Next ARINC Word) tEN tENEN tREADEN 120 140 1033 ns ns ns TRANSMITTER FIFO AND LABEL WRITE TIMING Pulse Width: /PL1 or /PL2 tPL 80 ns Setup: DATA BUS Valid to/PL Hi Hold: /PL Hi to DATA BUS Hi-Z tDWSET tDWHLD ns ns Spacing: /PL1 to /PL2 Spacing between Label Write pulses tPL12 tLABEL ns ns Delay: /PL2 Hi to TX/R Lo tTX/R 100 ns TRANSMISSION TIMING Spacing: /PL2 Hi to ENTX Hi tPL2EN 0 ns Delay: 32nd ARINC Bit to TX/R Hi tDTX/R 50 ns Spacing: TX/R Hi to ENTX Lo tENTX/R 0 ns REPEATER OPERATION TIMING Delay: /EN Lo to /PL Lo tENPL 0 ns Hold: /PL Hi to /EN Hi tPLEN 0 ns Delay: TX/R Lo to ENTX Hi tTX/REN 0 ns MASTER RESET PULSE WIDTH tMR 80 ns ARINC DATA RATE AND BIT TIMING ± 1% Table 9: 5V AC Characteristics

©2015 Device Engineering Inc. 13 of 15 DS-MW-01084-02 Rev. H 11/24/2015 PARAMETER SYMBOL MIN TYP MAX UNITS CONTROL WORD TIMING Pulse Width: /CWSTR Setup: DATA BUS Valid to /CWSTR Hi Hold: /CWSTR Hi to DATA BUS Hi-Z tCWSTR tCWSET tCWHLD ns ns ns RECEIVER FIFO AND LABEL READ TIMING Delay: Start ARINC 32nd bit to /DR Lo: High Speed Low Speed tD/R tD/R 128 µs µs Delay: /DR Lo to /EN Lo Delay: /EN Hi to /DR Hi tD/REN tEND/R 100 ns ns Setup: SEL to /EN Lo Hold: SEL to /EN Hi tSELEN tENSEL ns ns Delay: /EN Lo to DATA BUS Valid Delay: /EN Hi to DATA BUS Hi-Z tENDATA tDATAEN 140 100 ns ns Pulse Width: /EN1 or /EN2 Spacing: /EN Hi to next /EN Lo (Same ARINC Word) Spacing: /EN Hi to next /EN Lo (Next ARINC Word) tEN tENEN tREADEN 120 140 1033 ns ns ns TRANSMITTER FIFO AND LABEL WRITE TIMING Pulse Width: /PL1 or /PL2 tPL 80 ns Setup: DATA BUS Valid to/PL Hi Hold: /PL Hi to DATA BUS Hi-Z tDWSET tDWHLD ns ns Spacing: /PL1 to /PL2 Spacing between Label Write pulses tPL12 tLABEL ns ns Delay: /PL2 Hi to TX/R Lo tTX/R 100 ns TRANSMISSION TIMING Spacing: /PL2 Hi to ENTX Hi tPL2EN 0 ns Delay: 32nd ARINC Bit to TX/R Hi tDTX/R 50 ns Spacing: TX/R Hi to ENTX Lo tENTX/R 0 ns REPEATER OPERATION TIMING Delay: /EN Lo to /PL Lo tENPL 0 ns Hold: /PL Hi to /EN Hi tPLEN 0 ns Delay: TX/R Lo to ENTX Hi tTX/REN 0 ns MASTER RESET PULSE WIDTH tMR 50 ns ARINC DATA RATE AND BIT TIMING ± 1% ABSOLUTE MAXIMUM RATINGS Table 10: Absolute Maximum Ratings PARAMETER SYMBOL MIN MAX UNITS Supply Voltage VDD -0.5 +7.0 V DC Input Voltage, Logic inputs VIN-logic -0.6 VCC + 0.6 V DC Input Voltage, RX pins: RIN[1A/1B/2A/2B] aka DI[1A/1B/2A/2B] RIN[1A/1B/2A/2B]E aka DI[1A/1B/2A/2B]E at external 10K ohm series resistor VIN-rx VIN-rxe ±120 ±120 V Clamp diode current, any pin except RX inputs ±25 mA DC Output Current per pin ±25 mA DCV or GND current per pin ±50 mA Storage Temperature Tstg -65 +150 °C Junction Temperature, operating TJmax +145 °C

©2015 Device Engineering Inc. 14 of 15 DS-MW-01084-02 Rev. H 11/24/2015 ESD PROTECTION ESD protection is provided on all pins per 2KV HBM specification, except the receiver input pins. These will be limited to input resistor rupture voltage of ~1KV. PACKAGE DESCRIPTION Table 11 Package Characteristics PACKAGE TYPE PACKAGE REF THERMAL RESIST. șJC / șJA (ºC/W) JEDEC MOISTURE SENSITIVITY LEVEL & PEAK BODY TEMP LEAD FINISH MATERIAL / JEDEC Pb-Free DESIGNATION Pb Free Designation JEDEC MO 52L METRIC QUAD FLAT PACK 52L MQFP G 21 / 65 MSL 3 260ºC Matte Sn RoHS Compliant MS-022- AC 52L CERAMIC QUAD FLAT J- LEAD

52 CQFJ TBD HERMETIC Au

260ºC Matte Sn RoHS Compliant MO-220- VMMD Figure 13 52L MQFP G