DEI1022 DEIAZ | Alldatasheet

Document overview

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Technical content

Features

  • ARINC 429 Line Driver for high speed (100 KHz) and low speed (12.5 KHz) data rates.
  • Adjustable Slew rates via external capacitors.
  • Small foot print (14L SOIC NB)
  • Programmable output differential range via VREF pin.
  • Drives full ARINC load of 400 Ω and 30 nF.
  • -55 ºC to +85 ºC operating temperature range.
  • 100% Final testing. Functional Description The ARINC 429 Line Driver Circuit is a bipolar monolithic IC designed to meet the requirements of several general aviation serial data bus standards. These include the differential bipolar RZ types such as ARINC 429, ARINC 571, and ARINC 575. The DEI1022, DEI1023, DEI1024, and DEI1025 are a family of ARINC Line Driver circuits with variations in driver output resistance and output fusing. See the Product Matrix definition table below to find the correct version for your application. Serial data is presented on DATA(A) and DATA(B) logic inputs in the dual rail format of the DEI1016. The driver is enabled by the SYNC and CLOCK inputs. The output voltage level is programmed by the VREF input and is normally tied to +5VDC along with V1 to produce output levels of +5 volts, 0 volts, and -5 volts on each output for ±10 volt differential outputs. The driver output resistance of the DEI1022 and DEI1023 is 75Ω at room temperature; 37.5Ω on each output. The driver output resistance of the DEI1024 and the DEI1025 is zero. The output slew rate is controlled by external timing capacitors on CA and CB. Typical values are 75pF for 100KHz and 500pF for 12.5KHz data. Figure 1 Pinout Device Engineering Incorporated

385 East Alamo Drive

Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com DEI1022, DEI1023 DEI1024, DEI1025 ARINC 429 Line Driver Integrated Circuit

©2018 Device Engineering Incorporated Page 2 of 10 DS-MW-01022-01 Rev. E 04/18/2018 Pin # Pin Name Table 2: Pin Descriptions

1 V REF

Analog Input. The voltage on VREF sets the output voltage levels on AOUT and BOUT. The output logic levels swing between +VREF, 0 volts, and –VREF volts.

2 NC No Connect

3 SYNC Logic input. Logic 0 forces outputs to NULL state. Logic 1 enables data transmission. 13 CLOCK Logic input. Logic 0 forces outputs to NULL state. Logic 1 enables data transmission. DATA(A) DATA(B) Logic inputs. These signals contain the Serial Data to be transmitted on the ARINC 429 data bus CA CB Analog Nodes. External timing capacitors are tied from these points to ground to establish the output signal slew rate. Typical CA = CB = 75pF for 100 kHz data and CA = CB = 500pF for 12.5 kHz data.* AOUT BOUT Outputs. These are the line driver outputs which are connected to the aircraft serial data bus. 7 -V Negative Supply Input. –15VDC nominal. 8 GND Ground. 9 +V Positive Supply Input. +15VDC nominal. 14 V 1 Logic Supply Input. +5VDC nominal. *CA and CB pin voltages swing between +/-5 volts. Any electronic switching of the capacitor on the pins must not inhibit the full voltage swings. Figure 2 Function Diagram

©2018 Device Engineering Incorporated Page 3 of 10 DS-MW-01022-01 Rev. E 04/18/2018 Table 3: Truth Table INPUTS OUTPUTS SYNC CLOCK DATA(A) DATA(B) AOUT BOUT STATE L X H H H H X L H H H H X X L H H L X X L H L H +VREF -VREF -VREF +VREF NULL NULL NULL NULL ONE ZERO NOTE: X = Don’t Care DATA(A) DATA(B) +VREF +V REF -V REF -V REF A OUT B OUT Figure 3 Input / Output Waveforms

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Electrical Characteristics

Table 5: Operating Conditions PARAMETER SYMBOL MIN TYP MAX UNITS Positive Supply Voltage +V +11.4 +16.5 V Negative Supply Voltage -V -11.4 -16.5 V V1 V 1 +4.75 +5 +5.25 V VREF (For ARINC 429) V REF +4.75 +5 +5.25 V Operating Temperature T A -55 +85 °C Table 6: Power Dissipation 100% Duty Cycle, Full Load = 400Ω / 30nF, Half Load = 4,000Ω / 10nF DATA RATE LOAD +V @ 15V -V @ -15V V1, VREF @ Pd POWER LOAD POWER 0 to 100kbps NONE 2 mA 5 mA 4 mA 125 mW 0 mW 12.5kbps FULL 16 mA 19 mA 4 mA 485 mW 60 mW 100kbps FULL 48 mA 51 mA 4 mA 1194 mW * 325 mW 12.5kbps HALF 6 mA 8 mA 4 mA 196 mW 30 mW 100kbps HALF 22 mA 25 mA 4 mA 561 mW 162 mW Note: * May require heat sink @ TA = +85°C Table 4: Absolute Maximum Ratings PARAMETER SYMBOL RATING UNITS Voltage between pins +V and –V 40 V V1 Maximum Voltage V 1 7 V VREF Maximum Voltage V REF 6 V Logic Inputs (GND-0.3V) to (V1 + 0.3V) V Peak Body Temperature 260 °C Storage Temperature T STG -65 to +150 °C Max Junction Temperature Die Limit (short term operation) TJ MAX1 +175 °C Max Junction Temperature Plastic Package Limit (prolonged operation) TJ MAX2 +145 °C Output Short Circuit Duration See Note 1 Output Over-Voltage Protection See Note 2 Power Dissipation See Table 6 Notes: 1. One output at a time can be shorted to ground indefinitely. Both outputs can be shorted indefinitely to ground or to each other for TA < 45° C and Data Duty Cycle < 40%. 2. Both DEI1023 and DEI1025 outputs are fused at between 0.5 Amp DC and 1.0 Amp DC to prevent an over-voltage fault from coupling onto the system power bus. The DEI1022 and DEI1024 outputs are not fused. External fusing must be provided to meet the Transmitter Fault Isolation of the ARINC 429 Specification.

©2018 Device Engineering Incorporated Page 5 of 10 DS-MW-01022-01 Rev. E 04/18/2018 Table 7: DC Electrical Characteristics Conditions: Temperature: -55°C to +85°C, +V = +11.4 V to +16.5 V, –V = -11.4 V to –16.5 V, V1 = VREF = +5 V ±5% SYMBOL PARAMETER MIN TYP MAX UNIT TEST CONDITIONS IQ+V Quiescent +V supply current - 2 - mA No Load. DATA = CLOCK = SYNC = LOW IQ-V Quiescent -V supply current - 5 - mA No Load. DATA = CLOCK = SYNC = LOW IQV1 Quiescent V1 supply current - 4 - mA No Load. DATA = CLOCK = SYNC = LOW IQVREF Quiescent VREF supply current - 10 - uA No Load. DATA = CLOCK = SYNC = LOW VIH Logic 1 Input V 2.0 - - V No Load. VIL Logic 0 Input V - - 0.6 V No Load. IIH Logic 1 Input I - - 10 uA VIH = 2.0V IIL Logic 0 Input I - - -20 uA VIL = 0.6V IOHSC Output Short Circuit Current (Output High) - - -80 mA Short to Ground IOLSC Output Short Circuit Current (Output Low) 80 - - mA Short to Ground VOH Output Voltage HIGH. ( +1) VREF - 250mV VREF VREF + 250mV V No Load. VNULL Output Voltage NULL. ( 0 ) -250 - +250 mV No Load. VOL Output Voltage LOW. ( -1) -VREF – 250mV -VREF -VREF + 250mV V No Load. 429 Mode. ICT Timing Capacitor Charge Current CA (+1) CB (-1) CA (-1 ) CB (+1) - +200 –200 - uA uA No Load. SYNC = CLOCK = HIGH CA and CB held at zero volts. ISC (+V) +V Short Circuit Supply Current - - +150 mA Output short to ground ISC (-V) -V Short Circuit Supply Current - - -150 mA Output short to ground ROUT Resistance on each output See Note Ω Room Temp Only CIN Input Capacitor - - 15 pF by design Note: For DEI1022 and DEI1023, the typical resistance on each output is 30 to 45W. For DEI1024 and DEI1025, the resistance on each output is 0 W.

©2018 Device Engineering Incorporated Page 7 of 10 DS-MW-01022-01 Rev. E 04/18/2018 Thermal Management Device power dissipation varies greatly as a function of data rate, load capacitance, data duty cycle, and supply voltage. Proper thermal management is important in designs operating at the HI speed data rate (100KBS) with high capacitive loads and high data duty cycles. Power dissipation may be estimated from Table 6 “Power Dissipation Table”. Device power dissipation (Pd) is indicated for 100% data duty cycle with no word gap null times and should be adjusted for the appropriate data duty cycle (DC). Pd(application) = DC * [Pd(table) - 145mW] + 145mW, where DC is the application data duty cycle, Pd(table) is the Pd from the table for the indicated data rate and bus load, and 145mW is the quiescent power. The application’s data duty cycle (DC) for 100KBS operation is calculated as: DC = total bits transmitted in 10 sec period / 1,000,000 = 32 x total ARINC words transmitted in 10 sec period / 1,000,000 Heat transfer from the IC package should be maximized. Use maximum trace width on all power and signal connections at the IC. Place vias on the signal/power traces close to the IC to maximize heat flow to the internal power planes. If possible, design a solid heat spreader land under and beyond the IC to maximize heat flow from the device.

Applications

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Package Information

Table 9: Package Characteristics Characteristic Value REFERENCE 14 SOIC NB G THERMAL RESISTANCE: qJA (2 layer PCB) 115 °C/W qJA (4 layer PCB with Power Planes) 88 °C/W qJC 37 °C/W JEDEC MOISTURE SENSITIVITY LEVEL (MSL) MSL 1 / 260°C LEAD FINISH MATERIAL / JEDEC Pb-free CODE NiPdAu Pb-Free DESIGNATION RoHS Compliant JEDEC REFERENCE MS-012-AB Figure 8: Mechanical Outline

©2018 Device Engineering Incorporated Page 10 of 10 DS-MW-01022-01 Rev. E 04/18/2018 Table 10: Screening Process SCREENING METHODS ELECTRICAL TEST: ROOM TEMPERATURE 100% HIGH TEMPERATURE 100% @ +125 °C LOW TEMPERATURE 0.65% AQL@-55°C DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose. Table 11: Ordering Information DEI PART NUMBER MARKING (1) PACKAGE TEMPERATURE RANGE OUTPUT RESISTOR OUTPUT FUSE DEI1022-G DEI1022 E4 14 SOIC NB G -55 / +85 °C 37.5 W NO DEI1023-G DEI1023 E4 14 SOIC NB G -55 / +85 °C 37.5 W YES DEI1024-G DEI1024 E4 14 SOIC NB G -55 / +85 °C 0 W NO DEI1025-G DEI1025 E4 14 SOIC NB G -55 / +85 °C 0 W YES Notes: 1. All packages marked with Lot Code and Date Code. “E4” after Date Code denotes Pb Free category.