DEI1016

DEI1016 DEIAZ | Alldatasheet

Document overview

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Technical content

Features

• Two Receivers and One Transmitter
• Industry Standard Pin for Pin Replacement Part
• Wraparound Self-Test mode
• Word length can be configured for 25 bit or 32 bits operation
• Parity Status and generation of Receive and Transmit Words
• 8 Word Transmitter buffer
• Low Power CMOS
• Supports multiple ARINC protocols: 429, 571, 575, 706
• Available in extended (-55/+85°C) and Military (-55/+125°C) temperature ranges
• Available in QFP, PLCC, LCC and CDIP packages General Description: The DEI1016 provides an interface between a standard avionics type serial digital data bus and a 16-bit-wide digital data bus. The interface circuit consists of a single channel transmitter with an 8X32 bit buffer, two independent receive channels, and a host programmable control register to select operating options. The two receiver channels operate identically, each providing a direct electrical interface to an ARINC data bus. The transmitter circuit contains an 8 word by 32 bit buffer memory and control logic which allows the host to write a block of data into the transmitter. The block of data is transmitted automatically by enabling the transmitter with no further attention by the host computer. Data is transmitted in TTL format on the D0(A)/D0(B) output pins. The signal format is compatible with DEI’s extensive line of ARINC 429 Line drivers for easy connection to the ARINC data bus. DEI1016/DEI1016A/DEI1016B ARINC 429 Transceiver Family

385 East Alamo Drive

Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: info@deiaz.com Device Engineering Incorporated Control Register TX FIFO

8 Words X 32 Bits

/DR1, /DR2 TXR /OE1, /OE2 /LD1, /LD2 ENTX /LDCW /DBCEN /MR Figure 1: DEI1016 Block Diagram

© 2018 Device Engineering Inc. Page 2 of 16 DS-MW-01016-01 Rev G 5/2/2018 Table 1: DEI 1016 Absolute Maximum Ratings PARAMETER SYMBOL MIN MAX UNITS Supply Voltage V DD -0.5 +7.0 V DC Input Voltage (except pins DI1(A,B) and DI2(A,B)) V IN -0.6 V CC + 0.6 V Voltage at pins DI1(A,B) and DI2(A,B) V IN ±29 V Clamp diode current, any pin except DI inputs ±25 mA DC Output Current per pin ±25 mA DCV or GND current per pin ±50 mA Storage Temperature T STG -65 +150 °C Junction Temperature, operating T Jmax +145 °C Lead Temperature (soldering, 10 sec) T Lead +275 °C 1MCK Clock Frequency 1.16 MHz Table 2: DEI 1016 DC Electrical Characteristics Unless noted, operating conditions: VDD = 5V ± 10%, Extended Temp Devices: Ta = -55ºC to +85ºC, Military Temp Devices: Ta = -55ºC to +125ºC PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ARINC LINE INPUTS Logic 1 Input Voltage V IH V DIFF DI(A) and DI(B) 6.5 10 13 V Logic 0 Input Voltage V IL V DIFF DI(A) and DI(B) -6.5 -10 -13 V Null Input Voltage V NUL V DIFF DI(A) and DI(B) -2.5 0 +2.5 V Common Mode Voltage V CM -5 +5 V Differential Input Impedance R I 12 kW Input Impedance to VDD R H 12 kW Input Impedance to GND R G 12 kW Differential Input Capacitance C I 20 pF Input Capacitance to VDD C H 20 pF Input Capacitance to GND C G 20 pF LOGIC INPUTS (including bi-directional) Low Level Input Voltage V IL 0.8 V High Level Input Voltage V IH 2.0 V Input Leakage Current I IN V IN = GND to VDD -10 +10 mA Input Capacitance C IN 15 pF LOGIC OUTPUTS (including bi-directional) High Level Output Voltage V OH IOH = 20mA (CMOS) IOH = 6mA (TTL) VDD – 0.1 2.7 V Low Level Output Voltage V OL IOL = 20mA (CMOS) IOL = 6mA (TTL) 0.1 0.4 V POWER SUPPLY INPUT Supply Current I DD 1MCK = 1MHz 5 10 mA Supply Voltage V DD 4.5 5 5.5 VDC

© 2018 Device Engineering Inc. Page 3 of 16 DS-MW-01016-01 Rev G 5/2/2018 Table 3: DEI 1016 AC Electrical Characteristics PARAMETER SYMBOL Data Rate 100kbps Data Rate 12.5kbps MIN MAX MIN MAX UNITS 1MCK Frequency f 1MCK 1.01 1.01 MHz 1MCK Duty Cycle CK DC 40 60 40 60 % 1MCK Rise/Fall Time T CRF 10 10 ns Master Reset Pulse Width T MR 200 200 ns Transmitter Data Rate (1MCK = 1MHz) T DR 99 101 12.4 12.6 kbps Receiver Data Rate (1MCK = 1MHz),(DATA = 50% BIT/ 50% NULL TIME) RDR 95 105 8.0 14.5 kbps Table 4: Pin Definitions SYMBOL DEFINITION VDD Power Input. +5VDC ±10% GND Power Return and Signal Ground. DI1(A) ARINC 429 Input. Receiver Channel 1, “A” input DI1(B) ARINC 429 Input. Receiver Channel 1, “B” input DI2(A) ARINC 429 Input. Receiver Channel 2, “A” input DI2(B) ARINC 429 Input. Receiver Channel 2, “B” input /DR1 Logic Output. Data Ready, Receiver 1. A Low output indicates valid data in receiver 1. /DR2 Logic Output. Data Ready, Receiver 2. A Low output indicates valid data in receiver 2. SEL Logic Input. Receiver word select. A Low input selects receiver Word 1; Hi selects Word 2 to be read on D[15:0] port. /OE1 Logic Input. Receiver 1 Output Enable. A Low input enables the D[15:0] port to output Receiver 1 data. Word 1 or Word 2 will be output as determined by the SEL input. /OE2 Logic Input. Receiver 2 Output Enable. A Low input enables the D[15:0] port to output Receiver 2 data. Word 1 or Word 2 will be output as determined by the SEL input. D[15:0] Logic Input / Tri-state Output. This 16-bit bi-directional data port is the uP data interface. Receiver data is read from this port. Control Register and Transmitter FIFO data is written into this port. /LD1 Logic Input. Load Transmitter Word 1. A Low input pulse loads Word 1 into the Transmitter FIFO from D[15:0]. /LD2 Logic Input. Load Transmitter Word 2. A Low input pulse loads Word 2 into the Transmitter FIFO from D[15:0]. TXR Logic Output. Transmitter Ready. A Hi output indicates the Transmitter FIFO is empty and ready to accept new data. DO(A) Logic Output. Transmitter serial data ‘A’ output. This is a return-to-zero format signal which will normally feed an ARINC 429 Line Driver IC. A Hi output indicates the Transmitter data bit is a 1. The signal returns to zero for second half of bit time. DO(B) Logic Output. Transmitter serial data ‘B’ output. This is a return-to-zero format signal which will normally feed an ARINC 429 Line Driver IC. A Hi output indicates the Transmitter data bit is a 0. The signal returns to zero for second half of bit time. ENTX Logic Input. Enable Transmitter. A Hi input enables the Transmitter to send data from the Transmitter FIFO. This must be Low while writing data into Transmitter FIFO. Transmitter memory is cleared by high-to-low transition. /LDCW Logic Input. Load Control Register. A Low input pulse loads the Control Register from D[15:0]. 1MCK Logic Input. External Clock. Master clock used by both the Receivers and Transmitter. The 1MHz rate is a X10 clock for the HI data rate (100 kbps), and a X80 clock for LO data rate (12.5 kbps). TXCK Logic Output. Transmitter Clock. This outputs a clock frequency equal to the transmit data rate. The clock is always enabled and in phase with the data. The output is Hi during the first half of the data bit time. /MR Logic Input. Master Reset. A Lo input resets the Transmitter FIFO, bit counters, word counter, gap timers, /DRx, and TXR. The Control Register is not affected. Used on power up and system reset. /DBCEN Logic Input with internal pull up to V DD. Data Bit Control Enable. A Low input enables the transmitter parity bit control function as defined by control register bit 4 (PAREN). A Hi input forces transmitter parity bit insertion regardless of PAREN value. The pin is normally left open or tied to ground.

© 2018 Device Engineering Inc. Page 4 of 16 DS-MW-01016-01 Rev G 5/2/2018 Table 6: DEI1016 Control Word NAME DATA BIT DESCRIPTION PAREN D4 Transmitter Parity Enable. Enables parity bit insertion into transmitter data bit 32. Parity is always inserted if /DBCEN is open or HI. If /DBCEN is LO, Logic “0” on PAREN inserts data on bit 32, and Logic “1” on PAREN inserts parity on bit 32. /SLFTST1 D5 Self Test Enable. Logic “0” enables a “wrap around” test mode which internally connects the transmitter outputs to both receiver inputs, bypassing the receiver front end. The test data is inverted before going into receiver 2 so that its data is the complement of that received by receiver 1. The transmitter output is active during test mode. SDEN12 D6 S/D Code Check Enable for receiver 1. Logic “1” enables the Source/Destination Decoder for receiver 1. X1, Y12 D7, D8 S/D compare code RX1. If the receiver 1 S/D code check is enabled (SDENB1=1), then incoming receiver data S/D fields will be compared to X1, Y1. If they match, the word will be accepted by receiver 1; if not, it will be ignored. X1 (D7) is compared to serial data bit 9, Y1 (D8) is compared to serial data bit 10. SDEN22 D9 S/D Code Check Enable for receiver 1. Logic “1” enables the Source/Destination Decoder for receiver 1. X2, Y22 D10, D11 S/D compare code RX2. If the receiver 2 S/D code check is enabled (SDENB2=1), then incoming receiver data S/D fields will be compared to X2, Y2. If they match, the word will be accepted by receiver 2; if not, it will be ignored. X2 (D10) is compared to serial data bit 9, Y2 (D11) is compared to serial data bit 10. PARCK D12 Parity Check Enable. Logic “1” inverts the transmitter parity bit for test of parity circuits. Logic “0” selects normal odd parity; logic “1” selects even parity. TXSEL3 D13 Transmitter Data Rate Select. Logic “0” sets the transmitter to the HI data rate. HI rate is equal to the clock rate divided 10. Logic “1” sets the transmitter to the LO data rate. LO rate is equal to the clock rate divided by 80. RCVSEL4 D14 Receiver Data Rate Select. Logic “0” sets both receivers to accept the HI data rate. The nominal HI data rate is the input clock divided by 10. Logic “1” sets both receivers to the LO data rate. The nominal LO data rate is the input clock divided by 80. WLSEL5 D15 Word Length Select. Logic “0” sets the transmitter and receivers to a 32 bit word format. Logic ”1” sets them to a 25 bit word format. NOT USED D0-D3 When writing to the control register, the four “not used bits” are “don’t care” bits. These four bits will not be used on the chip. NOTES 1) The test mode should always conclude with ten null’s. This step prevents both receivers from accepting invalid data. 2) SDENBn, Xn & Yn should be changed within 20 bit times after /DRn goes low and the bit stream has been read, or within 30 bit times after a master reset has been removed. 3) TXSEL should only be changed during the time that TXR is high or Master Reset is low. 4) RCVSEL should be changed only during a Master Reset pulse. If changed at any other time, then the next bit stream from both Receiver 1 and Receiver 2 should be ignored. 5) When the control word is written the effect of the WLSEL bit will take effect immediately on the first complete ARINC word received or transmitted following the control word write operation. Functional Description: The DEI 1016 supports a number of various options which are selected by data written into the control register. Data is written into the control register from the 16-bit data bus when the /LDCW signal is pulsed to a logic “0”. The twelve control bits control the following functions: 1) Word Length (32 or 25 bits) 2) Transmitter bit 32 (Parity or Data) 3) Wrap around self test. 4) Source Destination code checking of received data. 5) Transmitter parity (even or odd) 6) Transmitter and Receiver data rate (100 or 12.5 kbps) Table 5: Control Register Format BIT SYMBOL BIT SYMBOL D15 (MSB) WLSEL D7 X1 D14 RCVSEL D6 SDENB1 D13 TXSEL D5 /SLFTST D12 PARCK D4 PAREN D11 Y2 D3 NOT USED D10 X2 D2 NOT USED D9 SDENB2 D1 NOT USED D8 Y1 D0 NOT USED

© 2018 Device Engineering Inc. Page 5 of 16 DS-MW-01016-01 Rev G 5/2/2018 Data Format: The ARINC serial data is shuffled and formatted into two 16 bit words (WORD1 and WORD2) used by the bi-directional data bus interface. Figure 2 shows the mapping between the 32 bit ARINC serial data and the two data words. Figure 3 describes the mapping for the 25 bit serial word used when control register bit WLSEL is set to logic “1”. Figure 2: Mapping of Serial Data to/from Word 1 and Word 2 in 32 bit format. Figure 2: Mapping of Serial Data to/from Word 1 and Word 2 in 25 bit format. 29 262728 123432 31 30 22 19202125 24 23 15 12131418 17 16 8 56711 10 9 123415 121314 08 56711 10 9 123415 121314 08 56711 10 9 PARITY SSM SIGN DATA MSB LSB S/D or DATA LABEL LSB MSB SIGN DATA MSB DATA LSB S/D or DATA SSM PARITY LABEL LSB MSB Word 2 Format Word 1 Format BIT FUNCTION BIT FUNCTION

32 Bit ARINC Serial Data Format (Bit 1 is Transmitted First)

123422 19202125 24 23 15 12131418 17 16 8 56711 10 9 123415 121314 08 56711 10 9 123415 121314 08 56711 10 9 PARITY DATA MSB LSB LABEL LSB MSB DATA MSB NOT USED PARITY LABEL LSB MSB Word 2 Format Word 1 Format BIT FUNCTION BIT FUNCTION

25 Bit ARINC Serial Data Format (Bit 1 is Transmitted First)

© 2018 Device Engineering Inc. Page 6 of 16 DS-MW-01016-01 Rev G 5/2/2018 Receiver Operation: Since the receivers function identically, only one will be discussed in detail. The receiver consists of the following circuits. Line Receiver The front end of the Line Receiver functions as a voltage level translator. It transforms the ±10 volt differential ARINC data signals into 5 Volt internal logic levels. The line receivers are protected against shorts to ±29 Volts and provides common mode voltage rejection. The outputs of the Line Receiver are one of two inputs to the Self-Test Data Selector. The other input to the Data Selector is the self-test signal from the transmitter section. The self-test signals are inverted going into Receiver 2. The data selector is controled by Control Register bit D5 (SLFTST). the received word has an odd number of 1’s (no error). Logic “1” indicates the received word has an even number of 1’s (error condition). If the data format has data in bit 32 instead of parity, the user software must calculate the value of the 32nd bit. If Word 1 and Word 2 together have an even number of 1’s, then data bit 32 is a logic “1”. Otherwise, it is a logic “0”. Data Access To access the receiver data, the user sets the receiver data select input (SEL) to a logic “0” and pulses the output enable (/OEn) line with a logic “0”. This causes Data Word 1 to be placed on the 16 bit data bus. To read Word 2, the user sets the data select input (SEL) to a logic “1” and pulses the output enable (/OEn) low to place Word 2 on the data bus. When both Word 1 and Word 2 have been read, DRn will be reset. This reset is triggered by the leading edge of the final /OEn pulse. Word 1 must be read first, then Word 2. If a new data word is received before the previous data has been read from the receiver buffer (as indicated by the /DRn signal flip-flop), the receive buffer will not be over written by the new data. The new data will remain in the shift register until either the /DRn signal is reset and it can be written into the receive buffer or it is overwritten by the next incoming data word. Data in the shift register will be overwritten by new incoming data, while data that has been latched into the receive buffer can not be overwritten. Data Error Conditions If the receiver input data word string is broken before the entire data word is received, the receiver will reset and ignore the partially received data word. If the receiver input data word string is not properly framed with at least 1 null bit before the word and 1 null bit after the word, the receiver will reset and ignore the improperly framed data word. Transmitter Operation: The transmitter section consists of an 8 word by 32 bit FIFO, parity generator, transmitter word gap timer, and a TTL output circuit. FIFO Buffer The 8x32 buffer memory allows the user to load up to 8 words into the transmitter, enable it, and then ignore it while the transmitter ships out the data without further attention. Data is loaded into the buffer by pulsing /LD1 to load the first 16 bits (WORD 1) from the data bus, and pulsing /LD2 to load WORD 2. /LD1 must always precede /LD2. The transmitter must always be disabled while loading the buffer (ENTX = logic "0"). If the buffer is full and new data is pulsed with /LD1 and /LD2, the last 32 bit word in the buffer will be overwritten. Data will remain in the buffer until ENTX is pulsed to a logic “1”, which will activate the FIFO clock and data is shifted out serially to the transmitter driver. Figure 4: Line Receiver Block Diagram Incoming Data The incoming data (either self test or ARINC) is triple sampled by the word gap timer to generate a data clock. The start of each bit is first detected and then verified two receive-clock cycles later. The receive clock is 1MHz for HI speed and 125 KHz for LO speed operation and is generated by the Receiver/Transmitter timing circuit. The receive clock is ten times the normal data rate to ensure no data ambiguity. Data Clock The derived data clock then shifts the data down a 32 bit long Data Shift Register. The data word length is selectable for either 25 or 32 bits long by Control Register Bit WLSEL. As soon as the data word is completely received, an internal signal is generated by the word gap timer circuit to enable loading data into the 32 bit receive buffer latch. S/D Decoder The Source/Destination decoder compares the user set code (X and Y) with bits 9 and 10 of the data word. The decoder can be enabled and disabled by the SDENB bit of the Control Register. If the two codes are matched, a signal is generated to latch in the received data into the receiver buffer. Otherwise the data word is ignored and not latched into the receive buffer. If the data is latched, the data ready flag (/DRn) is set to indicate to the user that a valid data word is ready to be read. Parity Control The parity of the incoming message is checked when either word of the receiver is read. Logic “0” indicates Self-Test Data Selector SLFTST DO(A) DI1(A) DI1(B) Comparator To Receive Decoder

© 2018 Device Engineering Inc. Page 10 of 16 DS-MW-01016-01 Rev G 5/2/2018 Figure 10: Transmitter Timing Diagram Table 7: DEI 1016 AC Timing Characteristics PARAMETER SYMBOL Data Rate 100kbps Data Rate 12.5kbps MIN MAX MIN MAX UNITS WRITE CYCLE TIMING /LD1, /LD2 and /LDCW Pulse Width t PWLD 130 130 ns Delay between consecutive Load Pulses t LL 0 0 ns Data to /LDÝ Set-Up Time tSDW 110 110 ns Data to /LDÝ Hold Time tHDW 0 0 ns Delay /LD2Ý to TXRß tDTXR 840 840 ns READ CYCLE TIMING Delay, Bit 32/25 in to /DRß tDDRN 16 128 ms Delay, /DRnß to /OEnß tDDROE 0 0 ns /OE1 or /OE2 Pulse Width t PWOE 200 200 ns Delay between consecutive /OE pulses t OEOE 50 50 ns Delay, 2nd /OEÝ to /DRnÝ tDOEDR 200 200 ns SEL to /OEß to valid data tSSEL 20 20 ns SEL to /OEÝ hold time tHSEL 20 20 ns Delay /OEß to valid data tDDR 200 200 ns SEL to /OEÝ to data HI-Z tDTS 10 50 10 50 ns TRANSMITTER TIMING Delay, ENTXÝ to output data1 tDTD 25 200 ms Output Data null time t NUL 4.95 5.05 39.6 40.4 ms Output data bit time t BIT 4.95 5.05 39.6 40.4 ms Data skew between TXCKÝ (ß) and DOÝ (ß) tSKTX 0 ±50 0 ±50 ns Data word gap time t GAP 39.6 40.4 316.8 323.2 ms Delay, end of TX Word to TXRÝ tDTXR 50 50 ns Delay, TXRÝ to ENTXß tDENTX 0 0 ns 1. This applies only when there has been a 4-bit null since the end of the transmitted data.

© 2018 Device Engineering Inc. Page 11 of 16 DS-MW-01016-01 Rev G 5/2/2018 Figure 11: Terminal Connections Serial Interface: The DEI1016 consists of two receive channels and one transmit channel. Each receive channel operates independently of each other and the transmitter. The receive data is asynchronous to the transmitter data and can also be at a different data rate than the transmitter. Transmitter The transmitter clock is free running and in phase with the transmitter data. The transmitter data (DO(A) and DO(B)) are TTL level signals. There are always at least 4 null bits between data words. An external ARINC line driver is required to interface the transmitter to the ARINC serial data bus. See ARINC 429 LINE DRIVERS below. Receiver The receiver signals (DI(A) and DI(B)) are differential, bipolar, return-to-zero logic signals. The ARINC channels can be connected directly to the receiver with no external components. ARINC 429 Line Driver Device Engineering offers a complete line of ARINC line drivers ICs that support the ARINC 429, 571, and 575 standards. Refer to DEI website at: http://www.deiaz.com. 3 2 1 44 24232221201918 6 5 4 DI1(B) DI1(A) /DBCEN DI2(A) DI2(B) GND N/C N/C D10 DO(B) DO(A) /LD1 /OE1 D15 D14 D12 D11 /OE2 TXR /LD2 D13 44L PLCC CLCC N/C N/C /LDCW ENTX VDD TXCK 1MCK N/C 7N/C /DR2 SEL /DR1 28272625 43 42 41 40/MR 41 40 39 38 18171615141312 44 43 42 DI1(B) DI1(A) /DBCEN DI2(A) DI2(B) GND N/C N/C D10 DO(B) DO(A) /LD1 /OE1 D15 D14 D12 D11 /OE2 TXR /LD2 D13 44L PQFP MLPQ N/C N/C /LDCW ENTX VDD TXCK 1MCK N/C 1N/C /DR2 SEL /DR1 22212019 37 36 35 34/MR

© 2018 Device Engineering Inc. Page 12 of 16 DS-MW-01016-01 Rev G 5/2/2018 f Figure 12 Typical Transceiver/Line Driver Interconnect Configuration

© 2018 Device Engineering Inc. Page 13 of 16 DS-MW-01016-01 Rev G 5/2/2018 Table 8: DEI1016 Ordering Information DEI PART NUMBER (2) MARKING (1) PACKAGE See Table 10 TEMP RANGE PROCESSING See Table 9 DEI1016 DEI1016 40 SBDIP -55 / +125 °C CERAMIC BURN-IN 100% TEST DEI1016-DMB DEI1016-DMB 40 SBDIP -55 / +125 °C CERAMIC BURN-IN SAMPLE TEST DEI1016A DEI1016A 44 PQFP -55 / +85 °C PLASTIC STANDARD DEI1016A-G DEI1016A E3 (1)

44 PQFP G -55 / +85 °C PLASTIC STANDARD

DEI1016B DEI1016B 44 PLCC -55 / +85 °C PLASTIC STANDARD DEI1016B-G DEI1016B E3 (1)

44 PLCC G -55 / +85 °C PLASTIC STANDARD

DEI1016-QMS DEI1016-QMS 44 PQFP -55 / +125 °C PLASTIC STANDARD DEI1016-QMS -G DEI1016-QMS E3 (1)

44 PQFP G -55 / +125 °C PLASTIC STANDARD

DEI1016-PMS DEI1016-PMS 44 PLCC -55 / +125 °C PLASTIC STANDARD DEI1016-PMS-G DEI1016-PMS E3 (1)

44 PLCC G -55 / +125 °C PLASTIC STANDARD

DEI1016-EES DEI1016-EES 44 CLCC -55 / +85 °C CERAMIC SAMPLE TEST DEI1016-EMS DEI1016-EMS 44 CLCC -55 / +125 °C CERAMIC SAMPLE TEST DEI1016-EMB DEI1016-EMB 44 CLCC -55 / +125 °C CERAMIC BURN-IN SAMPLE TEST Notes: 1. All packages marked with Lot Code and Date Code. “E3” or “E4” after Date Code denotes Pb Free category. 2. Suffix legend:-XYZ: X = package code, Y = temperature range code, Z = process flow code DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose.

© 2018 Device Engineering Inc. Page 14 of 16 DS-MW-01016-01 Rev G 5/2/2018 Table 9: DEI1016 Screening Process PLASTIC STANDARD -xxS CERAMIC SAMPLE TEST -xxS CERAMIC BURN-IN 100% TEST DEI1016 CERAMIC BURN-IN SAMPLE TEST -xxB WAFER PROBE ELECTRICAL TEST 100% HOT @ +125 °C 100% HOT @ +125 °C 100% HOT @ +125 °C 100% HOT @ +125 °C THERMAL CYCLE MIL-STD-883B M1010.4 Condition B NO 10 Cycles 10 Cycles 10 Cycles GROSS & FINE LEAK NO YES YES YES BURN IN MIL-STD-883B M1015 Condition A NO NO 96 hrs @ +125 °C 96 hrs @ +125 °C ELECTRICAL TEST: ROOM TEMPERATURE 100% 100% 100% 100% HIGH TEMPERATURE 0.1% AOQL @ +125 °C (MilTemp) 0.1% AOQL @ >+85 °C (ExtTemp) 0.1% AOQL @ +125 °C (MilTemp) 0.1% AOQL @ >+85 °C (ExtTemp) 100% @ +125 °C (Mil Temp) 0.1% AOQL @ +125 °C (MilTemp) LOW TEMPERATURE 0.1% AOQL @ -55°C 0.1% AOQL @ -55°C -55°C Note: AOQL samples use a Zero Acceptance Number sampling plan per AS9100 Table 10: DEI1016 Package Characteristics PACKAGE TYPE PACKAGE REF THERMAL RESIST. θJC / θJA (ºC/W) JEDEC MOISTURE SENSITIVITY LEVEL & PEAK BODY TEMP LEAD FINISH MATERIAL / JEDEC Pb-Free CODE Pb Free DESIGNATION JEDEC MO 40L CERAMIC SB DIP 40 SBDIP 15 / 55 HERMETIC Au Pb Free solder terminals MS-015- CE 44L PLASTIC QUAD FLAT PACK 44 PQFP 21 / 65 MSL 2 235ºC SnPb Not Pb-free M0-112- AA-1 44L PLASTIC QUAD FLAT PACK, GREEN

44 PQFP

260ºC Matte Sn RoHS Compliant M0-112- AA-1 44L PLASTIC CHIP CARRIER

44 PLCC 21 / 46 MSL 3

220ºC SnPb Not Pb-free MS-018- AC 44L PLASTIC CHIP CARRIER, GREEN

44 PLCC

245ºC Matte Sn RoHS Compliant MS-018- AC 44L CERAMIC LEADLESS CHIP CARRIER

44 CLCC - / - HERMETIC Au

© 2018 Device Engineering Inc. Page 15 of 16 DS-MW-01016-01 Rev G 5/2/2018 Figure 13: 40 Lead Ceramic Side Braze DIP Mechanical Outline (40 SBDIP) Figure 14: 44 Lead 13.90mm PQFP Mechanical Outline (44 PQFP)

0.100 TYP

0.180 MAX

0.040 - 0.065 0.015 - .020 0.125 - .200

2.060 MAX

0.008 - .012 .590 - .615 .575 - .605 Lead 1 ID N NOTES 1. ALL DIMENSIONS IN MILLIMETERS 2. DIMENSIONS SHOWN IN CHART ARE NOMINAL WITH TOLERANCES AS INDICATED A B D A A SDSA-BCMddd 0.17 MAX. 6DP4° STANDOFF 0.20 RAD. TYP. L A .25 b O 0.30 RAD. TYP. A 1 3. FOOT LENGTH "L" IS MEASURED AT GAGE PLANE AT 0.25 ABOVE THE SEATING PLANE. 10D TYP. 10D TYP. e BASIC P.25 P.25 P.10 P.10 MAX. O E D A A b e L E D A TOLS. LEADSDIMS. MIN./MAX. P.05 .25/.50 2.45 44L 10.00 10.00 .88 2.00 .80 .30 0D-7D 13.90 13.90 3.90 mm ddd .12 NOM. ccc MAX. .10 C SEATING PLANE Cccc LEAD COPLANARITY +.10/-.05 +.15/-.10 FOOTPRINT (BODY +) N ANOTHER VARIATION OF PIN 1 VISUAL AID E D D E