DEI0429-EES

BD429 DEIAZ | Alldatasheet

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© 2016 Device Engineering Incorporated 1 of 13 DS-MW-00429-01 Rev. G 01/13/2016 Figure 1: BD429 Block Diagram Device Engineering Incorporated 385 E. Alamo Drive Chandler, AZ 85225 Phone: (480) 303-0822 Fax: (480) 303-0824 E-mail: admin@deiaz.com BD429/DEI0429 FAMILY ARINC 429/RS-422 Line Driver Integrated Circuit Features:

• ARINC 429 Line Driver for HI speed (100 kHz) and LOW speed (12.5 kHz) data rates
• Pin for Pin replacement part for industry standard ARINC 429 Line Drivers
• Available in a 16 Pin SOIC (WB), 16 Pin CERDIP, 16 Lead Ceramic SOP,
• 28L CLCC and 28L PLCC
• Low EMI RS-422 line driver mode for data rates up to 100 kHz
• Adjustable slew rates via two external capacitors
• Inputs are TTL and CMOS compatible
• Low quiescent power of 125mW (typical)
• Programmable output differential range via V REF pin
• Outputs are fused for failsafe overvoltage protection
• Drives full ARINC load of 400 W and 30,000pF
• Extended (-55°C/+85°C) and Military (-55°C/+125°C) temperature ranges
• 100% Final Testing

© 2016 Device Engineering Incorporated 2 of 13 DS-MW-00429-01 Rev. G 01/13/2016 General Description: The BD429 ARINC Line Driver Circuit is a bipolar monolithic IC designed to meet the requirements of several general aviation serial data bus standards. These include the differential bipolar RZ types such as ARINC 429, ARINC 571, and ARINC 575, as well as the differential NRZ types such as the RS-422 standard. Functional Description: Modes: The BD429 operates in either a 429 mode or a 422 mode as controlled by the 429/422´ pin. 429 Mode: In 429 mode, the serial data is presented on the DATA(A) and DATA(B) inputs in the dual rail format defined in the MARK 33 Digital Information Transfer System – ARINC Specification 429-10 . The driver is enabled by the SYNC and CLOCK inputs. The output voltage level is programmed by the V REF input and is normally tied to +5VDC along with V 1 to produce output levels of +5 volts, 0 volts, and –5 volts on each output for ±10 volts differential outputs. * See Figure 4. 422 Mode: In 422 mode, the serial data is presented on DATA(A) input. The driver is enabled by the SYNC and CLOCK inputs. The outputs swings between 0 volts and +5 volts if VREF is at +5VDC. *See Figure 5. Output Resistance: The driver output resistance is 75 W ±20% at room temperature; 37.5 W on each output. The outputs are also fused for failsafe protection against shorts to aircraft power. The output slew rate is controlled by external timing capacitors on CA and CB. Typical values are 75pF for 100 KHz data and 500pF for 12.5 KHz data. Table 1: Truth Table

© 2016 Device Engineering Incorporated 3 of 13 DS-MW-00429-01 Rev. G 01/13/2016 Table 2: Pin Descriptions Pin Name Description VREF Analog Input. The voltage on VREF sets the output voltage levels on AOUT and BOUT. The output logic levels swing between +VREF, 0 volts, and –V REF volts. NC No Connect SYNC Logic input. Logic 0 forces outputs to NULL state. Logic 1 enables data transmission. DATA(A) DATA(B) Logic inputs. These signals contain the Serial Data to be transmitted on the ARINC 429 data bus. Refer to Figure 4and Figure 5. CA CB Analog Nodes. External timing capacitors are tied from these points to ground to establish the output signal slew rate. Typical CA = CB = 75pF for 100 kHz data and CA = CB = 500pF for 12.5 kHz data. * AOUT BOUT Outputs. These are the line driver outputs which are connected to the aircraft serial data bus. -V Negative Supply Input. –15VDC nominal. GND Ground. +V Positive Supply Input. +15VDC nominal. CLOCK Logic input. Logic 0 forces outputs to NULL state. Logic 1 enables data transmission. 429/422' Logic Input. Mode control for ARINC 429 and RS-422 modes. An internal 10KW pull up resistor keeps the chip in ARINC 429 mode when there is no external connection. This creates a default logic 1, enabling the ARINC 429 mode. A forced logic 0 enables the RS-422 mode. V1 Logic Supply Input. +5VDC nominal. *CA and CB pin voltages swing between ±5 volts. Any electronic switching of the capacitor on the pins must not inhibit the full voltage swings. Figure 2: PLCC & CLCC PinoutFigure 3: DIP, SOIC & CSOP Pinout 16 V1 CLOCK DATA(B) CB V REF +VGND AOUT C A DATA(A) SYNC NC BOUT NC 429/422' 1 28 27 26 18171615141312 4 3 2 VREF 429/422' NC NC NC NC NC SYNC AOUT GND BOUT CLOCK NC NC NC NC NC NC NC NC NC DATA(A) DATA(B) CB CA

© 2016 Device Engineering Incorporated 4 of 13 DS-MW-00429-01 Rev. G 01/13/2016 Table 3: Absolute Maximum Ratings PARAMETER SYMBOL RATING UNITS Voltage between pins +V and –V 40 V V1 Maximum Voltage V1 7 V VREF Maximum Voltage VREF 6 V DATA(A) Max Input Voltage DATA(B) Max Input Voltage VDATA(A) VDATA(B) (GND-0.3V) to (V1 + 0.3V) V Lead Soldering Temperature (10 sec duration, thru-hole packges) TSLD 280 oC Storage Temperature TSTG -65 to +150 oC Max Junction Temperature Ceramic Package & Plastic Package short term operation TJ MAX1 +175 oC Max Junction Temperature Plastic Package Limit (prolonged operation) TJ MAX2 +145 oC Output Short Circuit Duration See Note 1 Output Over-Voltage Protection See Note 2 Power Dissipation See Table 5 below Notes. 1. One output at a time can be shorted to ground indefinitely. 2. Both outputs are fused at between 0.5 Amp DC and 1.0 Amp DC to prevent an over-voltage fault from coupling onto the system power bus. Table 4: Operating Range PARAMETER SYMBOL MIN TYP MAX UNITS Positive Supply Voltage +V +11.4 16.5 VDC Negative Supply Voltage -V -11.4 -16.5 VDC V1 V1 +4.75 +5 +5.25 VDC VREF (For ARINC 429) VREF +4.75 +5 +5.25 VDC VREF (For other applications) VREF +3 +6 VDC Operating Temperature (Plastic Package) TA -55 +85 °C Operating Temperature (Ceramic Package) TA -55 +125 °C Thermal Management Device power dissipation varies greatly as a function of data rate, load capacitance, data duty cycle, and supply voltage. Proper thermal management is important in designs operating at the HI speed data rate (100KBS) with high capacitive loads and high data duty cycles. Power dissipation may be estimated from Table 5 “Power Dissipation Table”. Device power dissipation (Pd) is indicated for 100% data duty cycle with no word gap null times and should be adjusted for the appropriate data duty cycle (DC). Pd(application) = DC * [Pd(table) - 145mW] + 145mW, where DC is the application data duty cycle, Pd(table) is the Pd from the table for the indicated data rate and bus load, and 145mW is the quiescent power. The application’s data duty cycle (DC) for 100KBS operation is calculated as: DC = (total bits transmitted in 10 sec period / 1,000,000) = (32 x total ARINC words transmitted in 10 sec period / 1,000,000). Heat transfer from the IC package should be maximized. Use maximum trace width on all power and signal connections at the IC. Place vias on the signal/power traces close to the IC to maximize heat flow to the internal power planes. If possible, design a solid heat spreader land under and beyond the IC to maximize heat flow from the device.

© 2016 Device Engineering Incorporated 5 of 13 DS-MW-00429-01 Rev. G 01/13/2016 Table 5: Power Dissipation table 100% Duty Cycle, Full Load = 400W/30,000pF Half Load = 4,000W/10,000pF DATA RATE LOAD +V @ 15V -V @ -15V V1 + VREF @5V BD429 POWER LOAD POWER 0 to 100kbps NONE 2.0mA -5.0mA 4mA 125mW 0.0mW 12.5kbps FULL 16.0mA 19.0mA 4mA 485mW 60.0mW 100kbps FULL 48.0mA 51.0mA 4mA 1194mW 325.0mW 12.5kbps HALF 6.0mA 8.0mW 4mA 196mW 30.0mW 100kbps HALF 22.0mA 25.0mA 4mA 561mW 162.5mW Table 6: DC Electrical Characteristics Conditions: Temperature: -55°C to +125°C Ceramic, -55°C to +85°C Plastic, +V = +11.4VDC to +16.5VDC, –V = -11.4VDC to –16.5VDC; V1 = VREF = +5VDC ±5%, 429/422' = Open Circuit (unless otherwise noted.) SYMBOL PARAMETER MIN TYP MAX UNIT TEST CONDITIONS IQ+V Quiescent +V supply current - 2 - mA No Load. 429 mode. DATA = CLOCK = SYNC = LOW IQ-V Quiescent -V supply current - 5 - mA No Load. 429 mode. DATA = CLOCK = SYNC = LOW IQV1 Quiescent V1 supply current - 4 - mA No Load. 429 mode. DATA = CLOCK = SYNC = LOW IQVREF Quiescent VREF supply current - 10 - mA No Load. 429 mode. DATA = CLOCK = SYNC = LOW VIH Logic 1 Input V 2.0 - - V No Load. VIL Logic 0 Input V - - 0.6 V No Load. IIH Logic 1 Input I - - 10 mA No Load. IIL Logic 0 Input I - - -20 mA No Load. (429/422´ Pin IIL = -2mA max) IOHSC Output Short Circuit Current (Output High) -80 - - mA Short to Ground IOLSC Output Short Circuit Current (Output Low) 80 - - mA Short to Ground VOH Output Voltage HIGH. ( +1) VREF - 250mV VREF VREF+ 250mV V No Load. 429 Mode. VNULL Output Voltage NULL. ( 0 ) -250 - +250 mV No Load. 429 Mode. VOL Output Voltage LOW. ( -1 ) -VREF – 250mV -VREF -VREF + 250mV V No Load. 429 Mode. ICT Timing Capacitor Charge Current CA (+1 ) CB (-1 ) CA (-1 ) CB (+1 ) - +200 –200 - mA mA No Load. 429 Mode. SYNC = CLOCK = HIGH CA and CB held at zero volts. ISC (+V) +V Short Circuit Supply Current - - +150 mA Output short to ground ISC (-V) -V Short Circuit Supply Current - - -150 mA Output short to ground ROUT Resistance on each output - 37.5 - W Room Temp Only CIN Input Capacitor - - 15 pF -

© 2016 Device Engineering Incorporated 7 of 13 DS-MW-00429-01 Rev. G 01/13/2016 DATA(A) DATA(B) A OUT B OUT 50% 50% 50% 50% t PNH t PNL Figure 6: Propagation Delay Table 7: AC Electrical Characteristics Parameter Symbol MIN MAX UNITS NOTES Output Rise Time AOUT orBOUT CA = CB = 75pF CA = CB = 500pF tR tR 1.0 5.0 2.0 15.0 msec msec Output Fall Time AOUT orBOUT CA = CB = 75pF CA = CB = 500pF tF tF 1.0 5.0 2.0 15.0 msec msec Input to Output Propagation Delay tPNH tPNL - 3.0 msec See Figure 6 below AOUT / BOUT Skew Spec. - - 500 nsec

© 2016 Device Engineering Incorporated 9 of 13 DS-MW-00429-01 Rev. G 01/13/2016 Table 8: Ordering Information DEI PART NUMBER (2) MARKING (1) PACKAGE TEMP RANGE PROCESSING BD429 BD429 16 CERDIP -55 / +125 °C CERAMIC BURN IN BD429-G BD429 E3 (1) 16 CERDIP G -55 / +125 °C CERAMIC BURN IN BD429A-G BD429A E4 (1) 16 SOIC WB G -55 / +85 °C PLASTIC STANDARD BD429A1-G BD429A1 E4 (1) 16 SOIC WB G -55 / +85 °C PLASTIC BURN IN BD429B BD429B 28 PLCC -55 / +85 °C PLASTIC STANDARD BD429B-G BD429B E3 (1) 28 PLCC G -55 / +85 °C PLASTIC STANDARD DEI0429-WMS DEI0429-WMS 16 CSOP -55 / +125 °C CERAMIC STANDARD DEI0429-WMB DEI0429-WMB 16 CSOP -55 / +125 °C CERAMIC BURN IN DEI0429-EES DEI0429-EES 28 LCC -55 / +85 °C CERAMIC STANDARD DEI0429-EMS DEI0429-EMS 28 LCC -55 / +125 °C CERAMIC STANDARD DEI0429-EMB DEI0429-EMB 28 LCC -55 / +125 °C CERAMIC BURN IN Notes: 1. All packages marked with Lot Code and Date Code. “E3” or “E4” after Date Code Denotes Pb Free category. 2. Suffix legend: -XYZ: X = package code, Y = temperature range code, Z = process flow code. Table 9: Screening Process PLASTIC STANDARD PLASTIC BURN IN CERAMIC STANDARD CERAMIC BURN IN THERMAL CYCLE MIL-STD-883B M1010.4 Cond. B NO NO 10 Cycles 10 Cycles GROSS & FINE LEAK NO NO YES YES BURN IN MIL-STD-883B M1015 Cond. A NO 160 hrs @ +125 °C NO 96 hrs @ +125 °C ELECTRICAL TEST: ROOM TEMPERATURE 100% 100% 100% 100% HIGH TEMPERATURE 100% @ +125 °C 100% @ +125 °C 100% @ +125 °C 100% @ +125 °C LOW TEMPERATURE 0.65% AQL@-55°C0.65% AQL@-55°C 0.65% AQL@-55°C0.65% AQL@-55°C

© 2016 Device Engineering Incorporated 10 of 13 DS-MW-00429-01 Rev. G 01/13/2016 Figure 9: Typical Transceiver/Line Driver Interconnect Configuration Table 10: Package Characteristics PACKAGE TYPE PACKAGE REF THERMAL RESIST. θJC / θJA (ºC/W) JEDEC MOISTURE SENSITIVITY LEVEL & PEAK BODY TEMP LEAD FINISH MATERIAL / JEDEC Pb-Free CODE Pb Free DESIGNATON JEDEC MO 16L CERAMIC DIP 16 CERDIP 35 / 75 HERMETIC SnPb solder Not Pb-free MS-030- AC 16L CERAMIC DIP, GREEN

16 CERDIP

Sn96.5/Ag 3/Cu 0.5 Pb Free solder terminals MS-030- AC 16L SOIC WIDE BODY, GREEN

16 SOIC

(4L PCB) MSL 1 260ºC NiPdAu RoHS Compliant MS-013- AA 16L CERAMIC SOP 16 CSOP 23 / TBD HERMETIC Au Pb Free solder terminals na 28L PLCC 28 PLCC 25 /55 (4L PCB) MSL 3 235ºC SnPb Not Pb-free MS-018- AB 28L PLCC, GREEN 28 PLCC G 25 /55 (4L PCB) MSL 3 245ºC Matte Sn RoHS Compliant MS-018- AB 28L CERAMIC LEADLESS CHIP CARRIER

28 LCC 14 / 60 HERMETIC Au

© 2016 Device Engineering Incorporated 11 of 13 DS-MW-00429-01 Rev. G 01/13/2016 0.100 ± 0.010 (2.54 ± 0.25) 0.020 - 0.070 (0.51 - 1.78)

0.160 MAX

(4.06) 0.060 ±0.005 (1.52 ±0.13) 0.018 ±0.002 (0.46 ±0.05)

0.125 MIN

(3.18) 0 - 10 deg. 0.385 ±0.025 (9.78 ±0.64) 0.008 - 0.012 (0.20 - 0.30) 0.290 - 0.320 (7.37 - 8.13)

0.291 MAX

(7.39)

0.785 MAX

(19.94)

0.025 RAD

(0.64)

0.050 MAX

(1.27) Dimensions Are in Inches(mm)

© 2016 Device Engineering Incorporated 12 of 13 DS-MW-00429-01 Rev. G 01/13/2016

© 2016 Device Engineering Incorporated 13 of 13 DS-MW-00429-01 Rev. G 01/13/2016 DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or guarantee regarding suitability of its products for any particular purpose.