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Technical content

Features

  • Isolated Substrate High isolation voltage (>2500V) Excellent thermal transfer Increased temperature and power cycling capability
  • IXYS advanced low Q g process
  • Low gate charge and capacitances Easier to drive Faster switching
  • Low R DS(on)
  • Very low insertion inductance (<2nH)
  • No beryllium oxide (BeO) or other haz ardous materials Advantages
  • Optimized for RF and high speed switching at frequencies to 50MHz
  • Easy to mount—no insulators needed
  • High power density NChannel Enhancement Mode Low Q g and R g High dv/dt Nanosecond Switching 50MHz Maximum Frequency DRAIN SG1 SG2 GATE SD1 SD2

Symbol Test Conditions Characteristic Values min. typ. max. RG 0.2 Ω Ciss 3000 pF Coss VGS = 0 V, V DS = 0.8 V DSS(max) , f = 1 MHz 93 pF Crss 9 pF Cstray Back Metal to any Pin 33 pF Td(on) 5 ns Ton VGS = 15 V, V DS = 0.8 V DSS ID = 0.5 IDM RG = 0.2 Ω (External) 3 ns Td(off) 5 ns Toff 8 ns Qg(on) 57 nC Qgs VGS = 10 V, V DS = 0.5 V DSS ID = 0.5 ID25 24 nC Qgd 22 nC (TJ = 25°C unless otherwise specified ) SourceQDrain Diode Characteristic Values (TJ = 25°C unless otherwise specified ) Symbol Test Conditions min. typ. max. IS VGS = 0 V 15 A ISM Repetitive; pulse width limited by T JM 72 A VSD 1.4 V Trr 250 ns IF = IS, V GS = 0 V, Pulse test, t ≤ 300 µs, duty cycle ≤ 2% QRM IF = IS, di/dt = 100A/µs, VR = 100V 0.66 µC IRM 7.6 A IXYS RF reserves the right to change limits, test conditions and dimensions. IXYS RF MOSFETS are covered by one or more of the following U.S. patents: 4,835,592 4,860,072 4,881,106 4,891,686 4,931,844 5 ,017,508 5,034,796 5,049,961 5,063,307 5,187,117 5,237,481 5 ,486,715 5,381,025 5,640,045 For detailed device mounting and installation instructions, see the “ Device Installation & Mounting Instructions ” technical note on the IXYSRF web site at; http://www.ixysrf.com/pdf/switch_mode/appnotes/7de_series_mosfet_installation_instructions.pdf CAUTION: Operation at or above the Maximum Ratings values may impact device reliability or cause permanent damage to the device. Information in this document is believed to be accurate and reliable . IXYSRF reserves the right to make changes to information pub lished in this document at any time and without notice.

Fig. 1 Fig. 2 Fig. 3 Fig. 5 Fig. 4 Maximum Transient Thermal Impedance 0.010 0.100 1.000 0.0001 0.001 0.01 0.1 1 10 Pulse Time  Seconds Z(th)JC  ºC/W Fig. 6 Typical Transfer Characteristics VDS = 50V 6 7 8 9 10 11 12 VGS , Gate to Source (V) ID, Drain Current (A) Typical Output Characteristics 0 10 20 30 40 50 VDS , Drain to Source (V) ID, Drain Currnet (A) 7.5V 6.5V 12V 10V Gate Charge vs. Gate to Source Voltage 0 20 40 60 80 100 Gate Charge (nC) VGS ,Gate to Source (V) Extended Typical Output Characteristics 0 20 40 60 80 100 VDS , Drain to Source (V) ID, Drain Currnet (A) 7.5V 12V 10V COSS CRSS CISS Capacitance vs. V DS 100 1000 10000 0 100 200 300 400 500 600 700 800 VDS , Drain to Source (V) Capacitance (pF)

Fig. 7 Fig. 8 Fig. 9 Fig. 10 Transfer Curve vs. Temperature VDS = 50V 5 7 9 11 13 VGS , Gate to Source (V) ID, Drain Current (A) 150°C 25°C 40°C Normalized V GS(TH) vs. Temperature ID = 1mA 0.6 0.7 0.8 0.9 1.1 1.2 40 20 0 20 40 60 80 100 120 140 160 Temperature °C VGS(TH) Normalized Normalized R DS(ON) vs. Temperature ID = 7.5A V GS = 10V 0.5 0.75 1.25 1.5 1.75 2.25 2.5 40 20 0 20 40 60 80 100 120 140 160 Temperature (°C) RDS(ON) Normalized Normalized G FS vs. Temperature ID = 7.5A V DS = 50V 0.75 0.8 0.85 0.9 0.95 1.05 1.1 40 20 0 20 40 60 80 100 120 140 160 Temperature (°C) GFS Normalized

Fig. 11 Package Drawing Source Source Source Source Gate Drain

102N15A DEQSERIES SPICE Model The DESERIES SPICE Model is illustrated in Figure 12. The model is an expansion of the SPICE level 3 MOSFET model. It includes the stray inductive terms L G, L S and L D. Rd is the RDS(ON) of the device, Rds is the resistive leakage term. The output capacitance, C OSS , and reverse transfer capacitance, C RSS are modeled with reversed biased diodes. This provides a varactor type response necessary for a high power device model. The turn on delay and the turn off delay are adjusted via Ron and Roff. Figure 12 DESERIES SPICE Model Net List: .SUBCKT 102N15A 10 20 30 * TERMINALS: D G S * 1000 Volt 15 Amp 1 ohm NChannel Power MOSFET * REV.A 021012 M1 1 2 3 3 DMOS L=1U W=1U RON 5 6 0.2 DON 6 2 D1 ROFF 5 7 .1 DOF 2 7 D1 D1CRS 2 8 D2 D2CRS 1 8 D2 CGS 2 3 3.0N RD 4 1 1.0 DCOS 3 1 D3 RDS 1 3 5.0MEG LS 3 30 .5N LD 10 4 1N LG 20 5 1N .MODEL DMOS NMOS (LEVEL=3 VTO=3.0 KP=3.8) .MODEL D1 D (IS=.5F CJO=1P BV=100 M=.5 VJ=.6 TT=1N) .MODEL D2 D (IS=.5F CJO=400P BV=1000 M=.4 VJ=.6 TT=400N RS=10M) .MODEL D3 D (IS=.5F CJO=900P BV=1000 M=.3 VJ=.4 TT=400N RS=10M) .ENDS An IXYS Company Fort Collins, CO USA 80526 9704931901 Fax: 9702323025 Email: sales@ixyscolorado.com Web: http://www.ixyscolorado.com 150C Rev. 1 © 2012 IXYS RF