28F800F3 INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 INTRODUCTION
- 1.2 Product Overview
- 2.0 PRODUCT DESCRIPTION
- 2.1 Pinouts
- 2.2 Pin Description
- 2.3 Memory Blocking Organization
- 2.3.1 Parameter Blocks
- 2.3.2 Main Blocks
- 3.0 PRINCIPLES OF OPERATION
- 3.1 Bus Operations
- 3.1.1 Read
- 3.1.2 Output Disable
- 3.1.3 Standby
- 3.1.4 Write
- 3.1.5 Reset
- 4.0 COMMAND DEFINITIONS
- 4.1 Read Array Command
- 4.2 Read Identifier Codes Command
- 4.3 Read Status Register Command
- 4.4 Clear Status Register Command
- 4.5 Block Erase Command
- 4.6 Program Command
- 4.8 Program Suspend/Resume Command
- 4.9 Set Read Configuration Command
- 4.9.1 Read Configuration
- 4.9.2 Frequency Configuration
- 4.9.3 Data Output Configuration
- 4.9.4 WAIT# Configuration
- 4.9.5 Burst Sequence
- 4.9.6 Clock Configuration
- 4.9.7 Burst Length
- 5.0 DATA PROTECTION
- 5.2 WP# = VIL for Block Locking
- 5.3 WP# = VIH for Block Unlocking
- 6.0 VPP VOLTAGES
- 7.0 POWER CONSUMPTION
- 7.1 Active Power
- 7.2 Automatic Power Savings
- 7.3 Standby Power
- 7.4 Power-Up/Down Operation
- 7.4.1 RST# Connection
- 7.5 Power Supply Decoupling
- 7.5.1 VPP Trace on Printed Circuit Boards
- 8.0 ELECTRICAL SPECIFICATIONS
- 8.1 Absolute Maximum Ratings
- 8.2 Extended Temperature Operating
- 8.3 Capacitance
- 8.4 DC Characteristics—Extended
- 8.5 AC Characteristics—Read-Only
- 8.6 AC Characteristics—Write Operations—
- 8.7 AC Characteristics—Reset Operation—
- 8.8 Extended Temperature Block Erase and
- 8.9 Automotive Temperature Operating
E PRODUCT PREVIEW May 1998 Order Number: 290644-001 /c110 High Performance 54 MHz Effective Zero Wait-State Performance Synchronous Burst-Mode Reads Asynchronous Page-Mode Reads /c110 SmartVoltage Technology 2.7 V−3.6 V Read and Write Operations for Low Power Designs 12 V VPP Fast Factory Programming /c110 Flexible I/O Voltage 1.65 V I/O Reduces Overall System Power Consumption 5 V-Safe I/O Enables Interfacing to
5 V Devices
/c110 Enhanced Data Protection Absolute Write Protection with VPP = GND Block Locking Block Erase/Program Lockout during Power Transitions /c110 Density Upgrade Path 8- and 16-Mbit /c110 Manufactured on ETOX™ V Flash Technology /c110 Supports Code Plus Data Storage Optimized for Flash Data Integrator (FDI) Software Fast Program Suspend Capability Fast Erase Suspend Capability /c110 Flexible Blocking Architecture Eight 4-Kword Blocks for Data 32-Kword Main Blocks for Code Top or Bottom Configurations Available /c110 Extended Cycling Capability Minimum 10,000 Block Erase Cycles Guaranteed /c110 Low Power Consumption Automatic Power Savings Mode Decreases Power Consumption /c110 Automated Program and Block Erase Algorithms Command User Interface for Automation Status Register for System Feedback /c110 Industry-Standard Packaging 56-Lead SSOP µBGA* CSP Intel’s Fast Boot Block memory family renders high performance asynchronous page-mode and synchronous burst reads making it an ideal memory solution for burst CPUs. Combining high read performance with the intrinsic non-volatility of flash memory, this flash memory family eliminates the traditional redundant memory paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory for improved system performance. Therefore, it reduces the total memory requirement which helps increase reliability and reduce overall system power consumption and cost. This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They are available in industry-standard packages: the µBGA* CSP, ideal for board-constrained applications, and the rugged 56-lead SSOP. FAST BOOT BLOCK FLASH MEMORY FAMILY
8 AND 16 MBIT
28F800F3, 28F160F3 Includes Extended and Automotive Temperature Specifications
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F800F3, 28F160F3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel’s Website at http://www.intel.com COPYRIGHT © INTEL CORPORATION, 1998 CG-041493 *Third-party brands and names are the property of their respective owners
FAST BOOT BLOCK DATASHEET E
4 PRODUCT PREVIEW
8.11 DC Characteristics—Automotive
8.12 AC Characteristics—Read-Only
8.13 Automotive Temperature Frequency
8.14 Automotive Temperature Block Erase and
REVISION HISTORY
05/12/98 -001 Original version
E FAST BOOT BLOCK DATASHEET 5PRODUCT PREVIEW
1.0 INTRODUCTION
This datasheet contains 8- and 16-Mbit Fast Boot Block memory information. Section 1.0 provides a flash memory overview. Sections 2.0 through 8.0 describe the memory functionality and electrical specifications for extended and automotive temperature product offerings.
1.2 Product Overview
The Fast Boot Block flash memory family provides density upgrades with pinout compatibility for 8- and 16-Mbit densities. This family of products are high performance, low voltage memories with a 16-bit data bus and individually erasable blocks. These blocks are optimally sized for code and data storage. Eight 4-Kword parameter blocks are positioned at either the top (denoted by -T suffix) or bottom (denoted by -B suffix) of the address map. The rest of the device is grouped into 32-Kword main blocks. The upper two (or lower two) parameter and all main blocks can be locked for complete code protection. The device’s optimized architecture and interface dramatically increases read performance beyond previously attainable levels. It supports asynchronous page-mode and synchronous burst reads from main blocks (parameter blocks support single asynchronous and synchronous reads). Upon initial power-up or return from reset, the device defaults to a page-mode read configuration. Page-mode read configuration is ideal for non-clock memory systems and is compatible with page- mode ROM. Synchronous burst reads are enabled by writing to the read configuration register. In synchronous burst mode, the CLK input increments an internal burst address generator, synchronizes the flash memory with the host CPU, and outputs data on every rising (or falling) CLK edge up to 54 MHz (25 MHz for automotive temperature). An output signal, WAIT#, is also provided to ease CPU to flash memory communication and synchronization during continuous burst operations. In addition to the enhanced architecture and interface, this family of products incorporates SmartVoltage technology which enables fast factory programming and low power designs. Specifically designed for low voltage systems, Fast Boot Block flash memory components support read operations at 2.7 V (3.3 V for automotive temperature) V CC and block erase and program operations at 2.7 V (3.3 V for automotive temperature) and 12 V VPP . The 12 V VPP option renders the fastest program performance to increase factory programming throughput. With the 2.7 V (3.3 V for automotive temperature) V PP option, VCC and VPP can be tied together for a simple, low power design. In addition to the voltage flexibility, the dedicated V PP pin gives complete data protection when VPP ≤ VPPLK . The flexible input/output (I/O) voltage capability helps reduce system power consumption and simplify interfacing to sub 2.7 V and 5 V CPUs. Powered by V CCQ pins, the I/O buffers can operate at a lower voltage than the flash memory core. With V CCQ voltage at 1.65 V, the I/Os swing between GND and 1.65 V, reducing I/O power consumption by 65% over standard 3 V flash memory components. The low voltage and 5 V-safe feature also helps ease CPU interfacing by adapting to the CPU’s bus voltage. The device’s Command User Interface (CUI) serves as the interface between the system processor and internal flash memory operation. A valid command sequence written to the CUI initiates device automation. This automation is controlled by an internal Write State Machine (WSM) which automatically executes the algorithms and timings necessary for block erase and program operations. The status register provides WSM feedback by signifying block erase or program completion and status. Block erase and program automation allows erase and program operations to be executed using an industry-standard two-write command sequence. A block erase operation erases one block at a time, and data is programmed in word increments. Erase suspend allows system software to suspend an ongoing block erase operation in order to read from or program data to any other block. Program suspend allows system software to suspend an ongoing program operation in order to read from any other location. Fast Boot Block flash memory devices offer two low power savings features: Automatic Power Savings (APS) and standby mode. The device automatically enters APS mode following the completion of a read cycle. Standby mode is initiated when the system deselects the device by driving CE# inactive or RST# active. RST# also resets the device to read array, provides write protection, and clears the status register. Combined, these two features significantly reduce power consumption.
6 PRODUCT PREVIEW
2.0 PRODUCT DESCRIPTION
architecture of the device family.
2.1 Pinouts
2.2 Pin Description
The pin description table describes pin usage.
- Shaded connections indicate upgrade address connections. Lower density devices will not have upper address solder
balls. Routing is not recommended in this area.
- A 20 and A21 are the upgrade address for potential 32-Mbit and 64-Mbit devices (currently not on road map).
- Reference the Micro Ball Grid Array Package Mechanical Specification and Media Information on Intel’s World Wide Web
home page for detailed package specifications. **Figure 1. 56-Ball µBGA* Package Pinout (Top View, Ball Down)**
Figure 2. SSOP Pinout
8 PRODUCT PREVIEW
Table 1. Pin Descriptions A0–A19 INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during read and write cycles. are disabled. Data is internally latched during a write cycle. mode read and write operations. ADV# INPUT ADDRESS VALID: Indicates that a valid address is present on the address inputs. OE# INPUT OUTPUT ENABLE: Gates data outputs during a read cycle. latched on the rising edge of the WE# pulse. blocks and two parameter blocks. [block erase] will be set to indicate the operation failed. tied together to form one system WAIT# signal.
must be applied to this pin. With VPP ≤ VPPL K, memory contents cannot be altered. Block erase and program with an invalid VPP voltage should not be attempted. 12 V for a total of 80 hours maximum (see Section 6.0 for details). lowest power operation (see DC Characteristics for detailed information). This input may be tied directly to VCC . GND SUPPLY GROUND: Do not float any ground pins. NC NO CONNECT: Lead is not internally connected; it may be driven or floated.
2.3 Memory Blocking Organization
blocking) and Figure 4 (bottom boot blocking).
2.3.1 PARAMETER BLOCKS
(4,096-words) parameter blocks.
2.3.2 MAIN BLOCKS
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Figure 3. 8- and 16-Mbit Top Boot Memory Map
Figure 4. 8- and 16-Mbit Bottom Boot Memory Map
FAST BOOT BLOCK DATASHEET E
12 PRODUCT PREVIEW
3.0 PRINCIPLES OF OPERATION
The Fast Boot Block flash memory components include an on-chip WSM to manage block erase and program. It allows for CMOS-level control inputs, fixed power supplies, and minimal processor overhead with RAM-like interface timings.
3.1 Bus Operations
All bus cycles to and from flash memory conform to standard microprocessor bus cycles.
3.1.1 READ
The flash memory has three read modes available: read array, identifier codes, and status register. These modes are accessible independent of the V PP voltage. The appropriate read command (Read Array, Read Identifier Codes, or Read Status Register) must be written to the CUI to enter the requested read mode. Upon initial power-up or exit from reset, the device defaults to read array mode. When reading information from main blocks in read array mode, the device supports two high- performance read configurations: asynchronous page-mode and synchronous burst-mode. Asynchronous page-mode is the default state and provides high data transfer rate for non-clocked memory subsystems. In this state, data is internally read and stored in a high-speed page buffer. A 1:0 addresses data in the page buffer. The page size is four words. The other read configuration, synchronous burst-mode, is enabled by writing to read configuration register. This register sets the read configuration, burst order, frequency configuration, and burst length. In synchronous burst-mode, the device latches the initial address then outputs a sequence of data with respect to the input CLK and read configuration setting. Read operations from the parameter blocks, identifier codes and status register transpire as single asynchronous or synchronous read cycles. The read configuration register setting determines whether or not read operations are asynchronous or synchronous. For all read operations, CE# must be driven active to enable the devices, ADV# must be driven low to open the internal address latch, and OE# must be driven low to activate the outputs. In asynchronous mode, the address is latched when ADV# is driven high. In synchronous mode, the address is latched by ADV# going high or ADV# low in conjunction with a rising (falling) clock edge, whichever occurs first. WE# must be at V IH. Figures 14 through 19 illustrate different read cycles.
3.1.2 OUTPUT DISABLE
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0–DQ 15 are placed in a high-impedance state.
3.1.3 STANDBY
Deselecting the device by bringing CE# to a logic- high level (VIH) places the device in standby mode, which substantially reduces device power consumption. In standby, outputs are placed in a high-impedance state independent of OE#. If deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete.
3.1.4 WRITE
Commands are written to the CUI using standard microprocessor write timings when ADV#, WE#, and CE# are active and OE# inactive. The CUI does not occupy an addressable memory location. The address is latched on the rising edge of ADV#, WE#, or CE# (whichever occurs first) and data needed to execute a command is latched on the rising edge of WE# or CE# (whichever goes high first). Write operations are asynchronous. Therefore, CLK is ignored during write operations. Figure 20 illustrates a write operation.
3.1.5 RESET
required before a write sequence can be initiated.
4.0 COMMAND DEFINITIONS
Table 2. Bus Operations
- Refer to DC Characteristics. When VPP ≤ VPPLK , memory contents can be read, but not altered.
- X can be VIL or VIH for control and address input pins and VPPLK or VPPH1/2 for VPP . See DC Characteristics for VPPLK and
- Command writes involving block erase or program are reliably executed when VPP = VPPH1/2 and VCC = VCC1/2
(see Section 8 for operating conditions at different temperatures).
- Refer to Table 3 for valid DIN during a write operation.
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Table 3. Command Definitions(1)
- Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
- Bus operations are defined in Table 2.
- X = Any valid address within the device.
IA = Identifier Code Address. BA = Address within the block being erased. WA = Address of memory location to be written.
- SRD = Data read from status register. See Table 5 for a description of the status register bits.
WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). ID = Data read from identifier codes. See Table 4 for manufacturer and device codes. RCD = Data to be written to read configuration register. See Table 6 for a description of the read configuration register bits.
- Following the Read Identifier Codes command, read operations access manufacturer, device codes, and read
- Following a block erase, program, and suspend operation, read operations access the status register.
- To issue a block erase, program, or suspend operation to a lockable block, hold WP# at V
- Either 40H or 10H are recognized by the WSM as the program setup.
4.1 Read Array Command
4.2 Read Identifier Codes
Table 4. Identifier Codes
16 Mbit -T 00001 88F3
4.3 Read Status Register
burst reads are not supported in this read mode.
4.4 Clear Status Register
command, the device returns to read array mode.
4.5 Block Erase Command
erased (erase changes all block data to FFH). analyzing status register bit SR.7.
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Table 5. Status Register Definition command is written to the CUI. SR.3 does not provide a continuous VPP feedback. when VPP ≠ VPPH1/2 or VPPLK . command is written to the CUI. masked out when polling the status register.
E FAST BOOT BLOCK DATASHEET 17PRODUCT PREVIEW
4.6 Program Command
Program operation is executed by a two-cycle command sequence. Program setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data. The WSM then takes over, controlling the internal program algorithm. After the program sequence is written, the device automatically outputs status register data when read (see Figure 8, Automated Program Flowchart). The CPU can detect the completion of the program event by analyzing status register bit SR.7. When the program operation completes, check status register bit SR.4 for an error flag (“1”). If an error is detected, check status register bits SR.5, SR.3, and SR.1 to understand what caused the problem. After examining the status register, it should be cleared if an error was detected before issuing a new command. The device will remain in status register read mode until another command is written to the CUI.
4.7 Block Erase Suspend/Resume
The Block Erase Suspend command allows block erase interruption to read or program data in another blocks. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase operation after a certain latency period. The device continues to output status register data when read after the Block Erase Suspend command is issued. Status Register bits SR.7 and SR.6 indicate when the block erase operation has been suspended (both will be set to “1”). Specification t WHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Program command sequence can also be issued during erase suspend to program data in other blocks. Using the Program Suspend command (see Section 4.8), a program operation can be suspended during an erase suspend. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. During a block erase suspend, the chip can go into a pseudo-standby mode by taking CE# to V IH, which reduces active current draw. VPP must remain at VPPH1/2 while block erase is suspended. WP# must also remain at VIL or VIH. To resume the block erase operation, write the Block Erase Resume command to the CUI. This will automatically clear status register bits SR.6 and SR.7. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 9, Block Erase Suspend/Resume Flowchart). Block erase cannot resume until program operations initiated during block erase suspend have completed.
4.8 Program Suspend/Resume
The Program Suspend command allows program interruption to read data in other flash memory locations. Once the program process starts, writing the Program Suspend command requests that the WSM suspend the program operation after a certain latency period. The device continues to output status register data when read after issuing Program Suspend command. Status register bits SR.7 and SR.2 indicate when the block erase operation has been suspended (both will be set to “1”). Specification t WHRH1 defines the program suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. The only other valid commands while block erase is suspended are Read Status Register and Program Resume. During a program suspend, the chip can go into a pseudo-standby mode by taking CE# to V IH, which reduces active current draw. VPP must remain at VPPH1/2 while program is suspended. WP# must also remain at VIL or VIH. To resume the program, write the Program Resume command to the CUI. This will automatically clear status register bits SR.7 and SR.2. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 10, Program Suspend/Resume Flowchart).
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Table 6. Read Configuration Register Definition and identifier reads support single read cycles. implementations and should not be used. length always equals four words.
Figure 5. Frequency Configuration Table 7. Frequency Configuration Settings(1)
1 Reserved Reserved Reserved
- Reference Section 4.1. Automotive Temperature Frequency Configuration Settings for the corresponding frequency
configuration codes to different input CLK frequencies.
4.9 Set Read Configuration
4.9.1 READ CONFIGURATION
20 PRODUCT PREVIEW
configuration register sets the read configuration.
4.9.2 FREQUENCY CONFIGURATION
value is determined by the input clock frequency.
4.9.3 DATA OUTPUT CONFIGURATION
configurable as either one or two clocks. on the system CPU’s data setup requirement.
1 CLK
2 CLK
Figure 6. Output Configuration
4.9.4 WAIT# CONFIGURATION
system and CPU characteristic.
4.9.5 BURST SEQUENCE
4.9.6 CLOCK CONFIGURATION
interface to wide range of burst CPUs.
4.9.7 BURST LENGTH
configuration register set the burst length.
4.9.7.1 Continuous Burst Length
system is informed if this output delay occurs.
Table 8. Sequence and Burst Length
4 Word
8 Word
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Repeat for subsequent block erasures. Write FFH after the last operation to place device in read array mode. Figure 7. Automated Block Erase Flowchart
Repeat for subsequent byte writes. sequence of program operations. Figure 8. Automated Program Flowchart
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Figure 9. Block Erase Suspend/Resume Flowchart
Figure 10. Program Suspend/Resume Flowchart
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5.0 DATA PROTECTION
programmed or erased as necessary.
5.1 V PP ≤ VPPLK for Complete
5.2 WP# = V IL for Block Locking
and #8 through #22 for the 8-Mbit) are lockable.
5.3 WP# = V IH for Block Unlocking
the write protection methods. Table 9. Write Protection Truth Table
6.0 V PP VOLTAGES
cost, high-performance 12 V programming feature.
7.0 POWER CONSUMPTION
and system power consumption.
7.1 Active Power
especially for battery-operated devices.
7.2 Automatic Power Savings
outputs valid until a new location is read.
E FAST BOOT BLOCK DATASHEET 27PRODUCT PREVIEW
7.3 Standby Power
With CE# at a logic-high level (VIH) and the CUI in read mode, the flash memory is in standby mode, which disables much of the device’s circuitry and substantially reduces power consumption. Outputs (DQ 0–DQ 15) are placed in a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. System engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. This will provide a more accurate measure of application-specific power and energy requirements.
7.4 Power-Up/Down Operation
The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, V PP , VCC , or VCCQ , powers-up first.
7.4.1 RST# CONNECTION
The use of RST# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RST# to the system reset signal to allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when V CC voltages are above VLKO and VPP is active. Since both WE# and CE# must be low for a command write, driving either signal to V IH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RST# is brought to V IH, regardless of the state of its control inputs. By holding the device in reset during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 7.4.2 V CC , VPP AND RST# TRANSITIONS The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from deep power-down mode or after V CC transitions above VLKO (Lockout voltage), is read array mode. After any block erase or program operation is complete (even after VPP transitions down to VPPLK ), the CUI must be reset to read array mode via the Read Array command if access to the flash memory array is desired.
7.5 Power Supply Decoupling
Flash memory’s power switching characteristics require careful device decoupling. System designers should consider three supply current issues: 1. Standby current levels (I CCS ) 2. Active current levels (ICCR ) 3. Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each V CC and GND, and between its VPP and GND. These high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 7.5.1 V PP TRACE ON PRINTED CIRCUIT BOARDS Designing for in-system writes to the flash memory requires special consideration of the VPP power supply trace by the printed circuit board designer. The V PP pin supplies the flash memory cells current for programming and erasing. VPP trace widths and layout should be similar to that of VCC . Adequate VPP supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots.
FAST BOOT BLOCK DATASHEET E
28 PRODUCT PREVIEW
8.0 ELECTRICAL SPECIFICATIONS
8.1 Absolute Maximum Ratings*
(except V CC , VCCQ , and VPP )–0.5 V to +5.5 V(1) NOTICE: This datasheet contains preliminary information on products in the design phase of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. *WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. NOTES: 1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and –0.2 V on VCC and VPP pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on input/output pins and VCC is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods <20 ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. 4. V the main blocks and 2500 cycles on the parameter blocks during program/erase. VPP may be connected to 12 V for a total of 80 hours maximum.
8.2 Extended Temperature Operating Conditions
Symbol Parameter Notes Min Max Unit TA Operating Temperature –40 +85 °C VCC1 VCC Supply Voltage 1 2.7 2.85 V VCC2 VCC Supply Voltage 1 2.7 3.3 V VCC3 VCC Supply Voltage 1,4 2.7 3.6 V VCCQ1 I/O Voltage 1,2 1.65 2.5 V VCCQ2 I/O Voltage 1,2 1.8 2.5 V VCCQ3 I/O Voltage 1,2,4 2.7 3.6 V VPPH1 VPP Supply Voltage 1 2.7 3.6 V VPPH2 VPP Supply Voltage 1,4 11.4 12.6 V Cycling Block Erase Cycling 3 10,000 Cycles NOTES: 1. See DC Characteristics tables for voltage range-specific specifications. 2. The voltage swing on the inputs, VIN is required to match VCCQ . 3. Applying VPP = 11.4 V–12.6 V during a program or erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. A hard connection to VPP = 11.4 V–12.6 V is not allowed and can cause damage to the device. 4. V CC , VCCQ , and VPP1 must share the same supply when all three are between 2.7 V and 3.6 V.
8.3 Capacitance (1)
- Sampled, not 100% tested.
VCCQ /2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are when VCCQ = 2.7 V. Figure 11. Transient Input/Output Reference Waveform for VCC = 2.7 V−3.6 V See table for component values. Figure 12. Transient Equivalent Testing
2.7 V Standard Test 50 25K 25K
C L includes jig capacitance.
FAST BOOT BLOCK DATASHEET E
30 PRODUCT PREVIEW
8.4 DC Characteristics—Extended Temperature (1)
Sym Parameter Note Typ Max Typ Max Typ Max Unit Test Conditions ILI Input Load Current 6 ± 1 ± 1 ± 1 µA V CC = VCC Max VCCQ = VCCQ Max VIN = VCCQ or GND ILO Output Leakage Current 6 ± 10 ± 10 ± 10 µA V CC = VCC Max VCCQ = VCCQ Max Output Leakage Current for WAIT# ± 25 ± 25 ± 25 V IN = VCCQ or GND ICCS VCC Standby Current 6 30 50 20 50 150 250 µA V CC = VCC Max CE# = RP# = VCC or during Program/ Erase Suspend ICCR VCC Read Current 4,6 45 60 30 45 40 55 mA Asynchronous tAVAV = Min VIN = VIH or VIL 45 60 30 45 40 55 mA Synchronous CLK = 33 MHz CE# = V IL OE# = VIH Burst length = 1 ICCW VCC Program Current 3,6 8 20 8 20 8 20 mA V PP = VPP1, 2 Program in Progress ICCE VCC Erase Current 3,6 8 20 8 20 8 20 mA V PP = VPP1 , 2 Erase in Progress IPPR VPP Read Current 2 ±15 2 ±15 2 ±15 µA V PP ≤ VCC 3 50 200 50 200 50 200 µA V PP > VCC IPPW VPP Program Current 31 03 51 03 51 03 5 m A V PP =VPP1 Program in Progress 21 021 021 0 m A V PP = VPP2 Program in Progress IPPE VPP Erase Current 31 22 51 32 51 32 5 m A V PP = VPP1 Program in Progress 82 582 582 5 m A V PP = VPP2 Program in Progress IPPES IPPWS VPP Erase Suspend Current 3 50 200 50 200 50 200 µA V PP = VPP1 , 2 Program or Erase Suspend in Progress
E FAST BOOT BLOCK DATASHEET 31PRODUCT PREVIEW
8.4 DC Characteristics—Extended Temperature (Continued)
Sym Parameter Note Min Max Min Max Min Max Unit Test Conditions VIL Input Low Voltage VIH Input High Voltage VCCQ 0.4V VCCQ 0.2V VCCQ 0.2V V VOL Output Low Voltage VCCQ = VCCQ Min IOL = 100 µA VOH Output High Voltage VCCQ 0.1V VCCQ 0.1V VCCQ 0.1V VV CC = VCC Min VCCQ = VCCQ Min IOH = –100 µA VPPLK VPP Lock-Out Voltage 2 1.5 1.5 1.5 1.5 V Complete Write Protection VPP1 VPP during 2 2.7 3.6 V VPP2 Program and 2 2.7 2.85 V VPP3 Erase Operations 2 2.7 3.3 V VLKO VCC Prog/Erase Lock Voltage 1.5 1.5 1.5 V VLKO2 VCCQ Prog/Erase Lock Voltage 1.2 1.2 1.2 V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at normal VCC , T = +25 °C. 2. ICCES is specified with device deselected. If device is read while in erase suspend, current draw is sum of ICCES and ICCR . 3. Erases and program operations are inhibited when VPP ≤ VPPLK , and not guaranteed outside the valid VPP ranges of VPPH1 and VPPH2 . 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces I CCR to approximately standby levels, in static operation. 6. Applying VPP = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. 7. The specification is the sum of VCC and VCCQ currents.
FAST BOOT BLOCK DATASHEET E
32 PRODUCT PREVIEW
8.5 AC Characteristics—Read-Only Operations(1,6)— Extended Temperature
Product –95 –120 # Sym Parameter Notes Min Max Min Max Min Max Unit R1 t CLK CLK Period 15 15 15 ns R2 t CH (tCL ) CLK High (Low) Time 2.5 2.5 2.5 ns R3 t CHCL CLK Fall (Rise) Time 5 5 5 ns R4 t AVCH Address Valid Setup to CLK 7 7 7 ns R5 t VLCH ADV# Low Setup to CLK 7 7 7 ns R6 t ELCH CE# Low Setup to CLK 7 7 7 ns R7 t CHQV CLK to Output Delay 14 16 23 ns R8 t CHQX Output Hold from CLK 5 5 5 ns R9 t CHAX Address Hold from CLK 3 10 10 10 ns R10 t CHTL CLK to WAIT# delay 5 13 16 23 ns R11 t AVVH Address Setup to ADV# High 10 10 10 ns R12 t ELVH CE# Low to ADV# High 10 10 10 ns R13 t AVQV Address to Output Delay 90 95 120 ns R14 t ELQV CE# Low to Output Delay 2 90 95 120 ns R15 t VLQV ADV# Low to Output Delay 90 95 120 ns R16 t VLVH ADV# Pulse Width Low 10 10 10 ns R17 t VHVL ADV# Pulse Width High 4 10 10 10 ns R18 t VHAX Address Hold from ADV# High 3 3 3 3 ns R19 t APA Page Address Access Time 21 23 30 ns R20 t GLQV OE# Low to Output Delay 25 25 30 ns R21 t RHQV RST# High to Output Delay 600 600 600 ns R22 t EHQZ tGHQZ CE# or OE# High to Output in High Z, Whichever Occurs First 42 5 2 5 2 5 n s R23 t OH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 4 000 n s NOTES: 1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate. 2. OE# may be delayed up to t ELQV –tGLQV after the falling edge of CE# without impact on tELQV . 3. Address hold in synchronous burst-mode is defined as tCHAX or tVHAX , whichever timing specification is satisfied first. 4. Sampled, not 100% tested. 5. Output loading on WAIT# equals 15 pF. 6. Data bus voltage must be less than or equal to V CCQ when a read operation is initiated to guarantee AC specifications.
34 PRODUCT PREVIEW
Figure 15. AC Waveform for Asynchronous Page-Mode Read Operations
- Depending upon the frequency configuration code value in the read configuration register, insert clock cycles:
- Frequency Configuration 2 insert two clock cycles
- Frequency Configuration 3 insert three clock cycles
- Frequency Configuration 4 insert four clock cycles
- Frequency Configuration 5 insert five clock cycles
- Frequency Configuration 6 insert six clock cycles See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
Figure 16. AC Waveform for Single Synchronous Read Operations
36 PRODUCT PREVIEW
- Depending upon the frequency configuration code value in the read configuration register, insert clock cycles:
- Frequency Configuration 2 insert two clock cycles
- Frequency Configuration 3 insert three clock cycles
- Frequency Configuration 4 insert four clock cycles
- Frequency Configuration 5 insert five clock cycles
- Frequency Configuration 6 insert six clock cycles See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
Figure 17. AC Waveform for Synchronous Burst Read Operations, Four Word Burst Length,
FAST BOOT BLOCK DATASHEET E
38 PRODUCT PREVIEW
8.6 AC Characteristics—Write Operations(1, 2)—Extended Temperature
# Sym Parameter Notes Min Max Unit W1 t PHWL (tPHEL ) RST# High Recovery to WE# (CE#) Going Low 3 600 µs W2 t ELWL (tWLEL ) CE# (WE#) Setup to WE# (CE#) Going Low 6 0 ns W3 t WP Write Pulse Width 6 75 ns W4 t VLVH ADV# Pulse Width 10 ns W5 t DVWH (tDVEH ) Data Setup to WE# (CE#) Going High 4 70 ns W6 t AVWH (tAVEH ) Address Setup to WE# (CE#) Going High 4 75 ns W7 t VLEH (tVLWH ) ADV# Setup to WE# (CE#) Going High 75 ns W8 t AVVH Address Setup to ADV# Going High 10 ns W9 t WHEH (tEHWH ) CE# (WE#) Hold from WE# (CE#) High 0 ns W10 t WHDX (tEHDX ) Data Hold from WE# (CE#) High 0 ns W11 t WHAX (tEHAX ) Address Hold from WE# (CE#) High 0 ns W12 t VHAX Address Hold from ADV# Going High 3 ns W13 t WPH Write Pulse Width High 7 20 ns W14 t PHWH (tPHHEH ) WP# Setup to WE# (CE#) Going High 3 200 ns W15 t VPWH (tVPEH )V PP Setup to WE# (CE#) Going High 3 200 ns W16 t WHGL (tEHGL ) Write Recovery before Read 0 ns W17 t QVBH WP# Hold from Valid SRD 3,5 0 ns W18 t QVVL VPP Hold from Valid SRD 3,5 0 ns NOTES: 1. Read timing characteristics during block erase and program operations are the same as during read-only operations. Refer to AC Characteristics —Read-Only Operations. 2. A write operation can be initiated and terminated with either CE# or WE#. 3. Sampled, not 100% tested. 4. Refer to Table 3 for valid A IN and DIN for block erase or program. 5. V PP should be held at VPPH1/2 until determination of block erase or program success. 6. Write pulse width (tWP ) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH . 7. Write pulse width high (tWPH ) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL .
- V CC power-up and standby.
- Write block erase or program setup.
- Write block erase confirm or valid address and data.
- Automated erase or program delay.
- Read status register data.
- For read operations, OE# and CE# must be driven active, and WE# de-asserted.
Figure 20. AC Waveform for Write Operations
40 PRODUCT PREVIEW
8.7 AC Characteristics—Reset Operation—Extended Temperature
Figure 21. AC Waveform for Reset Operation Table 10. Reset Specifications
- These specifications are valid for all product versions (packages and speeds).
PLPH is < 100 ns the device may still reset but this is not guaranteed.
- If RST# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns.
- Sampled, but not 100% tested.
E FAST BOOT BLOCK DATASHEET 41PRODUCT PREVIEW
8.8 Extended Temperature Block Erase And Program Performance(3, 4, 5)
2.7 V VPP 12 V VPP
# Sym Parameter Notes Typ (1) Max Typ (1) Max Unit W19 t WHRH1 , Program Time 2 23.5 200 8 185 µs tEHRH1 Block Program Time (Parameter) 2 0.10 0.30 0.03 0.10 sec Block Program Time (Main) 2 0.8 2.4 0.24 0.8 sec tWHRH2 , Block Erase Time (Parameter) 2 1 4 0.8 4 sec tEHRH2 Block Erase Time (Main) 2 1.8 5 1.1 5 sec tWHRH5 , tEHRH5 Program Suspend Latency 6 10 5 10 µs tWHRH6 , tEHRH6 Erase Suspend Time 13 20 10 12 µs NOTES: 1. Typical values measured at TA = +25 °C and nominal voltages. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled, but not 100% tested. 5. Reference the AC Waveform for Write Operations Figure 20.
8.9 Automotive Temperature Operating Conditions
Except for the specifications given in this section, all DC and AC characteristics are identical to those listed in the extended temperature specifications. See Section 7.2 for extended temperature specifications. Symbol Parameter Notes Min Max Unit TA Operating Temperature -40 +125 °C VCC1 VCC Supply Voltage 1 3.0 3.6 V VCCQ1 I/O Voltage 1,2 3.0 3.6 V VPPH1 VPP Supply Voltage 1 3.0 3.6 V VPPH2 VPP Supply Voltage 1,3 11.4 12.6 V Cycling Parameter Block Erase Cycling 30,000 Cycles Main Block Erase Cycling 1,000 Cycles NOTES: 1. See DC Characteristics tables for voltage range-specific specifications. 2. The voltage swing on the inputs, V IN is required to match VCCQ . 3. Applying VPP = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on the main and parameter blocks. A hard connection to VPP = 11.4 V–12.6 V is not allowed and can cause damage to the device.
42 PRODUCT PREVIEW
8.10 Capacitance (1)
- Sampled, not 100% tested.
VCCQ /2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed conditions are when VCCQ = 3.0 V. Figure 22. Transient Input/Output Reference Waveform for VCC = 3.3 V ± 0.3 V See table for component values. Figure 23. Transient Equivalent Testing
3 V Standard Test 80 25K 25K
C L includes jig capacitance.
E FAST BOOT BLOCK DATASHEET 43PRODUCT PREVIEW
8.11 DC Characteristics(1) — Automotive Temperature
Sym Parameter Note Typ Max Unit Test Condition ICCS VCC Standby Current 2,6 40 60 µA V CC = VCC Max VCCQ = VCCQ Max CE# = RST# = VIH ICCR VCC Read Current 4,6 60 75 mA Asynchronous tAVAV = Min VCC = VCC Max VCCQ = VCCQ Max VIN = VIH or VIL 60 75 mA Synchronous CLK = 22 MHz CE# = VIL OE# = VIH Burst length = 1 ICCW VCC Program Current 3,5,7 8 20 mA V PP = VPPH1 (3.0 V–3.6 V) Program in progress 82 0 m A V PP = VPPH2 (11.4 V–12.6 V) Program in progress ICCE VCC Block Erase Current 3,5,7 8 20 mA V PP = VPPH1 (3.0 V–3.6 V) Block erase in progress 82 0 m A V PP = VPPH2 (11.4 V–12.6 V) Block erase in progress IPPW VPP Program Current 3,5,7 15 40 mA V PP = VPPH1 (3.0 V–3.6 V) Program in progress 10 25 mA V PP = VPPH2 (11.4 V–12.6 V) Program in progress IPPE VPP Block Erase Current 3,5,7 13 25 mA V PP = VPPH1 (3.0 V–3.6 V) Block erase in progress 82 5 m A V PP = VPPH2 (11.4 V–12.6 V) Block erase in progress NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at normal VCC , T = +25 °C. 2. Erases and program operations are inhibited when VPP ≤ VPPLK , and not guaranteed outside the valid VPP ranges of VPPH1 and VPPH2 . 3. Sampled, not 100% tested. 4. Automatic Power Savings (APS) reduces I CCR to approximately standby levels, in static operation. 5. 12 V (11.4 V–12.6 V) can only be applied to VPP for a maximum of 80 hours over the lifetime of the device. VPP should not be permanently tied to 12 V. 6. The specification is the sum of VCC and VCCQ currents.
FAST BOOT BLOCK DATASHEET E
44 PRODUCT PREVIEW
8.12 AC Characteristics—Read-Only Operations(1) — Automotive Temperature
# Sym Parameter Notes Min Max Unit R1 t CLK CLK Period 15 ns R2 t CH (tCL ) CLK High (Low) Time 2.5 ns R3 t CHCL (tCLCH ) CLK Fall (Rise) Time 5 ns R4 t AVCH Address Valid Setup to CLK 17 ns R5 t VLCH ADV# Low Setup to CLK 17 ns R6 t ELCH CE# Low Setup to CLK 17 ns R7 t CHQV CLK to Output Delay 30 ns R8 t CHQX Output Hold from CLK 5 ns R9 t CHAX Address Hold from CLK 3 10 ns R10 t CHTL (tCHTH ) CLK to WAIT# delay 5 30 ns R11 t AVVH Address Setup to ADV# Going High 19 ns R12 t ELVH CE# Low to ADV# Going High 19 ns R13 t AVQV Address to Output Delay 150 ns R14 t ELQV CE# Low to Output Delay 2 150 ns R15 t VLQV ADV# Low to Output Delay 150 ns R16 t VLVH ADV# Pulse Width 19 ns R17 t VHVL ADV# Pulse Width 19 ns R18 t VHAX Address Hold from ADV# Going High 3 3 ns R19 t APA Page Address Access Time 35 ns R20 t GLQV OE# Low to Output Delay 50 ns R21 t RHQV RST# High to Output Delay 600 ns R22 t EHQZ tGHQZ CE# or OE# High to Output in High Z, Whichever Occurs First 44 0 n s R23 t OH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 40 n s NOTES: 1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate. 2. OE# may be delayed up to t ELQV -tGLQV after the falling edge of CE# without impact on tELQV . 3. Sampled, not 100% tested. 4. Output loading on WAIT# equals 15 pF.
8.13 Automotive Temperature Frequency Configuration Settings
Table 11. Frequency Configuration Settings for Automotive Temperature Components
1 Reserved
8.14 Automotive Temperature Block Erase and Program Performance(3,4,5)
3.3 V VPP 12 V VPP
- Typical values measured at TA = +25°C and nominal voltages. Subject to change based on device characterization.
- Excludes system-level overhead.
- These performance numbers are valid for all speed versions.
- Sampled, but not 100% tested.
AC Waveform for Write Operations Figure 20.
FAST BOOT BLOCK DATASHEET E
46 PRODUCT PREVIEW
9.0 ORDERING INFORMATION
D T 2 8 F 1 6 0 F 3 T 1 2 0 Package DT = Extended temp., 56-Lead SSOP DE = Automotive temp., 56-Lead SSOP GT = Extended temp., 56-Ball µBGA* CSP Product line designator for all Intel Flash products Access Speed (ns) (95,120,150) Product Family F3 = Fast Boot Block V CC = 2.7V - 3.6V VPP = 2.7V - 3.6V or 11.4V - 12.6V Device Density 160 = x16 (16-Mbit) 800 = x16 (8-Mbit) T = Top Blocking B = Bottom Blocking VALID COMBINATIONS 56-Lead SSOP 56-Ball µBGA CSP (1) Extended 16M DT28F160F3T120 GT28F160F3T120 DT28F160F3B120 GT28F160F3B120 DT28F160F3T95 GT28F160F3T95 DT28F160F3B95 GT28F160F3B95 Extended 8M DT28F800F3T120 GT28F800F3T120 DT28F800F3B120 GT28F800F3B120 DT28F800F3T95 GT28F800F3T95 DT28F800F3B95 GT28F800F3B95 Automotive 8M DE28F800B3T150 DE28F800B3B150 NOTE: 1. The 56-Ball µBGA package top side mark reads F160F3 [or F800F3]. All product shipping boxes or trays provide the correct information regarding bus architecture.
E FAST BOOT BLOCK DATASHEET 47PRODUCT PREVIEW
10.0 ADDITIONAL INFORMATION (1,2)
Order Number Document/Tool
210830 Flash Memory Databook
292213 AP-655 Fast Boot Block Design Guide
Fast Boot Block CPU Design Guide
297846 Comprehensive User’s Guide for µBGA* Package
See Intel’s World Wide Web Home Page Micro Ball Grid Array Package Mechanical Specification and Media Information NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.