DE150-102N02A IXYS | Alldatasheet

Document overview

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Technical content

Features

  • Isolated Substrate − high isolation voltage (>2500V) − excellent thermal transfer − Increased temperature and power cycling capability
  • IXYS advanced low Qg process
  • Low gate charge and capacitances − easier to drive − faster switching
  • Low RDS(on)
  • Very low insertion inductance (<2nH)
  • No beryllium oxide (BeO) or other hazardous materials Advantages
  • Optimized for RF and high speed switching at frequencies to 30MHz
  • Easy to mount—no insulators needed
  • High power density N-Channel Enhancement Mode Low Qg and Rg High dv/dt Nanosecond Switching DRAIN SG1 SG2 GATE SD1 SD2

Symbol Test Conditions Characteristic Values (TJ = 25°C unless otherwise specified) min. typ. max. RG 5 Ω Ciss 500 pF Coss VGS = 0 V, VDS = 0.8 VDSS(max), f = 1 MHz 150 pF Crss 3 pF CStray Back Metal to any Pin 16 pF Td(on) 4 ns Ton VGS = 15 V, VDS = 0.8 VDSS ID = 0.5 IDM RG = 0.2 Ω (External) 4 ns Td(off) 4 ns Toff 4 ns Qg(on) 23 nC Qgs VGS = 10 V, VDS = 0.5 VDSS ID = 0.5 ID25 4.5 nC Qgd 14 nC Source-Drain Diode Characteristic Values (TJ = 25°C unless otherwise specified) Symbol Test Conditions min. typ. max. IS VGS = 0 V 1.5 A ISM Repetitive; pulse width limited by TJM 12 A VSD IF = IS, VGS = 0 V, Pulse test, t ≤ 300 µs, duty cycle ≤ 2% 1.8 V Trr 710 ns IXYS RF reserves the right to change limits, test conditions and dimensions. IXYS RF MOSFETS are covered by one or more of the following U.S. patents: 4,835,592 4,850,072 4,881,106 4,891,686 4,931,844 5,017,508 5,034,796 5,049,961 5,063,307 5,187,117 5,237,481 5,486,715 5,381,025 5,640,045 For detailed device mounting and installation instructions, see the “DE- Series MOSFET Mounting Instructions” technical note on IXYS RF’s web site at www.ixysrf.com/Technical_Support/App_notes.html

0 100 200 300 400 500 600 700 800 900 1000 Vds in Volts Capacitance in pF Ciss Coss Crss Capacitances vs Vds

2401 Research Blvd., Suite 108 Fort Collins, CO USA 80526 970-493-1901 Fax: 970-493-1903 Email: deiinfo@directedenergy.com Web: http://www.directedenergy.com 102N02A DE-SERIES SPICE Model The DE-SERIES SPICE Model is illustrated in Figure 1. The model is an expan- sion of the SPICE level 3 MOSFET model. It includes the stray inductive terms L G, LS and LD. Rd is the RDS(ON) of the device, Rds is the resistive leakage term. The output capacitance, COSS, and reverse transfer capacitance, CRSS are mod- eled with reversed biased diodes. This provides a varactor type response nec- essary for a high power device model. The turn on delay and the turn off delay are adjusted via Ron and Roff. Figure 1 DE-SERIES SPICE Model This SPICE model may be downloaded as a text file from the DEI web site at www.directedenergy.com/spice.htm Net List: *SYM=POWMOSN .SUBCKT 102N02A 10 20 30 * TERMINALS: D G S * 1000 Volt 1.4 Amp 7.8 ohm N-Channel Power MOSFET 10-30-2000 M1 1 2 3 3 DMOS L=1U W=1U RON 5 6 4.0 DON 6 2 D1 ROF 5 7 2.0 DOF 2 7 D1 D1CRS 2 8 D2 D2CRS 1 8 D2 CGS 2 3 500Pf RD 4 1 7.8 DCOS 3 1 D3 RDS 1 3 5.0MEG LS 3 30 .5N LD 10 4 1N LG 20 5 1N .MODEL DMOS NMOS (LEVEL=3 VTO=3 KP=.3) .MODEL D1 D (IS=.5F CJO=10P BV=100 M=.5 VJ=.2 TT=1N) .MODEL D2 D (IS=.5F CJO=100P BV=1000 M=.6 VJ=.6 TT=1N RS=10M) .MODEL D3 D (IS=.5F CJO=150P BV=1000 M=.35 VJ=.6 TT=400N RS=10M) .ENDS Doc #9200-0239 Rev 3 © 2003 IXYS RF