28F320J5 INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 PRODUCT OVERVIEW
- 2.0 PRINCIPLES OF OPERATION
- 2.1 Data Protection
- 3.0 BUS OPERATION
- 3.1 Read
- 3.2 Output Disable
- 3.3 Standby
- 3.4 Reset/Power-Down
- 3.5 Read Query
- 3.6 Read Identifier Codes
- 3.7 Write
- 4.0 COMMAND DEFINITIONS
- 4.1 Read Array Command
- 4.2 Read Query Mode Command
- 4.2.1 Query Structure Output
- 4.2.2 Query Structure Overview
- 4.2.3 Block Status Register
- 4.2.4 CFI Query Identification String
- 4.2.5 System Interface Information
- 4.2.6 Device Geometry Definition
- 4.2.7 Primary-Vendor Specific Extended
- 4.3 Read Identifier Codes Command
- 4.4 Read Status Register Command
- 4.5 Clear Status Register Command
- 4.6 Block Erase Command
- 4.7 Block Erase Suspend Command
- 4.8 Write to Buffer Command
- 4.9 Byte/Word Program Commands
- 4.10 Configuration Command
- 4.11 Set Block and Master Lock-Bit
- 4.12 Clear Block Lock-Bits Command
- 5.0 DESIGN CONSIDERATIONS
- 5.1 Three-Line Output Control
- 5.2 STS and Block Erase, Program, and Lock-
- 5.3 Power Supply Decoupling
- 5.5 Power-Up/Down Protection
- 5.6 Power Dissipation
- 6.0 ELECTRICAL SPECIFICATIONS
- 6.1 Absolute Maximum Ratings
- 6.2 Operating Conditions
- 6.3 Capacitance
- 6.4 DC Characteristics
- 6.5 AC Characteristics— Read-Only
- 6.6 AC Characteristics— Write Operations
- 6.7 Block Erase, Program, and Lock-Bit
- 7.0 ORDERING INFORMATION
- 8.0 ADDITIONAL INFORMATION
E ADVANCE INFORMATION January 1998 Order Number: 290606-004 /c110 High-Density Symmetrically-Blocked Architecture 64 128-Kbyte Erase Blocks (64 M) 32 128-Kbyte Erase Blocks (32 M) /c110 5 V VCC Operation 2.7 V I/O Capable /c110 Configurable x8 or x16 I/O /c110 120 ns Read Access Time (32 M) 150 ns Read Access Time (64 M) /c110 Enhanced Data Protection Features Absolute Protection with VPEN = GND Flexible Block Locking Block Erase/Program Lockout during Power Transitions /c110 Industry-Standard Packaging µBGA* Package, SSOP and TSOP Packages (32 M) /c110 Cross-Compatible Command Support Intel Basic Command Set Common Flash Interface Scaleable Command Set /c110 32-Byte Write Buffer 6 µs per Byte Effective Programming Time /c110 640,000 Total Erase Cycles (64 M) 320,000 Total Erase Cycles (32 M) 10,000 Erase Cycles per Block /c110 Automation Suspend Options Block Erase Suspend to Read Block Erase Suspend to Program /c110 System Performance Enhancements STS Status Output /c110 Intel StrataFlash™ Memory Flash Technology Capitalizing on two-bit-per-cell technology, Intel StrataFlash™ memory products provide 2X the bits in 1X the space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory devices are the first to bring reliable, two-bit-per-cell storage technology to the flash market. Intel StrataFlash memory benefits include: more density in less space, lowest cost-per-bit NOR devices, support for code and data storage, and easy migration to future devices. Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash memory devices take advantage of 400 million units of manufacturing experience since 1988. As a result, Intel StrataFlash components are ideal for code or data applications where high density and low cost are required. Examples include networking, telecommunications, audio recording, and digital imaging. By applying FlashFile™ memory family pinouts, Intel StrataFlash memory components allow easy design migrations from existing 28F016SA/SV, 28F032SA, and Word-Wide FlashFile memory devices (28F160S5 and 28F320S5). Intel StrataFlash memory components deliver a new generation of forward-compatible software support. By using the Common Flash Interface (CFI) and the Scaleable Command Set (SCS), customers can take advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices. Manufactured on Intel’s 0.4 micron ETOX™ V process technology, Intel StrataFlash memory provides the highest levels of quality and reliability. INTEL StrataFlash™ MEMORY TECHNOLOGY
32 AND 64 MBIT
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F320J5 and 28F640J4 may contain design defects or errors known as errata. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel’s website at http://www.intel.com COPYRIGHT © INTEL CORPORATION 1997, 1998 CG-041493 *Third-party brands and names are the property of their respective owners.
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E
4 ADVANCE INFORMATION
Figure 1. Intel StrataFlash™ Memory Block **Figure 2. µBGA* Package (64-Mbit and 32-Mbit)9** Figure 3. TSOP Lead Configuration (32-Mbit) ..10 Figure 4. SSOP Lead Configuration (64-Mbit Figure 6. Device Identifier Code Memory Map .14 Figure 10. Block Erase Suspend/Resume Figure 13. Transient Input/Output Reference Figure 14. Transient Input/Output Reference Figure 15. Transient Equivalent Testing Load Figure 16. AC Waveform for Read Operations.47 Figure 17. AC Waveform for Write Operations .49 Figure 18. AC Waveform for Reset Operation..50 Table 4. Intel StrataFlash™ Memory Command Table 5. Summary of Query Structure Output as Table 6. Example of Query Structure Output of Table 12. Primary Vendor-Specific Extended Table 17. eXtended Status Register Definitions33
REVISION HISTORY
09/01/97 -001 Original Version 09/17/97 -002 Modifications made to cover sheet 12/01/97 -003 V CC /GND Pins Converted to No Connects specification change added ICCS , ICCD , ICCW , and ICCE specification change added Order Codes specification change added 1/31/98 -004 The µBGA* chip-scale package in Figure 2 was changed to a 52-ball package and appropriate documentation added. The 64-Mb µBGA package dimensions were changed in Figure 2. Changed Figure 4 to read SSOP instead of TSOP.
E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 5ADVANCE INFORMATION
1.0 PRODUCT OVERVIEW
The Intel StrataFlash™ memory family contains high-density memories organized as 8 Mbytes or
4 Mwords (64-Mbit) and 4 Mbytes or 2 Mwords
(32-Mbit). These devices can be accessed as 8- or 16-bit words. The 64-Mbit device is organized as sixty-four 128-Kbyte (131,072 bytes) erase blocks while the 32-Mbits device contains thirty-two 128- Kbyte erase blocks. Blocks are selectively and individually lockable and unlockable in-system. See the memory map in Figure 5. A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward- compatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scaleable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board place- ment). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second— independent of other blocks. Each block can be independently erased 10,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments. This feature can improve system program performance by up to 20 times over non Write Buffer writes. Individual block locking uses a combination of bits, block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and program operations while the master lock-bit gates block lock-bit modification. Three lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands). The status register indicates when the WSM’s block erase, program, or lock-bit configuration operation is finished. The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/BY# pin. When low, STS indicates that the WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is suspended (and programming is inactive), or the device is in reset/power-down mode. Additionally, the configuration command allows the STS pin to be configured to pulse on completion of programming and/or block erases. Three CE pins are used to enable and disable the device. A unique CE logic design (see Table 2, Chip Enable Truth Table) reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM module. The BYTE# pin allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit mode; address A 0 selects between the low byte and high byte. BYTE# at logic high enables 16-bit operation; address A 1 becomes the lowest order address and address A0 is not used (don’t care). A device block diagram is shown in Figure 1. When the device is disabled (see Table 2, Chip Enable Truth Table) and the RP# pin is at VCC , the standby mode is enabled. When the RP# pin is at GND, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (t PHQV ) is required from RP# switching high until outputs
6 ADVANCE INFORMATION
and the status register is cleared. Figure 1. Intel StrataFlash™ Memory Block Diagram
Table 1. Lead Descriptions 0 input buffer is turned off when BYTE# is high). A1–A22 INPUT ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are internally latched during a program cycle. Register bit 7) to determine WSM status. outputs are disabled, or the WSM is busy. Truth Table), power reduces to standby levels. device (see Table 2, Chip Enable Truth Table). provides data protection during power transitions. during a read cycle. OE# is active low. the rising edge of the WE# pulse. alternate configurations of the STATUS pin, see the Configurations command. CCQ with a pull-up resistor.
8 ADVANCE INFORMATION
Table 1. Lead Descriptions (Continued) 0 input buffer. Address A1 then becomes the lowest order address. programming data, or configuring lock-bits. With VPEN ≤ VPENLK , memory contents cannot be altered. CCQ to the system supply voltage. GND SUPPLY GROUND: Do not float any ground pins. NC NO CONNECT: Lead is not internally connected; it may be driven or floated.
- V CC (Ball I7) and GND (Ball I2) have been removed. Future generations of Intel StrataFlash memory may make use of
these missing ball locations.
- The tolerances above indicate projected production accuracy. This product is in the design phase. The package body
for the 64 Mbit and ± 0.2 mm for the 32 Mbit.
- Address A22 is not included in 28F320J5.
- Figures are not drawn to scale.
**Figure 2. µBGA* Package (64 Mbit and 32 Mbit)**
10 ADVANCE INFORMATION
connected to their respected power supplies (i.e., Pin 37 = VCC and Pin 48 = GND). Figure 3. TSOP Lead Configuration (32 Mbit)
connected to their respected power supplies (i.e., Pin 42 = VCC and Pin 15 = GND). Figure 4. SSOP Lead Configuration (64 Mbit and 32 Mbit)
2.0 PRINCIPLES OF OPERATION
standby, and output disable operations.
12 ADVANCE INFORMATION
verified through the status register. program data from/to any other block.
2.1 Data Protection
the write lockout voltage VLKO or when RP# is VIL. alteration by gating erase and program operations.
3.0 BUS OPERATION
Figure 5. Memory Map
Table 2. Chip Enable Truth Table(1,2)
- See Application Note AP-647 Intel StrataFlash™
Memory Design Guide for typical CE configurations.
- For single-chip applications CE2 and CE1 can be
3.1 Read
PEN voltage. RP# can be at either VIH or VHH .
3.2 Output Disable
placed in a high-impedance state.
3.3 Standby
3.4 Reset/Power-Down
RP# at VIL initiates the reset/power-down mode.
14 ADVANCE INFORMATION
3.5 Read Query
3.6 Read Identifier Codes
blocks and master lock-bit setting.
3.7 Write
4.0 COMMAND DEFINITIONS
and lock-bit configuration operations.
32 Mbit
64 Mbit
in x16 mode (upper byte contains 00h). Figure 6. Device Identifier Code Memory Map
Table 3. Bus Operations
- Refer to DC Characteristics. When VPEN ≤ VPENLK , memory contents can be read, but not altered.
- X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN . See DC Characteristics for VPENLK and
- In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms.
- See Read Identifier Codes Command section for read identifier code data.
- See Read Query Mode Command section for read query data.
- Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN = VPENH and
and should not be attempted.
- Refer to Table 4 for valid DIN during a write operation.
- DQ refers to DQ0–DQ 7 if BYTE# is low and DQ0–DQ 15 if BYTE# is high.
- High Z will be VOH with an external pull-up resistor.
- See Table 2 for valid CE configurations.
- OE# and WE# should never be enabled simultaneously.
16 ADVANCE INFORMATION
Table 4. Intel StrataFlash™ Memory Command Set Definitions(14)
E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 17ADVANCE INFORMATION NOTES: 1. Bus operations are defined in Table 3. 2. X = Any valid address within the device. BA = Address within the block. IA = Identifier Code Address: see Figure 6 and Table 13. QA = Query database Address. PA = Address of memory location to be programmed. 3. ID = Data read from Identifier Codes. QD = Data read from Query database. SRD = Data read from status register. See Table 16 for a description of the status register bits. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#. CC = Configuration Code. 4. The upper byte of the data bus (DQ 8–DQ 15) during command writes is a “Don’t Care” in x16 operation. 5. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock codes. See Read Identifier Codes Command section for read identifier code data. 6. If the WSM is running, only DQ7 is valid; DQ15–DQ 8 and DQ6–DQ 0 float, which places them in a high-impedance state. 7. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing. 8. The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument. Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N = 000FH. The third and consecutive bus cycles, as determined by N, are for writing data into the Write Buffer. The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. Please see Figure 7, Write to Buffer Flowchart, for additional information. 9. The write buffer or erase operation does not begin until a Confirm command (D0h) is issued. 10. If the block is locked, RP# must be at V HH to enable block erase or program operations. Attempts to issue a block erase or program to a locked block while RP# is VIH will fail. 11. Either 40H or 10H are recognized by the WSM as the byte/word program setup. 12. If the master lock-bit is set, RP# must be at V HH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is VIH. 13. If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is VIH. 14. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 15. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E
18 ADVANCE INFORMATION
4.1 Read Array Command
Upon initial device power-up and after exit from reset/power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, program, or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend command. The Read Array command functions independently of the V PEN voltage and RP# can be VIH or VHH .
4.2 Read Query Mode Command
This section defines the data structure or “database” returned by the SCS (Scaleable Command Set) Query command. System software should parse this structure to gain critical information to enable programming, block erases, and otherwise control the flash component. The SCS Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI. The Query can only be accessed when the WSM is off or the device is suspended.
4.2.1 QUERY STRUCTURE OUTPUT
The Query “database,” described later, allows system software to gain critical information for controlling the flash component. This section describes the device’s CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest- order data outputs DQ 0–DQ 7 only. The Query table device starting address is a 10h word address. The first two bytes of the Query structure, “Q” and ”R” in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII “Q” in the low byte DQ 0–DQ 7 and 00h in the high byte DQ8–DQ 15. Since the device is x8/x16 capable, the x8 data is still presented in word-relative (16-bit) addresses. However, the “fill data” (00h) is not the same as driven by the upper bytes in the x16 mode. As in x16 mode, the byte address (A 0 or A1 depending on pinout) is ignored for Query output so that the “odd byte address” (A 0 or A1 high) repeats the “even byte address” data (A0 or A1 low). Therefore, in x8 mode using byte addressing, the device will output the beginning at byte-relative address 20h (which is equivalent to word offset 10h in x16 mode). In Query addresses where two or more bytes of information are located, the least significant data byte is presented on the lower address, and the most significant data byte is presented on the higher address.
Table 5. Summary of Query Structure Output as a Function of Device and Mode
- The system must drive the lowest order addresses to access all the device’s array data when the device is configured in x8
Table 6. Example of Query Structure Output of a x16- and x8-Capable Device
20 ADVANCE INFORMATION
4.2.2 QUERY STRUCTURE OVERVIEW
646 Common Flash Interface (CFI) and Command Sets (order number 292204) for a full description of CFI. The following sections describe the Query structure sub-sections in detail. Table 7. Query Structure
- Refer to Query Data Output section of Device Hardware interface for the detailed definition of offset address as a function
of device word width and mode.
- BA = The beginning location of a Block Address (i.e., 2000h is the beginning location of block 2 when the block size is
- The Primary Vendor-Specific Extended Query table (P) address may change among SCS-compliant devices. Software
should retrieve this address from address 15 to guarantee compatibility with future SCS-compliant devices.
4.2.3 BLOCK STATUS REGISTER
Table 8. Block Status Register
- BA = The beginning location of a Block Address (i.e., 2000h is the beginning location of block 2).
- Block Erase Status is an optional part of the SCS definition and is not incorporated on this device.
22 ADVANCE INFORMATION
4.2.4 CFI QUERY IDENTIFICATION STRING
Table 9. CFI Identification
4.2.5 SYSTEM INTERFACE INFORMATION
The following device information can optimize system interface software. Table 10. System Interface Information
24 ADVANCE INFORMATION
4.2.6 DEVICE GEOMETRY DEFINITION
This field provides critical details of the flash device geometry. Table 11. Device Geometry Definition
4.2.7 PRIMARY-VENDOR SPECIFIC EXTENDED QUERY TABLE
specifies this and other similar information. Table 12. Primary Vendor-Specific Extended Query
- The Primary Vendor-Specific Extended Query table (P) address may change among SCS-compliant devices. Software
should retrieve this address from address 15 to guarantee compatibility with future SCS-compliant devices.
26 ADVANCE INFORMATION
Table 12. Primary Vendor-Specific Extended Query (Continued)
- The Primary Vendor-Specific Extended Query table (P) address may change among SCS-compliant devices. Software
should retrieve this address from address 15 to guarantee compatibility with future SCS-compliant devices.
4.3 Read Identifier Codes
Table 13. Identifier Codes
- Block Is Unlocked DQ 0 = 0
- Block Is Locked DQ 0 = 1
- Reserved for Future Use DQ 1–7 Master Lock Configuration 00003
- Device Is Unlocked DQ 0 = 0
- Device Is Locked DQ 0 = 1
- Reserved for Future Use DQ 1–7 NOTE: 1. A 0 is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest order address line is A1. Data is always presented on the low byte in x16 mode (upper byte contains 00h). 2. X selects the specific block’s lock configuration code. See Figure 6 for the device identifier code memory map.
E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 27ADVANCE INFORMATION
4.4 Read Status Register
The status register may be read to determine when a block erase, program, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or the first edge of CE 0, CE1, or CE2 that enables the device (see Table 2, Chip Enable Truth Table). OE# must toggle to VIH or the device must be disabled (see Table 2, Chip Enable Truth Table) before further reads to update the status register latch. The Read Status Register command functions independently of the V PEN voltage. RP# can be VIH or VHH . During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid until the Write State Machine completes or suspends the operation. Device I/O pins DQ 0–DQ 6 and DQ 8– DQ 15 are placed in a high-impedance state. When the operation completes or suspends (check Status Register bit 7), all contents of the Status Register are valid when read.
4.5 Clear Status Register
Status register bits SR.5, SR.4, SR.3, and SR.1 are set to “1”s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 16). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied V PEN voltage. RP# can be VIH or VHH . The Clear Status Register Command is only valid when the WSM is off or the device is suspended.
4.6 Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires an appropriate address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 9). The CPU can detect block erase completion by analyzing the output of the STS pin or status register bit SR.7. Toggle OE#, CE 0, CE1, or CE2 to update the status register. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to “1.” Also, reliable block erasure can only occur when V CC is valid and VPEN = VPENH . If block erase is attempted while VPEN ≤ VPENLK , SR.3 and SR.5 will be set to “1.” Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that RP# = V HH . If block erase is attempted when the corresponding block lock-bit is set and RP# = V IH, SR.1 and SR.5 will be set to “1.” Block erase operations with VIH < RP# < V HH produce spurious results and should not be attempted.
4.7 Block Erase Suspend
The Block Erase Suspend command allows block-erase interruption to read or program data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bit SR.7 then SR.6 can determine when the block erase operation has been suspended (both will be set to “1”). In default mode, STS will also transition to
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E
28 ADVANCE INFORMATION
VOH . Specification tWHRH defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A program command sequence can also be issued during erase suspend to program data in other blocks. During a program operation with block erase suspended, status register bit SR.7 will return to “0” and the STS output (in default mode) will transition to V OL . The only other valid commands while block erase is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and STS (in default mode) will return to V OL . After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 10). V PEN must remain at VPENH (the same VPEN level used for block erase) while block erase is suspended. RP# must also remain at V IH or VHH (the same RP# level used for block erase). Block erase cannot resume until program operations initiated during block erase suspend have completed.
4.8 Write to Buffer Command
To program the flash device, a Write to Buffer command sequence is initiated. A variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the Write to Buffer setup command is issued along with the Block Address (see Figure 7, Write to Buffer Flowchart). At this point, the eXtended Status Register (XSR, see Table 17) information is loaded and XSR.7 reverts to "buffer available" status. If XSR.7 = 0, the write buffer is not available. To retry, continue monitoring XSR.7 by issuing the Write to Buffer setup command with the Block Address until XSR.7 = 1. When XSR.7 transitions to a “1,” the buffer is ready for loading. Now a word/byte count is given to the part with the Block Address. On the next write, a device start address is given along with the write buffer data. Subsequent writes provide additional device addresses and data, depending on the count. All subsequent addresses must lie within the start address plus the count. Internally, this device programs many flash cells in parallel. Because of this parallel programming, maximum programming performance and lower power are obtained by aligning the start address at the beginning of a write buffer boundary (i.e., A 4–A0 of the start address = 0). After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM (Write State Machine) to begin copying the buffer data to the flash array. If a command other than Write Confirm is written to the device, an “Invalid Command/Sequence” error will be generated and Status Register bits SR.5 and SR.4 will be set to a “1.” For additional buffer writes, issue another Write to Buffer setup command and check XSR.7. If an error occurs while writing, the device will stop writing, and Status Register bit SR.4 will be set to a “1” to indicate a program failure. The internal WSM verify only detects errors for “1”s that do not successfully program to “0”s. If a program error is detected, the status register should be cleared. Any time SR.4 and/or SR.5 is set (e.g., a media failure occurs during a program or an erase), the device will not accept any more Write to Buffer commands. Additionally, if the user attempts to program past an erase block boundary with a Write to Buffer command, the device will abort the Write to Buffer operation. This will generate an "Invalid Command/ Sequence" error and Status Register bits SR.5 and SR.4 will be set to a “1.” Reliable buffered writes can only occur when V PEN = VPENH . If a buffered write is attempted while VPEN ≤ VPENLK , Status Register bits SR.4 and SR.3 will be set to “1.” Buffered write attempts with invalid V CC and V PEN voltages produce spurious results and should not be attempted. Finally, successful programming requires that the corresponding Block Lock-Bit be reset or, if set, that RP# = V HH . If a buffered write is attempted when the corresponding Block Lock-Bit is set and RP# = V IH, SR.1 and SR.4 will be set to “1.” Buffered write operations with VIH < RP# < VHH produce spurious results and should not be attempted.
4.9 Byte/Word Program Commands
Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup (standard 40H or alternate 10H) is written followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM
E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 29ADVANCE INFORMATION then takes over, controlling the program and program verify algorithms internally. After the program sequence is written, the device automatically outputs status register data when read (see Figure 8). The CPU can detect the completion of the program event by analyzing the STS pin or status register bit SR.7. When program is complete, status register bit SR.4 should be checked. If a program error is detected, the status register should be cleared. The internal WSM verify only detects errors for “1”s that do not successfully program to “0”s. The CUI remains in read status register mode until it receives another command. Reliable byte/word programs can only occur when V CC and VPEN are valid. If a byte/word program is attempted while VPEN ≤ VPENLK , status register bits SR.4 and SR.3 will be set to “1.” Successful byte/word programs require that the corresponding block lock-bit be cleared or, if set, that RP# = V HH . If a byte/word program is attempted when the corresponding block lock-bit is set and RP# = V IH, SR.1 and SR.4 will be set to “1.” Byte/Word program operations with V IH < RP# < VHH produce spurious results and should not be attempted.
4.10 Configuration Command
The Status (STS) pin can be configured to different states using the Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued or RP# is asserted low. Initially, the STS pin defaults to RY/BY# operation where RY/BY# low indicates that the state machine is busy. RY/BY# high indicates that the state machine is ready for a new operation or suspended. Table 15 displays the possible STS configurations. To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed by the desired configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described below. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 00h configuration code with the Configuration command resets the STS pin to the default RY/BY# level mode. The possible configurations and their usage are described in Table 15. The Configuration command may only be given when the device is not busy or suspended. Check SR.7 for device status. An invalid configuration code will result in both status register bits SR.4 and SR.5 being set to “1.” When configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
4.11 Set Block and Master Lock-Bit
A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. The block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. With the master lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Master Lock-Bit command, in conjunction with RP# = V HH , sets the master lock-bit. After the master lock-bit is set, subsequent setting of block lock-bits requires both the Set Block Lock-Bit command and V HH on the RP# pin. These commands are invalid while the WSM is running or the device is suspended. See Table 14 for a summary of hardware and software write protection options. Set block lock-bit and master lock-bit commands are executed by a two-cycle sequence. The set block or master lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set master lock-bit confirm (and any device address). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Figure 11). The CPU can detect the completion of the set lock-bit event by analyzing the STS pin output or status register bit SR.7. When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block or Master Lock-Bit command will result in status register bits SR.4 and SR.5 being set to “1.” Also, reliable operations occur only when V CC and VPEN are valid. With VPEN ≤ VPENLK , lock-bit contents are protected against alteration.
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results and should not be attempted.
4.12 Clear Block Lock-Bits
hardware and software write protection options. mode until another command is issued. Table 14. Write Protection Alternatives
Table 15. Configuration Coding Definitions DQ 7–DQ 2 are reserved for future use. any flash device's WSM is busy. continuous buffer write operations. interrupt service routine is desired.
- When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns .
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Table 16. Status Register Definitions improper command sequence was entered. master and block lock-bit status.
Table 17. eXtended Status Register Definitions indicates that a Write Buffer is available.
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- Byte or word count values on DQ 0-DQ 7 are loaded into the
= 00H to 1FH and for word mode are N = 0000H to 000FH.
- The device now outputs the status register when read (XSR is
- Write Buffer contents will be programmed at the device start
address or destination flash address.
- Align the start address on a Write Buffer boundary for
- The device aborts the Write to Buffer command if the current
address is outside of the original block address.
- The status register indicates an "improper command
with a Clear Status Register command. Figure 7. Write to Buffer Flowchart
Repeat for subsequent programming operations. after a sequence of programming operations. implemeting lock-bit configuration. Figure 8. Byte/Word Program Flowchart
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- The Erase Confirm byte must follow Erase Setup when
the Erase Queue status (XSR.7) = 0. reset the device to read array mode. Figure 9. Block Erase Flowchart
Figure 10. Block Erase Suspend/Resume Flowchart
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Repeat for subsequent lock-bit operations. Figure 11. Set Block Lock-Bit Flowchart
Figure 12. Clear Block Lock-Bit Flowchart
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E
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5.0 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1, CE 2, OE#, and RP#) to accommodate multiple memory connections. This control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable the device (see Table 2, Chip Enable Truth Table) while OE# should be connected to all memory devices and the system’s READ# control line. This assures that only selected memory devices have active outputs while de- selected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
5.2 STS and Block Erase, Program,
and Lock-Bit Configuration Polling STS is an open drain output that should be connected to VCCQ by a pull-up resistor to provide a hardware method of detecting block erase, program, and lock-bit configuration completion. In default mode, it transitions low after block erase, program, or lock-bit configuration commands and returns to High Z when the WSM has finished executing the internal algorithm. For alternate configurations of the STS pin, see the Configuration command. STS can be connected to an interrupt input of the system CPU or controller. It is active at all times. STS, in default mode, is also High Z when the device is in block erase suspend (with programming inactive) or in reset/power-down mode.
5.3 Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE 0, CE 1, CE 2, and OE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Since Intel StrataFlash memory devices draw their power from three V CC pins (these devices do not include a VPP pin), it is recommended that systems without separate power and ground planes attach a 0.1 µF ceramic capacitor between each of the device’s three V CC pins (this includes VCCQ ) and ground. These high-frequency, low-inductance capacitors should be placed as close as possible to package leads on each StrataFlash device. Each device should have a 0.1 µF ceramic capacitor connected between its V CC and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed between V CC and GND at the array’s power supply connection. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance.
5.4 V CC , VPEN , RP# Transitions
Block erase, program, and lock-bit configuration are not guaranteed if V PEN or VCC falls outside of the specified operating ranges, or RP# ≠ VIH or VHH . If RP# transitions to VIL during block erase, program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of t PLPH + tPHRH until the reset operation is complete. Then, the operation will abort and the device will enter reset/power-down mode. The aborted operation may leave data partially corrupted after programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase and lock-bit configuration commands must be repeated after normal operation is restored. Device power-off or RP# = V IL clears the status register.
E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 41ADVANCE INFORMATION The CUI latches commands issued by system software and is not altered by VPEN , CE0, CE1, or CE 2 transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/power-down mode, or after V CC transitions below VLKO . VCC must be kept at or above VPEN during VCC transitions. After block erase, program, or lock-bit configuration, even after VPEN transitions down to VPENLK , the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. V PEN must be kept at or below VCC during VPEN transitions.
5.5 Power-Up/Down Protection
The device is designed to offer protection against accidental block erasure, programming, or lock-bit configuration during power transitions. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for V CC voltages above VLKO when VPEN is active. Since WE# must be low and the device enabled (see Table 2, Chip Enable Truth Table) for a command write, driving WE# to VIH or disabling the device will inhibit writes. The CUI’s two-step command sequence architecture provides added protection against data alteration. Keeping V PEN below VPENLK prevents inadvertent data alteration. In-system block lock and unlock capability protects the device against inadvertent programming. The device is disabled while RP# = V IL regardless of its control inputs.
5.6 Power Dissipation
When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed.
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E
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6.0 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings*
Commercial Operating Temperature During Read, Block Erase, Program, Voltage On Any Pin (except RP#) (2) RP# Voltage with Respect to GND during Lock-Bit Configuration Operations–2.0 V to +14.0 V (2,3,4) NOTICE: This datasheet contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design *WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and –0.2 V on V CC and VPEN pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on input/output pins, VCC , and VPEN is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 3. Maximum DC voltage on RP# may overshoot to +14.0 V for periods <20 ns. 4. RP# voltage is normally at VIL or VIH. Connection to supply of VHH is allowed for a maximum cumulative period of 80 hours. 5. Output shorted for no more than one second. No more than one output shorted at a time.
6.2 Operating Conditions
Temperature and VCC Operating Conditions Symbol Parameter Notes Min Max Unit Test Condition TA Operating Temperature 0 +70 °C Ambient Temperature VCC VCC1 Supply Voltage (5 V ± 10%) 4.50 5.50 V VCCQ1 VCCQ1 Supply Voltage (5 V ± 10%) 4.50 5.50 V VCCQ2 VCCQ2 Supply Voltage (2. 7V−3.6 V) 2.70 3.60 V
6.3 Capacitance (1)
TA = +25 °C, f = 1 MHz Symbol Parameter Typ Max Unit Condition C IN Input Capacitance 6 8 pF V IN = 0.0 V C OUT Output Capacitance 8 12 pF V OUT = 0.0 V NOTE: 1. Sampled, not 100% tested.
E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 43ADVANCE INFORMATION
6.4 DC Characteristics
Sym Parameter Notes Typ Max Unit Test Conditions ILI Input and VPEN Load Current 1 ±1 µAV CC = VCC Max VIN = VCC or GND ILO Output Leakage Current 1 ±10 µAV CC = VCC Max VIN = VCC or GND ICCS VCC Standby Current 1,3,5 80 150 µA CMOS Inputs, V CC = VCC Max, CE 0 = CE1 = CE2 = RP# = VCCQ1 ± 0.2 V 450 900 µA CMOS Inputs, RP# = VCC = VCC Max, CE 0 = CE1 = CE2 = VCCQ2 Min 325 650 µA CMOS Inputs, RP# = VCC = VCC Max, CE 2 = GND, CE0 = CE1 = VCCQ2 Min 210 400 µA CMOS Inputs, RP# = VCC = VCC Max, CE 1 = CE2 = GND, CE0 = VCCQ2 Min or CE 0 = CE2 = GND, CE1 = VCCQ2 Min 0.71 2 mA TTL Inputs, V CC = VCC Max, CE 0 = CE1 = CE2 = RP# = VIH ICCD VCC Power-Down Current 80 125 µA RP# = GND ± 0.2V IOUT (STS) = 0 mA ICCR VCC Read Current 1,5,6 35 55 mA CMOS Inputs, V CC = VCCQ =VCC Max Device is enabled (see Table 2, Chip Enable Truth Table) f = 5 MHz I OUT = 0 mA 45 65 mA TTL Inputs ,V CC = VCC Max Device is enabled (see Table 2, Chip Enable Truth Table) f = 5 MHz I OUT = 0 mA ICCW VCC Program or Set 1,6,7 35 60 mA CMOS Inputs, V PEN = VCC Lock-Bit Current 40 70 mA TTL Inputs, V PEN = VCC ICCE VCC Block Erase or Clear Block Lock-Bits 1,6,7 35 70 mA CMOS Inputs, V PEN = VCC Current 40 80 mA TTL Inputs, V PEN = VCC ICCES VCC Block Erase Suspend Current 1,2 10 mA Device is disabled (see Table 2, Chip Enable Truth Table)
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E
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6.4 DC Characteristics (Continued)
Sym Parameter Notes Min Max Unit Test Conditions VIL Input Low Voltage 7 –0.5 0.8 V VIH Input High Voltage 7 2.0 V CC + 0.5 V VOL Output Low Voltage 3,7 0.45 V V CCQ = VCCQ1 Min IOL = 5.8 mA
0.4 V V CCQ = VCCQ2 Min
IOL = 2 mA VOH1 Output High Voltage (TTL) 3,7 2.4 V VCCQ = VCCQ1 Min or VCCQ = VCCQ2 Min IOH = –2.5 mA (VCCQ1 ) –2 mA (VCCQ2 ) VOH2 Output High Voltage (CMOS) 3,7 0.85 VCCQ V VCCQ = VCCQ1 Min or VCCQ = VCCQ2 Min IOH = –2.5 mA VCCQ –0.4 V VCCQ = VCCQ1 Min or VCCQ = VCCQ2 Min IOH = –100 µA VPENLK VPEN Lockout during Normal Operations 4,7,11 3.6 V VPENH VPEN during Block Erase, Program, or Lock-Bit Operations 4,11 4.5 5.5 V VLKO VCC Lockout Voltage 8 3.25 V VHH RP# Unlock Voltage 9,10 11.4 12.6 V Set master lock-bit Override lock-bit NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical specifications. 2. I CCES is specified with the device de-selected. If the device is read or written while in erase suspend mode, the device’s current draw is ICCR or ICCW . 3. Includes STS. 4. Block erases, programming, and lock-bit configurations are inhibited when V PEN ≤ VPENLK , and not guaranteed in the range between VPENLK (max) and VPENH (min), and above VPENH (max). 6. Add 5 mA for VCCQ = VCCQ2 min. 7. Sampled, not 100% tested. 8. Block erases, programming, and lock-bit configurations are inhibited when V CC < VLKO , and not guaranteed in the range between VLKO (max) and VCC (min), and above VCC (max). 9. Master lock-bit set operations are inhibited when RP# = VIH. Block lock-bit configuration operations are inhibited when the master lock-bit is set and RP# = VIH. Block erases and programming are inhibited when the corresponding block-lock bit is set and RP# = VIH. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be attempted with VIH < RP# < VHH . 10. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours. 11. Tie VPEN to VCC (4.5 V–5.5 V).
INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E
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6.5 AC Characteristics— Read-Only Operations(1)
Versions 5 V ± 10% VCCQ –120/–150(4) (All units in ns unless otherwise noted)2.7 V—3.6V VCCQ –L120/–L150(4) # Sym Parameter Notes Min Max Min Max R1 t AVAV Read/Write Cycle Time 32 Mbit 120 120
64 Mbit 150 150
R2 t AVQV Address to Output Delay 32 Mbit 120 120 R3 t ELQV CE X to Output Delay 32 Mbit 2 120 120
64 Mbit 2 150 150
R4 t GLQV OE# to Output Delay 2 50 50 R5 t PHQV RP# High to Output Delay 32 Mbit 180 180
64 Mbit 210 210
R6 t ELQX CE X to Output in Low Z 3 0 0 R7 t GLQX OE# to Output in Low Z 3 0 0 R8 t EHQZ CE X High to Output in High Z 3 55 55 R9 t GHQZ OE# High to Output in High Z 3 15 15 R10 t OH Output Hold from Address, CEX, or OE# Change, Whichever Occurs First 30 0 R11 t ELFL tELFH CE X Low to BYTE# High or Low 3 10 10 R12 t FLQV tFHQV BYTE# to Output Delay 1000 1000 R13 t FLQZ BYTE# to Output in High Z 3 1000 1000 NOTES: CE X low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE 1, or CE2 that disables the device (see Table 2, Chip Enable Truth Table). 1. See Figure 16, AC Waveform for Read Operations for the maximum allowable input slew rate. 2. OE# may be delayed up to tELQV -tGLQV after the first edge of CE0, CE1, or CE2 that enables the device (see Table 2, Chip Enable Truth Table) without impact on tELQV . 3. Sampled, not 100% tested. 4. See Figures 13–15, Transient Input/Output Reference Waveform for VCCQ = 5.0 V ±10%, Transient Input/Output Reference Waveform for VCCQ = 2.7 V –3.6 V, and Transient Equivalent Testing Load Circuit for testing characteristics.
CE 1, or CE2 that disables the device (see Table 2, Chip Enable Truth Table). Figure 16. AC Waveform for Read Operations
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6.6 AC Characteristics— Write Operations(1,2)
# Sym Parameter Notes Min Max Unit W1 t PHWL (tPHEL ) RP# High Recovery to WE# (CEX ) Going Low 31 µs W2 t ELWL (tWLEL )C E X (WE#) Low to WE# (CEX) Going Low 8 0 ns W3 t WP Write Pulse Width 8 70 ns W4 t DVWH (tDVEH ) Data Setup to WE# (CEX ) Going High 4 50 ns W5 t AVWH (tAVEH ) Address Setup to WE# (CEX ) Going High 4 50 ns W6 t WHEH (tEHWH ) CE X (WE#) Hold from WE# (CEX) High 10 ns W7 t WHDX (tEHDX ) Data Hold from WE# (CEX ) High 0 ns W8 t WHAX (tEHAX ) Address Hold from WE# (CEX ) High 0 ns W9 t WPH Write Pulse Width High 9 30 ns W10 t PHHWH (tPHHEH ) RP# VHH Setup to WE# (CEX ) Going High 3 0 ns W11 t VPWH (tVPEH ) VPEN Setup to WE# (CEX ) Going High 3 0 ns W12 t WHGL (tEHGL ) Write Recovery before Read 6 35 ns W13 t WHRL (tEHRL ) WE# (CE X ) High to STS Going Low 5 90 ns W14 t QVPH RP# VHH Hold from Valid SRD, STS Going High 3,5,7 0 ns W15 t QVVL VPEN Hold from Valid SRD, STS Going High 3,5,7 0 ns NOTES: CE X low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE 1, or CE2 that disables the device (see Table 2, Chip Enable Truth Table). 1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics–Read-Only Operations. 2. A write operation can be initiated and terminated with either CEX or WE#. 3. Sampled, not 100% tested. 4. Refer to Table 4 for valid A IN and DIN for block erase, program, or lock-bit configuration. 5. STS timings are based on STS configured in its RY/BY# default mode. 6. For array access, t AVQV is required in addition to tWHGL for any accesses after a write. 7. V PEN should be held at VPENH (and if necessary RP# should be held at VHH ) until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0). 8. Write pulse width (tWP ) is defined from CEX or WE# going low (whichever goes low first) to CEX or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH . If CEX is driven low 10 ns before WE# going low, WE# pulse width requirement decreases to tWP - 10 ns. 9. Write pulse width high (tWPH ) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL .
CE 1, or CE2 that disables the device (see Table 2, Chip Enable Truth Table). STS is shown in its default mode (RY/BY#).
- V CC power-up and standby.
- Write block erase, write buffer, or program setup.
- Write block erase or write buffer confirm, or valid address and data.
- Read status register or query data.
- Write Read Array command.
Figure 17. AC Waveform for Write Operations
50 ADVANCE INFORMATION
STS is shown in its default mode (RY/BY#). Figure 18. AC Waveform for Reset Operation
- These specifications are valid for all product versions (packages and speeds).
- If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum
required RP# Pulse Low Time is 100 ns. PHQV , is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 51ADVANCE INFORMATION
6.7 Block Erase, Program, and Lock-Bit Configuration Performance(3,4)
# Sym Parameter Notes Min Typ (1) Max Unit W16 t WHQV1 tEHQV1 Write Buffer Byte Program Time 2,5 TBD 6 TBD µs W16 t WHQV2 tEHQV2 Write Buffer Word Program Time 2,5 TBD 12 TBD µs W16 t WHQV3 tEHQV3 Byte Program Time (Using Word/Byte Program Command)
2 TBD 120 TBD µs
Block Program Time (Using Write to Buffer Command) 2 TBD 0.8 TBD sec W16 t WHQV4 tEHQV4 Block Erase Time 2 TBD 1.0 TBD sec W16 t WHQV5 tEHQV5 Set Lock-Bit Time 2 TBD 12 TBD µs W16 t WHQV6 tEHQV6 Clear Block Lock-Bits Time 2 TBD 1.5 TBD sec W16 t WHRH tEHRH Erase Suspend Latency Time to Read 25 35 µs NOTES: 1. Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled but not 100% tested. 5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary.
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7.0 ORDERING INFORMATION
G = 56-Ball µBGA* CSP E = 56-Lead TSOP DA = 56-Lead SSOP Product line designator for all Intel Flash products Access Speed (ns) (120, 150) Product Family J = Intel StrataFlashTM memory, 2 bits-per-cell Device Density 640 = x8/x16 (64 Mbit) 320 = x8/x16 (32 Mbit) Voltage (VCC /VPEN ) 5 = 5V/5V Valid Operational Conditions Order Code by Density 5 V VCC 32 Mbit 64 Mbit 2.7 V – 3.6 V VCCQ
5 V ± 10%
DA28F320J5-120 DA28F640J5-150 Yes Yes G28F320J5-120 G28F640J5-150 Yes Yes E28F320J5-120 Yes Yes
E INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 53ADVANCE INFORMATION
8.0 ADDITIONAL INFORMATION (1,2)
210830 1997 Flash Memory Databook
292123 AP-374 Flash Memory Write Protection Techniques
292203 AP-644 Intel StrataFlash™ Memory Migration Guide
292204 AP-646 Common Flash Interface (CFI) and Command Sets
292205 AP-647 Intel StrataFlash™ Memory Design Guide
NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools.