87C51 INTEL | Alldatasheet
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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. October 1995COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 272335-003 87C51/80C51BH/80C31BH CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express 87C51/80C51BH/80C51BHP/80C31BH *See Table 1 for Proliferation Options Y High Performance CHMOS EPROM Y 24 MHz Operation Y Improved Quick-Pulse Programming Algorithm Y 3-Level Program Memory Lock Y Boolean Processor Y 128-Byte Data RAM Y 32 Programmable I/O Lines Y Two 16-Bit Timer/Counters Y Extended Temperature Range b40§Ct o a85§C) Y 5 Interrupt Sources Y Programmable Serial Port Y TTL- and CMOS-Compatible Logic Levels Y 64K External Program Memory Space Y 64K External Data Memory Space Y ONCE Mode Facilitates System Testing Y Power Control Modes Ð Idle Ð Power Down MEMORY ORGANIZATION PROGRAM MEMORY: Up to 4 Kbytes of the program memory can reside on-chip (except 80C31BH). In addition the device can address up to 64K of program memory external to the chip. DATA MEMORY: This microcontroller has a 12 8 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of external data memory. The Intel 87C51/80C51BH/80C31BH is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable CHMOS III-E technology. Being a member of the MCS É 51 controller family, the 87C51/80C51BH/80C31BH uses the same powerful instruction set, has the same architecture, and is pin-for- pin compatible with the existing MCS 51 controller family of products. The 80C51BHP is identical to the 80C51BH. When ordering the 80C51BHP, customers must submit the 64 byte encryption table together with the ROM code. Lock bit 1 will be set to enable the internal ROM code protection and at the same time allows code verification. The extremely low operating power, along with the two reduced power modes, Idle and Power Down, make this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. For the remainder of this document, the 87C51, 80C51BH, and 80C31BH will be referred to as the 87C51/BH, unless information applies to a specific device.
Table 1. Proliferation Options Figure 1. 87C51/BH Block Diagram
Reliability Handbook, Order No. 210997. Figure 2. Pin Connections
VCC: Supply voltage during normal, Idle and Power Down operations. VSS: Circuit ground. Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have 1’s written to them float, and in that state can be used as high-imped- ance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external memory. In this application it uses strong internal pullups when emit- ting 1’s. Port 0 also receives the code bytes during EPROM programming, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can drive LS TTL inputs. Port 1 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current IL, on the data sheet) because of the internal pull- ups. Port 1 also receives the low-order address bytes during EPROM programming and program verifica- tion. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current IL, on the data sheet) because of the internal pull- ups. Port 2 emits the high-order address byte during fetches from external Program memory and during accesses to external Data Memory that use 16-bit address (MOVX @DPTR). In this application it uses strong internal pullups when emitting 1’s. During accesses to external Data Memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the con- tents of the P2 Special Function Register. Port 2 also receives some control signals and the high-order address bits during EPROM programming and program verification. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can drive LS TTL inputs. Port 3 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current IL, on the data sheet) because of the pullups. Port 3 also serves the functions of various special features of the MCS-51 Family, as listed below: Pin Name Alternate Function P3.0 RXD Serial input line P3.1 TXD Serial output line P3.2 INT0 External Interrupt 0 P3.3 INT1 External Interrupt 1 P3.4 T0 Timer 0 external input P3.5 T1 Timer 1 external input P3.6 WR External Data Memory Write strobe P3.7 RD External Data Memory Read strobe Port 3 also receives some control signals for EPROM programming and program verification. RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the de- vice. The port pins will be driven to their reset condi- tion when a minimum V IH1 voltage is applied wheth- er the oscillator is running or not. An internal pull- down resistor permits a power-on reset with only a capacitor connected to V CC. ALE/PROG: Address Latch Enable output signal for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG ) during EPROM programming for the 87C51. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With this bit set, the pin is weakly pulled high. However, the ALE disable fea- ture will be suspended during a MOVX or MOVC in- struction, idle mode, power down mode and ICE mode. The ALE disable feature will be terminated by reset. When the ALE disable feature is suspended or terminated, the ALE pin will no longer be pulled up weakly. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
ues until the Power Down mode is transmitted. ternal interrupt can cause an exit from Power Down. the SFRs and on-chip RAM to retain their values. and stabilize (normally less than 10 ms). put the device into Power Down. window when the die is exposed to ambient light. ‘‘A’’ appended to the lot number. Table 2. Status of the External Pins during Idle and Power Down
- Pull ALE low while the device is in reset and
- Hold ALE low as RST is deactivated.
tended temperature range with or without burn-in. following guidelines in MIL-STD-883, Method 1015. prefixes are listed in Table 3. from their commercial temperature range limits. Table 3. Prefix Identification
ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias À b40§Ct o a85§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on EA /VPP Pin to V SS ÀÀÀÀÀÀÀ0V to a13.0V Voltage on Any Other Pin to V SS ÀÀb0.5V to a6.5V Maximum I OL per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W (Based on package heat transfer limitations, not de- vice power consumption.) NOTICE: This data sheet contains preliminary infor- mation on new products in production. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. OPERATING CONDITIONS Symbol Description Min Max Unit TA Ambient Temperature Under Bias Commercial 0 a70 §C Express b40 a85 §C VCC Supply Voltage 4.5 5.5 V fOSC Oscillator Frequency MHz 87C51/BH 3.5 12 87C51-1/BH-1 3.5 16 87C51-2/BH-2 0.5 12 87C51-24/BH-24 3.5 24 DC CHARACTERISTICS (Over Operating Conditions) All parameter values apply to all devices unless otherwise indicated. Symbol Parameter Min Typ(1) Max Unit Test Conditions VIL Input Low Voltage Commercial b0.5 0.2 V CC b 0.1 V Express b0.5 0.2 V CC b 0.15 V VIL1 Input Low Voltage EA Commercial 0 0.2 V CC b 0.3 V Express b0.5 0.2 V CC b 0.35 V VIH Input High Voltage (Except XTAL1, RST) Commercial 0.2 V CC a 0.9 V CC a 0.5 V Express 0.2 V CC a 1V CC a 0.5 V VIH1 Input High Voltage (XTAL1, RST) Commercial 0.7 V CC VCC a 0.5 V Express 0.7 V CC a 0.1 V CC a 0.5 V VOL Output Low Voltage (6) 0.3 V I OL e 100 mA(2) (Ports 1, 2, 3) 0.45 V I OL e 1.6 mA (2) 1.0 V I OL e 3.5 mA (2)
DC CHARACTERISTICS (Over Operating Conditions) (Continued) Symbol Parameter Min Typ(1) Max Unit Test Conditions VOL1 Output Low Voltage (6) 0.3 V I OL e 200 mA(2) (Port 0, ALE, PSEN ) 0.45 V I OL e 3.2 mA (2) 1.0 V I OL e 7.0 mA (2) VOH Output High Voltage V CC b 0.3 V I OH eb 10 mA(3) (Ports 1, 2, 3, ALE, PSEN ) VCC b 0.7 V I OH eb 30 mA(3) VCC b 1.5 V I OH eb 60 mA(3) VOH1 Output High Voltage V CC b 0.3 V I OH eb 200 mA(3) (Port 0 in External Bus Mode) VCC b 0.7 V I OH eb 3.2 mA (3) VCC b 1.5 V I OH eb 7.0 mA (3) IIL Logical 0 Input Current V IN e 0.45V (Ports 1, 2, 3) Commercial b50 mA Express b75 mA ILI Input Leakage Current g10 mA 0.45 k VIN k VCC (Port 0) ITL Logical 1-to-0 Transition Current V IN e 2V (Ports 1, 2, 3) Commercial b650 mA Express b750 mA RRST RST Pulldown Resistor 40 225 k X CIO Pin Capacitance 10 pF @ 1 MHz, 25 §C ICC Power Supply Current (Note 4) Active Mode @ 12 MHz (Figure 5) 11.5 20 mA @ 16 MHz 26 mA @ 24 MHz 38 mA Idle Mode @ 12 MHz (Figure 5) 3.5 7.5 mA @ 16 MHz 9.5 mA @ 24 MHz 13.5 mA Power Down Mode 5 50 mA
- ‘‘Typicals’’ are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp, 5V.
- Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the V
0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.
- Capacitive loading on Ports 0 and 2 may cause the V
cation when the address bits are stabilizing.
- See Figures 6 through 8 for I
CC test conditions. Minimum V CC for Power Down is 2V.
- Under steady state (non-transient) conditions, I OL must be externally limited as follows:
If I OL exceeds the test condition, V OL may exceed the related specification. Pins are not guaranteed to sink greater than the listed test conditions. Figure 5. 87C51/BH I CC vs Frequency
EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters. The first char- acter is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A:Address. C:Clock. D:Input data. H:Logic level HIGH. I:Instruction (program memory contents). L:Logic level LOW, or ALE. P:PSEN Q:Output data. R:RD signal. T:Time. V:Valid. W:WR signal. X:No longer a valid logic level. Z:Float. For example, TAVLL e Time from Address Valid to ALE Low. TLLPL e Time from ALE Low to PSEN Low. AC CHARACTERISTICS: (Over Operating Conditions; Load Capacitance for Port 0, ALE, and PSEN e 100 pF; Load Capacitance for All Other Outputs e 80 pF) EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to 87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. Symbol Parameter Oscillator Units12 MHz 24 MHz Variable Min Max Min Max Min Max 1/TCLCL Oscillator Frequency 87C51/BH 3.5 12 MHz 87C51-1/BH-1 3.5 16 MHz 87C51-2/BH-2 0.5 12 MHz 87C51-24/BH-24 3.5 24 MHz TLHLL ALE Pulse Width 127 43 2TCLCL b40 ns TAVLL Address Valid to ALE Low 87C51/BH 43 TCLCL b40 ns 87C51-24/BH-24 12 TCLCL b30 ns TLLAX Address Hold After ALE Low 53 12 TCLCL b30 ns TLLIV ALE Low to Valid Instr In 87C51/BH 234 4TCLCL b100 ns 87C51-24/BH-24 91 4TCLCL b75 ns TLLPL ALE Low to PSEN Low 53 12 TCLCL b30 ns TPLPH PSEN Pulse Width 205 80 3TCLCL b45 ns TPLIV PSEN Low to Valid Instr In 87C51/BH 145 3TCLCL b105 ns 87C51-24/BH-24 35 3TCLCL b90 ns
EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to 87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. (Continued) Symbol Parameter Oscillator Units12 MHz 24 MHz Variable Min Max Min Max Min Max TPXIX Input Instr Hold After PSEN 00 0 n s TPXIZ Input Instr Float After PSEN 87C51/BH 59 TCLCL b25 ns 87C51-24/BH-24 21 TCLCL b20 ns TAVIV Address to Valid Instr In 312 103 5TCLCL b105 ns TPLAZ PSEN Low to Address Float 10 10 10 ns TRLRH RD Pulse Width 400 150 6TCLCL b100 ns TWLWH WR Pulse Width 400 150 6TCLCL b100 ns TRLDV RD Low to Valid Data In 87C51/BH 252 5TCLCL b165 ns 87C51-24/BH-24 113 5TCLCL b95 ns TRHDX Data Hold After RD 00 0 n s TRHDZ Data Float After RD 107 23 2TCLCL b60 ns TLLDV ALE Low to Valid Data In 87C51/BH 517 8TCLCL b150 ns 87C51-24/BH-24 243 8TCLCL b90 ns TAVDV Address to Valid Data In 87C51/BH 585 9TCLCL b165 ns 87C51-24/BH-24 285 9TCLCL b90 ns TLLWL ALE Low to RD or WR Low 200 300 75 175 3TCLCL b50 3TCLCL a 50 ns TAVWL Address to RD or WR Low 87C51/BH 203 4TCLCL b130 ns 87C51-24/BH-24 77 4TCLCL b90 ns TQVWX Data Valid to WR Transition 87C51/BH 33 TCLCL b50 ns 80C51-24/BH-24 12 TCLCL b30 ns
EXTERNAL MEMORY CHARACTERISTICS All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to 87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. (Continued) Symbol Parameter Oscillator Units12 MHz 24 MHz Variable Min Max Min Max Min Max TWHQX Data Hold After WR 87C51/BH 33 TCLCL b50 ns 87C51-24/BH-24 7 TCLCL b35 ns TQVWH Data Valid to WR High 87C51/BH 433 7TCLCL b150 ns 87C51-24/BH-24 222 7TCLCL b70 ns TRLAZ RD Low to Address Float 0 0 0 ns TWHLH RD or WR High to ALE High 87C51/BH 43 123 TCLCL b40 TCLCL a40 ns 87C51-24/BH-24 12 71 TCLCL b30 TCLCL a30 ns EXTERNAL PROGRAM MEMORY READ CYCLE 272335–12 EXTERNAL DATA MEMORY READ CYCLE 272335–13
EXTERNAL DATA MEMORY WRITE CYCLE 272335-14 EXTERNAL CLOCK DRIVE All parameter values apply to all devices unless otherwise indicated. In this table, 87C51/BH refers to 87C51/BH, 87C51-1/BH-1 and 87C51-2/BH-2. Symbol Parameter Min Max Units 1/TCLCL Oscillator Frequency 87C51/BH 3.5 12 MHz 87C51-1/BH-1 3.5 16 MHz 87C51-2/BH-2 0.5 12 MHz 87C51-24/BH-24 3.5 24 MHz TCHCX High Time 87C51/BH 20 ns 8751-24/BH-24 0.35TCLCL 0.65TCLCL ns TCLCX Low Time 87C51/BH 20 ns 87C51-24/BH-24 0.35TCLCL 0.65TCLCL ns TCLCH Rise Time 87C51/BH 20 ns 87C51-24/BH-24 10 ns TCHCL Fall Time 87C51/BH 20 ns 87C51-24/BH-24 10 ns EXTERNAL CLOCK DRIVE WAVEFORM 272335–15
SERIAL PORT TIMINGÐSHIFT REGISTER MODE
12 MHz 24 MHz Variable OscillatorSymbol Parameter Oscillator Oscillator Units
TXLXL Serial Port Clock 1.0 0.500 12TCLCL ms Cycle Time TQVXH Output Data Setup 700 284 10TCLCL b133 ns to Clock Rising Edge TXHQX Output Data Hold ns After Clock Rising Edge 87C51/BH 50 2TCLCL b117 87C51-24/BH-24 34 2TCLCL b34 TXHDX Input Data Hold 0 0 0 ns After Clock Rising Edge TXHDV Clock Rising Edge 700 283 10TCLCL b133 ns to Input Data Valid SHIFT REGISTER MODE TIMING WAVEFORMS 272335–18 AC TESTING INPUT, OUTPUT WAVEFORMS 272335–19 AC inputs during testing are driven at V CC b 0.5 for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0.’’ Timing measurements are made at V IH min for a Logic ‘‘1’’ and V IL max for a Logic ‘‘0’’. FLOAT WAVEFORMS 272335–20 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded V OH/VOL level occurs. IOL/IOH e g20 mA.
returned to a high (also refer to timing diagrams). DATA LINES: P0.0–P0.7 for D0–D7. PROGRAM SIGNALS: ALE/PROG,E A /VPP. Table 4. EPROM Programming Modes Figure 10. Programming the EPROM
*For compatibility, 25 pulses may be used. Figure 11. Programming Waveforms 87C51 the following sequence must be exercised.
- Input the valid address on the address lines.
- Input the appropriate data byte on the data lines.
- Activate the correct combination of control sig-
/VPP from V CC to 12.75V g0.25V.
- Pulse ALE/PROG 5 times * for the EPROM array,
tects the onboard program against software piracy.
label be placed over the window. Erasure leaves the array in an all 1’s state. Table 5. Program Lock Bits and the Features
2 P U U MOVC instructions executed from external program memory are disabled from
reset, and further programming of the EPROM is disabled. 3 P P U Same as 2, also verify is disabled. 4 P P P Same as 3, also external execution is disabled.
EPROM PROGRAMMING, EPROM AND ROM VERIFICATION CHARACTERISTICS: (TA e 21§Ct o2 7 §C, V CC e 5V g10%, V SS e 0V) Symbol Parameter Min Max Units VPP Programming Supply Voltage 12.5 13.0 V IPP Programming Supply Current 75 mA 1/TCLCL Oscillator Frequency 4 6 MHz TAVGL Address Setup to PROG Low 48TCLCL TGHAX Address Hold After PROG 48TCLCL TDVGL Data Setup to PROG Low 48TCLCL TGHDX Data Hold After PROG 48TCLCL TEHSH P2.7 (ENABLE ) High to V PP 48TCLCL TSHGL V PP Setup to PROG Low 10 ms TGHSL V PP Hold After PROG 10 ms TGLGH PROG Width 90 110 ms TAVQV Address to Data Valid 48TCLCL TELQV ENABLE Low to Data Valid 48TCLCL TEHQZ Data Float After ENABLE 0 48TCLCL TGHGL PROG High to PROG Low 10 ms EPROM PROGRAMMING, EPROM AND ROM VERIFICATION WAVEFORMS 272335–23 *For programming conditions see Figure 10. **5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits.
All thermal impedance data is approximate for static air conditions at 1W of power dissipation. Values will change depending on operating conditions and ap- plications. See the Intel Packaging Handbook (Order No. 240800) for a description of Intel’s thermal im- pedance test methodology. Package iJA iJC Device P4 5 §C/W 16 §C/W 87C51 75§C/W 23 §C/W BH D4 5 §C/W 15 §C/W 87C51 36§C/W 13 §C/W BH N4 6 §C/W 16 §C/W All S9 8 §C/W 24 §C/W All DATA SHEET REVISION HISTORY Data sheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finaliz- ing a design or ordering devices. The following differences exist between this data- sheet (272335-003) and the previous version (272335-002): 1. Removed b20 and b3 spec, replaced with b24 spec. 2. Added b24 spec. 3. 80C51BHP is replaced by 80C51BH with 64-byte encryption table submitted and lock bit 1 set. 4. 80C51BH/80C31BH are now having some addi- tional features as 87C51. 5. Revised PRST value and I CC idle values. 6. Added P3.3 control pin to programming and veri- fication. 7. Added 80C51BH signature byte. The following differences exist between the ‘‘-002’’ and the ‘‘-001’’ version of the 87C51/80C51BH/ 80C31BH datasheet. 1. Removed bL, I OL e g10 mA from Float Wave- forms figure. 2. Removed QP, QD and QN (commercial with ex- tended burn-in) from Table 3. Prefix Identification. This data sheet (272335-001) replaces the following: 80C51BH/80C31BH Express 270218-003 80C51BHP 270603-004 87C51/80C51BH/80C31BH 270147-008 87C51 Express 270430-002 87C51-20/-3 272082-002