D8088-2

8088 INTEL | Alldatasheet

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Table 1. Pin Description local bus ‘‘hold acknowledge’’. during interrupt acknowledge and local bus ‘‘hold acknowledge’’. available on these lines during T2, T3, Tw, and T4. S6 is always low. beginning of each clock cycle. S4 and S3 are encoded as shown. These lines float to 3-state OFF during local bus ‘‘hold acknowledge’’. guaranteed to remain HIGH in T2 until the 8088 local bus has floated. This signal floats to 3-state OFF in ‘‘hold acknowledge’’.

Table 1. Pin Description (Continued) of the current instruction. This input is internally synchronized. RESET 21 I RESET: causes the processor to immediately terminate its present activity. returns LOW. RESET is internally synchronized. asymmetric with a 33% duty cycle to provide optimized internal timing. VCC 40 VCC: is the a5V g10% power supply pin. GND 1, 20 GND: are the ground pins. MN/MX 33 I MINIMUM/MAXIMUM: indicates what mode the processor is to operate in. The two modes are discussed in the following sections. functions which are unique to minimum mode are described; all other pin functions are as described above. LOW). IO/M floats to 3-state OFF in local bus ‘‘hold acknowledge’’. during T2, T3, and Tw of each interrupt acknowledge cycle. cycle. Note that ALE is never floated. 3-state OFF in local ‘‘hold acknowledge’’. during local bus ‘‘hold acknowledge’’.

the system cannot otherwise guarantee the set up time. indicate the end of a bus cycle. this first clock, they float to 3-state OFF.

GT1.R Q /GT has an internal pull-up resistor, so may be left unconnected.

1. A pulse of one CLK wide from another local bus master indicates a local

bus request (‘‘hold’’) to the 8088 (pulse 1).

1. During a T4 or TI clock cycle, a pulse one clock wide from the 8088 to the

as for when the bus is released.

1. A pulse one CLK wide from the requesting master indicates to the 8088

reclaim the local bus at the next CLK. The CPU then enters T4.

1. Request occurs on or before T2.
2. Current cycle is not the low bit of a word.
3. Current cycle is not the first acknowledge of an interrupt acknowledge
4. A locked instruction is not currently executing.
5. Local bus will be released during the next clock.
6. A memory cycle will start within 3 clocks. Now the four rules for a currently

active memory cycle apply with condition number 1 already satisfied. Ð 34 O Pin 34 is always high in the maximum mode.

Figure 3. Memory Organization dresses contained in high speed segment registers. segment type share the same logical attributes (e.g. shorter, faster, and more structured. significant byte in the next higher address location. Instructions CODE (CS) Automatic with all instruction prefetch. relative to BP base register except data references. of string operation, or explicity overridden.

Figure 5. Multiplexed Bus Configuration

Figure 8. Basic System Timing

ing the direction of the bus during read operations. In the event that a ‘‘NOT READY’’ indication is given by the addressed device, ‘‘wait’’ states (Tw) are in- serted between T3 and T4. Each inserted ‘‘wait’’ state is of the same duration as a CLK cycle. Periods can occur between 8088 driven bus cycles. These are referred to as ‘‘idle’’ states (Ti), or inactive CLK cycles. The processor uses these cycles for internal housekeeping. During T1 of any bus cycle, the ALE (address latch enable) signal is emitted (by either the processor or the 8288 bus controller, depending on the MN/MX strap). At the trailing edge of this pulse, a valid ad- dress and certain status information for the cycle may be latched. Status bits S0 ,S 1 , and S2 are used by the bus con- troller, in maximum mode, to identify the type of bus transaction according to the following table: S2 S1 S0 Characteristics 0(LOW) 0 0 Interrupt Acknowledge 0 0 1 Read I/O 0 1 0 Write I/O 0 1 1 Halt 1(HIGH) 0 0 Instruction Fetch 1 0 1 Read Data from Memory 1 1 0 Write Data to Memory 1 1 1 Passive (No Bus Cycle) Status bits S3 through S6 are multiplexed with high order address bits and are therefore valid during T2 through T4. S3 and S4 indicate which segment reg- ister was used for this bus cycle in forming the ad- dress according to the following table: S4 S3 Characteristics 0(LOW) 0 Alternate Data (Extra Segment) 0 1 Stack 1(HIGH) 0 Code or None 1 1 Data S5 is a reflection of the PSW interrupt enable bit. S6 is always equal to 0. I/O Addressing In the 8088, I/O operations can address up to a maximum of 64K I/O registers. The I/O address ap- pears in the same format as the memory address on bus lines A15–A0. The address lines A19–A16 are zero in I/O operations. The variable I/O instructions, which use register DX as a pointer, have full address capability, while the direct I/O instructions directly address one or two of the 256 I/O byte locations in page 0 of the I/O address space. I/O ports are ad- dressed in the same manner as memory locations. Designers familiar with the 8085 or upgrading an 8085 design should note that the 8085 addresses I/O with an 8-bit address on both halves of the 16- bit address bus. The 8088 uses a full 16-bit address on its lower 16 address lines. EXTERNAL INTERFACE Processor Reset and Initialization Processor initialization or start up is accomplished with activation (HIGH) of the RESET pin. The 8088 RESET is required to be HIGH for greater than four clock cycles. The 8088 will terminate operations on the high-going edge of RESET and will remain dor- mant as long as RESET is HIGH. The low-going transition of RESET triggers an internal reset se- quence for approximately 7 clock cycles. After this interval the 8088 operates normally, beginning with the instruction in absolute locations FFFF0H (See Figure 4). The RESET input is internally synchroniz- ed to the processor clock. At initialization, the HIGH to LOW transition of RESET must occur no sooner than 50 ms after power up, to allow complete initiali- zation of the 8088. NMI asserted prior to the 2nd clock after the end of RESET will not be honored. If NMI is asserted after that point and during the internal reset sequence, the processor may execute one instruction before responding to the interrupt. A hold request active immediately after RESET will be honored before the first instruction fetch. All 3-state outputs float to 3-state OFF during RESET. Status is active in the idle state for the first clock after RESET becomes active and then floats to 3-state OFF. ALE and HLDA are driven low. Interrupt Operations Interrupt operations fall into two classes: software or hardware initiated. The software initiated interrupts and software aspects of hardware interrupts are specified in the instruction set description in the iAPX 88 book or the iAPX 86,88 User’s Manual. Hardware interrupts can be classified as nonmaska- ble or maskable.

Interrupts result in a transfer of control to a new pro- gram location. A 256 element table containing ad- dress pointers to the interrupt service program loca- tions resides in absolute locations 0 through 3FFH (See Figure 4), which are reserved for this purpose. Each element in the table is 4 bytes in size and cor- responds to an interrupt ‘‘type.’’ An interrupting de- vice supplies an 8-bit type number, during the inter- rupt acknowledge sequence, which is used to vector through the appropriate element to the new interrupt service program location. Non-Maskable Interrupt (NMI) The processor provides a single non-maskable inter- rupt (NMI) pin which has higher priority than the maskable interrupt request (INTR) pin. A typical use would be to activate a power failure routine. The NMI is edge-triggered on a LOW to HIGH transition. The activation of this pin causes a type 2 interrupt. NMI is required to have a duration in the HIGH state of greater than two clock cycles, but is not required to be synchronized to the clock. Any higher going transition of NMI is latched on-chip and will be serv- iced at the end of the current instruction or between whole moves (2 bytes in the case of word moves) of a block type instruction. Worst case response to NMI would be for multiply, divide, and variable shift instructions. There is no specification on the occur- rence of the low-going edge; it may occur before, during, or after the servicing of NMI. Another high- going edge triggers another response if it occurs af- ter the start of the NMI procedure. The signal must be free of logical spikes in general and be free of bounces on the low-going edge to avoid triggering extraneous responses. Maskable Interrupt (INTR) The 8088 provides a single interrupt request input (INTR) which can be masked internally by software with the resetting of the interrupt enable (IF) flag bit. The interrupt request signal is level triggered. It is internally synchronized during each clock cycle on the high-going edge of CLK. To be responded to, INTR must be present (HIGH) during the clock peri- od preceding the end of the current instruction or the end of a whole move for a block type instruction. During interrupt response sequence, further inter- rupts are disabled. The enable bit is reset as part of the response to any interrupt (INTR, NMI, software interrupt, or single step), although the FLAGS regis- ter which is automatically pushed onto the stack re- flects the state of the processor prior to the inter- rupt. Until the old FLAGS register is restored, the enable bit will be zero unless specifically set by an instruction. During the response sequence (See Figure 9), the processor executes two successive (back to back) interrupt acknowledge cycles. The 8088 emits the LOCK signal (maximum mode only) from T2 of the first bus cycle until T2 of the second. A local bus ‘‘hold’’ request will not be honored until the end of the second bus cycle. In the second bus cycle, a byte is fetched from the external interrupt system (e.g., 8259A PIC) which identifies the source (type) of the interrupt. This byte is multiplied by four and used as a pointer into the interrupt vector lookup table. An INTR signal left HIGH will be continually responded to within the limitations of the enable bit and sample period. The interrupt return instruction includes a flags pop which returns the status of the original interrupt enable bit when it restores the flags. HALT When a software HALT instruction is executed, the processor indicates that it is entering the HALT state in one of two ways, depending upon which mode is strapped. In minimum mode, the processor issues ALE, delayed by one clock cycle, to allow the sys- tem to latch the halt status. Halt status is available on IO/M , DT/R , and SSO . In maximum mode, the processor issues appropriate HALT status on S2 , S1, and S0 , and the 8288 bus controller issues one ALE. The 8088 will not leave the HALT state when a local bus hold is entered while in HALT. In this case, the processor reissues the HALT indicator at the end of the local bus hold. An interrupt request or RESET will force the 8088 out of the HALT state. Read/Modify/Write (Semaphore) Operations via LOCK The LOCK status information is provided by the processor when consecutive bus cycles are required during the execution of an instruction. This allows the processor to perform read/modify/write opera- tions on memory (via the ‘‘exchange register with memory’’ instruction), without another system bus master receiving intervening memory cycles. This is useful in multiprocessor system configurations to ac- complish ‘‘test and set lock’’ operations. The LOCK signal is activated (LOW) in the clock cycle following decoding of the LOCK prefix instruction. It is deacti- vated at the end of the last bus cycle of the instruc- tion following the LOCK prefix. While LOCK is active, a request on a RQ /GT pin will be recorded, and then honored at the end of the LOCK.

Figure 9. Interrupt Acknowledge Sequence compatible bus control signals. dressed device will drive the READY line HIGH. Tw, the processor asserts the write control signal.

The basic difference between the interrupt acknowl- edge cycle and a read cycle is that the interrupt ac- knowledge (INTA ) signal is asserted in place of the read (RD ) signal and the address bus is floated. (See Figure 9) In the second of two successive INTA cycles, a byte of information is read from the data bus, as supplied by the interrupt system logic (i.e. 8259A priority interrupt controller). This byte identi- fies the source (type) of the interrupt. It is multiplied by four and used as a pointer into the interrupt vec- tor lookup table, as described earlier. Bus TimingÐMedium Complexity Systems (See Figure 10) For medium complexity systems, the MN/MX pin is connected to GND and the 8288 bus controller is added to the system, as well as a latch for latching the system address, and a transceiver to allow for bus loading greater than the 8088 is capable of han- dling. Signals ALE, DEN , and DT/R are generated by the 8288 instead of the processor in this configu- ration, although their timing remains relatively the same. The 8088 status outputs (S2 ,S 1 , and S0 ) pro- vide type of cycle information and become 8288 in- puts. This bus cycle information specifies read (code, data, or I/O), write (data or I/O), interrupt ac- knowledge, or software halt. The 8288 thus issues control signals specifying memory read or write, I/O read or write, or interrupt acknowledge. The 8288 provides two types of write strobes, normal and ad- vanced, to be applied as required. The normal write strobes have data valid at the leading edge of write. The advanced write strobes have the same timing as read strobes, and hence, data is not valid at the leading edge of write. The transceiver receives the usual T and OE inputs from the 8288’s DT/R and DEN outputs. The pointer into the interrupt vector table, which is passed during the second INTA cycle, can derive from an 8259A located on either the local bus or the system bus. If the master 8289A priority interrupt controller is positioned on the local bus, a TTL gate is required to disable the transceiver when reading from the master 8259A during the interrupt acknowl- edge sequence and software ‘‘poll’’. The 8088 Compared to the 8086 The 8088 CPU is an 8-bit processor designed around the 8086 internal structure. Most internal functions of the 8088 are identical to the equivalent 8086 functions. The 8088 handles the external bus the same way the 8086 does with the distinction of handling only 8 bits at a time. Sixteen-bit operands are fetched or written in two consecutive bus cycles. Both processors will appear identical to the software engineer, with the exception of execution time. The internal register structure is identical and all instruc- tions have the same end result. The differences be- tween the 8088 and 8086 are outlined below. The engineer who is unfamiliar with the 8086 is referred to the iAPX 86, 88 User’s Manual, Chapters 2 and 4, for function description and instruction set informa- tion. Internally, there are three differences between the 8088 and the 8086. All changes are related to the 8-bit bus interface. # The queue length is 4 bytes in the 8088, whereas the 8086 queue contains 6 bytes, or three words. The queue was shortened to prevent overuse of the bus by the BIU when prefetching instructions. This was required because of the additional time necessary to fetch instructions 8 bits at a time. # To further optimize the queue, the prefetching al- gorithm was changed. The 8088 BIU will fetch a new instruction to load into the queue each time there i s a 1 byte hole (space available) in the queue. The 8086 waits until a 2-byte space is available. # The internal execution time of the instruction set is affected by the 8-bit interface. All 16-bit fetches and writes from/to memory take an additional four clock cycles. The CPU is also limited by the speed of instruction fetches. This latter problem only occurs when a series of simple operations occur. When the more sophisticated instructions of the 8088 are being used, the queue has time to fill and the execution proceeds as fast as the exe- cution unit will allow. The 8088 and 8086 are completely software com- patible by virtue of their identical execution units. Software that is system dependent may not be com- pletely transferable, but software that is not system dependent will operate equally as well on an 8088 and an 8086. The hardware interface of the 8088 contains the ma- jor differences between the two CPUs. The pin as- signments are nearly identical, however, with the fol- lowing functional changes: # A8–A15ÐThese pins are only address outputs on the 8088. These address lines are latched in- ternally and remain valid throughout a bus cycle in a manner similar to the 8085 upper address lines. # BHE has no meaning on the 8088 and has been eliminated.

vide the complete bus status in minimum mode. status to be latched with ALE. Figure 10. Medium Complexity System Timing

ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias ÀÀÀÀ0 §Ct o a70§C Case Temperature (Plastic) ÀÀÀÀÀÀÀÀÀ0 §Ct o a95§C Case Temperature (CERDIP) ÀÀÀÀÀÀÀÀ0 §Ct o a75§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on Any Pin with Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b1.0 to a7V Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2.5 Watt NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. D.C. CHARACTERISTICS (TA e 0§Ct o7 0 §C, T CASE (Plastic) e 0§Ct o9 5 §C, T CASE (CERDIP) e 0§Ct o7 5 §C, TA e 0§Ct o5 5 §C and T CASE e 0§Ct o7 5 §C for P8088-2 only TA is guaranteed as long as T CASE is not exceeded) (VCC e 5V g10% for 8088, V CC e 5V g5% for 8088-2 and Extended Temperature EXPRESS) Symbol Parameter Min Max Units Test Conditions VIL Input Low Voltage b0.5 a0.8 V (Note 1) VIH Input High Voltage 2.0 V CC a 0.5 V (Notes 1, 2) VOL Output Low Voltage 0.45 V I OL e 2.0 mA VOH Output High Voltage 2.4 V I OH eb 400 mA ICC 8088 340 mA T A e 25§C Power Supply Current: 8088-2 350 P8088 250 ILI Input Leakage Current g10 mA0 V s VIN s VCC (Note 3) ILO Output and I/O Leakage Current g10 mA 0.45V s VOUT s VCC VCL Clock Input Low Voltage b0.5 a0.6 V VCH Clock Input High Voltage 3.9 V CC a 1.0 V CIN Capacitance If Input Buffer 15 pF fc e 1 MHz (All Input Except AD 0 –AD7, RQ/GT) CIO Capacitance of I/O Buffer 15 pF fc e 1 MHz AD0 –AD7, RQ/GT) NOTES: 1. V IL tested with MN/MX Pin e 0V VIH tested with MN/MX Pin e 5V MN/MX Pin is a strap Pin 2. Not applicable to RQ /GT0 and RQ /GT1 Pins (Pins 30 and 31) 3. HOLD and HLDA I LI Min e 30 mA, Max e 500 mA

A.C. CHARACTERISTICS (TA e 0§Ct o7 0 §C, T CASE (Plastic) e 0§Ct o9 5 §C, T CASE (CERDIP) e 0§Ct o7 5 §C, TA e 0§Ct o5 5 §C and T CASE e 0§Ct o8 0 §C for P8088-2 only TA is guaranteed as long as T CASE is not exceeded) (VCC e 5V g10% for 8088, V CC e 5V g5% for 8088-2 and Extended Temperature EXPRESS) MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS Symbol Parameter 8088 8088-2 Units Test Min Max Min Max Conditions TCLCL CLK Cycle Period 200 500 125 500 ns TCLCH CLK Low Time 118 68 ns TCHCL CLK High Time 69 44 ns TCH1CH2 CLK Rise Time 10 10 ns From 1.0V to 3.5V TCL2CL2 CLK Fall Time 10 10 ns From 3.5V to 1.0V TDVCL Data in Setup Time 30 20 ns TCLDX Data in Hold Time 10 10 ns TR1VCL RDY Setup Time into 8284 35 35 ns (Notes 1, 2) TCLR1X RDY Hold Time into 8284 0 0 ns (Notes 1, 2) TRYHCH READY Setup Time 118 68 ns into 8088 TCHRYX READY Hold Time 30 20 ns into 8088 TRYLCL READY Inactive to CLK b8 b8n s (Note 3) THVCH HOLD Setup Time 35 20 ns TINVCH INTR, NMI, TEST Setup Time 30 15 ns (Note 2) TILIH Input Rise Time (Except CLK) 20 20 ns From 0.8V to 2.0V TIHIL Input Fall Time (Except CLK) 12 12 ns From 2.0V to 0.8V

A.C. CHARACTERISTICS (Continued) TIMING RESPONSES Symbol Parameter 8088 8088-2 Units Test Min Max Min Max Conditions TCLAV Address Valid Delay 10 110 10 60 ns TCLAX Address Hold Time 10 10 ns TCLAZ Address Float Delay TCLAX 80 TCLAX 50 ns TLHLL ALE Width TCLCH b20 TCLCH b10 ns TCLLH ALE Active Delay 80 50 ns TCHLL ALE Inactive Delay 85 55 ns TLLAX Address Hold Time to TCHCL b10 TCHCL b10 ns ALE Inactive TCLDV Data Valid Delay 10 110 10 60 ns TCHDX Data Hold Time 10 10 ns TWHDX Data Hold Time after WR TCLCHb30 TCLCH b30 ns TCVCTV Control Active Delay 1 10 110 10 70 ns TCHCTV Control Active Delay 2 10 110 10 60 ns TCVCTX Control Inactive Delay 10 110 10 70 ns TAZRL Address Float to READ 0 0 ns Active TCLRL RD Active Delay 10 165 10 100 ns TCLRH RD Inactive Delay 10 150 10 80 ns TRHAV RD Inactive to Next TCLCL b45 TCLCL b40 ns Address Active TCLHAV HLDA Valid Delay 10 160 10 100 ns TRLRH RD Width 2TCLCL b75 2TCLCL b50 ns TWLWH WR Width 2TCLCL b60 2TCLCL b40 ns TAVAL Address Valid to ALE Low TCLCH b60 TCLCH b40 ns TOLOH Output Rise Time 20 20 ns From 0.8V to 2.0V TOHOL Output Fall Time 12 12 ns From 2.0V to 0.8V NOTES: 1. Signal at 8284A shown for reference only. See 8284A data sheet for the most recent specifications. 2. Set up requirement for asynchronous signal only to guarantee recognition at next CLK. 3. Applies only to T2 state (8 ns into T3 state).

A.C. TESTING INPUT, OUTPUT WAVEFORM 231456–11 A.C. Testing; Inputs are driven at 2.4V for a logic ‘‘1’’ and 0.45V for a logic ‘‘0’’. Timing measurements are made at 1.5V for both a logic ‘‘1’’ and logic ‘‘0’’. A.C. TESTING LOAD CIRCUIT 231456–12 CL Includes Jig Capacitance WAVEFORMS BUS TIMINGÐMINIMUM MODE SYSTEM 231456–13

WAVEFORMS (Continued) BUS TIMINGÐMINIMUM MODE SYSTEM (Continued) 231456–14 NOTES: 1. All signals switch between V OH and V OL unless otherwise specified. 2. RDY is sampled near the end of T 2,T 3,T w to determine if T w machines states are to be inserted. 3. Two INTA cycles run back-to-back. The 8088 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown for the second INTA cycle. 4. Signals at 8284 are shown for reference only. 5. All timing measurements are made at 1.5V unless otherwise noted.

A.C. CHARACTERISTICS MAX MODE SYSTEM (USING 8288 BUS CONTROLLER) TIMING REQUIREMENTS Symbol Parameter 8088 8088-2 Units Test Min Max Min Max Conditions TCLCL CLK Cycle Period 200 500 125 500 ns TCLCH CLK Low Time 118 68 ns TCHCL CLK High Time 69 44 ns TCH1CH2 CLK Rise Time 10 10 ns From 1.0V to 3.5V TCL2CL1 CLK Fall Time 10 10 ns From 3.5V to 1.0V TDVCL Data in Setup Time 30 20 ns TCLDX Data in Hold Time 10 10 ns TR1VCL RDY Setup Time into 8284 35 35 ns (Notes 1, 2) TCLR1X RDY Hold Time into 8284 0 0 ns (Notes 1, 2) TRYHCH READY Setup Time into 8088 118 68 ns TCHRYX READY Hold Time into 8088 30 20 ns TRYLCL READY Inactive to CLK b8 b8n s (Note 4) TINVCH Setup Time for Recognition 30 15 ns (INTR, NMI, TEST) (Note 2) TGVCH RQ/GT Setup Time 30 15 ns TCHGX RQ Hold Time into 8088 40 30 ns TILIH Input Rise Time (Except CLK) 20 20 ns From 0.8V to 2.0V TIHIL Input Fall Time (Except CLK) 12 12 ns From 2.0V to 0.8V

A.C. CHARACTERISTICS (Continued) TIMING RESPONSES Symbol Parameter 8088 8088-2 Units Test Min Max Min Max Conditions TCLML Command Active Delay 10 35 10 35 ns (Note 1) TCLMH Command Inactive Delay 10 35 10 35 ns (Note 1) TRYHSH READY Active to 110 65 ns Status Passive (Note 3) TCHSV Status Active Delay 10 110 10 60 ns TCLSH Status Inactive Delay 10 130 10 70 ns TCLAV Address Valid Delay 10 110 10 60 ns TCLAX Address Hold Time 10 10 ns TCLAZ Address Float Delay TCLAX 80 TCLAX 50 ns TSVLH Status Valid to ALE High 15 15 ns (Note 1) TSVMCH Status Valid to MCE High 15 15 ns (Note 1) TCLLH CLK Low to ALE Valid 15 15 ns (Note 1) TCLMCH CLK Low to MCE (Note 1) 15 15 ns TCHLL ALE Inactive Delay (Note 1) 15 15 ns TCLMCL MCE Inactive Delay (Note 1) 15 15 ns TCLDV Data Valid Delay 10 110 10 60 ns TCHDX Data Hold Time 10 10 ns CL e 20–100 pF forTCVNV Control Active Delay 5 45 5 45 ns All 8088 Outputs(Note 1) in Addition to TCVNX Control Inactive Delay 10 45 10 45 ns Internal Loads (Note 1) TAZRL Address Float to 0 0 ns Read Active TCLRL RD Active Delay 10 165 10 100 ns TCLRH RD Inactive Delay 10 150 10 80 ns TRHAV RD Inactive to Next TCLCL b45 TCLCL b40 ns Address Active TCHDTL Direction Control 50 50 ns Active Delay (Note 1) TCHDTH Direction Control 30 30 ns Inactive Delay (Note 1) TCLGL GT Active Delay 85 50 ns TCLGH GT Inactive Delay 85 50 ns TRLRH RD Width 2TCLCL b75 2TCLCL b50 ns TOLOH Output Rise Time 20 20 ns From 0.8V to 2.0V TOHOL Output Fall Time 12 12 ns From 2.0V to 0.8V NOTES: 1. Signal at 8284 or 8288 shown for reference only. 2. Setup requirement for asynchronous signal only to guarantee recognition at next CLK. 3. Applies only to T3 and wait states. 4. Applies only to T2 state (8 ns into T3 state).

A.C. TESTING INPUT, OUTPUT WAVEFORM 231456–11 A.C. Testing; Inputs are driven at 2.4V for a logic ‘‘1’’ and 0.45V for a logic ‘‘0’’. Timing measurements are made at 1.5V for both a logic ‘‘1’’ and logic ‘‘0’’. A.C. TESTING LOAD CIRCUIT 231456–12 CL Includes Jig Capacitance WAVEFORMS (Continued) BUS TIMINGÐMAXIMUM MODE SYSTEM 231456–15

WAVEFORMS (Continued) BUS TIMINGÐMAXIMUM MODE SYSTEM (USING 8288) NOTES: 231456–16 1. All signals switch between V OH and V OL unless otherwise specified. 2. RDY is sampled near the end of T 2,T 3,T w to determine if T w machines states are to be inserted. 3. Cascade address is valid between first and second INTA cycles. 4. Two INTA cycles run back-to-back. The 8088 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is shown for second INTA cycle. 5. Signals at 8284 or 8288 are shown for reference only. 6. The issuance of the 8288 command and control signals (MRDC , MWTC , AMWC , IORC , IOWC , AIOWC , INTA and DEN) lags the active high 8288 CEN. 7. All timing measurements are made at 1.5V unless otherwise noted. 8. Status inactive in state just prior to T 4.

WAVEFORMS (Continued) ASYNCHRONOUS SIGNAL RECOGNITION NOTE: 231456–17 1. Setup requirements for asynchronous signals only to guarantee recognition at next CLK. BUS LOCK SIGNAL TIMING (MAXIMUM MODE ONLY) 231456–18 REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY) NOTE: 231456–19 1. The coprocessor may not drive the busses outside the region shown without risking contention. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY) 231456–20

8086/8088 Instruction Set Summary Mnemonic and Instruction CodeDescription DATA TRANSFER MOV e Move: 76543210 76543210 76543210 76543210 Register/Memory to/from Register 100010dw m o d r e g r / m Immediate to Register/Memory 1100011w m o d000r / m data data if w e 1 Immediate to Register 1011wr e g data data if w e 1 Memory to Accumulator 1010000w addr-low addr-high Accumulator to Memory 1010001w addr-low addr-high Register/Memory to Segment Register 10001110 m o d0r e gr / m Segment Register to Register/Memory 10001100 m o d0r e gr / m PUSH e Push: Register/Memory 11111111 m o d110r / m Register 01010r e g Segment Register 000r e g110 POP e Pop: Register/Memory 10001111 m o d000r / m Register 01011r e g Segment Register 000r e g111 XCHG e Exchange: Register/Memory with Register 1000011w m o dr e gr / m Register with Accumulator 10010r e g IN e Input from: Fixed Port 1110010w port Variable Port 1110110w OUT e Output to: Fixed Port 1110011w port Variable Port 1110111w XLAT e Translate Byte to AL 11010111 LEA e Load EA to Register 10001101 m o dr e gr / m LDS e Load Pointer to DS 11000101 m o dr e gr / m LES e Load Pointer to ES 11000100 m o dr e gr / m LAHF e Load AH with Flags 10011111 SAHF e Store AH into Flags 10011110 PUSHF e Push Flags 10011100 POPF e Pop Flags 10011101

8086/8088 Instruction Set Summary (Continued) Mnemonic and Instruction CodeDescription ARITHMETIC 76543210 76543210 76543210 76543210 ADD e Add: Reg./Memory with Register to Either 000000dw m o dr e gr / m Immediate to Register/Memory 100000sw m o d000r / m data data if s:w e 01 Immediate to Accumulator 0000010w data data if w e 1 ADC e Add with Carry: Reg./Memory with Register to Either 000100dw m o dr e gr / m Immediate to Register/Memory 100000sw m o d010r / m data data if s:w e 01 Immediate to Accumulator 0001010w data data if w e 1 INC e Increment: Register/Memory 1111111w m o d000r / m Register 01000r e g AAA e ASCII Adjust for Add 00110111 BAA e Decimal Adjust for Add 00100111 SUB e Subtract: Reg./Memory and Register to Either 001010dw m o dr e gr / m Immediate from Register/Memory 100000sw m o d101r / m data data if s:w e 01 Immediate from Accumulator 0010110w data data if w e 1 SSB e Subtract with Borrow Reg./Memory and Register to Either 000110dw m o dr e gr / m Immediate from Register/Memory 100000sw m o d011r / m data data if s:w e 01 Immediate from Accumulator 000111w data data if w e 1 DEC e Decrement: Register/memory 1111111w m o d001r / m Register 01001 r e g NEG e Change sign 1111011w m o d011 r / m CMP e Compare: Register/Memory and Register 001110dw m o dr e gr / m Immediate with Register/Memory 100000sw m o d111r / m data data if s:w e 01 Immediate with Accumulator 0011110w data data if w e 1 AAS e ASCII Adjust for Subtract 00111111 DAS e Decimal Adjust for Subtract 00101111 MUL e Multiply (Unsigned) 1111011w m o d100r / m IMUL e Integer Multiply (Signed) 1111011w m o d101r / m AAM e ASCII Adjust for Multiply 11010100 00001010 DIV e Divide (Unsigned) 1111011w m o d110r / m IDIV e Integer Divide (Signed) 1111011w m o d111r / m AAD e ASCII Adjust for Divide 11010101 00001010 CBW e Convert Byte to Word 10011000 CWD e Convert Word to Double Word 10011001

8086/8088 Instruction Set Summary (Continued) Mnemonic and Instruction CodeDescription LOGIC 76543210 76543210 76543210 76543210 NOT e Invert 1111011w m o d010r / m SHL/SAL e Shift Logical/Arithmetic Left 110100vw m o d100r / m SHR e Shift Logical Right 110100vw m o d101r / m SAR e Shift Arithmetic Right 110100vw m o d111r / m ROL e Rotate Left 110100vw m o d000r / m ROR e Rotate Right 110100vw m o d001r / m RCL e Rotate Through Carry Flag Left 110100vw m o d010r / m RCR e Rotate Through Carry Right 110100vw m o d011r / m AND e And: Reg./Memory and Register to Either 001000dw m o dr e gr / m Immediate to Register/Memory 1000000w m o d100r / m data data if w e 1 Immediate to Accumulator 0010010w data data if w e 1 TEST e And Function to Flags. No Result: Register/Memory and Register 1000010w m o dr e gr / m Immediate Data and Register/Memory 1111011w m o d000r / m data data if w e 1 Immediate Data and Accumulator 1010100w data data if w e 1 OR e Or: Reg./Memory and Register to Either 000010dw m o dr e gr / m Immediate to Register/Memory 1000000w m o d001r / m data data if w e 1 Immediate to Accumulator 0000110w data data if w e 1 XOR e Exclusive or: Reg./Memory and Register to Either 001100dw m o dr e gr / m Immediate to Register/Memory 1000000w m o d110r / m data data if w e 1 Immediate to Accumulator 0011010w data data if w e 1 STRING MANIPULATION REP e Repeat 1111001z MOVS e Move Byte/Word 1010010w CMPS e Compare Byte/Word 1010011w SCAS e Scan Byte/Word 1010111w LODS e Load Byte/Wd to AL/AX 1010110w STOS e Stor Byte/Wd from AL/A 1010101w CONTROL TRANSFER CALL e Call: Direct Within Segment 11101000 disp-low disp-high Indirect Within Segment 11111111 m o d010r / m Direct Intersegment 10011010 offset-low offset-high seg-low seg-high Indirect Intersegment 11111111 m o d011r / m

8086/8088 Instruction Set Summary (Continued) Mnemonic and Instruction CodeDescription JMP e Unconditional Jump: 76543210 76543210 76543210 Direct Within Segment 11101001 disp-low disp-high Direct Within Segment-Short 11101011 disp Indirect Within Segment 11111111 m o d100r / m Direct Intersegment 11101010 offset-low offset-high seg-low seg-high Indirect Intersegment 11111111 m o d101r / m RET e Return from CALL: Within Segment 11000011 Within Seg Adding Immed to SP 11000010 data-low data-high Intersegment 11001011 Intersegment Adding Immediate to SP 11001010 data-low data-high JE/JZ e Jump on Equal/Zero 01110100 disp JL/JNGE e Jump on Less/Not Greater 01111100 dispor Equal JLE/JNG e Jump on Less or Equal/ 01111110 dispNot Greater JB/JNAE e Jump on Below/Not Above 01110010 dispor Equal JBE/JNA e Jump on Below or Equal/ 01110110 dispNot Above JP/JPE e Jump on Parity/Parity Even 01111010 disp JO e Jump on Overflow 01110000 disp JS e Jump on Sign 01111000 disp JNE/JNZ e Jump on Not Equal/Not Zero 01110101 disp JNL/JGE e Jump on Not Less/Greater 01111101 dispor Equal JNLE/JG e Jump on Not Less or Equal/ 01111111 dispGreater JNB/JAE e Jump on Not Below/Above 01110011 dispor Equal JNBE/JA e Jump on Not Below or 01110111 dispEqual/Above JNP/JPO e Jump on Not Par/Par Odd 01111011 disp JNO e Jump on Not Overflow 01110001 disp JNS e Jump on Not Sign 01111001 disp LOOP e Loop CX Times 11100010 disp LOOPZ/LOOPE e Loop While Zero/Equal 11100001 disp LOOPNZ/LOOPNE e Loop While Not 11100000 dispZero/Equal JCXZ e Jump on CX Zero 11100011 disp INT e Interrupt Type Specified 11001101 type Type 3 11001100 INTO e Interrupt on Overflow 11001110 IRET e Interrupt Return 11001111

8086/8088 Instruction Set Summary (Continued) Mnemonic and Instruction CodeDescription 76543210 76543210 PROCESSOR CONTROL CLC e Clear Carry 11111000 CMC e Complement Carry 11110101 STC e Set Carry 11111001 CLD e Clear Direction 11111100 STD e Set Direction 11111101 CLI e Clear Interrupt 11111010 STI e Set Interrupt 11111011 HLT e Halt 11110100 WAIT e Wait 10011011 ESC e Escape (to External Device) 11011xxx m o dxxxr / m LOCK e Bus Lock Prefix 11110000 NOTES: AL e 8-bit accumulator AX e 16-bit accumulator CX e Count register DS e Data segment ES e Extra segment Above/below refers to unsigned value Greater e more positive: Less e less positive (more negative) signed values if d e 1 then ‘‘to’’ reg; if d e 0 then ‘‘from’’ reg if w e 1 then word instruction; if w e 0 then byte instruction if mod e 11 then r/m is treated as a REG field if mod e 00 then DISP e 0*, disp-low and disp-high are absent if mod e 01 then DISP e disp-low sign-extended to 16 bits, disp-high is absent if mod e 10 then DISP e disp-high; disp-low if r/m e 000 then EA e (BX) a (SI) a DISP if r/m e 001 then EA e (BX) a (DI) a DISP if r/m e 010 then EA e (BP) a (SI) a DISP if r/m e 011 then EA e (BP) a (DI) a DISP if r/m e 100 then EA e (SI) a DISP if r/m e 101 then EA e (DI) a DISP if r/m e 110 then EA e (BP) a DISP* if r/m e 111 then EA e (BX) a DISP DISP follows 2nd byte of instruction (before data if re- quired) *except if mod e 00 and r/m e then EA e disp-high: disp-low. if s:w e 01 then 16 bits of immediate data form the oper- and if s:w e 11 then an immediate data byte is sign extended to form the 16-bit operand if v e 0 then ‘‘count’’ e 1; if v e 1 then ‘‘count’’ in (CL) register x e don’t care z is used for string primitives for comparison with ZF FLAG SEGMENT OVERRIDE PREFIX 001r e g110 REG is assigned according to the following table: 16-Bit (w e 1) 8-Bit (w e 0) Segment

000 AX 000 AL 00 ES

001 CX 001 CL 01 CS

010 DX 010 DL 10 SS

011 BX 011 BL 11 DS

100 SP 100 AH

101 BP 101 CH

110 SI 110 DH

111 DI 111 BH

Instructions which reference the flag register file as a 16-bit object use the symbol FLAGS to represent the file: FLAGS e X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF) Mnemonics © Intel, 1978 DATA SHEET REVISION REVIEW The following list represents key differences be- tween this and the -005 data sheet. Please review this summary carefully. 1. The Intel 8088 implementation technology (HMOS) has been changed to (HMOS-II).