D8085AH INTEL | Alldatasheet
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Technical content
8085AH-1 are faster versions of the BO85AH. Provided for the 8080A, thereby offering a higher level of system integration.
2317181 Contig ti
Figure 1. 8085AH CPU Functional Block Diagram
Table 1. Pin Description ' \\/O address, 3-stated during Hold and Halt modes and during RESET. cycle. It then becomes the data bus during the second and third clock cycles. cycle and enables the address to get latched into the on-chip latch of peripherals. information. ALE is never 3-stated. edge of ALE may be used to latch the state of these lines. Hold and Halt modes and during RESET. of WR. 3-stated during Hold and Halt modes and during RESET. or write cycle. READY must conform to specified setup and hold times.
Table 1. Pin Description (Continued) ! activate an 8259A Interrupt chip or some other interrupt port. RST 65 ‘except they cause an internal RESTART to be automatically inserted. internal registers and flags may be altered by RESET with unpredictable results. frequency is divided by 2 to give the processor's internal operating frequency. whenever a RIM instruction is executed. veo |_| POWER: +5 vot suppy. Table 2. Interrupt Priority, Restart Address and Sensitivity :
- The processor pushes the PC on the stack before branching to the indicated address.
- The address branched to depends on the instruction provided to the CPU when the interrupt is acknowledged.
TRAP interrupt, and a bus vectored interrupt, INTR. Figure 3. Power-On Reset Circult nownashable, The 80B5AH has twelve addressable 8-bit registers. “79e-sensitive. sP Stack Pointer _16-Bit Address interrupt is masked out. dress is split between the higher 8-bit Address Bus User's Manual) . signals for bus control. An Interrupt Acknowledge —_fore the end of the RST 7.5 routine.
Figure 4. TRAP and RESET In Circuit than approximately 5 MHz. rent interrupt enable status. Performing a RIM in- matoly 3 MHz ie ney tocomme ae that PP r on. current Interrupt Enable status, revealing that inter- _ °S greatly higher or lower attempted. must be twice the desired internal clock frequency; _&Ck to X; through the driving circuit.
nique is as shown in Figure 7. 1/0 using 8085AH. space is assigned for I/O address, thereby, using shown in Figure 9. Figure 7. 8085AH Minimum System (Standard I/O Technique)
Figure 8. 8085 Minimum System (Memory Mapped 1/0)
Figure 9. 8085 System (Using Standard Memories)
would occur during processing of the OUT instruc- data is to take place, so are used as command lines. status of the three status lines (IO/M, Sy, Sq) and _ ble states, shown in Table 4. Table 3. 8085AH Machine Cycle Chart Table 4. 8085AH Machine State Chart ALE not generated during 2nd and Grd machine cycies of DAD instruction. TIO/M = 1 during T4-Te of INA machine cycte.
Figure 10. 8085AH Basic System Timing
8085AH/8085AH-2/8085AH-1 intel : ABSOLUTE MAXIMUM RATINGS* ' Voltage on Any Pin Those are wress ratnge only Cooraion Desond to may atfect device reliability. D.C. CHARACTERISTICS 8085AH, 8085AH-2: Ta = 0°C to 70°C, Voc = 5V +10%, Vgg = OV; unless otherwise ‘specified* 8085AH-1: Ta = 0°C to 70°C, Voc = 5V +5%, Vsg = OV; unless otherwise specified* [| symbot [Parameter [Min | Max | Unite | TeetGondltione | | vu | inputtowVotage | -os [| +oe [ v [i | vn | inputighvottage [20 | vec+os [ v | [ Yo. | Outputtowvotage || oa Tv | tema | You | OuputighVotage | 24 | | Vi t= —400nA | loo Power SupplyCurent | | 138 | mA | @085AH, B085AH-2 | [| rsevonn [fe tm | seston | | m ___| tnputteakage || eto [nA | OS VS Veo | [to | Outputteakege || et [nA | 0.48 < Vour < Voo _| | Yun | inputtowLever Reser | -os | +oe [| v |_| | Vina | inputtigh Level RESET | 24 | Voo+os | v | _—i L vay | HystoresisneseT | ors [| ov | Cd A.C. CHARACTERISTICS 8085AH, 8085AH-2: Ta = 0°C to 70°C, Voc = 5V +10%, Vss = OV* 8085AH-1: Ta = 0°C to 70°C, Voc = 5V +5%, Vos = OV pes reeme e ee | [min | Max | in | Max [ min [ wax | ltove [CLK OyclePeriod | 820 | 2000 200 | 2000 | 167 | 2000 | ns | [tr___ [otk Low Time Standard CLK Loading) [eo [| 40 | | 20 | ‘| as | |tz___ [CLK High Time Standard GLK Loading) | 120 [| 70 | | 50 | | ne | ltt _[CikRiseandraitime || go | | 30 | «| 30 | re | [ix _[XrRlisingtoCLKRising | 20 ‘| 120 | 20 | 100 | 20 | 100 | re | lixr _[XrRiisingtoCLKFaling | 20 | 150 | 20 | 110 | 20 | 110 | ns | [two |As-15Valid to Leading Edge of Control | 270 [ [115] | 70 | ‘| ns | [tac _[Ao-rValidtoLeading Edge otContr [240 [| tis] | 60 | ‘| ns | [mo [Ao-ssValidtoVaiddatan || 76 | | 50 | | 22s | as | Gam ia READ (INTA) [w___[Av-15 Valid before Traling Edge of ALEC] 115 | [60 | | 25 | | re | *NOTE: For Extended Temperature EXPRESS use MB085AH Electricals Parameters. 1-22 |
intel . 8085AH/8085AH-2/8085AH-1 A.C. CHARACTERISTICS (Continued) ! [pre ream a | | Min | Max | Min | Max | Min | Max | [tar _[Ao-7Validbetore Trailing Edge of ALE | 90 | | 50 | | 25 | ‘| _ns | [way [READY ValidtromAddress Vaid |_| 220 | ‘| 100 | | 40 | ns | [tca [Address (Ag-16) Validafter Control | 120 | | 60 | | 30 | ‘| ns | ill Ra ad Rd Edge of ALE ie al of ALE [tow [Data Valid to TriaingEdge of WRITE | 420 || 200 [| 40 || ns | [tuase [HUDAtoBusenable || ato | [160 | | 150 | ns | [tuase [BusFloatafterHiDA || ato || t50 || 150 | ns | [tuack [HLDA Valid to Trailing Edge of CLK [tio [| ao [| oo [| ns | [ton [HOLDHoldTime | TT oo To Ts | [tos [HOLD Setup Time to Trailing Edge of cLK| 170 | | 120 [| 120 | | ns | [wn [INTRHoWTime To TC lo | CP lo fC ns | ial il Rd i Falling Edge of CLK [wa___[AddressHoldTimeafteraLE [| too [| 50 | | 20 | ins | i lal of Control [tox [ALE Low During CLKHigh [too [Tso [Tas [| ns | won [ALE toValid DataduringRead || 460 || 270 | [175 | ns | [wow [ALE toValid DataduringWrte [| 200 || 140 | [110 | ns | tux faLewidtn to Teo [0 Ts | [tury [ALEtOREADY Stable Tf to || 30 [10 ‘| ns | ld of Address [tao [READ (orINTA)toValidData || 300 || 50 | [75 | ns | ice dK of Next Control [taon _|DataHold Time ater READINTA | o | | o [| o [| ns | [tavn [READYHoldTime | TT oo Ts | ns | iia Ad al of CLK [two [Data Valid after Traiing Edge ofwAITE | too | | 60 | | 30 | ‘| ns | [wor [LEADING Edge of WRITE toDatavaid [| {40 | [ 20 | [ 90 | ns | Noias address Specs apply 10/M, So, and S; except Ag~A1s are undefined during Ty-Ts of OF cycle whereas 10/M, So, and S; are stable. 2. Test Conditions: tcyc = 320 ns (8085AH)/200 ns (8085AH-2);/167 ns (8085AH-1); C, = 150 pF. 3. For all output timing where C % 150 pF use the following correction factors: 25 pF < Cy < 150 pF: —0.10 ns/pF 150 pF < G, < 300 pF: +0.30 ns/pF 4. Output timings are measured with purely capacitive load. 5. To calculate timing specifications at other values of tcyc use Table 5. | 1-23
Logic “1" and 0.8V for a Logic “0”. Table 5. Bus Timing Specification as a Tcyc Dependent N is equal to the total WAIT states. T = toyc.
intel ° 8085AH/8085AH-2/8085AH-1 WAVEFORMS CLOCK +4) ne sae zarrt8-17 READ I in l ” ! 4 1 y ko| = a Ap ADs > gee See | RONNTA Lue NL ws 231718-18 WRITE | % ] ® \\ 5 \\ 5 FE kx—| fe tom toa ft —l im IEEE he: ta} “ 231718-19 | 1-25
8085AH/8085AH-2/8085AH-1 intel . WAVEFORMS (Continued) HOLD a ty Twouw Two 5 wre loo | torre READ OPERATION WITH WAIT CYCLE (TYPICAL}—SAME READY TIMING APPLIES TO WRITE Jo we | l-—tca —e| wan MO Taconess [xX ROBT jo— tee > tan ete net reso i sarne-as NOTE: 1, Ready must remain stable during setup and hold times. 1-26 |
intel : 8085AH/8085AH-2/8085AH-1 WAVEFORMS (Continued) INTERRUPT AND HOLD fs fs fu fu [wu fw | ww fos fs | nl | =X) —) i | _ ‘naa tat tet te | wore LF \\R.i | ‘wos. oH ) At. zarrie-22 “NOTE: 10/M is also floating during this time. | 1-27
Table 6. Instruction Set Summary
Table 6. Instruction Set Summary (Continued) ) [rst [1 1 AAA 1 1 1]Rosan | prom A wih borrow.
Table 6. instruction Set Summary (Continued) , Rotate A right INEW 8085AH INSTRUCTIONS.
- Two possible cycle times (6/12) indicate instruction cycles dependent on condition flags.
All mnemonics copyrighted ©intel Corporation 1976.