D8051

P8031AH INTEL | Alldatasheet

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• ~S INTEL CORP (UP/PRPHLS) a0— D MM 4426175 0079078 6 a intel’ : . PRELIMINARY -. MCS®-51 T#9-19-07 8-BIT CONTROL-ORIENTED MICROCOMPUTERS 8031AH/8051AH 8032AH/8052AH 8751H/8751H-8 m High Performance HMOS Process @ Boolean Processor mw Internal Timers/Event Counters m Bit-Addressable RAM - m@ 2-Level Interrupt Priority Structure m Programmable Full Duplex Serial m 32 1/0 Lines (Four 8-Bit Ports) Channel mm 64K Program Memory Space . 111 Instructions (64 Single-Cycle) m Security Feature Protects EPROM Parts 64K Data Memory Space Against Software Piracy . The MCS®-51 products are optimized for control applications. Byte-processing and numerical operations on small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instruc- tions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit manipulation and testing in control and logic systems that require Boolean processing. . ‘The 8051 Is the original member of the MCS-51 family. The 8051AH Is identical to the 8051, but itis fabricated with HMOS II technology. The 8751H is an EPROM version of the 8051AH; that is, the on-chip Program Memory can be electrically programmed, and can be erased by exposure to ultraviolet light. it is fully compatible with its predecessor, the 8751-8, but incorporates two new features: a Program Memory Security bit that can be used to protect the EPROM against unauthorized read-out, and a programmable baud rate modification bit (SMOD). The 8751H-8 is identical to the 8751H but only operates up to 8 MHz. ‘The 8052AH is an enhanced version of the 8051AH. It is backwards compatible with the 8051AH and is fabricated with HMOS II technology. The 8052AH enhancements are listed in the table below. Also refer to this table for the ROM, ROMless, and EPROM versions of each product. Timers/ 8052AH 8K x8 ROM 256 x8 RAM 8x 16-Bit 8051AH 4K x8 ROM 128 x8 RAM 2x 16-Bit 8051 4K x8 ROM 128x8 RAM 2x 16-Bit 8032AH none 256 x8 RAM 3x 16-Bit 8031AH none 128 x8 RAM 2x 16-Bit 8031 none 128 x8 RAM 2x 16-Bit 8751H 4K x 8 EPROM 128 x8 RAM 2x 16-Bit 8751H-8 4K x 8 EPROM 128 x8 RAM 2x 16-Bit ES : October 1988 7-44 Order Number: 270048-004 I g i a ry

Figure 1. MCS®-51 Block Diagram . 44-Pin PLCC. that state can be used as high-impedance inputs. 8751H-8 44-Pin LCC sink 8 LS TTL inputs.

INTEL CORP (UP/PRPHLS) 20€ D mm 4826175 0079080 & intel MCS®-514 PRELIMINARY a T-49-19-07 Lan 6052/8092 ONLY ns & po cfi rr) 5) e p12Cj3 38 Po. aot z z 2 eds 276 po avz R2iiie S222? pra cds 386 po apa SEER lciokG piss 35 P04 ADS pis ys 3] P04 (ADA) ers C7 4B pos aps pis ty; 4] P08 (A058) pre 235 Pos ADS pi7 [x2 St] Pos (ave) RST C]9 32/5 p07 ao7 ast fies 4] P07 (ann) XO P30 C10 31D EWVpp* (AKO) P20 313 Gt] EAVpp* x0 P31 Git 32055 ALEPROG: we fas tine INTO P3.2 Cj 12 23 PSEN qxopeas tis - i] ALE/PROG : NTi aa ia 20Fie2z ais (nto) eas fs . i] PSEN Torsha a7 pzsats ant paa fat tiifea7am T1pas Cts 26 P25 a3 ‘qo paa Hit talenseate) Wass 16 2565 p24 Anz qayeas Hit ueleastata) RO P37 h17 Be r2aat 2D RU RARERAR xTAL2 C] 18 23D P22 ato ae . AAS xTALI Ch9 225 p21 a 5 a ce: ee tor PErETT eH ee 83228 Pin (DIP) sroos-3 Pad (LCC, PLCC) . “EPROM only : Figure 2, MCS®-51 Connections Port 1; Port 1 is an 8-bit bidirectional I/O port with ing accesses to external Data Memory that use 8-bit internal pullups. The Port 1 output buffers can sink/ addresses (MOVX @Ri), Port 2 emits the contents of source 4 LS TTL inputs. Port 1 pins that have 1s the P2 Special Function Register. written to them are pulled high by the internal pull- ups, and in that state can be used as inputs, As Port 2 also receives the high-order address bits dur- inputs, Port 1 pins that are externally being pulled ing programming of the EPROM parts and during tow will source current (Ij_ on the data sheet) be- program verification of the ROM and EPROM parts. cause of the internal pullups. Port 3; Port 3 is an 8-bit bidirectional I/O port with Port 1 also’ receives the low-order address bytes internal pullups, The Port 3 output buffers can sink/ during programming of the EPROM parts and during source 4 LS TTL inputs. Port 3 pins that have 1s program verification of the ROM and EPROM parts. —_ written to them are pulled high by the internal pull- ups, and in that state can be used as inputs. As In the 8032AH and 8052AH, Port 1 pins P1.0 and inputs, Port 3 pins that are externally being pulled P1.1 also serve the T2 and T2EX functions, respec- low will source current (Ii_ on the data sheet) be- tively. cause of the pullups. Port 2: Port 2 is an 8-bit bidirectional [/O port with Port 3 also serves the functions of various special internal pullups. The Port 2 output buffers can sink/ features of the MCS-51 Family, as listed below: t source 4 LS TTL inputs. Port 2 pins that have 1s | written to them are pulled high by the internal pull- [ et | ternative Function | ups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled P3.0 | RXD (serial input port) low will source current (I, on the data sheet) be- P3.1 | TXD (serial output port) cause of the internal pullups. P3.2 | INTO (external interrupt 0) P3.3 | INT? (external interrupt 1) Port 2 emits the high-order address byte during P3.4 | TO (Timer 0 external input) fetches from external Program Memory and during P35 | T1 {Timer 4 external input) accesses to external Data Memory that use 16-bit P3.6 | WR (external data memory write strobe) addresses (MOVX @DPTA). In this application it P3.7_|_RO (external data memory read strobe) uses strong internal pullups when emitting 1s. Dur- 7-46 r i i i FS

EL CORP (UP/PRPHLS) 2cE PD MP 4426175 0079082 T intel : mese-51 . PRELIMINARY OO . ~ 7249-19-07 ABSOLUTE MAXIMUM RATINGS* “Notice: Stresses above those listed under “Abso- Jute Maximum Ratings" may cause permanent dam- _ other con 1s above those indicat in the opera- D.C. CHARACTERISTICS Ta = 0°C to 70°C; Voc = SV + 10%; Vs = OV 7 [Symbot[ Parameter | Min | Max | Units| Test Conditions Vie Input Low Voltage (Except EA Pin of Vv 8751H & 8751H-8) Vit1__| Input Low Voltage to EA Pin of 07 v 8751H & 8751H-8 Sl a RST) Input High Voltage to XTAL2, RST | 25 [Vcc +0.5| V_|XTALI = Ves Output Low Voltage (Ports 1, 2, 3)* [| 045 | V [lo = 1.6mA . Vout | Output Low Voltage (Port 0, ALE, PSEN)* ee 8751H, 8751H-8 0.60 V lo, = 3.2mA 0.45 V_ [lon = 2.4mA All Others [ | 045 | Vv [to = 9.2mA [Vor | Output High Voltage (Ports 1,2,3,ALE,PSEN) [24 | | V Iloy=—80nA | Vout | Output High Voltage (Port 0 in 24 V_ [lon = —400 pA ‘ External Bus Mode) Me Logical 0 Input Current (Ports 1, 2, 3, RST) 8032AH, 8052AH 800 | pA | Vin = 0.45V All Others =500 A_| Vin = 0.45V fu Logical 0 Input Current to EA Pin of Vin = 0.48V 8751H & 8751H-8 Only . [ing | Logical 0 Input Current (XTAL2) [| =3.2 [ma |Vin=o4sv | Input Leakage Current (Port 0) 8751H & 8751H-8 +100 | pA | 0.45 < Vin < Veo AllOthers £10 A_| 0.45 < Vin < Vox Logical 1 Input Current to EA Pin of BA | Vin = 2.4V 8751H & 8751H-8 [tas __| Input Current to RST to Activate Reset [ {| 500 | pA |Vin< (Voc —1.5V) Ioc Power Supply Current: 8031/8051 160 mA 8031AH/8051AH 125 mA | All Outputs 8032AH/8052AH 175 | mA | Disconnected; : 8751H/8751H-8 250__| mA | EA = Vo [Gio__[PinGapactance Tt | Test frog = 1 MHz “NOTE: Capacitive loading on Ports 0 and 2 may cause spurious nolse pulses to be superimposed on the Vo,s of ALE and Ports 1 and 3, The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt ‘Trigger STROBE input. . 7-48 bs

— a ee INTEL CORP (UP/PRPHLS) 20E D MM 4826175 0079083 1 me intel McS®-51 PRELIMINARY T-49-19-07 A.C. CHARACTERISTICS Ta = 0°C to +70°C; Voc = 5V + 10%; Vgg = OV; Load Capacitance for Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF | Parametar | 12 MHz Oscillator Varlable Oscillator uns Parameter | syne | [win [Max [Min [Max | T/TCLCL | Oscillator Frequen: ee SO TLHLL | ALE Pulse Width [ser ff arouot—40 | ns | TAVLL | Address ValidtoALELow | 43 | ‘(| toici-4ao | sds AddressHoldatterALELow | 48. [| Touc.-35 [| “ns _| TLUV | ALE Lowto Valid Instr In 8751H 183 ATCLCL— 150 ns All Others 233 4TCLCL-100 | _ns : ALELowtoPSENLow | 68 | | Touct-25 | ns TPLPH | PSEN Pulse Width 8761H 190 3TCLCL—60 ns All Others 215 STCLCL—35 ns TPLIV PSEN Low to Valid Instr In 8751H STCLCL~—150 ns All Others STCLCL—125 |_ns. InputinstrHoldafterPSEN | 0 | | Tn . TPXAV __| PSEN to Address Valid [7 | | toc-s | | ns | TAVIV | Address to Valid Instr In 8751H 267 STOLCL— 150 All Others, 302 STCLOL—115 FSENLowtoAddressFloat [| 20 | | 20s | TRLRH _ | RD Pulse Width [400 [ [ercuci-too [ns | WA Pulse Width [400 [ fercuci-too [ns TALDV |ADlowtoValidDatain || 262 | | srcuci—165| ns’ | TRHDX__| Data Hold after RD [oo fos | TRHOZ_| Data Float after AD [er arovcr=70 | ns _| TULOV |-AlELowtoValidDatain | | si7_| | arcuci—160| ns | ALELowtoRDorWAtow | 200 | 300 | srcici—so | stouc.+so | ns _| AddresstoRDorWAtow | 203 | | arouci—190] ns TQVWX | Data Valid to WR Transition 8751H TCLCL-70

7 All Others TCLCL—60

i TWHOX_| Data Hold after WAL [ss [ touci-so | ns | TRLAZ | ADlowtoAddessFloat [| 20 | | aos | TWHLH | RD or WA High to ALE High a751H ToLCL—s0 | TCLCL+60 . All Others TCLCL—40 TCLCL +40 NOTE: “This table does not include the 8751-8 A.C, characteristics (see next page). 7-49 i i K i FA

INTEL CORP (UP/PRPHLS) 20€ DP MH 4826175 0079084 3 mm intel mcse-51 PRELIMINARY T-49-19-07 This Table Is only for the 8751H-8 : A.C, CHARACTERISTICS Ta = 0°C to +70°G; Voc = 5V + 10%; Vsg = OV; Load Capacitance for Port 0, ALE, and PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF [tin fax [aroucr | OscilatorFrequeney || | as ao [we | [mute [AtePusowian | ato [| arcuc—ao [| [Tavit | Address VatdtoaLetow | as [| rouc-ao [| [TuLAx | AddressHoidatterae tow | eo | | rouc-ss | ns | [muti | AtELowtovaidinarin | | a0 [| arcucu—ts0| ns | [mur [ALELowtoPSENLow | too [| rouc-as | | ns [reuPH | PsENPusewatn [ats [| srcuct-eo | rs [tuv | PSENLowtovatdinetrin | |" 225 | | roucu-s60| ns | [Texx [inputinstrHoidanterPaeN [9 | [oT ns | | texiz —[inputinstrFlostaterPSEN | | tos [| rouou-20 | ns | [texav | PSENtoAddressvaid | a7 | | rota [| ns [aviv [AddresstoVatdinain | | ave || stouci-160| ns | - [TPLAZ | PSENLowtoAddressFioat | | 20 | | aos [TRLAH [AOPusewin | eso | erouci-too| ns [TwuwH | WrPusewian | eso ercuci-soo | | | trupv | ROLowtovaiadatain [| eo | | stcucu—te5 | ns | [TRHOK [DatarowanerAD | oT ToT | [TRHOZ | DataFioataterAD || veo | | arcucu—zo | os [mov [ALELowtovaiapatain [| eso [| stoucu-s50{ ns [tavov [Address toVatdbatain | | eo | | orcucu—tes | ns | [Tui [ALELowtoRDorwWAtow | 25 | 426 | srcuci—so | arcuc+so | ne | [Tavwi | AdéresstoRDorWALow | avo | | arouci—iao| os [Tavwx | DatavaidtoWATranstion | 65 | | rouci-7o | | ns | [Tavwii | DatavaiatowRHigh | 725 [| roucu-sso | [rwHiox [DatatoldanerwA | 7s || rouc-so | ns [TRLAZ | ADLowtoAddressrioat | | 20 [| aos [mw [RO orWAignto ALEHign | 76 [175 | ToLc.-so | rorci+60 | ns_| 7-50 t t i

INTEL CORP (UP/PRPHLS) 2oe D M 4826175 0079085 5 a intel wose-st "PRELIMINARY EXTERNAL PROGRAM MEMORY READ CYCLE ~ 4492-19-07 ru . ; . ALE . . . wh fon ; Tuy - - a Texav : rexiz mie : Tay 2700486 7-51 f i

INTEL CORP (UP/PRPHLS) 20 D MM 4426175 0079086 7 a intel Mcse-s1 PRELIMINARY EXTERNAL DATA MEMORY READ CYCLE . T-49-19-07 TULL \\ + THHLH ae \\ : bi . ° |) - TRHOZ . mm IF TRHOX Tan. . avo : . 270048-7, EXTERNAL DATA MEMORY WRITE CYCLE TRHLE TWHLH. . ne \\ . rn Tuwe wwe ravwn - wax aut raw . eel awed | TAVWL 270048-8 7-62 i ra

INTEL CORP (UP/PRPHLS) 2gE D @™ 4826175 0079087 7 a intel wese-s1 PRELIMINARY SERIAL PORT TIMING—SHIFT REGISTER MODE - 7 : Test Conditions: Ta = 0°C to 70°C; VCC = 5V +10%; VSS = OV; Load Capacitance = 80 pF a co | win | mex [min [Mex | [Tax [SerialPort clock OyeleTime [x0 [| arouse [ns | il i Edge TXHOQX | Output Data Hold after Clock 2TCLCL—117 Rising Edge TXHDX | Input Data Hold after Clock Rising Edge . lisa Ma ec Valid SHIFT REGISTER TIMING WAVEFORMS “ULL ema] [ere] feroor | oarerease CD CD CC CD CRD GCN GUND GERI t me vale _— momen Kee XXX Xe XK Xe Kee X KK Kee X Xe) - t uaa “ 270048-9 7-63 t i

INTEL CORP (UP/PRPHLS) 20— BD mm 4aebur7s oo790a8 Oo ml inte! wese-st PRELIMINARY . T-49-19-07 EXTERNAL CLOCK DRIVE _ [_symbot_ [ "Parameter [min [Max [Units 1/TCLCL Oscillator Frequency (except 8751H-8) 8751H-8 - [ree [ign tine ee roux | townie tos | [toto |“ Aisotine |) mr | [roo [ratte to re | EXTERNAL CLOCK DRIVE WAVEFORM TCHOX ToLcn |<—ToHCL 25 25 2 os os . TeLex TeLe. : 270048~10 A.C, TESTING INPUT, OUTPUT WAVEFORM is Er) En) > weston ; aus oe : on. 270048-11 AG, Testing: Inputs are driven at 2.4V for a Logie "1" and 0.45V for a Logic "0". Timing measurements are made at 2.0V for a Logic "1" and 0.8V for a Logic “0. 7-54

Table 3. EPROM Programming Modes used to transfer address and program data to appro- and free of glitches.

0004 OFF 0K Fam bara 3

Figure 6. Program Verification

‘setup and procedure are the same as for normal 20 Po x . thus clearing the Security Bit, restores the device's . Figure 7. Programming the Security Bit tent erasure. If an application subjects the device to Eraure leaves the array in an all 18 state. label be placed over the window.

INTEL CORP (UP/PRPHLS) e0E 9 M@ 44eb175 0079051 0 mm intel . MCS®-51 PRELIMINARY . —_WJH,_-- T-49-19-07 EPROM PROGRAMMING AND VERIFICATION WAVEFORMS PROGRAMMING VERIFICATION P20-P23 a mer tava ALE/PROG a Bavep TENN muon | mnion ‘TEHSH veLav reHaz P27 (ENABLE) 270048-16 For programming conditions see Figure 5, For verification conditions see Figure 6. DATA SHEET REVISION SUMMARY , The following are the kay differences between this and the -003 version of this data sheet: 1. Introduction was expanded to include product descriptions, 2. Package table was added. ~ : 8. Design Considerations added. 4. Test Conditions for IiL1 and Iiy specifications added to the DC Characteristics. §, Data Sheet Revision Summary added. . 7-87 ry