D8031AH

8051AH INTEL | Alldatasheet

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mu @ MCS@ 51 8-BITCONTROL-ORIENTED MICROCONTROLLERSCommercial/Express 8031AH18051AH18051AHP 8032N+18052N-I 8751W8751H-8 8751BW8752BI-I ■ High Performance HMOS Process ■ ■ InternalTimers/Event Counters ■ ■ 2-LevelinterruptPriorityStructure ■ ■ 32 1/0 Lines(Four 8-BitPorts) ■ 64K ExternalProgram Memory Space ■ ■ SecurityFeature ProtectsEPROM Parts ■ AgainstSoftware Piracy ■ Boolean Processor Bit-AddressableRAM Programmable FullDuplex Serial Channel

111 Instructions(64 Single-Cycle)

64K ExternalData Memory Space Extended Temperature Range (–40”C to +85”C) The MCS@ 51 controllersareoptimizedforcontrolapplications.Byte-processingand numericaloperationson smalldatastructuresarefacilitatedby a varietyoffastaddressingmodes foraccessingtheinternalRAM. The instructionsetprovidesa convenientmenu of8-bitarithmeticinstructions,includingmultiplyand divideinstruc- tions.Extensiveon-chipsupportisprovidedforone-bitvariablesas a separatedatatype,allowingdirectbit manipulationand testingincontroland logicsystemsthatrequireBooleanprocessing. The 8751H isan EPROM versionofthe8051AH. Ithas 4 KbytesofelectricallyprogrammableROM whichcan be erasedwithultravioletlight.Hisfullycompatiblewiththe8051AH butincorporatesone additionalfeature:a Program Memory Securitybitthatcan be used to protectthe EPROM againstunauthorizedreadout.The 8751H-8 isidenticaltothe8751H butonlyoperatesup to8 MHz. The 8051AHP isidenticalto the 8051AH withthe exceptionofthe ProtectionFeature.To incorporatethis ProtectionFeature,programverificationhas been disabledand externalmemory accesseshave been limited to4K. The 8052AH isan enhanced versionof the 8051AH. Itisbackwards compatiblewiththe 8051AH and is fabricatedwithHMOS IItechnology.The 8052AH enhancements arelistedinthetablebelow.Alsorefertothis tableforthe ROM, ROMless and-EPROM versionsofeach product. Device IntsrnalMemory Timera/ Event Counters Interrupts Program Data 8031AH none 128 X 8 RAM 2 x 18-Bit 5 8051AH 4K X 8 ROM 128 X 8 RAM 2 x 16-Bit 5 6051AHP 4K X 6 ROM 128 X 8 RAM 2 x 16-Bit 5 8751H 4K X 8 EPROM 128 X 8 RAM 2 x 16-Bit 5 8751H-8 4K X 8 EPROM 128 X 6 RAM 2 x 16-Bit 5 6751BH 4K X 8 EPROM 128 X 8 RAM 2 x 16-Bit 5 8032AH none 256 X 6 RAM 3 x 16-Bit 6 6052AH 8K X 8 ROM 256 X 8 RAM 3 x 16-Bit 6 8752BH 8K X 8 EPROM 256 X 8 RAM 3 x 16-Bit 6 I IntelCorporationassumes no responsibilityfortheuse ofany circuit~otherthancircuitryembodied inan Intelproduct.No othercircuitpatent licensesare implied.Informationcontainedhereinsupersedes previouslypublishedspecificationson theaadavicesfrom Intel. O INTEL CORPORATION, 1994 October 1994 Order Numben 272318-002

MCS” 51 CONTROLLER MO-M 7 P2.&P2 7 I I i fl 13 I I II ,, , JK2UAcc bSTACKPOINTER ~M ‘f2#fi+-oN,TMoD,TJ+1 L“ L-J I <>1 I 1 ml I... ,, ,I PSEN ALE ‘% “TyG g~ E RST-+ ‘* II I 1==4 119 P0nT3 h-+ T LATCH ni- ,,(-1--% =2 w PI O*1 7 5Pm LHvI!RS P] O-P3 7 7W3 I x 272318-1 Figure1.MCSI@ 51 ControllerBlock Diagram PROCESS INFORMATION The 8031AH/8051AH and 8032AH/8052AH devic- es are manufacturedon P414.1,an HMOS IIpro- cess.The 8751H/8751 H-8 devicesare manufac- turedon P421.X,an HMOS-E process.The 8751BH and 8752BH devicesare manufacturedon P422. Additionalprocessand reliabilityinformationisavail- able in Intel’sComponentsQuality and Reliability Handbook, Order No, 210997.

MCS@ 51 CONTROLLER PACKAGES Part Prefix Package Type ‘ja Ojc 8051AH P 40-PinPlasticDIP 45°chV 16“C/W 8031AH D 40-PinCERDIP 4!5”CIW 15“CAIV 8052AH N 44-PinPLCC 46°C/W 18°CfW 8032AH 6752BH* 8751H D 40-PinCERDIP 45”CIW 45“CIW 8751H-8 8051AHP P 40-PinPlasticDIP 45”CIW 16°CfW D 40-PinCERDIP 45°c/w 15“cfw 8751BH P 40-PinPlasticDIP 36”CIW 12°cfw N 44-PinPLCC 47”C1W 16”CfW NOTE: *8752BHis36”/10”forD,and38”/22”forN. Allthermalimpedance data isapproximateforstaticairconditionsat IW of power dissipation.Valueswill change dependingon operatingconditionsand application.See theIntelPac/ragingHandbook (OrderNumber 240800)fora descriptionof Intel’sthermalimpedance testmethodology. ~“52’80320NL’ ~ L { T2 T2EX I’__”llPI.’ 1 40 Vcc P1.1 2 39 P’,’ P1.2 3 38 PO.1 P1.3 4 37 PO.2 P1.4 5 36 PO.3 P1.5 6 35 PO.4 P1,6 7 34 PO.5 P1.7 6 33 P06 ‘1RST 9 RU2 P3.O 10 TXD P3.1 11 INTO P3.2 12 INT1 P3,3 13 TO P3 4 14 11 P3.5 15 ~ P3.6 16 t% P3.7 17 XTAL2 16 XTAL1 19 ‘ss+!-- ADO AD1 A02 A03 AD4 AD5 AD’ 3 PO.7 A07 EIJvpp” Z ALEIPROG” 3%FFI 3 P2.7 A15 2 P2.6A14 3 P2.5 A13 I P2.4 A12 1 P2.3 Al 1 > P2.2 AlO

3 P2 1 A9

PI.6 ::8:; P*,7 .:,.: RST io; (Rxo) P3.O :ji: neaslvsd**.1:; fTXD)P3.1 :ji; (INTo)P3.2 :!;; (INT1)P3.3 :j:; fTo)P3.4 :>!: 8X5X 272318-2 DIP PLCC

• EPROM only “*Donot connect reserved pins. Figure2.MCS@ 51 ControllerConnections

MCS” 51 CONTROLLER PIN DESCRIPTIONS Vcc: Supplyvoltage. Vss: Circuitground. PortO:PortO isan 8-bitopen drainbidirectional1/0 port.As an outputporteach pincan sink8 LS TTL inputs. PortO pinsthathave 1‘swrittentothem float,and in thatstatecan be used as high-impedanceinputs. PortO isalsothemultiplexedlow-orderaddressand data bus duringaccesses to externalProgram and Data Memory. Inthisapplicationituses stronginter- nalpullupswhen emitting1‘sand can sourceand sink8 LS TTL inputs. PortO alsoreceivesthecode bytesduringprogram- ming of the EPROM parts,and outputsthe code bytesduringprogram verificationof the ROM and EPROM parts.Externalpullupsare requiredduring programverification. Port 1:Port1 isan 8-bitbidirectional1/0 portwith internalpullups,The Port1 outputbufferscan sink/ source4 LS TTL inputs.Port1 pinsthathave 1‘s writtento them are pulledhighby the internalpull- UPS, and inthatstatecan be used as inputs.As inputs,Port1 pinsthatareexternallypulledlow will sourcecurrent(IILon thedatasheet)because ofthe internalpullups. Port 1 also receivesthe low-orderaddress bytes duringprogrammingoftheEPROM partsand during programverificationofthe ROM and EPROM parts. Inthe 8032AH, 8052AH and 8752BH, Port1 pins P1.O and P1.1 alsoserve the T2 and T2EX func- tions,respectively. w Port 2 emits the high-orderaddress byte during fetchesfrom externalProgram Memory and during accesses to externalData Memory thatuse 16-bit addresses (MOVX @DPTR). In thisapplicationit uses stronginternalpullupswhen emitting1‘s.Dur- ingaccessestoexternalData Memory thatuse 8-bit addresses(MOVX @Ri),Port2 emitsthecontentsof theP2 SpecialFunctionRegister. Port2 alsoreceivesthehigh-orderaddressbitsdur- ing programming of the EPROM partsand during programverificationoftheROM and EPROM parts. The protectionfeatureofthe 8051AHP causes bits P2.4throughP2.7tobe forcedtoO,effectivelylimit- ingexternalData and Code space to4K each during externalaccesses. Port 3:Port3 isan 8-bitbidirectionall/O portwith internalpullups.The Port3 outputbufferscan sink/ source4 LS TTL inputs.Port3 pinsthathave 1‘s writtento them are pulledhighby the internalpull- UPS,and inthatstatecan be used as inputs.As inputs,Port3 pinsthatareexternallypulledlow will sourcecurrent(IILon thedatasheet)because ofthe pullups. Port3 alsoservesthe functionsof variousspecial featuresofthe MCS 51 Family,as listedbelow: Port Pin P3,0 P3.1 P3.2 P3,3 P3.4 P3.5 P3.6 P3.7 AlternativeFunction RXD (serialinputport) TXD (serialoutputport) INTO (externalinterruptO) INT1 (externalinterrupt1) TO (TimerO externalinput) T1 (Timer1 externalinput) WR (externaldatamemory writestrobe) ~ (externaldatamemory readstrobe) I Port Pin I AlternativeFunction IP1.0 T2 (Timer/Counter2 ExternalInput) P1.1 T2EX (Timer/Counter2 Capture/ReloadTrigger) Port 2:Port2 isan 8-bitbidirectionall/O portwith internalpullups.The Port2 outputbufferscan sink/ source 4 LS TTL inputs.Porl2 pinsthathave 1‘s writtento them are pulledhighby the internalpull- UPS,and inthatstatecan be used as inputs.As inputs,Port2 pinsthatareexternallypulledlow will sourcecurrent(IILon thedatasheet)because ofthe internalpullups. RST: Resetinput.A highon thispinfortwo machine cycleswhilethe oscillatorisrunningresetsthe de- vice, ALE/PROG: Address LatchEnableoutputpulsefor latchingthelowbyteoftheaddressduringaccesses to externalmemory. This pin isalsothe program pulse input(PROG) during programming of the EPROM parts. In normal operationALE isemittedat a constant rateof1/6theoscillatorfrequency,and may be used forexternaltimingorclockingpurposes.Note,how- ever,thatone ALE pulseisskippedduringeach ac- cess toexternalData Memory.

MCS” 51 CONTROLLER w PSEN: Program StoreEnable isthe read strobeto externalProgram Memory. When the deviceisexecutingcode from external Program Memory, PSEN isactivatedtwiceeach ma- chinecycle,exceptthattwo PSEN activationsare skippedduringeach accesstoexternalData Memo- ry ~/Vpp: ExternalAccess enable ~ must be strappedtoVSS inordertoenableany MCS 51 de- viceto fetchcode from externalProgram memory locationsstartingatOOOOH up to FFFFH. ~ must be strappedtoVCC forinternalprogram execution. Note,however,thatiftheSecurityBitintheEPROM devicesisprogrammed, the devicewillnot fetch code fromany locationinexternalProgram Memory. Thispinalsoreceivestheprogrammingsupplyvolt- age (VPP)duringprogrammingoftheEPROM parts. C2 I ElXTAL2 n XTAL1 cl Vss 272318-3 Cl, C2 = 30 PF +10 PF forCrystals ForCeramic Resonatorscontactresonatormanufacturer. Figure3.OscillatorConnections XTAL1: Inputtothe invertingoscillatoramplifier. XTAL2: Outputfrom the invertingoscillatoramplifi- er, OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 aretheinputand output,respec- tively,ofan invertingamplifierwhich can be config- ured foruse as an on-chiposcillator,as shown in Figure3.Eithera quartzcrystalorceramicresonator may be used.More detailedinformationconcerning theuse oftheon-chiposcillatorisavailableinAppli- cationNote AP-155; “Oscillators Iers,”Order No, 230659. I forMicrocontrol- To drivethe devicefrom an externalclocksource, XTAL1 shouldbe grounded,whileXTAL2 isdriven, as shown inFigure4.There areno requirementson thedutycycleoftheexternalclocksignal,sincethe inputto the internalclockingcircuitryisthrougha divide-by-twoflip-flop,but minimum and maximum highand lowtimesspecifiedon thedatasheetmust be observed. EXTERNAL OSCILLATOR SIGNAL XTAL2 XTAL1 Vss 272318-4 Figure4.ExternalDriveConfiguration EXPRESS Version The IntelEXPRESS system offersenhancements to the operationalspecificationsofthe MCS 51 family of microcontrollers.These EXPRESS productsare designedto meet the needs of those applications whose operatingrequirementsexceed commercial standards. The EXPRESS program includesthe commercial standardtemperaturerangewithburn-in,and an ex- tendedtemperaturerangewithorwithoutburn-in. With the commercialstandardtemperaturerange, operationalcharacteristicsare guaranteedover the temperaturerange of O“C to + 70”C.With the ex- tended temperaturerange option,operationalchar- acteristicsareguaranteedovera rangeof –40”C to + 85”C. The optionalburn-inisdynamic,fora minimum time of 160 hours at 125°C withVCC = 5.5V * 0.25V, followingguidelinesinMIL-STD-883,Method 1015. Package typesand EXPRESS versionsareidentified by a one-ortwo-letterprefixtothepartnumber.The prefixesare listedinTable 1. For the extended temperaturerange option,this data sheetspecifiesthe parameterswhich deviate from theircommercialtemperaturerangelimits.

MCS@ 51 CONTROLLER Table 1.EXPRESS PrefixIdentification Prefix Package Type Temperature Range Burn-In P Plastic Commercial No D Cerdip Commercial No N PLCC Commercial No TD Cerdip Extended No TP Plastic Extended No TN PLCC Extended No LD Cerdip Extended Yes LP Plastic Extended Yes NOTE: ContactdistributororlocalsalesofficetomatchEXPRESS prefixwithproperdevice. DESIGN CONSIDERATIONS Ifan 8751BH or8752BH isreplacingan 8751H in a futuredesign,the user shouldcarefullycom- pare bothdatasheetsforDC orAC Characteris- ticdifferences.Note thattheVIH and IIHspecifi- cationsforthe~ pindiffersignificantlybetween thedevices. Exposureto lightwhen the EPROM deviceisin operationmay cause logicerrors.Forthisreason, itissuggestedthatan opaque labelbe placed overthewindow when thedieisexposed toam- bientlight.

• The 8051AHP cannot access externalProgram or Data memory above 4K. Thismeans thatthe followinginstructionsthatuse the Data Pointer onlyread/writedata at addresslocationsbelow OFFFH: MOVXA,@DPTR MOVX(6JDPTR,A When the Data Pointercontainsan address above the4K limit,thoselocationswillnotbe ac- cessed. To access Data Memory above 4K, the MOVX @Ri,A or MOVX A,@Ri instructionsmust be used.

MCS” 51 CONTROLLER ABSOLUTE MAXIMUM RATINGS* AmbientTemperatureUnder Bias –40”C to + 85°C StorageTemperature . –65°C to + 150°C Voltageon EA/Vpp PintoVss 8751BH/6752BH –0.5V tO + 13.OV Voltageon Any OtherPintoVss . –0.5V to + 7V OPERATING CONDITIONS NOTICE:Thisisa productiondatasheet.Itisvalidfor the devicesindicatedin the revisionhistory.The specificationsaresubjecttochangewithoutnotice. *WARNING: Stressingthedevicebeyond the “Absolute Maximum Ratings” may cause permanent damage. These are stressratingsorr~.Operation beyond the “OperatingConditions”is not recommended and ex- tended exposure beyond the “Operating Conditions” may affectdevicereliabili~. Symbol Description Min Msx Units TA Ambient Temperature Under Bias Commercial o +70 “c Express –40 +65 “c Vcc SupplyVoltage 4.5 5.5 v Fosc OscillatorFrequency 3.5 12 MHz DC CHARACTERISTICS (OverOperatingConditions) Allparametervaluesapplytoalldevicesunlessotherwiseindicated Symbol Parameter Min Max Units Test Conditions VIL InputLow Voltage(Except~ Pinof –0.5 0.8 v 6751H and 8751H-8) VIL1 InputLow Voltageto~ Pinof o 0.7 v 6751H and 8751H-8 VIH InputHighVoltage(ExceptXTAL2, RST) 2.0 Vcc + 0.5 v VIH1 InputHighVoltagetoXTAL2, RST 2.5 Vcc + 0.5 v XTAL1 = Vss VIH2 InputHighVoltageto~ pin 4.5 5.5V of6751BH and 8752BH VoL OutputLow Voltage(Ports1,2,3)* 0.45 v loL= 1.6mA VoLl OutputLow Voltage(PortO,ALE, PSEN)* 8751H,8751H-8 0.60 v ioL= 3.2mA 0.45 v !OL= 2.4mA AllOthers 0.45 v IOL= 3.2mA VOH OutputHighVoltage(Ports1,2,3,ALE, PSEN) 2.4 v IOH = –80 PA VOH1 OutputHighVoltage(PortO in 2.4 v IOH = –400 pA ExternalBus Mode) IIL LogicalO InputCurrent(Ports1,2,3,and RST) –500 pA VIN = 0.45V IILI LogicalO InputCurrent(~) 8751H and 8751H-8 –15 mA VIN = 0.45V 8751BH –lo mA VIN = Vss 8752BH –lo mA VIN = Vss 0.5 mA

MCS” 51 CONTROLLER DC CHARACTERISTICS (OverOperatingConditions) Symbol Parameter Min Max Units Teat Conditions 11L2 LogicalO InputCurrent(XTAL2) –3.2 mA VIN = 0.45V ILI InputLeakage Current(PorfO) 8751H and 8751H-8 * 1or) pA 0.45< VIN < VCC AllOthers t 10 pA 0.45< VIN < VCC IIH Logical1 InputCurrent(~) 8751H and 8751H-8 500pA VIN=2.4V 8751BH/8752BH 1 mA 4.5V < VIN < 5.5V IIH1 InputCurrenttoRST toActivateReset 500 pA VIN < (Vcc – 1.5V) Icc Power SupplyCurrent: 8031AH/8051 AH/8051AHP 125 mA AllOutputs 8032AH/8052AH/8751 BH/8752BH 175 mA Disconnected; 8751H/8751 H-8 250 mA m = Vcc Clo PinCapacitance 10 pF Testfreq= 1 MHz NOTES: 1. Capacitive loading on PortsO and 2 may csuse spurious noise pulses to be superimposed on the VOLS of ALE/PROG and Ports 1 and 3. The noise isduetoexternalbuscapacitancedischargingintothePortO andPort2 pinswhen thesepins make 1-to-Otransitionsduringbusoperations.Intheworstcases(capacitiveloading> 100 pF),thenoisepulseon the ALE/PROG pinmay exceed0.8V.Insuchcasesitmaybe desirabletoqualifyALE witha SchmittTrigger,oruseanaddress latchwitha Schmi~TriggerSTROBE input. 2,ALE/PROG referstoa pinon the8751BH.ALE referstoa timingsignalthatisoutputon theALE/PROG pin. 3.Understeadystate(non-transient)conditions,loLmustbe externallylimitedasfollows: Maximum loLperportpin: 10mA Maximum loLper8-bitpori- Porto: 26 mA Ports1,2,and3: 15mA MaximumtotaltoLforalloutputpins: 71 mA IfloLexceedsthetestcondition,VOL may exceedtherelatedspecification.Pinsarenotguaranteedtosinkcurrentgreater thanthelistedtestconditions.

MCS@ 51 CONTROLLER EXPLANATION OF THE AC SYMBOLS Each timingsymbol has 5 characters.The firstchar- acterisalways a ‘T’(standsfortime).The other characters,depending on theirpositions,standfor the name of a signalor the logicalstatusof that signal.The followingisa listofallthecharactersand what theystandfor. A:Address C: Clock D: InputData H: LogiclevelHIGH 1:Instruction(programmemory contents) L:~level LOW, orALE P:PSEN Q: Outputdata R:~ signal T:Time V:Valid W: WR signal X: No longera validlogiclevel Z: Float For example, TAVLL = Time from AddressValidtoALE Low. TLLPL = Time from ALE Low toPSEN Low. AC CHARACTERISTICS (UnderOperatingConditions;Load CapacitanceforPortO,ALE/PROG, and PSEN = 100 pF;Load CapacitanceforAllOtherOutputs= 80 pF) EXTERNAL PROGRAM MEMORY CHARACTERISTICS Symbol Parameter 12 MHz Oscillator VariableOscillator Units Min Max Min Max 1/TCLCL OscillatorFrequency 3.5 12.0 MHz TLHLL ALE PulseWidth 127 2TCLCL–40 ns TAVLL AddressValidtoALE Low 43 TCLCL–40 ns TLLAX AddressHoldafterALE Low 48 TCLCL–35 ns TLLIV ALE Low toValidInstrIn 8751H 183 4TCLCL– 150 ns AllOthers 233 4TCLCL– 100 ns TLLPL ALE LOW toPSEN LOW 58 TCLCL–25 ns TPLPH PSEN PulseWidth 8751H 190 3TCLCL–60 ns AllOthers 215 3TCLCL–35 ns TPLIV PSEN Low toValidInstrIn 8751H 100 3TCLCL– 150 ns AllOthers 125 3TCLCL– 125 ns TPXIX InputInstrHoldafterPSEN o 0 ns TPXIZ InputInstrFloatafterPSEN 63 TCLCL–20 ns TPXAV PSEN toAddressValid 75 TCLCL–8 ns TAVIV AddresstoValidInstrIn 8751H 287 5TCLCL–1 50 ns AllOthers 302 5TCLCL–1 15 ns TPLAZ PSEN Low toAddressFloat 20 20 ns TRLRH ~ PulseWidth 400 6TCLCL– 100 ns TWLWH WR PulseWidth 400 6TCLCL– 100 ns TRLDV ~ Low toValidData In 252 5TCLCL– 165 ns TRHDX Data Holdafter~ o 0 ns TRHDZ Data Floatafter~ 97 2TCLCL–70 ns TLLDV ALE Low toValidData In 517 8TCLCL–1 50 ns

MCS@ 51 CONTROLLER EXTERNAL PROGRAM MEMORY CHARACTERISTICS (Continued) Symbol TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH ‘arame’erI---%#ALE Low toRD orWR Low 200 Addressto~ orWR Low 203 DataValidtoWR Transition 8751H I 13 AllOthers 23 DataValidtoWR High 433 Data HoldafterWR 33 RD Low toAddressFloat RD orWR HightoALE High 8751H 33 AllOthers 43 cillator VariableOscillator Units Max Min Max 300 3TCLCL–50 3TCLCL+ 50 ns 4TCLCL– 130 ns TCLCL–70 ns TCLCL–60 ns 7TCLCL– 150 ns TCLCL–50 ns 20I I 20 Ins I

133 TCLCL–50 TCLCL+ 50 ns

123 TCLCL–40 TCLCL+40 ns

NOTE: “The8751H-8isidenticaltothe8751H butonlyo~eratesutIto8 MHz.When calculatingtheAC Characteristicsforthe 8751 H-8, use the 8751 H formula for variable oscillators.

MCS@ 51 CONTROLLER EXTERNAL PROGRAM MEMORY READ CYCLE w--- TLHLL _ ALE \\ , / \\ TLLPL -~ TPLPH -TAVLL+ + TLLIV PSEN / TLLAX PORT O PORT 2 x AO-A15 x A8 -A15 272318-5 EXTERNAL DATA MEMORY READ CYCLE ALE Y \\ / +TLHLL+ TWHLH PSEN ‘LLOv ~ — TLLWL TRLRH –— m + TAVLL + b i ‘ _TLLAX —TRLDV4 TRHOX+ PORTO AO-A7 FROM RI OR OPL OATA IN . TAVOV b PORT 2 x r P2.O-P2.7 OR A8-A15 FROM DPH x A8-A15 FROM PCH 272318-6 EXTERNAL DATA MEMORY WRITE CYCLE ALE \\ , \\ / TLHLL— TWHLH m / ‘TLLwL~TwLwH * WT 1TAVLL k 1 ‘ +TLLAX 7t=-TQVWX : r TWHQX TQVWH II I 1 PORTO AO-A7 FROM RIOR OPL M OATA OUT xxAO-A7 FROM FCL I PORT2 x P2.O-P2.7 OR A8-A15 FROM OPH x A8-A15 FROM PCH 272318-7

M=” 51 CONTROLLER SERIAL PORT TIMING—SHIFT TestConditions:Over ODeratinaConditions:Load Capacitance= 80 rJF Symbol TXLXL TQVXH TXHQX TXHDX TXHDV Parameter 12 MHz Oscillator VariableOscillator Unite Min Max Min Max SerialPortClockCycleTime 1.0 12TCLCL ps OutputData SetuptoClockRising 700 1OTCLCL– 133 ns Edge OutputData HoldafterClock 50 2TCLCL–1 17 ns RisingEdge InputData HoldafterClockRising o 0 ns Edge ClockRisingEdge toInputData 700 10TCLCL– 133 ns Valid ;HI17REGISTER MODE TIMING WAVEFORMS INSTRUCTION I O I 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 I ALE n n n n n n n n n n n n n n n n n n I I-TXLXL-7 CLOCK WI-TXHQX I OUTPUT OATA o 1)( 1 2 x 3 x 4 x 5 x 6 x 7 / , +SET TI INPUT DATA ~ 4 SET RI 272318-8

MCS@ 51 CONTROLLER EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 11/TCLCL OscillatorFrequency(except8751H-8) 3.5 12 MHz 8751H-8 3.5 8 MHz TCHCX HighTime 20 ns TCLCX Low Time 20 ns I TCLCH I RiseTime I I 20 I ns I TCHCL FallTime 20 ns EXTERNAL CLOCK DRIVE WAVEFORM — TCHCX — TCLCH _ — — ~ TCliCL 2.5 t a t 2.5 A -— TCLCX — + TCLCL w 272318-9 AC TESTING INPUT, OUTPUT WAVEFORM 2.4 2.0 2.0 TEST POINTS 0.s 0.8 0.45 272318-10 AC Testing:Inputsare drivenat2.4V fora Logic“1” and 0.45V fora Logic “O”.Timing measurements ara made at 2.OV fora Logic“1” and 0.8V fora Logic“O”.

MCS@ 51 CONTROLLER EPROM CHARACTERISTICS Table3.EPROM ProgrammingModea Mode RST PSEN ALE m P2.7 P2.6 P2.5 P2.4 Program 1 0 o* VPP 1 0 x x Verify 1 0 1 1 0 0 x x SecuritySet 1 0 o* VPP 1 1 x x NOTE: “1”= logichighforthatpin “O”= logiclowforthatpin “X” = “don’tcare” PROGRAMMING THE 8751H To be programmed, thepartmust be runningwitha 4 to 6 MHz oscillator.(The reason the oscillator needs tobe runningisthattheinternalbus isbeing used totransferaddressand programdatatoappro- priateinternalregisters.)The addressofan EPROM locationto be programmed isappliedto Port1 and pinsP2.O-P2.3ofPort2,whilethecode bytetobe programmed intothatlocationisappliedto PortO. The otherPorl2 pins,and RST, PSEN, and ~/Vpp shouldbe heldatthe “Program” levelsindicatedin Table3.ALE/PROG ispulsed lowfor50 ms topro- gram the code byteintothe addressedEPROM lo- cation.The setupisshown inFigure5. Normally~~is held at a logichighflntiljust beforeALE/PROG istobe pulsed.Then EA/Vpp is raisedto +21 V, ALE/PROG ispulsed,and then ~/Vpp isreturnedto a logichigh.Waveforms and detailedtimingspecificationsareshown inlatersec- tionsofthisdatasheet. +5V a Vcc AOOR A&b? p? —FFH w PGM DATA P2.0– U–All P2.3 8751H ‘=’’-”TCAREJ=E‘LEl=$=- UVlli P2.7 XTAU 5 F&vPP 4-SUN* n XTAL1 RST VIH1 Vss PSEN . . 27231a-1 I Figure5.ProgrammingConfiguration “VPP” = +21V *0.5V *ALEispulsedlowfor50 ms Note thatthe~/VPP pinmust notbe allowedtogo above themaximum specifiedVPP levelof21.5Vfor any amount oftime.Even a narrowglitchabove that voltageIeveican cause permanent damage to the device.The VPP source should be wellregulated and freeofglitches. Program Verification IftheSecurityBithas notbeen programmed,theon- chipProgram Memory can be read outforverifica- tionpurposes,ifdesired,eitherduringor afterthe programmingoperation.The addressoftheProgram Memory locationtobe readisappiiedtoPort1 and pinsP2.O-P2.3.The otherpinsshouldbe heldatthe “Verify”IeveisindicatedinTabie3.The contentsof theaddressedlocationwillcome outon PortO.Ex- ternalpullupsare requiredon PortO forthisopera- tion. The setup,which isshown inFigure6,isthe same as forprogrammingtheEPROM exceptthatpinP2.7 isheldata logiclow,or may be used as an active- Iow readstrobe +5V Vcc mu w + DATA —FFH (USE 10K PULLUPS] W51H x~ . ,,W,, CARE,. - ~~b X-9 P2.5 ALE VILd P2.S VIH ENAS4E . P2 7 G XTAU 4-6MHZ m RST h VIH1 XTAL1 Vss PSEN 27231S-12 Figure6.ProgramVerification

MCS@ 51 CONTROLLER EPROM Security The securityfeatureconsistsofa ‘locking”bitwhich when programmed denieselectricalaccess by any externalmeans to the on-chipProgram Memory. The bitisprogrammed as shown inFigure7.The setup and procedureare the same as fornormal EPROM programming,exceptthatP2.6isheldata logichigh,PorlO,Port1 and pinsP2.O–P2.3may be inany state.The otherpinsshouldbe heldat the “Security”levelsindicatedinTable3. Once theSecurityBithas been programmed, itcan be clearedonlyby fullerasureoftheProgram Mem- ory.While itisprogrammed, the internalProgram Memory can notbe readout,thedevicecan notbe furtherprogrammed, and itcan notexecuteoutof externalprogram memory. Erasingthe EPROM, thusclearingthe SecurityBit,restoresthe device’s fullfunctionality.Itcan thenbe reprogrammed. +5V X = OGN’T CARE” o f Vcc {: ‘-PI m x P2.0- X P2.3 8751H P2.4 ALE ALE/PROO P2.5 50 ma PULSE TO GND P2.6 VIM P2,7 fi + EAYPP XTAU m RST — WH1 XTAL1 Vss PSEN 7* * 272318-13 ErasureCharacteristics Erasureof the EPROM beginsto occur when the deviceisexposed to lightwithwavelengthsshorter thanapproximately4,000Angstroms.Sincesunlight and fluorescentlightinghave wavelengthsin this range,exposureto these lightsourcesover an ex- tendedtime(about1 week insunlight,or3 yearsin room-levelfluorescentlighting)couldcause inadver- tenterasure.Ifan applicationsubjectsthedeviceto thistypeofexposure,itissuggestedthatan opaque labelbe placedoverthewindow. Figure7.ProgrammingtheSecurityBit The recommended erasureprocedureisexposure toultravioletlight(at2537 Angstroms)toan integrat- ed dose of at least15 W-sec/cm2. Exposingthe EPROM to an ultravioletlamp of 12,000 pW/cm2 ratingfor20 to 30 minutes,ata distanceof about 1 inch,shouldbe sufficient. Erasureleavesthearrayinan all1‘sstate. EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS TA = 21°C to27”C;VCC = 5V + 10%; VSS = OV Symbol Parameter Min Max Unita VPP ProgrammingSupplyVoltage 20.5 21.5 v IPP ProgrammingSupplyCurrent 30 mA 1/TCLCL OscillatorFrequency 4 6 MHz TAVGL AddressSetuptoPROG Low 46TCLCL TGHAX AddressHoldafterPROG 48TCLCL TDVGL DataSetuptoPROG Low 48TCLCL TGHDX Data Holdafter~ 48TCLCL TEHSH P2.7(ENABLE) HightoVPP 48TCLCL TSHGL VPP SetuptoPROG Low 10 ps TGHSL VPP HoldafterPROG 10 ps TGLGH PROG Width 45 55 ms TAVQV AddresstoDataValid 48TCLCL TELQV ENABLE Low toDataValid 48TCLCL TEHQZ Data FloatafterENABLE o 48TCLCL

MCS” 51 CONTROLLER PROGRAMMING VERIFICATION P1.O-PI.7 P3,0-P3,3 ( ADDRESS $ J PORT O { , DATA IN TOVGL — — —TGHOX TAVGL — TGHAX kLE/PROG \\ ~ ‘ TSHGL — — — TGHSL TGLGH 21V * .5V r \\m HIGHFi.vPP TTL HIGH TTL HIGH TSHSN — TELOV P3.7 (ENABLE) 1 ‘ 272318-14 For programming conditionssee Figure5. For verificationconditionssee Figure6.

inlA MCS” 51 CONTROLLER Programming the 8751BH/8752BH To be programmed, the 875XBH must be running witha 4 to6 MHz oscillator.(Thereasontheoscilla- torneeds to be runningisthatthe internalbus is beingused totransferaddressand programdatato appropriateinternalregisters.)The address of an EPROM locationto be programmed isappliedto Porl1 and pinsP2.O-P2.4ofPort2,whilethecode byteto be programmed intothatlocationisapplied to PortO. The otherPort2 and 3 pins,and RST, PSEN, and ~/Vpp shouldbe heldatthe“Program” levelsindicatedinTable1.ALE/PROG ispulsedlow to croaram the code bvte into the addressed Normally~&is held at a logichigh untiljust beforeALE/PROG istobe pulsed.Then ~/Vpp is raisedto Vpp, ALE/PROG ispulsedlow,and then ~/Vpp isreturnedtoa validhighvoltage.The volt- age on the~/Vpp pinmust be atthevalidEA/Vpp highlevelbeforea verifyisattempted.Waveforms and detailedtimingspecificationsareshown inlater sectionsofthisdatasheet. Note thatthe~/Vpp pinmust notbe allowedtogo above the maximum specifiedVpp levelfor any amount oftime.Even a narrowglitchabove thatvolt- age levelcan cause permanent damage tothe de- vice.The Vpp sourceshouldbe wellregulatedand EPROfl location.The setu’pisshown inFigure8. freeofglitches. +5V Vcc Po 1~ RST E/vpp ~ +12.75V ALE/PROG ~25 100 p, PULSES TO GND 1~ P3.6 875X,, ~ ~“ 1~ P3.7 P2.7 ~1 lJ- XTAL 2 P2.6 ~o 4-6 MHz ❑ T= ; XTAL 1 P2.O -P2,4 ‘ks 272318-15 —. —Figure8.Programmingthe EPROM Table4.EPROM ProgrammingModea for875XBH MODE RST ALE/PSEN — ml PROG Vpp P2.7 P2.6 P3.6 P3.7 ProgramCode Data 1 0 o* Vpp 1 0 1 1 VerifyCode Data 1 0 1 1 0 0 1 1 Program EncryptionTabie 1 0 o* Vpp 1 0 0 1 Use AddressesO-1FH Program Lock ~= 1 1 0 o* Vpp 1 1 1 1 Bits(LBx) x=2 1 0 o* Vpp 1 1 0 0 Read Signature 1 0 1 1 0 0 0 0 NOTES: “1”= Validhighforthatpin “O”= Validlowforthatpin *ALE/PROG ispulsedlowfor100US forprogramming.(Quick-PulseProgramming)

MCS@ 51 CONTROLLER QUICK-PULSE PROGRAMMING ALGORITHM The 875XBH can be programmed usingthe Quick- Pulse Programming Algorithmformicrocontrollers. The featuresofthenew programmingmethod area lowerVpp (12.75voltsas compared to21 volts)and a shorterprogrammingpulse.Forexample,itispos- sibleto program the entire8 Kbytes of 875XBH EPROM memory inlessthan 25 seconds withthis algorithm! To program the partusingthe new~rithm, Vpp must be 12,75 f 0.25 Volts.ALE/PROG ispulsed low for 100 pseconds, 25 times as shown in Figure9,Then, the bytejustprogrammed may be verified.Afterprogramming,the entirearrayshould be verified.The Program Lock featuresare pro- grammed usingthesame method,butwiththesetup as shown inTable4.The onlydifferenceinprogram- ming Lock featuresisthatthe Lock featurescannot be directlyverified.Instead,verificationofprogram- ming isby observingthattheirfeaturesareenabled. PROGRAM VERIFICATION IftheLock Bitshave notbeen programmed,theon- chipProgram Memory can be read outforverifica- tionpurposes,ifdesired,eitherduringor afterthe programmingoperation.The addressoftheProgram Memory locationtobe readisappliedtoPort1 and pinsP2.O - P2.4.The otherpinsshouldbe heldat the “Verify”levelsindicatedinTable 1.The con- tentsoftheaddressedlocationwillcome outon Port O. Externalpullupsare requiredon PortO forthis operation.(Ifthe EncryptionArrayinthe EPROM has been programmed, the data presentat PortO willbe Code Data XNOR EncryptionData.The user must know theEncryptionArraycontentstomanual- ly“unencrypt”thedataduringverify.) The setup,which isshown inFigure10,isthesame as forprogrammingtheEPROM exceptthatpinP2.7 isheldata logiclow,or may be used as an active low readstrob~. ,~25p”LsEs ~ ALEM I “

10 P,MIN 100JM

*lops ALE/PROG : 0 1 272318-16 Figure9.PROG Waveforma +~v ‘rh 10kJl AO-A7 P! RST P3.6 1 P3.7 LXTAL 2 4-6 MHz ❑ XTAL 1 Vss Vcc -F’X8 Po PGM DATA rmpp ALE/PRW 1 B75xBH = 0 P2.7 0 (i-mm P2.6 0 P2.O -P2.4 F A8-A12 272318-17 Figure10.VerifyingtheEPROM

The two-levelProgram Lock system consistsof 2 Lock bitsand a 32-byteEncryptionArraywhich are used to protectthe program memory againstsoft- ware piracy. ENCRYPTION ARRAY WithintheEPROM arrayare32 bytesofEncryption Arraythatare initiallyunprogrammed (all1s).Every timethata byteisaddressedduringa verify,5 ad- dresslinesareused toselecta byteofthe Encryp- tion Array.This byte is then exclusive-NORed (XNOR) withthe code byte,creatingan Encrypted Verifybyte.The algorithm,withthe arrayinthe un- programmed state(all1s),willreturnthecode inits original,unmodifiedform. Itisrecommended thatwhenever theEncryptionAr- ray isused,at leastone of the Lock Bitsbe pro- grammed as well. LOCK BITS AlsoincludedintheEPROM Program Lock scheme aretwo Lock Bitswhichfunctionas shown inTable Erasingthe EPROM alsoerasesthe EncryptionAr- rayand the Lock Bits,returningthe partto fullun- lockedfunctionality. MCS@ 51 CONTROLLER Table5.LockBitsand theirFeatures LogicEnabled LB1 u Minimum Program Lockfeatures enabled.(Code VerifyWIIIstillbe P u MOVC instructionsexecutedfrom externalprogrammemory are disabledfromfetchingcode bytes frominternalmemory, EA is sampledand latchedon reset, and furtherprogrammingofthe EPROM isdisabled P I P Same as above,butVerifyisalso disabled U I P IReservedforFutureDefinition I = Programmed = Unprogrammed READING THE SIGNATURE BYTES The signaturebytesarereadby thesame procedure as a normalverificationoflocations030H and 031H, exceptthatP3.6 and P3.7 need to be pulledto a logiclow.The valuesreturnedare: (030H) = 89H indicatesmanufacturedby Intel (031H) = 51H indicates8751BH 52H indicates8752BH To ensureproperfunctionalityofthechip,the inter- nallylatchedvalueofthe~ pinmust agreewithits externalstate.

MCS” 51 CONTROLLER ERASURE CHARACTERISTICS Erasureof the EPROM beginsto occur when the 8752BH isexposed tolightwithwavelengthsshorter thanapproximately4,000Angstroms.Sincesunlight and fluorescentlightinghave wavelengthsin this range,exposureto these lightsourcesover an ex- tendedtime(about1 week insunlight,or3 yearsin room-levelfluorescentlighting)couldcause inadver- tenterasure.Ifan applicationsubjectsthedeviceto thistypeofexposure,itissuggestedthatan opaque labelbe placedoverthewindow. The recommended erasureprocedureisexposure toultravioletlight(at2537 Angstroms)toan integrat- ed dose of at lease 15 W-see/cm. Exposingthe EPROM toan ultravioletlamp of12,000pW/cm rat- ingfor30 minutes,at a distanceof about 1 inch, shouldbe sufficient. Erasureleavesthearrayinan allIs state. EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS (T,4= 21°C to27”C,Vcc = 5.OV + 10%, Vss = OV) Symbol Parameter Min Max Units Vpp Programming Supply Voltage 12.5 13.0 v Ipp Programming Supply Current 50 mA 1/TCLCL OscillatorFrequency 4 8 MHz TAVGL AddressSetuptoPROG Low 48TCLCL TGHAX AddressHoldAfterPROG 48TCLCL TDVGL DataSetuptoPROG Low 48TCLCL TGHDX Data HoldAfterPROG 48TCLCL TEHSH P2.7(ENABLE) HightoVpp 48TCLCL TSHGL Vpp SetuptoPROG Low 10 ps TGHSL Vpp HoldAfterPROG 10 ps TGLGH PROG Width 90 110 ps TAVQV AddresstoDataValid 48TCLCL TELQV ENABLE Low toDataValid 48TCLCL TEHQZ Data FloatAfterENABLE o 48TCLCL TGHGL PROG HightoPROG Low 10 ps EPROM PROGRAMMING AND VERIFICATION WAVEFORMS PROGRAMMING VERIFICATION ADDRESS ADDRFSS TAvQV DATA IN DATA OUT TDVGL TGHDX TAVGL Pu& TGHAX TSHGL d TGHsL TGLGH TGHGL ~wpp t [A/HIGH TELQV L TEHQZ P2.7 272318-18

MCS@ 51 CONTROLLER DATA SHEET REVISION HISTORY Datasheetsarechanged as new deviceinformationbecomes available.VerifywithyourlocalIntelsalesoffice thatyou have thelatestversionbeforefinalizinga designororderingdevices. The followingdifferencesexistbetween thisdatasheet(272318-002)and thepreviousversion(272318-001): 1.Removed QP and QD (commercialwithextendedburn-in)from Table1.EXPRESS PrefixIdentification. Thisdatasheet(272318-001)replacesthefollowingdatasheets: MCS@ 51 Controllers(270048-007) 8051AHP (270279-004) 8751BH (270248-005) 8751BH EXPRESS (270708-001) 8752BH (270429-004) 8752BH EXPRESS (270650-002)