D64569-007 INTEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 76
Technical content
Intel® Server Board S5000VCL Technical Product Specification Intel order number: D64569-007 Revision 2.3 January 2008 Enterprise Platforms and Services Division - Marketing
Intel® Server Board S5000VCL TPS Table of Contents Revision 2.3 Intel order number: D64569-007 iii
Revision History
Sept. 2006 1.0 Initial release. Nov. 2006 2.0 Added technical updates and SAS board information. Jan. 2007 2.1 Removed processor that is not supported by board; added Post-Code Diagnostic LED information. Sept. 2007 2.2 Updated product codes and processor information. Jan. 2008 2.3 Updated processor information. Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Server Board S5000VCL may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel Corporation server baseboards support peripheral components and contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel’s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation can not be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits. Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation. *Other brands and names may be claimed as the property of others. Copyright © Intel Corporation 2008.
Table of Contents Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3 iv Table of Contents
Intel® Server Board S5000VCL TPS Table of Contents Revision 2.3 Intel order number: D64569-007 v
Table of Contents Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3 vi
Table 30. Dual-Core Intel® Xeon® processor 5100 series and Quad-Core Intel® Xeon®
List of Tables Intel ® Server Board S5000VCL/S5000VCLSASBB TPS Intel order number: D64569-007 Revision 2.3 x < This page intentionally left blank. >
Intel® Server Board S5000VCL TPS Overview Revision 2.3 Intel order number: D64569-007 1. Introduction This Technical Product Specification (TPS) provides board-specific information about the features, functionality, and high-level architecture of the Intel® Server Board S5000VCL. See the Intel® 5000 Series Chipsets Server Board Family Datasheet more information about board sub- systems, including chipset, BIOS, system management, and system management software. There are four product codes of the Intel Server Board S5000VCL:
- SS5000VCL
- S5000VCLSASBB
- BBS5000VCLR
- BBS5000VCLSASR All references to the Intel® Server Board S5000VCL refer to all product codes listed above, unless noted otherwise.
1.1 Server Board Use Disclaimer
Intel Corporation server boards support add-in peripherals and contain high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits.
Product Overview Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3 2. Product Overview The Intel® Server Board S5000VCL is a monolithic printed circuit boards that support the high- density 1U server market.
2.1 Feature Set
Processors 771-pin LGA sockets supp orting one or two Dual-Core Intel® Xeon® processors 5100 series, low-voltage Quad-Core® Xeon® processors 5300 series, and low-voltage Quad- Core® Xeon® processors 5400 series with system bus speeds of 1066 MHz or 1333 MHz. For a complete list of supported processors, see the following link: http://support.intel.com/support/motherboards/server/S5000VCL Memory Six keyed DIMM slots support fully buffered DIMM technology (FBDIMM) memory. 240- pin DDR2-677 FBDIMMs must be used. Chipset Intel ® 5000V Chipset family, which includes the following components: Intel ® 5000V Memory Controller Hub Intel ® 6321ESB I/O Controller Hub On-board Connectors / Headers External connections: Stacked PS/2* ports for keyboard and mouse Two RJ45 NIC connectors for 10/100/1000 Mb connections Two USB 2.0 ports Video connector Com 1 or Serial A (DB9) Internal connectors/headers: One USB port header, capable of providing two USB 2.0 ports One DH10 Serial B header Six SATA ports or four SAS ports via the Intel ® 6321ESB I/O Controller Hub. These ports support 3Gb/s and integrated SW RAID 0 or 1 One 40-pin (power + I/O) ATA/100 c onnector for optical drive support SSI-compliant 24-pin control panel header SSI-compliant 24-pin main power connec tor support the ATX-12 V standard on the first 20 pins 8-pin +12 V processor power connector Add-in PCI, PCI-X*, PCI Express* Cards One PCI super-slot that will support one 1U riser card with one PCI-X* and one PCI Express* connectors On-board Video ATI* ES1000 video controller with 16 MB DDR SDRAM On-board Hard Drive Controller Six 3 Gb/s SATA ports, or four SAS ports Intel® Embedded Server RAID Technology II with RAID levels 0, 1, 10 LAN Two 10/100/1000 NICs supporting Intel® I/O Acceleration Technology System Fans Two CPU 4-pin fan headers supporti ng two system blowers and one 3-pin fan header supporting a system fan System Management Support for Intel® System Management Software
2.2 Server Board Layout
Figure 1. Components and Connector Location Diagram
2.2.1 Intel ® Light-Guided Diagnostics LED Locations
Figure 2. Intel® Light-Guided Diagnostics LED Locations
2.2.2 External I/O Connector Locations
Figure 3. ATX I/O Layout
Functional Architecture Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3 3. Functional Architecture The architecture and design of the Intel® Server Board S5000VCL is based on the Intel® 5000V Chipset. The chipset is for systems based on the Dual-Core Intel® Xeon® processor 5100 series, low-voltage Quad-Core Intel® Xeon® processor 5300 series and low-voltage Quad-Core Intel® Xeon® processor 5400 series with system bus speeds of 1067 MHz and 1333 MHz. The chipset has two main components: the Intel® 5000V Memory Controller Hub (MCH) for the host bridge and the Intel® 6321ESB I/O Controller Hub for the I/O subsystem. This chapter provides a high-level description of the functionality associated with each chipset component and the architectural blocks that make up this server board. For in depth information on each of the chipset components and each of the functional architecture blocks, see the Intel 5000 Series Chipsets Server Board Family Datasheet.
1333 MT/s
Figure 4. Functional Block Diagram
Functional Architecture Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3
3.1 Intel ® 5000V Memory Controller Hub (MCH)
The memory controller hub (MCH) is a single 1432 pin FCBGA package that includes these core platform functions:
- System bus interface for the processor sub-system
- Memory controller
- PCI Express* ports including the enterprise south bridge interface (ESI)
- FBD thermal management
- SMBUS interface
3.1.1 System Bus Interface
The MCH is configured for symmetric multi-processing across two independent front side bus interfaces that connect to the processors. Each front side bus on the MCH uses a 64-bit wide 1066- or 1333-MHz data bus. The 1333-MHz data bus can transfer data at up to 10.66 GB/s. The MCH supports a 36-bit wide address bus, capable of addressing up to 64 GB of memory. The MCH is the priority agent for both front side bus interfaces, and is optimized for one processor on each bus.
3.1.2 Processor Support
The server board supports one or two Dual-Core Intel® Xeon® processors 5100 series or low voltage Quad-Core Intel® Xeon® processor 5300 series, or low voltage Quad-Core Intel® Xeon® processor 5400 series with system bus speeds of 1066 MHz, and 1333 MHz, and core frequencies starting at 1.6 GHz. Previous generations of the Intel ® Xeon® processor are not supported. For a complete list of supported processors, see the following link: http://support.intel.com/support/motherboards/server/S5000VCL Note: Only Dual-Core Intel® Xeon® processors 5100 series or low-voltage Quad-Core Intel® Xeon® processor 5300 and 5400 series, that support system bus speeds of 1066 MHz, and 1333 MHz are supported.
3.1.2.1 Processor Population Rules
bus/core speed. When only one processor is installed, it must be in the socket labeled CPU1. The other socket must be empty. requirements are not supported.
3.1.2.2 Common Enabling Kit (CEK) Design Support
stacking order of the chassis, CEK spring, server board, TIM, and heat sink. The CEK spring is removable, allowing for the use of non-Intel heat sink retention solutions. Figure 5. CEK Processor Mounting
3.1.3 Memory Sub-system
Figure 6. Memory Layout needed to program the MCH memory registers. Table 1. I2C Addresses for Memory Module SMB
3.1.3.1 Supported Memory
Up to six DDR2-667 fully-buffered DIMMs (FBD memory) can be installed. Table 2. Maximum Six-DIMM System Memory Configuration – x4 Single Rank
512 Mb 3 GB
1024 Mb 6 GB
2048 Mb 12 GB
Table 3. Maximum Six-DIMM System Memory Configuration – x8 Dual Rank S5000VCL Tested Memory List for a list of supported memory.
Functional Architecture Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3
3.1.3.2 DIMM Population Rules and Supported DIMM Configurations
DIMM population rules depend on the operating mode of the memory controller. The operating mode is determined by the number of DIMMs installed. DIMMs must be populated in pairs in DIMM slot order: A1 & B1, A2 & B2. DIMMs within a pair must be identical with respect to size, speed, and organization, but DIMM capacities can be different across different DIMM pairs. Note: The server board supports single DIMM mode operation. Intel will only validate and support this configuration with a single 512 MB x8 FBDIMM installed in DIMM slot A1.
3.2 Intel ® 6321ESB I/O Controller Hub
The Intel® 6321ESB I/O Controller Hub is a multi-function device that provides four distinct functions: an IO Controller, a PCI-X* Bridge, a GB Ethernet Controller, and a baseboard management controller (BMC). Each function within the controller hub has its own set of configuration registers. Once configured, each appears to the system as a distinct hardware controller. The controller hub provides the gateway to all PC-compatible I/O devices and features. The server board uses these Intel® 6321ESB I/O Controller Hub features: 1. PCI-X* bus interface 2. Six channel SATA interface w/SATA busy and fault LED control 3. Dual GbE MAC 4. Baseboard management controller (BMC) 5. Single ATA interface, with Ultra DMA 100 capability 6. Universal Serial Bus 2.0 (USB) interface 7. Removable media drives 8. LPC bus interface 9. PC-compatible timer/counter and DMA controllers 10. APIC and 8259 interrupt controller 11. Power management 12. System RTC 13. VT technology 14. General purpose I/O For additional information, see the Intel ® 5000 Series Chipsets Server Board Family Datasheet.
3.2.1 PCI Sub-system
Table 4. PCI Bus Segment Characteristics
3.2.1.1 PXA: 64-bit, 133MHz PCI Subsystem
PXA, supports up to three PCI add-in cards on the full-height riser card.
3.2.1.2 PE2: One x4 PCI Express* Bus Segment
PE2, supports one x8 PCI Express segment to the proprietary I/O module mezzanine connector.
3.2.1.3 PCI Riser Slot
- One low-profile PCI Express* x8 and one mid-height PCI-X* 133
- Or one low-profile PCI Express*x4 and one mid-height PCI Express* x4.
3.2.2 Serial ATA Support
SATA ports can be enabled/disabled and/or configured through the BIOS Setup Utility.
Functional Architecture Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3
3.2.2.1 Intel ® Embedded Server RAID Technology Support
The embedded Intel® Embedded Server RAID Technology solution offers data stripping (RAID Level 0) and data mirroring (RAID Level 1). For higher performance, data stripping alleviates disk bottlenecks by taking advantage of the dual independent DMA engines that each SATA port offers. Data mirroring is for data security. If a disk fails, a mirrored copied of the failed disk is brought on-line. There is no loss of either PCI resources (request/grant pair) or add-in card slots. Intel® Embedded Server RAID Technology functionality requires these items: 15. Intel® 6321ESB I/O Controller Hub 16. Intel® Embedded Server RAID Technology Option ROM 17. Intel® Application Accelerator RAID edition drivers, most recent revision
- At least two SATA hard disk drives Intel® Embedded Server RAID Technology is not available in these configurations: 18. The SATA controller in compatible mode
- Intel® Embedded Server RAID Technology has been disabled
3.2.3 Parallel ATA (PATA) Support
The integrated IDE controller of the 6321ESB ICH6 provides one IDE channel. It redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 100 MB/s. The IDE channel provides optical drive support. The BIOS initializes and supports ATAPI devices such as LS-120/240, CD-ROM, CD-RW and DVD-ROM. The IDE channel is accessed through a high-density 40-pin connector ((J2K5) that provides I/O signals. The ATA channel can be configured and enabled or disabled through the BIOS Setup Utility. 3.2.4 USB 2.0 Support The USB controller functionality integrated into the 6321ESB provides the interface for up to four USB 2.0 ports. Two external connectors are located on the back edge of the server board and one internal 2x5 header supports two optional USB 2.0 ports.
3.3 Video Support
An ATI* ES1000 PCI graphics accelerator with 16 MB of video DDR SDRAM and support circuitry for an embedded SVGA video sub-system is provided. The ATI ES1000 chip contains an SVGA video controller, clock generator, 2D engine, and RAMDAC in a 359-pin BGA. One 4M x 16 x 4 bank DDR SDRAM chip provides 16 MB of video memory. The SVGA sub-system supports modes up to 1024 x 768 resolution in 8 / 16 / 32 bpp modes under 2D. It also supports both CRT and LCD monitors up to a 100 Hz vertical refresh rate. Video is accessed using a standard 15-pin VGA connector found on the back edge of the server board. Video signals are also made available through the 120-pin bridge-board connector that provides signals for an optional video connector on the control panel. Video is routed to both the
3.3.1.1 Video Modes
supported for both CRT and LCD. Table 5. Video Modes
3.3.1.2 Video Memory Interface
integrity and maximum CPU/co-processor drawing performance.
3.4 Network Interface Controller (NIC)
they provide support for dual LAN ports designed for 10/100/1000 Mbps operation.
operation when amber, 100-Mbps operation when green, and 10-Mbps when off. Table 6. NIC2 Status LED
3.4.1 Intel ® I/O Acceleration Technolgy
systems and virtualized environments. such as teaming and failover.
3.5 Super I/O
- GPIOs
- Serial ports
- Keyboard and mouse support
- Wake up control
- System health support
3.5.1.1 Serial Ports
The server board provides an external DB9 serial port and an internal serial header. Table 7. Serial A Port Header Pin-out (External DB9)
1 Request to Send RTS 7
2 Data Terminal Ready DTR 4
3 Transmitted Data TD 3
4 Signal Ground SGND 5
5 Ring Indicator RI 9
6 Received Data RD 2
7 DCD or DSR DCD/DSR 1 or 6 (see note)
8 Clear To Send CTS 8
Table 8. Internal Serial B Port Header Pin-out
1 DCD
2 DSR
4 RTS
6 CTS
7 DTR
9 GND
connector, as it can also be configured to support either DSR or DCD.
3.5.1.2 Floppy Disk Controller
recognizes USB floppy devices.
Functional Architecture Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3
3.5.1.3 Keyboard and Mouse Support
Dual stacked PS/2 ports on the back edge of the server board support a keyboard and mouse. Either port can support a mouse or keyboard. Neither port supports hot plugging.
3.5.1.4 Wake-up Control
The super I/O contains functionality allows events to power-on and power-off the system.
3.5.1.5 System Health Support
The super I/O provides an interface via GPIOs for BIOS and system management firmware to activate the diagnostic LEDs, the FRU fault indicator LEDs for processors, FBDIMMS, fans, and the system status LED. See section 7 to locate the LEDs.
the Intel® 5000 Series Chipsets Server Board Family Datasheet. Figure 7. SMBUS Block Diagram
- Connector / Header Locations and Pin-outs
5.1 Board Connectors
Table 9. Board Connector Matrix
2 J2K3, J2K4 Header 4
2 JA6A1, JA5A1 External LAN connector
4 J1C2, J1C4 Jumper 3
5.2 Power Connectors
Table 10. Power Connector Pin-out (J3K3)
3 GND Black 15 GND Black
5 GND Black 17 GND Black
7 GND Black 19 GND Black
8 PWR_OK Gray 20 RSVD_(-5V) White
Table 11. 12V Power Connector Pin-out (J9E1)
1 GND Black
2 GND Black
3 GND Black
4 GND Black
Table 12. Power Supply Signal Connector Pin-out (J9C1)
1 SMB_CLK_ESB_FP_PWR_R Orange
2 SMB_DAT_ESB_FP_PWR_R Black
3 SMB_ALRT_3_ESB_R Red
5.3 Riser Card Slots
5.4 SSI Control Panel Connector
chassis. The following table provides the pin-out for this connector. Table 13. Front Panel SSI Standard 24-pin Connector Pin-out (J2K2)
1 P3V3_STBY 2 P3V3_STBY
3 Key 4 P5V_STBY
7 P3V3 8 FP_STATUS_LED1_R
9 HDD_LED_ACT_R 10 FP_STATUS_LED2_R
11 FP_PWR_BTN_L 12 LAN_ACT_A_L
13 GND 14 LAN_LINKA_L
15 Reset Button 16 PS_I2C_3VSB_SDA
17 GND 18 PS_I2C_3VSB_SCL
19 FP_ID_BTN_L 20 FP_CHASSIS_INTRU
21 TEMP_SENSOR 22 LAN_ACT_B_L
23 FP_NMI_BTN_L
24 LAN_LINKB_L
5.5 I/O Connector Pinout Definition
5.5.1 VGA Connector
The following table details the pin-out of the VGA connector (J7A1). Table 14. VGA Connector Pin-out (J7A1)
1 V_IO_R_COnN Red (analog color signal R)
2 V_IO_G_COnN Green (analog color signal G)
3 V_IO_B_COnN Blue (analog color signal B)
4 TP_VID_COnN_B4 No connection
5 GND Ground
6 GND Ground
7 GND Ground
8 GND Ground
9 TP_VID_COnN_B9 No Connection
10 GND Ground
11 TP_VID_COnN_B11 No connection
12 V_IO_DDCDAT DDCDAT
13 V_IO_HSYNC_COnN HSYNC (horizontal sync)
14 V_IO_VSYNC_COnN VSYNC (vertical sync)
15 V_IO_DDCCLK DDCCLK
5.5.2 NIC Connectors
the board (JA6A1, JA5A1). The pin-out for each connector is identical. Table 15. RJ-45 10/100/1000 NIC Connector Pin-out (JA6A1, JA5A1)
1 GND 9 NIC_A_MDI0P
2 P1V8_NIC 10 NIC_A_MDI0N
3 NIC_A_MDI3P 11 (D1) NIC_LINKA_1000_N (LED
4 NIC_A_MDI3N 12 (D2) NIC_LINKA_100_N (LED)
5 NIC_A_MDI2P 13 (D3) NIC_ACT_LED_N
6 NIC_A_MDI2N 14 NIC_LINK_LED_N
7 NIC_A_MDI1P 15 GND
8 NIC_A_MDI1N 16 GND
5.5.3 IDE Connector
Table 16. 44-pin IDE Connector Pin-out (J2K5)
1 ESB_PLT_RST_IDE_N 2 GND
3 RIDE_DD_7 4 RIDE_DD_8
5 RIDE_DD_6 6 RIDE_DD_9
7 RIDE_DD_5 8 RIDE_DD_10
9 RIDE_DD_4 10 RIDE_DD_11
11 RIDE_DD_3 12 RIDE_DD_12
13 RIDE_DD_2 14 RIDE_DD_13
15 RIDE_DD_1 16 RIDE_DD_14
17 RIDE_DD_0 18 RIDE_DD_15
19 GND 20 KEY
21 RIDE_DDREQ 22 GND
23 RIDE_DIOW_N 24 GND
25 RIDE_DIOR_N 26 GND
27 RIDE_PIORDY 28 GND
29 RIDE_DDACK_N 30 GND
31 IRQ_IDE 32 TP_PIDE_32
33 RIDE_DA1 34 IDE_PRI_CBLSNS
35 RIDE_DA0 36 RIDE_DA2
37 RIDE_DCS1_N 38 RIDE_DCS3_N
39 LED_IDE_N 40 GND
5.5.4 SATA Connectors
Table 17. SATA Connector Pin-out (J1J2, J1J1)
1 GND GND1
2 SATA#_TX_P_C Positive side of transmit differential pair
3 SATA#_TX_N_C Negative side of transmit differential pair
4 GND GND2
5 SATA#_RX_N_C Negative side of Receive differential pair
6 SATA#_RX_P_C Positive side of Receive differential pair
7 GND GND3
Table 18. SATA / SAS Connector Pin-out (J1G2, J1G1, J1F1, J1E4)
5.5.5 Serial Port Connectors
B port header (J1A1). The following tables define the pin-outs for each. Table 19. 9-pin Serial Header Pin-out (J8A1, J1A1)
1 SPA_DCD DCD (carrier detect)
2 SPA_DSR DSR (data set ready)
3 SPA_SIN RXD (receive data)
4 SPA_CTS CTS (clear to send)
5 TP_SPA_RI RI (Ring Indicate)
6 SPA_RTS RTS (request to send)
7 SPA_SOUT SOUT (serial out)
8 SPA_DTR DTR (Data terminal ready)
9 GND Ground
5.5.6 Keyboard and Mouse Connector
support a mouse or a keyboard. The following table details the pin-out of the PS/2 connector. Table 20. Stacked PS/2 Keyboard and Mouse Port Pin-out (J9A2)
1 KB_DATA_F Keyboard Data
2 NC No Connect
3 GND Ground
4 P5V_KB_F Keyboard / mouse power
5 KB_CLK_F Keyboard Clock
6 NC No Connect
7 MS_DATA_F Mouse Data
8 NC No Connect
10 P5V_KB_F Keyboard / mouse power
11 MS_CLK_F Mouse Clock
12 NC No Connect
13 GND Ground
14 GND Ground
15 GND Ground
16 GND Ground
17 GND Ground
5.5.7 USB Connector
Table 21. External USB Connector Pin-out (J9A2)
1 USB_OC1_LAN USB_Power
2 USB_P1N_LAN DATAL1 (Differentia l data line paired with DATAH1)
3 USB_P1P_LAN DATAH1 (Different ial data line paired with DATAL1)
4 GND Ground
5 USB_OC0_LAN USB_Power
6 USB_P0N_LAN DATAH0 (Different ial data line paired with DATAL0)
7 USB_P0P_LAN DATAH0 (Different ial data line paired with DATAL0)
Table 22. Internal USB Connector Pin-out (J3K1)
1 P5V USB Power
2 P5V USB Power
3 USB_ESB_P5N USB Port 5 Negative Signal
4 USB_ESB_P4N USB Port 4 Negative Signal
5 USB_ESB_P5P USB Port 5 Positive Signal
6 USB_ESB_P4P USB Port 4 Positive Signal
7 Ground Ground
8 Ground Ground
10 NC No Conncet
5.6 Fan Headers
two 4-pin fan connectors are for processor cooling fans: CPU1 fan (J2K3) and CPU2 fan (J2K4). Management Software can monitor all system fans in use. The pin configuration for each fan connector is identical. Table 23. CPU Fan Connector Pin-out (J2K3, J2K4)
1 Ground GND GROUND is the power supply ground
3 Fan Tach Out FAN_TACH signal is connected to the BMC to monitor the fan speed
4 Fan PWM In FAN_PWM signal to control fan speed
Table 24. PCI Fan Connector Pin-out (J1K1) number of high-density VLSI and power delivery components that need adequate airflow to cool. any of their published operating or non-operating limits.
recover specific features of the server board. Pin 1 on each jumper block is denoted by “▼”.
6.1 Recovery Jumper Blocks
Table 25. Recovery Jumpers (J3A1, J1C1, J1C2) reset. These pins should not be jumpered for normal operation.
Figure 8. Recovery Jumper Blocks (J3A1, J1C2, J1C4)
6.1.1 CMOS Clear and Password Reset Usage Procedure
server boards. The following procedure outlines the new usage model.
- Power down and remove AC power.
- Move jumper from the Default operating position (Pins1-2) to the Reset/Clear position
- Move jumper back to default position (Pins 1-2).
- Close the server chassis.
- Reconnect AC and power up the server.
The password and/or CMOS is cleared and can be reset in BIOS setup.
Intel® Server Board S5000VCL TPS Jumper Block Settings Revision 2.3 Intel order number: D64569-007
6.1.2 BMC Force Update Procedure
When performing a standard BMC firmware update procedure, the update utility places the BMC into an update mode, allowing the firmware to load safely onto the flash device. In the unlikely event that the BMC firmware update process fails due to the BMC not being in the proper update state, the server board provides a BMC Force Update jumper which will force the BMC into the proper update state. The following procedure should be following in the event the standard BMC firmware update process fails. 1. Power down and remove AC power. 2. Open the server. 3. Move jumper from the Default operating position (pins1-2) to the Enabled position (pins 2-3). 4. Close the server chassis. 5. Reconnect AC and power up the server. 6. Perform the BMC firmware update procedure that is documented in README.TXT file that is included in the given BMC Firmware Update package. 7. After successful completion of the firmwa re update process, the firmware update utility may generate an error stating that the BMC is still in update mode. 8. Power down and remove the AC power. 9. Open the server. 10. Move the jumper from the Enabled position (pins 2-3) to the Disabled position (pins 1-2). 11. Close the server chassis. 12. Reconnect AC and power up the server. Note: Normal BMC functionality is disabled with the Force BMC Update jumper set to the “Enabled” position. The server should never be run with the BMC Force Update jumper set in this position and should only be used when the standard firmware update process fails. This jumper should remain in the Default – Disabled position when the server is running normally.
6.2 BIOS Select Jumper
The jumper block located at J3A2, is used to select which BIOS image the system will boot to. Pin 1 on the jumper is identified by ‘▼’. This jumper should only be moved to force the BIOS to boot to the secondary bank, which may hold a different version of BIOS. The rolling BIOS feature of the server board will automatically alternate the Boot BIOS to the secondary bank if the BIOS image in the primary bank is corrupted and cannot boot.
Table 26. BIOS Select Jumper (J3A2)
6.3 PCIe Select Jumper
**Table 27. PCI Express* x4/x8 Select Jumper (J1E1)**
- Intel ® Light Guided Diagnostics
the Intel® 5000 Series Chipsets Server Board Family Datasheet. board by the power supply. See the figure below to locate this LED. Figure 9. System Status / Fault LED Location
Intel® Light Guided Diagnostics Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3 When the AC power is first applied to the system and 5-volt standby is present, the BMC on the server board requires 15-20 seconds to initialize. During this time, the system status LED blinks amber and green, and the power button functionality is disabled, preventing the server from powering up. Once BMC initialization has completed, the status LED will stop blinking and the power button functionality is restored and can be used to turn on the server. The bi-color 5V Standby System Status LED operates as follows: Color State Criticality Description Off N/A Not ready AC power off Green / Amber Alternating Blink Not ready Pre-DC power on – 15-20 second BMC initialization when AC is applied to the server. Control Panel buttons are disabled until the BMC initialization is complete. Green Solid on System OK System booted and ready. Green Blink Degraded System degraded Unable to use all of the insta lled memory (more than one DIMM installed). Correctable errors over a th reshold of 10 and migrating to a spare DIMM (memory sparing). This indicates that the user no longer has spared DIMMs indicating a redundancy lost condition. Corresponding DIMM LED should light up. In mirrored configuration, when memory mirroring takes place and system loses memory redundancy. This is not covered by the bullet above. Redundancy loss such as power-supply or fan. This does not apply to non-redundant sub-systems. PCI-e link errors CPU failure / disabled – if there are two processors and one of them fails Fan alarm – Fan failure. Number of operational fans should be more than minimum number needed to cool the system Non-critical threshold crossed – Temperature and voltage Amber Blink Non-critical Non-fatal alarm – system is likely to fail Critical voltage threshold crossed VRD hot asserted Minimum number of fans to cool the system not present or failed In non-sparing and non-mirroring mode if the threshold of ten correctable errors is crossed within the window Amber Solid on Critical, non- recoverable Fatal alarm – system has failed or shutdown DIMM failure when there is one DIMM present, no good memory present Run-time memory uncorrectabl e error in non-redundant mode IERR signal asserted Processor 1 missing Temperature (CPU ThermTrip, memory TempHi, critical threshold crossed) No power good – power fault Processor configuration error (f or instance, processor stepping mismatch)
7.2 DIMM LEDs
Series Chipsets Server Board Family Datasheet. Figure 10. DIMM LED Locations
7.3 Post Code Diagnostic LEDs
process, the Diagnostic LEDs can be used to identify the last POST process to be executed. Figure 11. POST Code Diagnostic LED Location
- Power and Environmental Specifications
8.1 Intel ® Server Board S5000VCL Design Specifications
extended periods may affect system reliability. Table 28. Server Board Design Specifications 5100 series or Quad-Core Intel® Xeon® processor 5300 series maximum case temperature. number of high-density VLSI and power delivery components that need adequate airflow to cool.
8.2 Baseboard Powe r Requirements
8.2.1 Processor Power Support
series family and Quad-Core Intel® Xeon® processor 5300 series family. Table 29. Dual-Core Intel® Xeon® processor 5100 series and Quad-Core Intel® Xeon® processor
108 W 70º C 90 A
series Datasheet values will supersede these, and should be used.
8.2.2 Power Supply Output Requirements
Table 30. 400W Load Ratings
- Combined 3.3 V and 5 V power shall not exceed 100 W.
- Maximum continuous total DC output power should not exceed 400 W.
- Peak load on the combined 12 V output shall not exceed 49 A.
- Maximum continuous load on the combined 12 V output shall not exceed 44 A.
- Peak total DC output power should not exceed 650 W.
- Peak power and current loading shall be supported for a minimum of 12 seconds.
8.2.3 Turn On No Load Operation
Table 31. No-load Operating Range
- Maximum continuous total DC output power should not exceed 400 W.
- Peak load on the combined 12 V output shall not exceed 49 A.
- Maximum continuous load on the combined 12 V output shall not exceed 44 A.
- Peak total DC output power should not exceed 650 W.
8.2.4 Grounding
The grounds of the pins of the power supply output connector provide the power return path. The output connector ground pins shall be connected to safety ground (power supply enclosure). chassis shall not exceed 1.0 mΩ. This path may be used to carry DC current.
8.2.5 Standby Outputs
8.2.6 Remote Sense
200 mV drop on the +3.3 V output. range of voltage drops from the power supply’s output connector to the remote sense points.
8.2.7 Voltage Regulation
steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise. Table 32. Voltage Regulation Limits
8.2.8 Dynamic Loading
Table 33. Transient Load Requirements
- Step loads on each 12 V output may happen simultaneously.
- The +12 V should be tested with 2200 μF evenly split between the four +12 V rails.
8.2.9 Capacitive Loading
Table 34. Capacitive Loading Conditions
8.2.10 Closed-Loop Stability
ensured at the maximum and minimum loads as applicable.
8.2.11 Common Mode Noise
- The measurement shall be made across a 100 Ω resistor between each of the DC outputs, including ground, at the DC power connector and chassis ground (power subsystem enclosure).
- The test set-up shall use an FET probe such as Tektronix* model P6046 or equivalent.
8.2.12 Ripple / Noise
The maximum allowed ripple/noise output of the power supply is defined in the following table. Table 35. Ripple and Noise
8.2.13 Soft Starting
8.2.14 Timing Requirements
shall reach regulation within 50 ms (Tvout_on) of each other during turn on of the power supply. on and off via the AC input with PSOn held low, and the PSOn signal with the AC input applied. Table 36. Output Voltage Timing
Figure 12. Output Voltage Timing Table 37. Turn On/Off Timing
5 VSB
Figure 13. Turn On/Off Timing (Power Supply Signals)
8.2.15 Residual Voltage Immunity in Standby Mode
protection circuits during turn on. when AC voltage is applied and the PSOn# signal is de-asserted.
Intel® Server Board S5000VCL TPS Regulatory and Certification Information Revision 2.3 Intel order number: D64569-007 9. Regulatory and Certification Information WARNING To ensure regulatory compliance, you must adhere to the assembly instructions in this guide to ensure and maintain compliance with existing product certifications and approvals. Use only the described, regulated components specified in this guide. Use of other products / components will void the UL listing and other regulatory approvals of the product and will most likely result in noncompliance with product regulations in the region(s) in which the product is sold. To help ensure EMC compliance with your local regional rules and regulations, before computer integration, make sure that the chassis, power supply, and other modules have passed EMC testing using a server board with a microprocessor from the same family (or higher) and operating at the same (or higher) speed as the microprocessor used on this server board. The final configuration of your end system product may require additional EMC compliance testing. For more information please contact your local Intel Representative. This is an FCC Class A device. Integration of it into a Class B chassis does not result in a Class B device.
9.1 Product Regulatory Compliance
Intended Application – This product was evaluated as Information Technology Equipment (ITE), which may be installed in offices, schools, computer rooms, and similar commercial type locations. The suitability of this product for other product categories and environments (such as: medical, industrial, telecommunications, NEBS, residential, alarm systems, test equipment, etc.), other than an ITE application, may require further evaluation. This is an FCC Class A device. Integration of it into a Class B chassis does not result in a Class B device.
9.1.1 Product Safety Compliance
- UL60950 – CSA 60950 (USA / Canada)
- EN60950 (Europe)
- IEC60950 (International)
- CB Certificate & Report, IEC60950 (report to include all country national deviations)
- GOST R 50377-92 – Listed on one System License (Russia)
- Belarus License – Listed on System License (Belarus)
- CE - Low Voltage Directive 73/23/EEE (Europe)
- IRAM Certification (Argentina)
Regulatory and Certification Information Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3
9.1.2 Product EMC Compliance – Class A Compliance
- FCC /ICES-003 - Emissions (USA/Canada) Verification
- CISPR 22 – Emissions (International)
- EN55022 - Emissions (Europe)
- EN55024 - Immunity (Europe)
- CE – EMC Directive 89/336/EEC (Europe)
- VCCI Emissions (Japan)
- AS/NZS 3548 Emissions (Australia / New Zealand)
- BSMI CNS13438 Emissions (Taiwan)
- GOST R 29216-91 Emissions - Listed on one System License (Russia)
- GOST R 50628-95 Immunity –Listed on one System License (Russia)
- Belarus License – Listed on one System License (Belarus)
- RRL MIC Notice No. 1997-41 (EMC) & 1997-42 (EMI) (Korea)
9.1.3 Certifications / Registrations / Declarations
- UL Certification or NRTL (US/Canada)
- CE Declaration of Conformity (CENELEC Europe)
- FCC/ICES-003 Class A Attestation (USA/Canada)
- C-Tick Declaration of Conformity (Australia)
- MED Declaration of Conformity (New Zealand)
- BSMI Certification (Taiwan)
- GOST – Listed on one System License (Russia)
- Belarus – Listed on one System License (Belarus)
- RRL Certification (Korea)
- Ecology Declaration (International)
Intel® Server Board S5000VCL TPS Regulatory and Certification Information Revision 2.3 Intel order number: D64569-007
9.2 Product Regulatory Compliance Markings
The server board is provided with the following regulatory marks. Regulatory Compliance Region Marking UL Mark USA/Canada CE Mark Europe EMC Marking (Class A) Canada CANADA ICES-003 CLASS A CANADA NMB-003 CLASSE A BSMI Marking (Class A) Taiwan C-tick Marking Australia / New Zealand RRL MIC Mark Korea Country of Origin Exporting Requirements MADE IN xxxxx (Provided by label, not silk screen) Model Designation Regulatory Identification Examples (Intel ® Server Board S5000VCL) for boxed type boards; or Board PB number for non- boxed boards (typically high-end boards)
Regulatory and Certification Information Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3
9.3 Electromagnetic Compatibility Notices
9.3.1 FCC Verification Statement (USA)
This device complies with Part 15 of the FCC Rules. Operation is subject to two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Intel Corporation 5200 N.E. Elam Young Parkway Hillsboro, OR 97124-6497 Phone: 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of these measures:
- Reorient or relocate the receiving antenna.
- Increase the separation between the equipment and the receiver.
- Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
- Consult the dealer or an experienced radio/TV technician for help. Any changes or modifications not expressly approved by the grantee of this device could void the user’s authority to operate the equipment. The customer is responsible for ensuring compliance of the modified product. All cables used to connect to peripherals must be shielded and grounded. Operation with cables, connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception.
Intel® Server Board S5000VCL TPS Regulatory and Certification Information Revision 2.3 Intel order number: D64569-007
9.3.2 ICES-003 (Canada)
Cet appareil numérique respecte les limites bruits radioélectriques applicables aux appareils numériques de Classe B prescrites dans la norme sur le matériel brouilleur: “Appareils Numériques”, NMB-003 édictée par le Ministre Canadian des Communications. English translation of the notice above: This digital apparatus does not exceed the Class B limits for radio noise emissions from digital apparatus set out in the interference-causing equipment standard entitled “Digital Apparatus,” ICES-003 of the Canadian Department of Communications.
9.3.3 Europe (CE Declaration of Conformity)
This product has been tested in accordance too, and complies with the Low Voltage Directive (73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark to illustrate its compliance.
9.3.4 VCCI (Japan)
English translation of the notice above: This is a Class B product based on the standard of the Voluntary Control Council for Interference (VCCI) from Information Technology Equipment. If this is used near a radio or television receiver in a domestic environment, it may cause radio interference. Install and use the equipment according to the instruction manual.
Regulatory and Certification Information Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3
9.3.5 BSMI (Taiwan)
The BSMI Certification Marking and EMC warning is located on the outside rear area of the product.
9.3.6 RRL (Korea)
Following is the RRL certification information for Korea. English translation of the notice above: 1. Type of Equipment (Model Name): On License and Product 2. Certification No.: On RRL certificate. Obtain certificate from local Intel representative 3. Name of Certification Recipient: Intel Corporation 4. Date of Manufacturer: Refer to date code on product 5. Manufacturer/Nation: Intel Corporation/Refer to country of origin marked on product
9.3.7 CNCA (CCC-China)
The CCC Certification Marking and EMC warning is located on the outside rear area of the product.
Intel® Server Board S5000VCL TPS Regulatory and Certification Information Revision 2.3 Intel order number: D64569-007
9.4 Restriction of Hazardous Substances (RoHS)
Intel has a system in place to restrict the use of banned substances in accordance with the European Directive 2002/95/EC. Compliance is based on declaration that materials banned in the RoHS Directive are either (1) below all applicable substance threshold limits or (2) an approved/pending RoHS exemption applies. Note: RoHS implementing details are not fully defined and may change. Threshold limits and banned substances are noted below.
- Quantity limit of 0.1% by mass (1000 PPM) for: - Lead - Mercury - Hexavalent Chromium - Polybrominated Biphenyl s Diphenyl Ethers (PBDE)
- Quantity limit of 0.01% by mass (100 PPM) for: - Cadmium
Appendix A: Integration and Usage Tips Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3 Appendix A: Integration and Usage Tips
- When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-volt standby is still present even though the server board is powered off.
- When two processors are installed, both mu st be of identical revision, core voltage, and bus/core speed. Mixed processor steppings is supported. However, the stepping of one processor can not be greater then one stepping back of the other.
- Processors must be installed in order. CPU 1 is located near the edge of the server board and must be populated to operate the board.
- Only fully buffered DIMMs (FBD) are supported on this server board. For a list of supported memory for this server board, see the Intel® Server Board S5000VCL Tested Memory List.
- For a list of Intel supported operating systems, add-in cards, and peripherals for this server board, see the Intel® Server Board S5000VCL Tested Hardware and OS List.
- Only Dual-Core Intel ® Xeon® processors 5100 series or low- voltage Quad-Core Intel® Xeon® processor 5300 series, with system bus speeds of 1066, or 1333 MHz are supported on this server board. Previous generation Intel® Xeon® processors are not supported. − For a complete list of supported processors, see the following link: http://support.intel.com/support/motherboards/server/S5000VCL
- Removing AC power before performing t he CMOS clear operation will cause the system to automatically power up and immediately power down after the procedure is followed and AC power is re-applied. If this happens remove the AC power cord again, wait 30 seconds, and then reconnect the AC power cord. Power up the system and proceed to the <F2> BIOS setup utility to reset desired settings.
- Normal BMC functionality is disabled with the force BMC update jumper set to the “enabled” position (pins 2-3). The server should never be run with the BMC force update jumper set in this position and should only be used when the standard firmware update process fails. This jumper should remain in the default (disabled) position (pins 1-2) when the server is running normally.
- When performing a BIOS update, the BIOS select jumper must be set to its default position (pins 2-3).
Intel® Server Board S5000VCL TPS Appendix B: Sensor Tables Revision 2.3 Intel order number: D64569-007 Appendix B: Sensor Tables This appendix lists the sensor identification numbers and information regarding the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 1.5, for sensor and event/reading-type table information.
- Sensor Type The Sensor Type references the values enumerated in the Sensor Type Codes table in the IPMI specification. It provides the context in which to interpret the sensor, e.g., the physical entity or characteristic that is represented by this sensor.
- Event / Reading Type The Event/Reading Type references values from the Event/Reading Type Code Ranges and Generic Event/Reading Type Codes tables in the IPMI specification. Note that digital sensors are a specific type of discrete sensors, which have only two states.
- Event Offset/Triggers Event Thresholds are ‘supported event generating thresholds’ for threshold types of sensors. - [u,l][nr,c,nc] upper nonrecoverable, upper critical, upper noncritical, lower nonrecoverable, lower critical, lower noncritical - uc, lc upper critical, lower critical Event Triggers are ‘supported event generating offsets’ for discrete type sensors. The offsets can be found in the Generic Event/Reading Type Codes or Sensor Type Codes tables in the IPMI specification, depending on whether the sensor event/reading type is generic or a sensor specific response.
- Assertion / De-assertion Enables Assertion and de-assertion indicators reveal the type of events the sensor can generate: - As: Assertions - De: De-assertion
- Readable Value / Offsets - Readable Value indicates the type of value returned for threshold and other non- discrete type sensors. - Readable Offsets indicate the offsets for discrete sensors that are readable via the Get Sensor Reading command. Unless otherwise indicated, all event triggers are readable, i.e., Readable Offsets consists of the reading type offsets that do not generate events.
Appendix B: Sensor Tables Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3
- Event Data This is the data that is included in an event message generated by the associated sensor. For threshold-based sensors, these abbreviations are used: - R: Reading value - T: Threshold value
- Rearm Sensors - The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. This column indicates the type supported by the sensor. The following abbreviations are used in the comment column to describe a sensor: A: Auto-rearm M: Manual rearm
- Default Hysteresis - Hysteresis setting applies to all threshol ds of the sensor. This column provides the count of hysterisis for the sensor, which can be 1 or 2 (positive or negative hysteresis).
- Criticality - Criticality is a classification of the severity and nature of the condition. It also controls the behavior of the Control Panel Status LED.
- Standby - Some sensors operate on standby power. These sensors may be accessed and / or generate events when the main (system) power is off, but AC power is present.
Whenever possible, the BIOS will output the current boot progress codes on the video screen. the progress port. The progress codes may be reported by the system BIOS or option ROMs.
- Pause: The message is displayed in the Error Manager screen, an error is logged to the SEL, and user input is required to continue. The user can take immediate corrective action or choose to continue booting.
- Halt: The message is displayed in the Error Manager screen, an error is logged to the SEL, and the system cannot boot unless the error is resolved. The user needs to replace the faulty part and restart the system.
Table 38. POST Error Messages and Handling
0012 CMOS date / time not set Pause
5220 Configuration cleared by jumper Pause
5221 Passwords cleared by jumper Pause
5223 Configuration default loaded Pause
0048 Password check failed Halt
0141 PCI resource conflict Pause
0146 Insufficient memory to shadow PCI ROM Pause
8110 Processor 01 internal error (IERR) on last boot Pause
8111 Processor 02 internal error (IERR) on last boot Pause
8120 Processor 01 thermal trip error on last boot Pause
8121 Processor 02 thermal trip error on last boot Pause
8130 Processor 01 disabled Pause
8131 Processor 02 disabled Pause
8160 Processor 01 unable to apply BIOS update Pause
8161 Processor 02 unable to apply BIOS update Pause
8190 Watchdog timer failed on last boot Pause
8198 Operating system boot watchdog timer expired on last boot Pause
0192 L3 cache size mismatch Halt
0194 CPUID, processor family are different Halt
0195 Front side bus mismatch Pause
0197 Processor speeds mismatched Pause
8300 Baseboard management controller failed self-test Pause
8306 Front panel controller locked Pause
Appendix C: POST Error Messages and Handling Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3 Error Code Error Message Response
8305 Hotswap controller failed Pause
84F2 Baseboard management controller failed to respond Pause 84F3 Baseboard management controller in update mode Pause 84F4 Sensor data record empty Pause 84FF System event log full Pause 8500 Memory Component could not be conf igured in the selected RAS mode. Pause 8520 DIMM_A1 failed Self Test (BIST). Pause 8521 DIMM_A2 failed Self Test (BIST). Pause 8522 DIMM_A3 failed Self Test (BIST). Pause 8523 DIMM_A4 failed Self Test (BIST). Pause 8524 DIMM_B1 failed Self Test (BIST). Pause 8525 DIMM_B2 failed Self Test (BIST). Pause 8526 DIMM_B3 failed Self Test (BIST). Pause 8527 DIMM_B4 failed Self Test (BIST). Pause 8528 DIMM_C1 failed Self Test (BIST). Pause 8529 DIMM_C2 failed Self Test (BIST). Pause 852A DIMM_C3 failed Self Test (BIST). Pause 852B DIMM_C4 failed Self Test (BIST). Pause 852C DIMM_D1 failed Self Test (BIST). Pause 852D DIMM_D2 failed Self Test (BIST). Pause 852E DIMM_D3 failed Self Test (BIST). Pause 852F DIMM_D4 failed Self Test (BIST). Pause 8540 Memory Component lost redundancy during the last boot. Pause 8580 DIMM_A1 Correctable ECC error encountered. Pause 8581 DIMM_A2 Correctable ECC error encountered. Pause 8582 DIMM_A3 Correctable ECC error encountered. Pause 8583 DIMM_A4 Correctable ECC error encountered. Pause 8584 DIMM_B1 Correctable ECC error encountered. Pause 8585 DIMM_B2 Correctable ECC error encountered. Pause 8586 DIMM_B3 Correctable ECC error encountered. Pause 8587 DIMM_B4 Correctable ECC error encountered. Pause 8588 DIMM_C1 Correctable ECC error encountered. Pause 8589 DIMM_C2 Correctable ECC error encountered. Pause 858A DIMM_C3 Correctable ECC error encountered. Pause 858B DIMM_C4 Correctable ECC error encountered. Pause 858C DIMM_D1 Correctable ECC error encountered. Pause 858D DIMM_D2 Correctable ECC error encountered. Pause 858E DIMM_D3 Correctable ECC error encountered. Pause 858F DIMM_D4 Correctable ECC error encountered. Pause 8600 Primary and secondary BIOS IDs do not match. Pause
8601 Override jumper is set to force boot from lower alternate BIOS bank of flash
8602 WatchDog timer expired (secondary BIOS may be bad!) Pause
8603 Secondary BIOS checksum fail Pause
visible code on POST Progress LEDs. Table 39. POST Error Beep Codes
3 Memory error System halted because a fatal error related to the memory
6 BIOS rolling back
part, and is rolling back to the last good BIOS. by a sequence of beeps whose count is equal to the digit. Table 40. BMC Beep Codes
board. The Diagnostic LEDs identify the last POST process to be executed. are clear, then the LED is off.
- red bits = 1010b = Ah
- green bits = 1100b = Ch Since the red bits correspond to the upper nibble and the green bits correspond to the lower nibble, the two are concatenated as ACh.
Table 41. Example POST Progress Code LED Figure 14. Diagnostic LED Placement Diagram
Intel® Server Board S5000VCL TPS Appendix D: POST Code Diagnostic LED Decoder Revision 2.3 Intel order number: D64569-007 Table 42. Diagnostic LED POST Code Decoder
Description
0x10h OFF OFF OFF R Power-on initialization of the host processor (bootstrap processor) 0x11h OFF OFF OFF A Host processor cache initialization (including AP) 0x12h OFF OFF G R Starting application processor initialization 0x13h OFF OFF G A SMM initialization Chipset 0x21h Off Off R G Initializing a chipset component Memory 0x22h Off Off A Off Reading configurat ion data from memory (SPD on DIMM) 0x23h Off Off A G Detecting presence of memory 0x24h Off G R Off Programming timing par ameters in the memory controller 0x25h Off G R G Configuring memory parameters in the memory controller 0x26h Off G A Off Optimizing memory controller settings 0x27h Off G A G Initializing memory, such as ECC init 0x28h G Off R Off Testing memory PCI Bus 0x50h Off R Off R Enumerating PCI busses 0x51h Off R Off A Allocating resources to PCI busses 0x52h Off R G R Hot Plug PCI controller initialization 0x53h Off R G A Reserved for PCI bus 0x54h Off A Off R Reserved for PCI bus 0x55h Off A Off A Reserved for PCI bus 0x56h Off A G R Reserved for PCI bus 0x57h Off A G A Reserved for PCI bus USB 0x58h G R Off R Resetting USB bus 0x59h G R Off A Reserved for USB devices ATA / ATAPI / SATA 0x5Ah G R G R Resetting PATA / SATA bus and all devices 0x5Bh G R G A Reserved for ATA SMBUS 0x5Ch G A Off R Resetting SMBUS 0x5Dh G A Off A Reserved for SMBUS Local Console 0x70h Off R R R Resetting the video controller (VGA) 0x71h Off R R A Disabling the video controller (VGA) 0x72h Off R A R Enabling the video controller (VGA) Remote Console 0x78h G R R R Resetting the console controller 0x79h G R R A Disabling the console controller 0x7Ah G R A R Enabling the console controller
Appendix D: POST Code Diagnostic LED Decoder Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3 Diagnostic LED Decoder G=Green, R=Red, A=Amber Checkpoint MSB LSB Keyboard (PS2 or USB) 0x90h R Off Off R Resetting the keyboard 0x91h R Off Off A Disabling the keyboard 0x92h R Off G R Detecting the presence of the keyboard 0x93h R Off G A Enabling the keyboard 0x94h R G Off R Clearing keyboard input buffer 0x95h R G Off A Instructing keyboard c ontroller to run Self Test (PS2 only) Mouse (PS2 or USB) 0x98h A Off Off R Resetting the mouse 0x99h A Off Off A Detecting the mouse 0x9Ah A Off G R Detecting the presence of mouse 0x9Bh A Off G A Enabling the mouse Fixed Media 0xB0h R Off R R Resetting fixed media device 0xB1h R Off R A Disabling fixed media device 0xB2h R Off A R Detecting presence of a fixed media device (IDE hard drive detection, etc.) 0xB3h R Off A A Enabling / configuring a fixed media device Removable Media 0xB8h A Off R R Resetting removable media device 0xB9h A Off R A Disabling removable media device 0xBAh A Off A R Detecting presence of a removable media device (IDE CDROM detection, etc.) 0xBCh A G R R Enabling / configuring a removable media device Boot Device Selection 0xD0 R R Off R Trying boot device selection 0xD1 R R Off A Trying boot device selection 0xD2 R R G R Trying boot device selection 0xD3 R R G A Trying boot device selection 0xD4 R A Off R Trying boot device selection 0xD5 R A Off A Trying boot device selection 0xD6 R A G R Trying boot device selection 0xD7 R A G A Trying boot device selection 0xD8 A R Off R Trying boot device selection 0xD9 A R Off A Trying boot device selection 0XDA A R G R Trying boot device selection 0xDB A R G A Trying boot device selection 0xDC A A Off R Trying boot device selection 0xDE A A G R Trying boot device selection 0xDF A A G A Trying boot device selection Pre-EFI Initialization (PEI) Core 0xE0h R R R Off Started dispatching early initialization modules (PEIM) 0xE2h R R A Off Initial memory found, configured, and installed correctly
Intel® Server Board S5000VCL TPS Appendix D: POST Code Diagnostic LED Decoder Revision 2.3 Intel order number: D64569-007 Diagnostic LED Decoder G=Green, R=Red, A=Amber Checkpoint MSB LSB 0xE1h R R R G Reserved for initialization module use (PEIM) 0xE3h R R A G Reserved for initialization module use (PEIM) Driver Execution Environment (DXE) Core 0xE4h R A R Off Entered EFI driver execution phase (DXE) 0xE5h R A R G Started dispatching drivers 0xE6h R A A Off Started connecting drivers DXE Drivers 0xE7h R A A G Waiting for user input 0xE8h A R R Off Checking password 0xE9h A R R G Entering BIOS setup 0xEAh A R A Off Flash Update 0xEEh A A A Off Calling Int 19. One beep unless silent boot is enabled. 0xEFh A A A G Unrecoverable boot failure / S3 resume failure Runtime Phase / EFI Operating System Boot 0xF4h R A R R Entering Sleep state 0xF5h R A R A Exiting Sleep state 0xF8h A R R R Operating system has requested EFI to close boot services (ExitBootServices ( ) has been called) 0xF9h A R R A Operating system has switched to virtual address mode (SetVirtualAddressMap ( ) has been called) 0xFAh A R A R Operating system has requested the system to reset (ResetSystem () has been called) Pre-EFI Initialization Module (PEIM) / Recovery 0x30h Off Off R R Crisis recovery has been initiated because of a user request 0x31h Off Off R A Crisis recovery has been initiated by software (corrupt flash) 0x34h Off G R R Loading crisis recovery capsule 0x35h Off G R A Handing off control to the crisis recovery capsule 0x3Fh G G A A Unable to complete crisis recovery.
Server System SR1530HCL/SR1530HCLR. Server System SR1530HCLS/SR1530HCLSR. Figure 15. Intel® Server System SR1530CL/SR1530CLR
Figure 16. Intel® Server System SR1530HCL/SR1530HCLR
Glossary Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3 Glossary Term Definition ACPI Advanced Configuration and Power Interface APIC Advanced Programmable Interrupt Control ASMI Advanced Server Management Interface BIOS Basic Input/Output System BIST Built-In Self Test BMC Baseboard Management Controller Bridge Circuitry connecting one computer bus to anot her, allowing an agent on one to access the other BSP Bootstrap Processor byte 8-bit quantity. CBC Chassis Bridge Controller (A microcontroller co nnected to one or more other CBCs, together they bridge the IPMB buses of multiple chassis. CEK Common Enabling Kit CHAP Challenge Handshake Authentication Protocol CMOS In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytes of memory, which normally resides on the server board. DPC Direct Platform Control EEPROM Electrically Erasable Programmable Read-Only Memory EHCI Enhanced Host Controller Interface EMP Emergency Management Port EPS External Product Specification ESB2 Enterprise South Bridge 2 FBD Fully Buffered DIMM FMB Flexible Mother Board FRB Fault Resilient Booting FRU Field Replaceable Unit FSB Front Side Bus GB 1024MB GPIO General Purpose I/O GTL Gunning Transceiver Logic HSC Hot-Swap Controller Hz Hertz (1 cycle/second) I2C Inter-Integrated Circuit Bus IA Intel ® Architecture IBF Input Buffer ICH I/O Controller Hub ICMB Intelligent Chassis Management Bus IERR Internal Error IFB I/O and Firmware Bridge INTR Interrupt IP Internet Protocol
Intel® Server Board S5000VCL TPS Glossary Revision 2.3 Intel order number: D64569-007 Term Definition IPMB Intelligent Pla tform Management Bus IPMI Intelligent Platform Management Interface IR Infrared ITP In-Target Probe KB 1024 bytes KCS Keyboard Controller Style LAN Local Area Network LCD Liquid Crystal Display LED Light Emitting Diode LPC Low Pin Count LUN Logical Unit Number MAC Media Access Control MB 1024KB MCH Memory Controller Hub MD2 Message Digest 2 – Hashing Algorithm MD5 Message Digest 5 – Hashing Algorithm – Higher Security ms milliseconds MTTR Memory Type Range Register Mux Multiplexor NIC Network Interface Controller NMI Nonmaskable Interrupt OBF Output Buffer OEM Original Equipm ent Manufacturer Ohm Unit of electrical resistance PEF Platform Event Filtering PEP Platform Event Paging PIA Platform Information Area (This feature config ures the firmware for the platform hardware) PLD Programmable Logic Device PMI Platform Management Interrupt POST Power-On Self Test PSMI Power Supply Management Interface PWM Pulse-Width Modulation RAM Random Access Memory RASUM Reliability, Availability, Serviceability, Usability, and Manageability RISC Reduced Instruction Set Computing ROM Read Only Memory RTC Real-Time Clock (Component of ICH peripheral chip on the server board) SDR Sensor Data Record SECC Single Edge Connector Cartridge SEEPROM Serial Electrically Erasable Programmable Read-Only Memory SEL System Event Log SIO Server Input/Output SMI Server Management Interrupt (SMI is the highest priority nonmaskable interrupt) SMM Server Management Mode
Glossary Intel ® Server Board S5000VCL TPS Intel order number: D64569-007 Revision 2.3 Term Definition SNMP Simple Network Management Protocol TBD To Be Determined TIM Thermal Interface Material UART Universal Asynchronous Receiver/Transmitter UDP User Datagram Protocol UHCI Universal Host Controller Interface UTC Universal time coordinare VID Voltage Identification VRD Voltage Regulator Down Word 16-bit quantity ZIF Zero Insertion Force
Intel® Server Board S5000VCL TPS Reference Documents Revision 2.3 Intel order number: D64569-007 Reference Documents
- Intel ® 5000 Series Chipsets Server Board Family Datasheet