D5C031 INTEL | Alldatasheet
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. . intel. 5C031
300 GATE CMOS PLD
m High Density, Low Power Replacement mw CMOS EPROM Technology Based UV for SSI & MSI Devices and Bipolar Erasable. PLDs. @ Programmable “Security Bit” Allows m Up to 18 Inputs (10 Dedicated & 8 1/0) Total Protection of Proprietary Designs and 8 Outputs. Ic (standby) 35 mA (max) m Eight Macrocells with Programmable lee (10 MHz) 40 mA (max) 1/0 Architecture. m 100% Generically Testable EPROM m@ tpp = 40 ns (max), 29.4 MHz Pipelined, Logic Control Array. 22.2 MHz with Feedback m 20-pin 0.3” Windowed CERDIP Package mw Low Power Upgrade for All Commonly (See Packaging Spec., Order # 231369) Used 20-pin PLDs. m 100% Compatible with EP310 wy, (weuT/cLK C1 2012) Yee InPuT [9 2 190 1/o input C3 1811/0 ° inPuT C94 170 1/o inpuT C95 16f1 1/0 INPUT C6 @) 15{ 1/0 INPUT [97 140 1/0 input C] 8 g 1301/0 INPUT C9 fo} 120 1/o cnd CJ 10 al 11 EI 1/Vpp 290154-1 Pin Configuration 2-232
INTRODUCTION ARCHITECTURE DESCRIPTION The Intel 5CO31 PLD (Programmable Logic Device) The architecture of the 5C031 is based on the “Sum is capable of implementing over 300 equivalent of Products” PLA (Programmable Logic Array) struc- gates of user-customized logic functions through ture with a programmable AND array feeding into a Programming. This device can be used to replace fixed OR array. This device can accommodate both bipolar programmable logic arrays and LS TTL and combinational and sequential logic functions. A pro- 74HC (CMOS) SSI and MSI logic devices. The prietary programmable |/O architecture provides in- 5C031 can also be used as a direct, low-power re- dividual selection of either combinational or regis- placement for almost all common 20-pin fuse-based tered output and feedback signals, all with select- programmable logic devices. With its flexible pro- able polarity. grammable 1/O architecture, this device has ad- vanced functional capabilities beyond that of typical The 5C031 contains 10 dedicated inputs as well as 8 programmable logic. input/output pins. These I/O pins can be individually configured to be inputs, outputs or bi-directional 1/O The 5C031 PLD uses CMOS EPROM (floating gate) pins. Each of these I/O pins is connected to a mac- cells as logic control elements instead of fuses. The rocell. The 5C031 contains 8 identical macrocells or- CMOS EPROM technology reduces power con- ganized as shown in Figure 1. sumption of PLDs to less than 20% of a comparable bipolar device without sacrificing speed perform- Each macrocell (see Figure 2) consists of a PLA ance. In addition, the use of Intel’s advanced CMOS (programmable logic array) block and an I/O archi- \\l-E EPROM process technology enables greater tecture block, which contains a “D” type register. logic densities to be achieved with superior speed The PLA block consists of eight 36-input AND gates and low-power performance over other comparable (TRUE & COMPLEMENT of 10 dedicated inputs devices. EPROM technology allows these devices plus the 8 feedback inputs from the eight macro- to be 100% factory tested by programming and cells), feeding into an OR gate. The output of this erasing all the EPROM logic control elements. PLA block is fed into the I/O architecture block. The different 1/O and feedback options that are achiev- The 5C031 is housed in a windowed 0.3” 20-pin DIP able from the 5C031 1/O block are shown in and has the benefits of being an ideal prototyping Figure 3. tool with its highly flexible I/O architecture. | 2-233
7 PRESET RESET CK
9 BR ——T TTT rrr |
Figure 1. 5C031 Architecture
Figure 2. Logic Array Macrocell
Figure 3. 5C031 I/O Architecture Control
20 PIN CMOS COMPATIBILITY
20 pin PLD configurations by utilizing the individual logic and output controls of each macrocell. List of PAL devices logically compatible with the 5C031. *PAL is a registered trademark of Advanced Micro Devices.
intel ° 5C031 Erased-State Configuration The intelligent Programming Algorithm is particularly suited to the production programming environment. Prior to programming or after erasing, the 1/O struc- This method greatly decreases the overall program- ture is configured for combinatorial active low output —_—ming time while programming reliability is ensured as with input (pin) feedback. the incremental program margin of each bit is con- tinually monitored to determine when the bit has been successfully programmed. ERASURE CHARACTERISTICS Erasure characteristics of the 5C031 are such that FUNCTIONAL TESTING erasure begins to occur upon exposure to light with wavelengths shorter than approximately 4000A. It Since the logical operation of the 5C031 is con- should be noted that sunlight and certain types of _trolled by EPROM elements, the device is complete- flourescent lamps have wavelengths in the 3000- ly testable. Each programmable EPROM bit control- 4000A. Data shows that constant exposure to room _ling the internal logic is tested using application-in- level flourescent lighting could erase the typical dependent test program patterns. After testing, the 5C031 in approximately three years, while it would devices are erased before shipment to customers. take approximately one week to cause erasure when No post-programming tests of the EPROM array are exposed to direct sunlight. If the 5C031 is to be ex- required. 2 posed to these types of lighting conditions for ex- tended periods of time, conductive opaque labels The testability and reliability of EPROM-based pro- should be placed over the device window to prevent grammable logic devices is an important feature unintentional erasure. over similar devices based on fuse technology. Fuse-based programmable logic devices require a The recommended erasure procedure for the 5C031 user to perform post-programming tests to insure is exposure to shortwave ultraviolet light with a proper programming. These tests must be done at wavelength of 2537A. The integrated dose (i.e., UV the device level because of the cummulative error intensity x exposure time) for erasure should be a _— effect. For example, a board containing ten devices minimum of fifteen (15) Wsec/cm2. The erasure each possessing a 2% device fallout translates into time with this dosage is approximately 15 to 20 min- an 18% fallout at the board level (it should be noted utes using an ultraviolet lamp with a 12,000 zW/cm2 _ that programming fallout of fuse-based programma- power rating. The 5C031 should be placed within ble logic devices is typically 2% or higher). ‘one inch of the lamp tubes during erasure. The maxi- mum integrated dose the 5C031 can be exposed to without damage is 7258 Wsec/cm2 (1 week at DESIGN RECOMMENDATIONS 12,000 pW/cm2). Exposure to high intensity UV light . for longer periods may cause permanent damage to For proper operation, it is recommended that all in- the device. put and output pins be constrained to the voltage range GND < (Vin or Vout) < Voc. Unused inputs should be tied to an appropriate logic level (e.g. ei- PROGRAMMING CHARACTERISTICS ther Vcc or GND) to minimize device power con- sumption. Reserved pins (as indicated in the iPLDS Initially, and after erasure, all the EPROM control REPORT file) should be left floating (no connect) so bits of the 5C031 are connected (in the “1” state). that the pin can attain the appropriate logic level. A Each of the connected control bits are selectively Power supply decoupling capacitor of at least 0.2 uF disconnected by programming the EPROM cells into must be connected directly between Vcc and GND their “0” state. Programming voltage and waveform pins of the device. specifications are available by request from Intel to support programming of the 5C031. As with all CMOS devices, ESD handling procedures should be used with the 5C031 to prevent damage to the device during programming, assembly, and Intelligent Programming Algorithm test. The 5C031 supports the intelligent Programming Al- gorithm which rapidly programs Intel LPDs (and EPROMs) using an efficient and reliable method. | 2-237
5C031 inte | ° PLDshell Plus design software is Intel's new, user- DESIGN SECURITY friendly design tool for zPLD design. PLDshell Plus A single EPROM bit provides a programmable de- allows users to incorporate their preferred text edi- sign security feature that controls the access to the tor, programming software, and additional design data programmed into the device. If this bit is set, a tools into a easy-to-use, menuéd design environ- Proprietary design within the device cannot be cop- ment that includes Intel's PLDasm logic compiler ied. This EPROM security bit enables a higher de- and simulation software along with disassembly, gree of design security than fused-based devices conversion and translation utilities. The PLDasm since programmed data within EPROM cells is invisi- compiler and simulator software accepts industry- ble even to microscopic evaluation. The EPROM se- standard PDS source files that express designs as curity bit, along with all the other EPROM control Boolean equations, truth tables, or state machines. bits, will be reset by erasing the device. On-line help, datasheet briefs, technical notes, and error message information, along with waveform viewing/printing capability make the design task as LATCH-UP IMMUNITY easy as possible. PLDshell Plus software is available from Intel Literature channels or from your local Intel All of the input, I/O, and clock pins of the 5C031 sales representative. have been designed to resist latch-up which is inher- ent in inferior CMOS structures. The 5C031 is de- Tools that support schematic capture and timing signed with Intel’s proprietary CMOS II-E EPROM simulation for the 5C031 are available. Please reter Process. Thus, each of the 5C031 pins will not expe- to the “Development Tools” section of the Program- rience latch-up with currents up to 100 mA and volt- mable Logic handbook. ages ranging from —1V to (Voc + 1V). Further- more, the programming pin is designed to resist The 5C031 is also supported by third-party logic latch-up to the 13.5V maximum device limit. compilers such as ABEL*, CUPL*, PLDesigner*, Log/IC*, etc. Programming support is provided by third-party programmer companies such as Data INTEL PROGRAMMABLE LOGIC 1/0, Logical Devices, STAG, etc. Please refer to the SOFTWARE SUPPORT “Third-Party Support” lists in the Programmable Logic handbook for complete information and ven- Full logic compilation and functional simulation for dor contacts. the 5C031 is supported by PLDshell Plus software.
ORDERING INFORMATION
(ns) Code Range | 40 [ae [208 | pscoai-a0 [eno | Commercial _| [ “so [28 [225 | osco01-s0 [cero | Commercas | “ABEL is a trademark of Data I/O, Corporation. CUPL is a trademark of Logical Devices, Inc. PLDesigner is a trademark of MING, Inc. Logic/IC is a ‘trademark of ISDATA, inc. 2-238 |
ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. [symboi] Parameter | [win [wax [unt *WARNING: Stressing the device beyond the “Absolute Supply Voltage(") [-20[ 70 | v | Maximum Ratings” may cause permanent damage. - These are stress ratings only. Operation beyond the Vee Programming (1) 29] 8 | v “Operating Conditions” is not recommended and ex- Supply Voltage! tended exposure beyond the “Operating Conditions” DC Input Voltage(12) [-o.5]Voctos| v_| may affect device reliability. lg [Storage Tomperanre | -e5] +180 | °c | [tems —_| Ambient Temperature(3) [-10] +05 | <c | NOTES: 1. Voltages with respect to ground. 2. Minimum DC input is —0.5V. During transitions, the in- puts may undershoot to —2.0V or overshoot to 7.0V for periods less than 20 ns under no load conditions. 3. Under bias. Extended temperature versions are also 2 available. RECOMMENDED OPERATING CONDITIONS [symbol [Parameter | min, [max | unt Supply Voltage [ars | sas | Output Voltage a ee Operating Temperate | oo | evo |e D.C. CHARACTERISTICS Ty, = 0° to +70°C, Voc = 5V +5% [_Symbot | Parameter/TestConaitions | min | Typ | Max [Unit _| Vou!) High Level Output Voltage 2.4 Vv lo = —4.0mA D.C., Voc = min. Vor Low Level Output Voltage Vv lo = 4.0 mA D.C., Veg = min. input Leakage Current +10 BA Voc = max., GND < Vin < Voc | 2-239
s sen intel. D.C. CHARACTERISTICS T, = 0° to +70°C, Voc = 5V +5% (Continued) [| _symboi_|_Parameter/Test Conditions [win | Typ | Max | Unit | Output Leakage Current +10 pA Voc = max., GND < Vout < Voc Isc (6) Output Short Circuit Current mA Voc = max., Vout = 0.5V loc Power Supply Current mA Voc = max., Vin = Voc or GND No Load, Input Freq. = 1 MHz Device prog. as 8-bit Ctr. NOTES: 4. Absolute values with respect to device GND; all over and undershoots due to ‘system or tester noise are included. 5. Ig at CMOS levels (3.84V) = —2 mA. 6. Not more than 1 output should be tested at a time. Duration of that test must not exceed 1 second. A.C. TESTING LOAD CIRCUIT A.C. TESTING INPUT, OUTPUT WAVEFORM Sv 30 FFG 20 8550 0 DEVICE To TEST
3410 C, (INCLUDES VIG 200154-7
CAPACITANCE) AC. Testing: Inputs are Driven at 3.0V for a Logic “1” and OV for . a Logic “0”. Timing Measurements are made at 2.0V for a Logic = “1” and 0.8V for a Logic “0” on inputs. Outputs are measured at = a 1.5V point. Device input rise and fall times < 6 ns. 290154-6 Cy = 50 pF CAPACITANCE | Svmboi_| Parameter [Conditions [win | Typ | Max | Unit | InputCapacitance | Viy=ov.t=10MHz [| | [20 | pF | Output Capacitance | Vour=ov.t=1omHz | | [20 | oF | Clock PinGapacitance | Viy=ov.t=10MHz | | [20 | pF | | Cwe | veppin Tints | STS | 2-240 |
intel ° 5C031 A.C. CHARACTERISTICS T, = 0°C to + 70°C, Voc = 5V +5%, Turbo Bit Programmed(?) 5C031-40 5031-50 | win | typ | Max | win | typ | max | Ltn | Asyncn Reset | ares | | | a [| [50 {ns | NOTES: 7. Typical Values are at Ta = 25°C, Voc = 5V, Active Mode 8 ‘pax. ond tpxz are measured at +0.5V from steady state voltage as driven by spec. output load. tpxz is measured with L= . SYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS Ta = 0°C to + 70°C, Voc = 5.0V +5%, Turbo Bit On(7) Parameter £P310-3 EP310 | min | typ | Max | min | Typ | Max | = eee TT 1/(to + tcH)— No Feedback porter! | (=P TTI 1/tont — With Internal Feedback [uy [toervoHoWatercixrn | 0 | | | 0] | |» | a Register Input — Internal Path ln fokrigntime st | | St me | Td Fiscr | cikHigntosmen ase | | | | |] » | r= | | 2-241
sonst intel. SWITCHING WAVEFORMS COMBINATORIAL MODE INPUT OR 1/0 INPUT tpo COMBINATORIAL OUTPUT | ) — texz COMBINATORIAL OR | HIGH IMPEDANCE REGISTERED OUTPUT ‘3= STATE t- tpzx HIGH IMPEDANCE d VALII UT Sc siaTe LID OUTPI tour ASYNCHRONOUSLY CLEAR OUTPUT 290154-8 SYNCHRONOUS CLOCK MODE ton ter cLKI tsy ty INPUT MAY CHANGE Kume| INPUT MAY CHANGE EE sn tser (FROM REGISTER To OUTPUT) VALID OUTPUT 290154-9 2-242 |
5C031 Current in Relation to Frequency eg a og a A
70 Poo
¢ of Lee 30 et
20 HH | {|
fo (MHz) 290154-10 Conditions: Ta = 0°C, Voc = 5.25V | 2-243