D41763-005

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Intel® Server Boards S5000PSL and S5000XSL Technical Product Specification Intel order number: D41763-005 Revision 1.4 November 2007 Enterprise Platforms and Services Division – Marketing Revision 1.4 Intel order number: D41763-005 ii

Intel® Server Boards S5000PSL and S5000XSL Revision History

Revision History

November 2005 0.5 Preliminary Draft March 2006 0.9 Updated all sections with the latest product information, updated illustrations, added section for Regulatory/Certification, added appendix for Sensor Table, POST Code Diagnostic LED’s, POST Code & Error Handling, Supported Chassis, Added references for the S5000XSL. May 2006 1.0 Updated the Server Board picture and Block Diagram, added information for which slot the ROMB card goes into, added information on the HDD LED Header, added information on the Snoop Filter, and cleaned other general things up in the document. September 2006 1.1 Updated legal disclaimer; Updated Processor Table; Updated Memory Section September 2006 1.2 Updated Reference Documents Aug 2007 1.3 Updated to reflect new processor support and new product codes where and Appendix E; November 2007 1.4 Added board dimension to Table 1, Server Board Features; Corrected processor naming convention; Removed Table 2, Processor Support Matrix; Corrected Table 8, NIC Status LED; Removed unused BNB temp sensor from Table 46, BMC Sensors. Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and / or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Server Boards S5000PSL and S5000XSL may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Refer to the Intel® Server Boards S5000PSL and S5000XSL Specification Update for published errata. Intel Corporation server baseboards contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel’s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation can not be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits. Revision 1.4 Intel order number: D41763-005 iii

Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation. *Other brands and names may be claimed as the property of others. Copyright © Intel Corporation 2006, 2007. Revision 1.4 Intel order number: D41763-005 iv

Intel® Server Boards S5000PSL and S5000XSL TPS Table of Contents Table of Contents Revision 1.4 Intel order number: D41763-005 v

Table of Contents Intel® Server Boards S5000PSL and S5000XSL TPS Revision 1.4 Intel order number: D41763-005 vi

Intel® Server Boards S5000PSL and S5000XSL TPS Table of Contents Revision 1.4 Intel order number: D41763-005 vii

Table of Contents Intel® Server Boards S5000PSL and S5000XSL TPS Revision 1.4 Intel order number: D41763-005 viii

List of Tables Intel® Server Boards S5000PSL and S5000XSL TPS Revision 1.4 Intel order number: D41763-005 xii This page intentionally left blank

Intel® Server Boards S5000PSL and S5000XSL TPS List of Tables 1. Introduction This Technical Product Specification (TPS) provides board-specific information about the features, functionality, and high-leve l architecture of the Intel® Server Boards S5000PSL and S5000XSL. See the Intel® S5000 Server Board Family Datasheet for details about board sub-systems, including the chipset, BIOS, and server management. In addition, design level information for specific sub-systems can be obtained by ordering the External Product Specifications (EPS) for a given sub-system. EPS documents are not publicly available and must be ordered through your local Intel representative.

1.1 Chapter Outline

This document is divided into the following chapters ƒ Chapter 1 – Introduction ƒ Chapter 2 – Server Board Overview ƒ Chapter 3 – Functional Architecture ƒ Chapter 4 – Platform Management ƒ Chapter 5 – Connector and Header Location and Pin-out ƒ Chapter 6 – Configuration Jumpers ƒ Chapter 7 – Light-Guided Diagnostics ƒ Chapter 8 – Power and Environmental specifications ƒ Chapter 9 – Regulatory and Certification Information ƒ Appendix A – Integration and Usage Tips ƒ Appendix B – BMC Sensor Tables ƒ Appendix C – POST Code Diagnostic LED Decoder ƒ Appendix D – POST Code Errors ƒ Appendix E – Supported Intel® Server Chassis

1.2 Server Board Use Disclaimer

Intel Corporation server boards support add-in peripherals and contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel se rver Revision 1.4 Intel order number: D41763-005

Server Board Overview Intel® Server Boards S5000PSL and S5000XSL TPS building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is the responsibility of the system integrator who chooses not to use Intel-developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits. Revision 1.4 Intel order number: D41763-005

2.1 Server Board Feature Set

Table 1. Server Board Features

Server Board Overview Intel® Server Boards S5000PSL and S5000XSL TPS Feature Description Server Board Dimension 13.0 inches x12.0 inches (330.2 mm x 304.8 mm) On-board Connectors/Headers External connections: ƒ Stacked PS/2* ports for keyboard and mouse ƒ Stacked video / DB9 serial port A connector ƒ Two RJ45 / 2xUSB connectors for 10 / 100 / 1000 Mb and USB 2.0 support ƒ One USB 2x5 pin header, which supports two USB ports ƒ One USB port Type A connector ƒ One DH10 serial port B header ƒ Six SATA-2 connectors with embedded RAID 0, 1, and 10 support [2]. Software RAID 5 support through an optional SATA Software RAID 5 KEY[3] ƒ Two SATA-2 connectors and four SAS/ SATA-2 c onnectors with embedded RAID 0, 1, and 10 support[1]. Software RAID 5 support through an optional SAS RAID KEY[3]. The embedded SAS RAID supports up to 8 hard drives with expander backplane ƒ One ATA100 40-pin connector ƒ One RMM/RMM2 connector to support the optional Intel ® Remote Management Module or Intel® Remote Management Module 2 ƒ One I/O connector supporting an optional RMM/RMM2 NIC I/O module ƒ SSI-compliant front panel header ƒ SSI-compliant 24-pin main power connector, s upporting the ATX-12 V standard on the first 20 pins Video On-board ATI* ES1000 video controller with 16-MB DDR SDRAM Hard Drive Support for six SATA-2 hard drives Support for four SAS/SATA-2 hard drives with non-expanded backplane[4]. LAN Two 10 / 100 / 1000 Intel® 82563EB PHYs supporting Intel® I/O Acceleration Technology Fans Support for ƒ Two processor fans ƒ Four front hot-swap fans ƒ Two rear system fans Server Management Support for Intel® System Management Software Note 1: Available with product codes S5000PSLSAS/S5000PSLSASR, BB5000PSLSAS/BB5000PSLSASR Note 2: Available with product codes S5000PSLSATA/S5000PSLSATAR, S5000PSLROMB/S5000PSLROMBR, BB5000PSLSATA/BB5000PRLSATAR, BB5000PSLROMB/BB5000PSLROMBR, or BB5000XSLSATA/BB5000XSLSATAR Note 3: The SATA software RAID 5 key is same as SAS software RAID 5 key, but install to different on-board connector. Note 4: Available with product codes S5000PSLSAS/S5000PSASR, BB5000PSLSAS/BB5000PSLSASR, S5000PSLROMB/S5000PSLROMBR, or BB5000PSLSROMB/BB5000PSLROMBR Revision 1.4 Intel order number: D41763-005

2.2 Server Board Layout

Figure 1. Server Board Photograph

Server Board Overview Intel® Server Boards S5000PSL and S5000XSL TPS

2.2.1 Server Board Connector and Component Layout

The following figure shows the board layout of the server board. Each connector and major component is identified by a letter. A table of component descriptions follows the figure. Revision 1.4 Intel order number: D41763-005

Figure 2. Major Board Components

2.2.2 Server Board Mechanical Drawings

Figure 3. Mounting Hole Positions

Figure 4. Component Positions

8 PLCS

Figure 5. Restricted Areas on Side 1

11 PLCS

1 PLACE

Figure 6. Restricted Areas on Side 2

Figure 7. Restricted Areas on Side 2, “Detail B”

Figure 8. CPU and Memory Duct Keepout

2.2.3 Server Board ATX I/O Layout

The drawing below shows the layout of the rear I/O components for the server board. Figure 9. ATX I/O Layout

Intel® Server Boards S5000PSL and S5000XSL TPS List of Tables 3. Functional Architecture The architecture and design of the Intel® Server Boards S5000PSL and S5000XSL are based on the Intel® S5000P and S5000X chipsets respectively. These chipsets are designed for systems that use the Intel® Multi-Core Xeon® processor with system bus speeds of 667 MHz, 1066 MHz, and 1333 MHz. The chipset contains two main components: the Memory Controller Hub (MCH) for the host bridge and the I/O controller hub for the I/O sub-system. The chipset uses the Enterprise South Bridge (ESB2-E) for the I/O controller hub. This chapter provides a high-level description of the functionality associated with each chipset component and the architectural blocks that make up the server bo ard. For more information about the functional architecture blocks, see the Intel® S5000 Server Board Family Datasheet. Revision 1.4 Intel order number: D41763-005

Figure 10. Functional Block Diagram

Intel® Server Boards S5000PSL and S5000XSL TPS List of Tables

3.1 Intel ® 5000P / 5000X Memory Controller Hub (MCH)

The Memory Controller Hub (MCH) is a single 1432-pin FCBGA package, which includes the following core platform functions: ƒ System Bus Interface for the processor sub-system ƒ Memory Controller ƒ PCI-Express Ports including the Enterprise South Bridge Interface (ESI) ƒ FBD Thermal Management ƒ SMBUS Interface This section provides a high-level overview of some of these core functions as they pertain to this server board. Additional information can be obtained from the Intel S5000 Server Board Family Datasheet and the Intel 5000 Series Chipset Memory Controller Hub Datasheet.

3.1.1 System Bus Interface

The MCH is configured for symmetric multi-processing across two independent front side bus interfaces that connect to the Multi - Core Intel® Xeon® processors. Each front side bus on the MCH uses a 64-bit wide 667-, 1066-, or 1333-MHz data bus. The 1333- MHz data bus is capable of transferring data at up to 10.66 GB/s. The MCH supports a 36-bit wide address bus, capable of addressing up to 64 GB of memory. The MCH is the priority agent for both front side bus interfaces, and is optimized for one processor on each bus.

3.1.2 Processor Support

The server board supports the following processors:

• One or two Dual-Core Intel ® Xeon® Processors 5000 series with a 667-, 1066-, or 1333-MHz front side bus with frequencies starting at 2.67GHz.
• One or two Dual-Core Intel ® Xeon® Processors 5100 series with a 1066- , or 1333-MHz front side bus with frequencies starting at 1.60GHz.
• One or two Dual-Core Intel ® Xeon® Processors 5300 series with a 1066-, or 1333-MHz front side bus with frequencies starting at 1.60GHz. Revision 1.4 Intel order number: D41763-005

Server Board Overview Intel® Server Boards S5000PSL and S5000XSL TPS

• One or two Dual-Core Intel ® Xeon® Processors 5200 series with a 1066-, or 1333-MHz front side bus with frequencies starting at 1.86GHz. – only product code ending with “R” supports this processor series.
• One or two Quad-Core Intel ® Xeon® Processors 5400 series with a 1066-, or 1333-MHz front side bus with frequencies starting at 2.33GHz. – only product code ending with “R” supports this processor series. Previous generations of the Intel® Xeon® Processors are not supported on the server board. See the following table for a detailed list of supported Multi-Core Intel® Xeon® Processors. See http://support.intel.com/support/motherboards/server/s5000psl/ for a complete updated list of supported processors. On the Support tab, look for “Compatibility” and then “Supported processor list”. Note: Only Intel® multi-core Xeon processors with 667MHz, 1066MHz or 1333MHz front side bus are supported.

3.1.2.1 Processor Population Rules

When two processors are installed, both must be of identical revision, core voltage, and bus/core speed. When only one processor is installed, it must be in the socket labeled CPU1. The other socket must be empty. The board is designed to provide up to 130A of current per processor. Processors with higher current requirements are not supported. No terminator is required in the second processor socket when using a single processor configuration.

3.1.2.2 Common Enabling Kit (CEK) Design Support

The server board complies with Intel’s Common Enabling Kit (CEK) processor mounting and heatsink retention solution. The server board ships with a CEK spring snapped onto the underside of the server board, beneath each processor socket. The heatsink attaches to the CEK, over the top of the processor and the thermal interface material (TIM). See the figure below for the stacking order of the chassis, CEK spring, server board, TIM, and heatsink. The CEK spring is removable, allowing for the use of non-Intel heatsink retention solutions. Note: The processor heat sink and CEK spring shown in the following diagram are for reference purposes only. The actual processor heat sink and CEK solutions compatible with this generation server board may be of a different design. Revision 1.4 Intel order number: D41763-005

Figure 11. CEK Processor Mounting

3.1.3 Memory Sub-system

is supported by a separate memory controller. The two channels on each branch operate in lock-step to increase FBD bandwidth.

667 FBDIMM memory which gives a total read bandwidth of 21.4 GB/s for four DIMM channels. Figure 12. Memory Layout the MCH memory registers. The following table provides the I2C addresses for each DIMM socket.

Table 2. I2C Addresses for Memory Module SMB

3.1.3.1 Memory RASUM Features

See the Intel® S5000 Server Board Family Datasheet for more information about these features.

3.1.3.2 Supported Memory

maximum memory configurations supported with the specified memory technology. Table 3. Maximum Eight-DIMM System Memory Configruation – x8 Single Rank

256 Mb 1 GB 2 GB

512 Mb 2 GB 4 GB

1024 Mb 4 GB 8 GB

2048 Mb 8 GB 16 GB

Table 4. Maximum Eight-DIMM System Memory Configuration – x4 Dual Rank

256 Mb 4 GB 8 GB

512 Mb 8 GB 16 GB

1024 Mb 16 GB 32 GB

2048 Mb 16 GB 32 GB

S5000PSL/S5000XSL Tested Memory List for a list of supported memory for this server board.

3.1.3.3 DIMM Population Rules and Supported DIMM Configurations

can be different between different DIMM pairs.

Intel® Server Boards S5000PSL and S5000XSL TPS List of Tables For example, a valid mixed DIMM configuration may have 512MB DIMMs installed in DIMM Slots A1 & B1, and 1GB DIMMs installed in DIMM slots C1 & D1. Intel supported DIMM configurations for this server board are shown in the following table. Supported and Validated configuration : Slot is populated Supported but not validated configuration : Slot is populated Slot is not populated Mirroring: Y = Yes. Indicates that c onfiguration supports Memory Mirroring. Sparing: Y(x) = Yes. Indicates that configuration supports Memory Sparing. Where x = 0 : Sparing supported on Branch0 only 1 : Sparing supported on Branch1 only 0,1 : Sparing supported on both branches Branch 0 Branch 1 Channel A Channel B Channel C Channel D DIMM_A1 DIMM_A2 DIMM_B1 DIMM B2 DIMM C1 DIMM C2 DIMM D1 DIMM D2 Mirroring Possible Sparing Possible Y (0) Y Y (0) Y Y (0, 1) Notes: - Single channel mode is only tested and supported with a 512MB x8 FBDIMM installed in DIMM Slot A1. - The supported memory configurations mu st meet population rules defined above. Revision 1.4 Intel order number: D41763-005

er Board Overview Intel® Server Boards S5000PSL and S5000XSL TPS Revision 1.4 - For best performance, the number of DIMMs installed should be balanced across both memory branches. For Example: a four DIMM configuration will perform better than a two DIMM configuration and should be installed in DIMM Slots A1, B1, C1, and D1. An eight DIMM configuration will perform better then a six DIMM configuration. - Although mixed DIMM capacities between channel s is supported, Intel does not validate DIMMs in mixed DIMM configurations. Intel order number: D41763-005 Serv

3.1.3.3.1 Minimum Non-Mirrored Mode Configuration

system performance reasons, Intel’s recommendation is that at least 2 DIMMs be installed. The following diagram shows the recommended minimum DIMM memory configuration. Populated DIMM slots are shown in Grey. Figure 13. Minimum Two DIMM Memory Configuration support this configuration with a single 512 MB x8 FBDIMM installed in DIMM socket A1.

3.1.3.4 Non-mirrored Mode Memory Upgrades

and organization. DIMMs that cover adjacent slot positions do not need to be identical. Figure 14. Recommended Four DIMM Configuration when both branches operate in parallel.

Intel® Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Revision 1.4 Intel order number: D41763-005

3.1.3.4.1 Mirrored Mode Memory Configuration

When operating in mirrored mode, both branches operate in lock step. In mirrored mode, branch 1 contains a replicate copy of the data in branch 0. The minimum DIMM configuration to support memory mirroring is four DIMMs, populated as shown in Figure 14, above. All four DIMMs must be identical with respect to size, speed, and organization. To upgrade a four DIMM mirrored memory configuration, four additional DIMMs must be added to the system. All four DIMMs in the second set must be identical to the first with the exception of speed. The MCH will adjust to the lowest speed DIMM.

3.1.3.4.2 Sparing Mode Memory Configuration

The MCH provides memory sparing capabilities. Sparing is a RAS feature that involves configuring a DIMM to be placed in reserve so it can be use to replace a DIMM that fails. DIMM sparing occurs within a given bank of memory and is not supported across branches. There are two supported Memory Sparing configurations. ƒ Single Branch Mode Sparing ƒ Dual Branch Mode Sparing

Figure 15. Single Branch Mode Sparing DIMM Configuration ƒ DIMM_A1 and DIMM_B1 must be identical in organization, size and speed. ƒ DIMM_A2 and DIMM_B2 must be identical in organization, size and speed. ƒ DIMM_A1 and DIMM_A2 need not be identical in organization, size and speed. ƒ DIMM_B1 and DIMM_B2 need not be identical in organization, size and speed. ƒ Sparing should be enabled in BIOS setup. ƒ The BIOS will configure Rank Sparing Mode. selected as the spare pair unit.

Intel® Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Revision 1.4 Intel order number: D41763-005 Dual branch mode sparing requires that all eight DIMM sockets be populated and must comply with the following population rules. ƒ DIMM_A1 and DIMM_B1 must be identical in organization, size and speed. ƒ DIMM_A2 and DIMM_B2 must be identical in organization, size and speed. ƒ DIMM_C1 and DIMM_D1 must be identical in organization, size and speed. ƒ DIMM_C2 and DIMM_D2 must be identical in organization, size and speed. ƒ DIMM_A1 and DIMM_A2 need not be identical in organization, size and speed. ƒ DIMM_B1 and DIMM_B2 need not be identical in organization, size and speed. ƒ DIMM_C1 and DIMM_C2 need not be identical in organization, size and speed. ƒ DIMM_D1 and DIMM_D2 need not be identical in organization, size and speed. ƒ Sparing should be enabled in BIOS setup. ƒ The BIOS will configure Rank Sparing Mode. ƒ The larger of the pairs {DIMM_A1, DIMM_B1}, {DIMM_A2, DIMM_B2}, {DIMM_C1, DIMM_D1}, and {DIMM_C2, DIMM_D2} are selected as the spare pair units. When a dual-ranked FBDIMM is used as a spare, the BIOS has the ability to independently select a physical rank on that FBDIMM as the spare unit and utilize the other physical rank as a normal unit. This selective sparing ensures maximization of available memory while still providing RAS. However, populating differently-ranked FBDIMMs for sparing is not a good practice and may yield unpredictable results.

3.1.4 Snoop Filter (5000X MCH only)

The 5000X version of the MCH includes a snoop filter. Depending on the application of the server, this feature can be used to enhance the performance of the server by eliminating traffic on the snooped system bus of the processor being snooped. By removing snoops form the snooped bus, the full bandwidth is available for other transactions.

3.2 Enterprise South Bridge (ESB2-E)

The ESB2-E is a multi-function device that provides four distinct functions: an I/O controller, a PCI-X* bridge, a GB Ethernet controller, and a baseboard management controller (BMC). Each function has its own set of configuration registers. Once configured, each appears to the system as a distinct hardware controller. The ESB2-E provides the gateway to all PC-compatible I/O devices and features. The server boards use the following ESB2-E features: ƒ PCI-X bus interface ƒ Six-channel SATA interface with SATA Busy LED Control ƒ Dual GbE MAC ƒ Baseboard Management Controller (BMC)

Intel 631xESB/632xESB I/O Controller Hub Datasheet.

3.2.1 PCI Sub-system

each bus segment follow the table. Table 5. PCI Bus Segment Characteristics

3.3 V X4 10 Gb/S PCI

3.3 V X8 20 Gb/S PCI

Intel® Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Revision 1.4 Intel order number: D41763-005

3.2.1.1 PCI32: 32-bit, 33-MHz PCI Sub-system

All 32-bit, 33-MHz PCI I/O is directed through the ESB2-E ICH6. The 32-bit, 33-MHz PCI segment created by the ESB2-E-ICH6 is known as the PCI32 segment. The PCI32 segment supports the following embedded devices: ƒ 2D Graphics Accelerator: ATI* ES1000 Video Controller

3.2.1.2 PXA: 64-bit, 133-MHz PCI Sub-system

One 64-bit PCI-X bus segment is directed through the ESB2-E ICH6. This PCI-X segment, PXA, is routed to PCI-X Slots 1 and 2. With only one PCI-X adapter populated in Slot 2 and Slot 1 left empty, PCI-X Slot 2 supports a maximum speed of 133MHz. With both Slot 1 and Slot 2 populated, Slot 2 supports a maximum speed of 100MHz. PCI-X Slot 1 supports a maximum speed of 100MHz even when Slot 2 is not populated.

3.2.1.3 PE0: One x4 PCI Express* Bus Segment

One x4 PCI Express* bus segment is directed through the ESB2-E. This PCI Express* segment, PE0, is routed to PCI Express* Slot 4 that is special keyed to support ROMB card.

3.2.1.4 PE1: One x4 PCI Express* Bus Segment

One x4 PCI Express* bus segment is directed through the ESB2-E. This PCI Express* segment, PE1, is routed to PCI Express* Slot 3. This becomes a x8 PCI Express* bus segment by combining PE2 with PE1 for SATA server board or ROMB server board that do not have on- board SAS controller.

3.2.1.5 PE2: One x4 PCI Express* Bus Segment

One x4 PCI Express* bus segment is directed through the ESB2-E. This PCI Express* segment, PE2, is routed to PCI Express* Slot 3 for server boards that do not have on-board SAS controller (SATA server board or ROMB server board), or to the onboard SAS controller for server boards that do have on-board SAS controller (SAS server board).

3.2.1.6 PE4, PE5: Two x4 PCI Express* Bus Segments

Two x4 PCI Express* bus segments are directed through the MCH. These PCI Express* segments, PE4 and PE5, are routed to PCI Express* Slot 5.

3.2.1.7 PE6, PE7: Two x4 PCI Express* Bus Segments

Two x4 PCI Express* bus segments are directed through the MCH. These PCI Express* segments, PE6 and PE7, are routed to PCI Express* Slot 6.

3.2.1.8 PCI Express* Riser Slot

PCI Express* Slot 6 supports 3rd party riser cards for both 1U and 2U system configurations. Two PCI Express* pins are designated as Riser Type pins with the definitions noted in the table below.

Design and Environmental Specifications Intel® Server Boards S5000PSL and S5000XSL TPS Revision 1.4 Intel order number: D41763-005 LP Riser TYPE 1 LP Riser Type 0 GPI: ESB2 GPI 28 GPI: ESB2 GPI 27 SLOT 6 SETUP 1 PCI-E Pin: B48 [RSVD] PCI-E Pin: B49 [GND] 2U Riser, 2 x4 PCI Express* Slots2 0 1 1U Riser, 1 x8 PCI Express* Slot3 1 0 Notes: 1 The server board contains a weak pull-up resistor on the two Riser Type nets.

2 The 2U riser card needs to pull-down the PCI Express* pin B48 with a 0 ohm resistor

and leave as a No-Connect (NC) PCI Express* pin B49.

3 The 1U riser card needs to follow the standard PCI Express* Adapter pin-out by leaving

pin B48 as a No-Connect (NC) and pin B49 as ground. The following table provides the supported bus throughput for the given riser card used and the number of add-in cards installed. PCI Express* Slot 6 Riser Support 1 add-in card 2 add-in cards 1U Riser Card X8 NA 2U Riser Card X4 X4 Note: There are no population rules for installing a single add-in card in the 2U riser card; a single add in card can be installed in either PCI Express* slot.

3.2.2 Serial ATA Support

The ESB2-E has an integrated Serial ATA (SATA) controller that supports independent DMA operation on six ports and supports data transfer rates of up to 3.0 Gb/s. The six SATA ports on the server board are numbered SATA-0 thru SATA-5. The SATA ports can be enabled/disabled and/or configured by accessing the BIOS Setup utility during POST.

3.2.2.1 Intel ® Embedded Server RAID Technology II Support

The onboard storage capability of this server board includes support for Intel® Embedded Server RAID Technology which provides three standard software RAID levels: data stripping (RAID Level 0), data mirroring (RAID Level 1), and data stripping with mirroring (RAID Level 10). For higher performance, data stripping can be used to alleviate disk bottlenecks by taking advantage of the dual independent DMA engines that each SATA port offers. Data mirroring is used for data security. Should a disk fail, a mirrored copy of the failed disk is brought on-line. There is no loss of either PCI resources (request/grant pair) or add-in card slots. With the addition of an optional Intel RAID Activation Key, Intel® Embedded Server RAID Technology is also capable of providing fault tolerant data stripping (software RAID Level 5), such that if a SATA hard drive should fail, the lost data can be restored on a replacement drive from the other drives that make up the RAID 5 pack. See Figure 2 Major Board Components for the location of Intel RAID Activation Key connector location. Intel® Embedded Server RAID Technology functionality requires the following items:

Intel® Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Revision 1.4 Intel order number: D41763-005

• Intel ® ESB-2 IO Controller Hub
• Intel ® Embedded Server RAID Technology Option ROM
• Intel ® Embedded Server RAID Technology II drivers, most recent revision
• At least two SATA hard disk drives Intel® Embedded Server RAID Technology is not available in the following configurations:
• The SATA controller in Legacy mode or AHCI mode
• Intel ® Embedded Server RAID Technology II has been disabled

3.2.2.2 Intel ® Embedded Server RAID Technology Option ROM

The Intel® Embedded Server RAID Technology for SATA Option ROM provides a pre-OS user interface for the Intel® Embedded Server RAID Technology implementation and provides the ability for an Intel® Embedded Server RAID Technology volume to be used as a boot disk as well as to detect any faults in the Intel® Embedded Server RAID Technology volume(s) attached to the Intel® RAID controller.

3.2.3 Parallel ATA (PATA) Support

The integrated IDE controller of the ESB2-E ICH6 provides one IDE channel. It redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 100 MB/s. For this server board, the IDE channel was designed to provide optical drive support to the platform. The BIOS initializes and supports ATAPI devices such as LS-120/240, CD-ROM, CD-RW and DVD-ROM. The IDE channel is accessed through a single standard 40- pin IDE connector (J2J2) that provides the I/O signals. The ATA channel can be configured and enabled or disabled by accessing the BIOS Setup utility during POST. 3.2.4 USB 2.0 Support The USB controller functionality integrated into ESB2-E provides the server board with the interface for up to eight USB 2.0 ports. Four external connectors are located on the back edge of the server board. One internal 2x5 header (J3J1) is provided, capable of supporting two optional USB 2.0 ports. One USB port Type A connector (J3G1) is provided to support installation of a USB device inside the server chassis. An additional USB port is dedicated to the Intel ® Remote Management Module (Intel® RMM) connector.

3.3 Video Support

The server board provides an ATI* ES1000 PCI graphics accelerator, along with 16 MB of video DDR SDRAM and support circuitry for an embedded SVGA video sub-system. The ATI ES1000 chip contains an SVGA video controller, clock generator, 2D engine, and RAMDAC in a 359-pin BGA. One 4M x 16 x 4-bank DDR SDRAM chip provides 16 MB of video memory. The SVGA sub-system supports a variety of modes, up to 1024 x 768 resolution in 8 / 16 / 32 bpp modes under 2D. It also supports both CRT and LCD monitors up to a 100 Hz vertical refresh rate.

Design and Environmental Specifications Intel® Server Boards S5000PSL and S5000XSL TPS Revision 1.4 Intel order number: D41763-005 Video is accessed using a standard 15-pin VGA connector found on the back edge of the server board. The on-board video controller can be disabled using the BIOS Setup Utility or when an add-in video card is installed. The system BIOS provides the option for dual-video operation when an add-in video card is configured in the system.

3.3.1 Video Modes

2D modes supported for both CRT and LCD. Table 6. Video Modes

3.3.2 Video Memory Interface

integrity and maximum CPU/co-processor drawing performance.

3.3.3 Dual Video

The BIOS supports single- and dual-video modes. The dual-video mode is enabled by default. when an add-in video card is detected. Setup utility provides options to configure the feature as follows.

3.4 SAS Controller

Serial Attached SCSI Standard, version 1.0. The controller also supports SAS 1.1 features. Flash ROM and NVSRAM devices.

3.4.1 SAS RAID Support

drives with expander backplane.

3.4.2 SAS / SATA Connector Sharing

functionality. For SATA server boards, all six SATA connectors are used for SATA functionality.

3.5 Network Interface Controller (NIC)

10-Mbps when off. The table below provides an overview of the LEDs. Table 7. NIC Status LED

Intel® Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Revision 1.4 Intel order number: D41763-005

3.5.1 Intel ® I/O Acceleration Technolgy

Intel® I/O Acceleration Technology moves network data more efficiently through Dual-Core Intel® Xeon® processor 5000 sequence-based servers for improved application responsiveness across diverse operating systems and virtualized environments. Intel® I/OAT improves network application responsiveness by unleashing the power of Dual-Core Intel® Xeon® processors 5000 sequence through more efficient network data movement and reduced system overhead. Intel multi-port network adapters with Intel® I/OAT provide high-performance I/O for server consolidation and virtualization via stateless network acceleration that seamlessly scales across multiple ports and virtual machines. Intel ® I/OAT provides safe and flexible network acceleration through tight integration into popular operating systems & virtual machine monitors, avoiding the support risks of 3rd-party network stacks and preserving existing network requirements such as teaming and failover.

3.5.2 MAC Address Definition

Each Intel® Server Board S5000PSL / S5000XSL has four MAC addresses assigned to it at the Intel factory. During the manufacturing process, each server board will have a white MAC address sticker placed on the board. The sticker will display the MAC address in both bar code and alpha numeric formats. The printed MAC address is assigned to NIC 1 on the server board. NIC 2 is assigned the NIC 1 MAC address + 1. Two additional MAC addresses are assigned to the Baseboard Management Controller (BMC) embedded in the ESB-2. These MAC addresses are used by the BMC’s embedded network stack to enable IPMI remote management over LAN. BMC LAN Channel 1 is assigned the NIC1 MAC address + 2, and BMC LAN Channel 2 is assigned the NIC2 MAC address + 2

3.6 Super I/O

Legacy I/O support is provided by using a National Semiconductor* PC87427 Super I/O device. This chip contains all of the necessary circuitry to support the following functions: ƒ GPIOs ƒ Two serial ports ƒ Keyboard and mouse support ƒ Wake up control ƒ System health support

3.6.1 Serial Ports

follows the standard RS232 pin-out as defined in the following table. Table 8. Serial B Header Pin-out

1 DCD

2 DSR

4 RTS

6 CTS

7 DTR

9 GND

3.6.2 Floppy Disk Controller

recognizes USB floppy devices.

3.6.3 Keyboard and Mouse Support

3.6.4 Wake-up Control

3.6.5 System Health Support

7 for the location of the LEDs on the server board. for the system fans and monitors server board and front panel temperature.

Intel® Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Revision 1.4 Intel order number: D41763-005 4. Platform Management The platform management sub-system is based on the integrated Baseboard Management Controller features of the ESB2-E. The on-board platform management sub-system consists of communication buses, sensors, system BIOS, and server management firmware. The following diagram provides an overview of the Server Management Bus (SMBUS) architecture used on this server board. See Appendix B for on-board sensor data. For more detailed platform management information, see the Intel® S5000 Server Board Family Datasheet.

Figure 16. SMBUS Block Diagram

1. Connector / Header Locations and Pin-outs

5.1 Board Connector Information

Table 9. Board Connector Matrix

2 JA6A1, JA6A2 External LAN

1 J7A1 External DSub /

4 J1D2 (Password Clear), J1D1 (CMOS Clear), J1C3

5.2 Power Connectors

The following tables define the connector pin-outs. Table 10. Power Connector Pin-out (J9B5)

3 GND Black 15 GND Black

5 GND Black 17 GND Black

7 GND Black 19 GND Black

8 PWR_OK Gray 20 RSVD_(-5 V) White

Table 11. 12 V Power Connector Pin-out (J3J2)

1 GND Black

2 GND Black

3 GND Black

4 GND Black

Table 12. Power Supply Signal Connector Pin-out (J9D1)

1 SMB_CLK_ESB_FP_PWR_R Orange

2 SMB_DAT_ESB_FP_PWR_R Black

3 SMB_ALRT_3_ESB_R Red

Table 13. P12V4 Power Connector Pin-out (J5A2)

5.3 System Management Headers

5.3.1 Intel ® Remote Management Module (Intel® RMM) Connector

Edition (Product Code AXXIMMADV). Table 14. RMM Connector Pin-out (J5B1)

1 Reserved - NC 2 GND

3 ESB_PLT_RST_G1_N 4 Reserved - NC

5 GND 6 Reserved - NC

7 Reserved - NC 8 GND

9 Reserved - NC 10 GND

11 GND 12 Reserved - NC

13 GND 14 IRQ_SERIAL_R

15 USB_ESB_P7P 16 GND

17 USB_ESB_P7N 18 GND

19 GND 20 Reserved - NC

21 P3V3 22 Reserved - NC

23 LPC_LAD<0> 24 GND

25 LPC_LAD<1> 26 LPC_FRAME_N

27 P3V3 28 LPC_LAD<2>

29 LPC_LCLK 30 LPC_LAD<3>

31 P3V3 32 P3V3

33 SMB_1_3V3SB_MS_DAT 34 SMB_IPMB_3V3SB_DAT

35 SMB_1_3V3SB_SL_DAT 36 SMB_IPMB_3V3SB_CLK

37 SMB_1_3V3SB_MS_CLK 38 SMB_0_3V3SB_MS_CLK

39 SMB_1_3V3SB_INT 40 SMB_0_3V3SB_INT

41 P3V3_AUX 42 SMB_0_3V3SB_MS_DAT

43 SPB_IMM_DSR_N 44 SMB_0_3V3SB_SL_DAT

45 SPB_IMM_RTS_N 46 P3V3_AUX

47 SPB_IMM_CTS_N 48 FM_IMM_PRESENT_N

49 SPB_IMM_DCD_N 50 SPB_IMM_DTR_N

51 SPB_RI_N 52 SPB_IMM_SIN

53 SPB_IMM_SOUT 54 P3V3_AUX

55 P3V3_AUX 56 V_LCDDATA7

57 V_LCDCNTL3 56 V_LCDDATA6

59 P3V3_AUX 60 V_LCDDATA5

61 Reserved - NC 62 V_LCDDATA4

63 Reserved - NC 64 V_LCDDATA3

65 GND 66 V_LCDCNTL1

67 V_LCDCNTL0 68 GND

69 Reserved - NC 70 V_LCDDATA15

71 GND 72 V_LCDDATA714

73 V_LCDDATA23 74 V_LCDDATA13

75 V_LCDDATA22 76 V_LCDDATA12

77 V_LCDDATA21 78 V_LCDDATA11

79 V_LCDDATA20 80 GND

81 V_LCDDATA19 82 V_LCDCNTL2

83 GND 84 V_DVO_DDC_SDA

85 FM_MAN_LAN_TYPE1 86 V_DVO_DDC_SCL

87 FM_MAN_LAN_TYPE2 88 RST_PS_PWRGD

89 Reserved - NC 90 Reserved - NC

91 Reserved - NC 92 Reserved - NC

93 MII_MDC_RMII_SPARE 94 Reserved - NC

95 MII_COL_RMIIB_RXER 96 GND

97 GND 98 MII_CRS_RMIIB_CRS

99 MII_TXER_RMIIB_TXEN 100 MII_TXCLK_RMIIB_RXCLK

101 MII_MDIO_RMIIB_PRESENT 102 GND

103 GND 104 MII_TXD3_RMIIB_TXD1

105 MII_RXD3_RMIIB_RXD1 106 MII_TXD2_RMIIB_TXD0

107 MII_RXD2_RMIIB_RXD0 108 GND

109 GND 110 MII_TXD1_RMIIA_TXD1

111 MII_RXD1_RMIIA_RXD1 112 MII_TXD0_RMIIA_TXD0

113 MII_RXD0_RMIIA_RXD0 114 GND

115 GND 116 MII_TXEN_RMIIA_TXEN

117 MII_RXCLK 118 MII_RXER_RMIIA_TXER

119 MII_RXDV_RMIIA_CRS 120 GND

5.3.2 LCP / AUX IPMB Header

Table 15. LPC / AUX IPMB Header Pin-out (J2J1)

1 SMB_IPMB_5VSB_DAT BMC IMB 5V standby data line

2 GND Ground

3 SMB_IPMB_5VSB_CLK BMC IMB 5V standby clock line

4 P5V_STBY +5 V standby power

5.3.3 IPMB Header

Table 16. IPMB Header Pin-out (J4J1)

5.3.4 HSBP Header

Table 17. HSBP Header Pin-out (J1J7, J1J2)

1 SMB_IPMB_5V_DAT BMC IMB 5V Data Line

3 SMB_IPMB_5V_CLK BMC IMB 5V Clock Line

4 GND – HSBP_A

5.3.5 SGPIO Header

Table 18. SGPIO Header Pin-out (J2H1, J1J5)

1 SGPIO_CLOCK SGPIO Clock Signal

2 SGPIO_LOAD SGPIO Load Signal

3 SGPIO_DATAOUT SGPIO Data Out

4 SGPIO_DATAIN SGPIO Data In

5.3.6 SES I 2C

Table 19. SES I2C Header Pin-out (J1J3)

1 SMB_SAS_3V3_DAT BMC SAS 3V Data Line

3 SMB_SAS_3V3_CLK BMC SAS 3V Clock Line

5.3.7 HDD Activity LED Header

Table 20. HDD Activity LED Header Pin-out (J2J3)

1 LED_SCSI_CONN_N HDD Activity LED Input

5.4 Front Panel Connector

third-party chassis. The following table provides the pin-out for this connector. Table 21. Front Panel SSI Standard 24-pin Connector Pin-out (J1E4)

1 P3V3_STBY 2 P3V3_STBY

3 Key 4 P5V_STBY

7 P3V3 8 FP_LED_STATUS_GREEN_N

9 LED_HDD_ACTIVITY_N 10 FP_LED_STATUS_A MBER_N

11 FP_PWR_BTN_N 12 NIC1_ACT_LED_N

13 GND 14 NIC1_LINK_LED_N

15 BMC_RST_BTN_N 16 SMB_SENSOR_3V3STB_DATA

17 GND 18 SMB_SENSOR_3V3STB_CLK

19 FP_ID_BTN_N 20 FP_CHASSIS_INTRU

21 FM_SIO_TEMP_SENSOR 22 NIC2_ACT_LED_N

23 FP_NMI_BTN_N 24 NIC2_LINK_LED_N

5.5 I/O Connectors

5.5.1 VGA Connector

stacked video / serial port A connector. Table 22. VGA Connector Pin-out (J7A1)

1 V_IO_R_CONN Red (analog color signal R)

2 V_IO_G_CONN Green (analog color signal G)

3 V_IO_B_CONN Blue (analog color signal B)

4 TP_VID_CONN_B4 No connection

5 GND Ground

6 GND Ground

7 GND Ground

8 GND Ground

9 TP_VID_CONN_B9 No connection

10 GND Ground

11 TP_VID_CONN_B11 No connection

12 V_IO_DDCDAT DDCDAT

13 V_IO_HSYNC_CONN HSYNC (horizontal sync)

14 V_IO_VSYNC_CONN VSYNC (vertical sync)

15 V_IO_DDCCLK DDCCLK

5.5.2 NIC Connectors

Table 23. RJ-45 10/100/1000 NIC Connector Pin-out (JA6A1, JA6A2)

1 GND

2 P1V8_NIC

3 NIC_A_MDI3P

4 NIC_A_MDI3N

5 NIC_A_MDI2P

6 NIC_A_MDI2N

7 NIC_A_MDI1P

8 NIC_A_MDI1N

9 NIC_A_MDI0P

10 NIC_A_MDI0N

14 NIC_LINK_LED_N

15 GND

16 GND

5.5.3 IDE Connector

defined in the following table. Table 24. IDE 40-pin Connector Pin-out (J2J2)

1 ESB_PLT_RST_IDE_N 2 GND

3 RIDE_DD_7 4 RIDE_DD_8

5 RIDE_DD_6 6 RIDE_DD_9

7 RIDE_DD_5 8 RIDE_DD_10

9 RIDE_DD_4 10 RIDE_DD_11

11 RIDE_DD_3 12 RIDE_DD_12

13 RIDE_DD_2 14 RIDE_DD_13

15 RIDE_DD_1 16 RIDE_DD_14

17 RIDE_DD_0 18 RIDE_DD_15

19 GND 20 KEY

21 RIDE_DDREQ 22 GND

23 RIDE_DIOW_N 24 GND

25 RIDE_DIOR_N 26 GND

27 RIDE_PIORDY 28 GND

29 RIDE_DDACK_N 30 GND

31 IRQ_IDE 32 TP_PIDE_32

33 RIDE_DA1 34 IDE_PRI_CBLSNS

35 RIDE_DA0 36 RIDE_DA2

37 RIDE_DCS1_N 38 RIDE_DCS3_N

39 LED_IDE_N 40 GND

5.5.4 Intel ® Remote Management Module NIC Connector

out of the Intel® RMM NIC module connector. Table 25. 40-pin RMM NIC Module Connector Pin-out (J3B2)

1 FM_MAN_LAN_TYPE2 2 FM_MAN_LAN_TYPE1

3 P3V3_AUX 4 MII_MDIO_RMIIB_PRESENT

5 P3V3_AUX 6 MII_MDC_RMII_SPARE

7 GND 8 MII_RXD3_RMIIB_RXD1

9 GND 10 MII_RXD2_RMIIB_RXD0

11 GND 12 MII_RXD1_RMIIA_RXD1

13 GND 14 MII_RXD0_RMIIA_RXD0

15 GND 16 MII_RXDV_RMIIA_CRS

17 GND 18 MII_RXCLK

19 GND 20 MII_RXER_RMIIA_RXER

21 GND 22 KEY

23 GND 24 MII_TXCLK_RMIIB_RXCLK

25 GND 26 MII_TXEN_RMIIA_TXEN

27 GND 28 MII_TXD0_RMIIA_TXD0

29 GND 30 MII_TXD1_RMIIA_TXD1

31 GND 32 MII_TXD2_RMIIB_TXD0

33 GND 34 MII_TXD3_RMIIB_TXD1

Design and Environmental Specifications Intel® Server Boards S5000PSL and S5000XSL TPS Revision 1.4 Intel order number: D41763-005 Pin Signal Name Pin Signal Name

35 P3V3_AUX 36 MII_COL_RMIIB_RXER

37 P3V3_AUX 38 MII_CRS_RMIIB_CRS

39 P3V3_AUX 40 MII_TXER_RMIIB_TXEN

5.5.5 SATA / SAS Connectors

The pin configuration for each connector is identical and is defined in the following table. Table 26. SATA / SAS Connector Pin-out (J1J1, J1H2, J1H1, J1G2, J1G1, J1F2)

1 GND Ground

2 SATA/SAS_TX_P_C Positive side of transmit differential pair

3 SATA/SAS_TX_N_C Negative side of transmit differential pair

4 GND Ground

5 SATA/SAS_RX_N_C Negative side of receive differential pair

6 SATA/SAS_RX_P_C Positive side of receive differential pair

5.5.6 Serial Port Connectors

header (J1B1). The following tables define the pin-outs. Table 27. External DB9 Serial A Port Pin-out (J7A1)

1 SPA_DCD DCD (carrier detect)

2 SPA_SIN_L RXD (receive data)

3 SPA_SOUT_N TXD (Transmit data)

4 SPA_DTR DTR (Data terminal ready)

6 SPA_DSR DSR (data set ready)

7 SPA_RTS RTS (request to send)

8 SPA_CTS CTS (clear to send)

9 SPA_RI RI (Ring Indicate)

Table 28. Internal 9-pin Serial B Header Pin-out (J1B1)

1 SPB_DCD DCD (carrier detect)

2 SPB_DSR DSR (data set ready)

3 SPB_SIN_L RXD (receive data)

4 SPB_RTS RTS (request to send)

5 SPB_SOUT_N TXD (Transmit data)

6 SPB_CTS CTS (clear to send)

7 SPB_DTR DTR (Data terminal ready)

8 SPB_RI RI (Ring indicate)

9 SPB_EN_N Enable

5.5.7 Keyboard and Mouse Connector

a mouse or keyboard. The following table details the pin-out of the PS/2 connectors. Table 29. Stacked PS/2 Keyboard and Mouse Port Pin-out (J9A1)

1 KB_DATA_F Keyboard data

2 TP_PS2_2 Test point – keyboard

3 GND Ground

4 P5V_KB_F Keyboard / mouse power

5 KB_CLK_F Keyboard clock

6 TP_PS2_6 Test point – keyboard / mouse

7 MS_DAT_F Mouse data

8 TP_PS2_8 Test point – keyboard / mouse

9 GND Ground

10 P5V_KB_F Keyboard / mouse power

11 MS_CLK_F Mouse clock

12 TP_PS2_12 Test point – keyboard / mouse

13 GND Ground

14 GND Ground

15 GND Ground

16 GND Ground

17 GND Ground

5.5.8 USB Connector

the back edge of the server board. Table 30. External USB Connector Pin-out (JA6A1, JA6A2)

1 USB_OC USB_PWR

2 USB_PN DATAL0 (Differential data line paired with DATAH0)

3 USB_PP DATAH0 (Differential data line paired with DATAL0)

USB ports. The pin-out of the connector is detailed in the following table. Table 31. Internal USB Connector Pin-out (J3J1)

1 USB2_VBUS5 USB power (port 5)

2 USB2_VBUS4 USB power (port 4)

3 USB_ESB_P5N_CONN USB port 5 negative signal

4 USB_ESB_P4N_CONN USB port 4 negative signal

5 USB_ESB_P5P_CONN USB port 5 positive signal

6 USB_ESB_P4P_CONN USB port 4 positive signal

7 Ground

8 Ground

9 Key No pin

10 TP_USB_ESB_NC Test point

5.6 Fan Headers

identical and is defined in the following tables. Table 32. SSI 4-pin Fan Header Pin-out (J9J1, J5J1, J9B3, J9B4)

1 Ground GND Ground is the power supply ground

3 Fan Tach In FAN_TACH signal is connected to the BMC to monitor the fan speed

4 Fan PWM Out FAN_PWM signal to control fan speed

Table 33. SSI 6-pin Fan Header Pin-out (J3H1, J3H2, J3H3, J3H4)

5 Fan Presence In Indicates the fan is present

6 Fan Fault LED Out Lights the fan fault LED

Intel® Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Revision 1.4 Intel order number: D41763-005 components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation can not be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits.

recover specific features of the server board. Figure 17. Jumper Blocks (J1C3, J1D1, J1D2, J1E32) Table 34. Server Board Jumpers (J1C3, J1D1, J1D2, J1E3) after removing AC power. These pins should not be jumpered for normal operation.

Intel® Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Revision 1.4 Intel order number: D41763-005

6.1 CMOS Clear and Password Reset Usage Procedure

The CMOS Clear (J1D1) and Password Reset (J1D2) recovery features are designed such that the desired operation can be achieved with minimal system down time. The usage procedure for these two features has changed from previous generation Intel server boards. The following procedure outlines the new usage model.

6.1.1 Clearing the CMOS

1. Power down server. Do not unplug the power cord. 2. Open the server chassis. For instructions, see your server chassis documentation. 3. Move jumper (J1D1) from the default operating position, covering pins 1 and 2, to the reset / clear position, covering pins 2 and 3. 4. Remove AC power. 5. Wait 5 seconds. 6. Move the jumper back to default position, covering pins 1 and 2. 7. Close the server chassis. 8. Power up the server. The CMOS is now cleared and can be reset by going into BIOS setup. Note: Removing AC Power before performing the CMOS Clear operation will cause the system to automatically power up and immediately power down, after the procedure is followed and AC power is re-applied. If this happens, remove the AC power cord again, wait 30 seconds, and re- install the AC power cord. Power up system and proceed to the <F2> BIOS Setup Utility to reset the desired settings.

6.1.2 Clearing the Password

1. Power down server. Do not unplug the power cord. 2. Open the chassis. For instructions, see your server chassis documentation. 3. Move jumper (J1D20 from the default operating position, covering pins 1 and 2, to the password clear position, covering pins 2 and 3. 4. Close the server chassis. 5. Power up the server, wait 10 seconds or POST completes. 6. Power down the server. 7. Open the chassis and move the jumper back to default position, covering pins 1 and 2. 8. Close the server chassis. 9. Power up the server. The password is now cleared and can be reset by going into BIOS setup.

Design and Environmental Specifications Intel® Server Boards S5000PSL and S5000XSL TPS Revision 1.4 Intel order number: D41763-005

6.2 BMC Force Update Procedure

When performing a standard BMC firmware update procedure, the update utility places the BMC into an update mode, allowing the firmware to load safely onto the flash device. In the unlikely event that the BMC firmware update process fails due to the BMC not being in the proper update state, the server board provides a BMC Force Update jumper (J1E3) which will force the BMC into the proper update state. The following procedure should be following in the event the standard BMC firmware update process fails. 1. Power down and remove the AC power cord. 2. Open the server chassis. See your serv er chassis documentation for instructions. 3. Move jumper from the default operating position, covering pins1 and 2, to the enabled position, covering pins 2 and 3. 4. Close the server chassis. 5. Reconnect the AC cord and power up the server. 6. Perform the BMC firmware update procedure as documented in the README.TXT file that is included in the given BMC firmware update package. After successful completion of the firmware update process, the firmware update utility may generate an error stating that the BMC is still in update mode. 7. Power down and remove the AC power cord. 8. Open the server chassis. 9. Move jumper from the enabled position, covering pins 2 and 3 to the disabled position, covering pins 1 and 2. 10. Close the server chassis. 11. Reconnect the AC cord and power up the server. Note: Normal BMC functionality is disabled with the Force BMC Update jumper is set to the enabled position. The server should never be run with the BMC Force Update jumper set in this position. This jumper setting should only be used when the standard firmware update process fails. This jumper should remain in the default / disabled position when the server is running normally.

6.3 BIOS Select Jumper

The jumper block at J1C3, located at the left of PCI-X* slot 1, is used to select which BIOS image the system will boot to. Pin 1 on the jumper is identified with a ‘▼’. This jumper should only be moved if you want to force the BIOS to boot to the secondary bank, which may hold a different version of BIOS. The rolling BIOS feature of the server board will automatically alternate the boot BIOS to the secondary bank if the BIOS image in the primary bank is corrupted and cannot boot.

1. Intel ® Light Guided Diagnostics

® S5000 Server Board Family Datasheet. and optional RMM connector with Intel RMM installed. voltage is supplied to the server board by the power supply. Figure 18. 5 Volt Standby Status LED Location

7.2 Fan Fault LEDs

are located next to each rear system fan header are shown in the following figure. Figure 19. Fan Fault LED Locations

7.3 System ID LED and System Status LED

Figure 20. System ID LED and System Status LED Locations The blue System ID LED can be illuminated using either of two mechanisms. solid blue color, until the button is pressed again. Chassis Identify value is issued to turn it off.

Table 35. System Status LED Green Solid on System OK System booted and ready.

• Unable to use all of the installed memory (more than one DIMM installed).
• Correctable errors over a threshold of 10 and migrating to a spare DIMM (memory sparing). This indicates that the user no longer has spared DIMMs indicating a redundancy lost condition. Corresponding DIMM LED should light up.
• In mirrored configuration, when memory mirroring takes place and system loses memory redundancy. This is not covered by (2).
• Redundancy loss such as power-supply or fan. This does not apply to non-redundant sub-systems.
• PCI-e link errors
• CPU failure / disabled – if there are two processors and one of them fails
• Fan alarm – Fan failure. Number of operational fans should be more than minimum number needed to cool the system
• Non-critical threshold cr ossed – Temperature and voltage Amber Blink Non-critical Non-fatal alarm – system is likely to fail
• Critical voltage threshold crossed
• VRD hot asserted
• Minimum number of fans to c ool the system not present or failed
• In non-sparing and non-mirroring mode if the threshold of ten correctable errors is crossed within the window Amber Solid on Critical, non- recoverable Fatal alarm – system has failed or shutdown
• DIMM failure when there is one DIMM present, no good memory present
• Run-time memory uncorrectable error in non-redundant mode
• IERR signal asserted
• Processor 1 missing
• Temperature (CPU ThermTrip, memory TempHi, critical threshold crossed)
• No power good – power fault
• Processor configuration erro r (for instance, processor stepping mismatch)

7.3.1 System Status LE D – BMC Initialization

Intel® Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Revision 1.4 Intel order number: D41763-005 BMC initialization has completed, the status LED will stop blinking and the power button functionality is restored and can be used to turn on the server.

7.4 DIMM Fault LEDs

towards the rear of the server board next to each DIMM connector. Figure 21. DIMM Fault LED Locations

7.5 Processor Fault LEDs

Figure 22. Processor Fault LED Locations

7.6 Post Code Diagnostic LEDs

of all supported POST codes. Figure 23. POST Code Diagnostic LED Location

1. Design and Environmental Specifications

8.1 Server Boards S5000PSL and S5000XSL Design Specifications

extended periods may affect system reliability. Table 36. Server Board Design Specifications

1 Chassis design must provide proper airflow to avoid exceeding the Dual-Core Intel® Xeon®

processor 5000 sequence maximum case temperature. when used outside any of their published operating or non-operating limits.

8.2 Board-level Calculated MTBF

power distribution implemented on these server boards. Figure 24. Power Distribution Block Diagram

8.3 Server Board Power Requirements

8.3.1 Processor Power Support

core Intel® Xeon® processor 5000 sequence family. Table 37. Intel® Xeon® Processor Dual Processor TDP Guidelines

130 W 70º C 150 A

supersede these, and should be used.

8.4 Power Supply Output Requirements

power supply requirements Intel used to develop a power supply for its 5U server system. The combined power of all outputs shall not exceed the rated output power of the power supply. Table 38. 550 W Load Ratings

1. Maximum continuous total DC out put power should not exceed 550 W.
2. Maximum continuous combined load on +3.3 VDC and +5 VDC outputs shall not exceed 140W.
3. Maximum peak total DC output power should not exceed 660W.
4. Peak power and current loading shall be supported for a minimum of 12 seconds.
5. Maximum combined current for the 12 V outputs shall be 41 A.
6. Peak current for the combined 12 V outputs shall be 50A.

Design and Environmental Specifications Intel® Server Boards S5000PSL and S5000XSL TPS Revision 1.4 Intel order number: D41763-005

8.4.1 Grounding

The grounds of the pins of the power supply output connector provide the power return path. The output connector ground pins is connected to safety ground (power supply enclosure). This grounding should is designed to ensure passing the maximum allowed common mode noise levels.

8.4.2 Standby Outputs

The 5 VSB output shall be present when an AC input greater than the power supply turn on voltage is applied.

8.4.3 Remote Sense

The power supply has remote sense return to regulate out ground drops for all output voltages: +3.3 V, +5 V, +12 V1, +12 V2, +12 V3, -12 V, and 5 VSB. The power supply uses remote sense (3.3 VS) to regulate out drops in the system for the +3.3 V output. The +5 V, +12 V1, +12 V2, +12 V3, –12 V and 5 VSB outputs only use remote sense referenced to the remote sense return signal. The remote sense input impedance to the power supply must be greater than 200 Ω on 3.3 VS and 5 VS. This is the value of the resistor connecting the remote sense to the output voltage internal to the power supply. Remote sense must be able to regulate out a minimum of a 200 mV drop on the +3.3 V output. The remote sense return must be able to regulate out a minimum of a 200 mV drop in the power ground return. The current in any remote sense line shall be less than 5 mA to prevent voltage sensing errors. The power supply must operate within specification over the full range of voltage drops from the power supply’s output connector to the remote sense points.

8.4.4 Voltage Regulation

steady state and dynamic loading conditions. These limits include the peak-peak ripple / noise. Table 39. Voltage Regulation Limits

1. Maximum continuous total output power should not exceed 670 W.
2. Maximum continuous load on the comb ined 12 V output shall not exceed 48 A.
3. Peak load on the combined 12 V output shall not exceed 52 A.
4. Peak total DC output pow er should not exceed 730 W.

8.4.5 Dynamic Loading

Table 40. Transient Load Requirements

1. Step loads on each 12V output may happen simultaneously.

8.4.6 Capacitive Loading

Table 41. Capacitive Loading Conditions

1. Maximum continuous total output power should not exceed 670 W.
2. Maximum continuous load on the comb ined 12 V output shall not exceed 48 A.
3. Peak load on the combined 12 V output shall not exceed 52 A.
4. Peak total DC output pow er should not exceed 730 W.

8.4.7 Ripple / Noise

The maximum allowed ripple/noise output of the power supply is defined in the following table. Table 42. Ripple and Noise

1. Maximum continuous total output power should not exceed 670 W.
2. Maximum continuous load on the comb ined 12 V output shall not exceed 48 A.
3. Peak load on the combined 12 V output shall not exceed 52 A.
4. Peak total DC output pow er should not exceed 730 W.

8.4.8 Timing Requirements

voltage shall fall out of regulation within 400 msec (Tvout_off) of each other during turn off.

Table 43. Output Voltage Timing

1. The 5VSB output voltage rise time is from 1.0 ms to 25 ms

Figure 25. Output Voltage Timing

Table 44. Turn On/Off Timing Figure 26. Turn On/Off Timing (Power Supply Signals)

Intel® Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Revision 1.4 Intel order number: D41763-005

8.4.9 Residual Voltage Immunity in Standby Mode

The power supply should be immune to any residual voltage placed on its outputs (typically, a leakage voltage through the system from standby output) up to 500 mV. There shall be no additional heat generated, nor stressing of any internal components with this voltage applied to any individual output, and all outputs simultaneously. It also should not trip the power supply protection circuits during turn on. Residual voltage at the power supply outputs for a no load condition shall not exceed 100 mV when AC voltage is applied and the PSON# signal is de-asserted.

Design and Environmental Specifications Intel® Server Boards S5000PSL and S5000XSL TPS Revision 1.4 Intel order number: D41763-005 9. Regulatory and Certification Information To help ensure EMC compliance with your local regional rules and regulations, before computer integration, make sure that the chassis, power supply, and other modules have passed EMC testing using a server board with a microprocessor from the same family (or higher) and operating at the same (or higher) speed as the microprocessor used on this server board. The final configuration of your end system product may require additional EMC compliance testing. For more information please contact your local Intel Representative. This is an FCC Class A device. Integration of it into a Class B chassis does not result in a Class B device.

9.1 Product Regulatory Compliance

Intended Application – This product was evaluated as Information Technology Equipment (ITE), which may be installed in offices, schools, computer rooms, and similar commercial type locations. The suitability of this product for other product categories and environments (such as: medical, industrial, telecommunications, NEBS, residential, alarm systems, test equipment, etc.), other than an ITE application, may require further evaluation.

9.1.1 Product Safety Compliance

ƒ UL60950 – CSA 60950(USA / Canada) ƒ EN60950 (Europe) ƒ IEC60950 (International) ƒ CB Certificate & Report, IEC60950 (report to include all country national deviations) ƒ GOST R 50377-92 – Listed on one System License (Russia) ƒ Belarus License – Listed on System License (Belarus) ƒ CE - Low Voltage Directive 73/23/EEE (Europe) ƒ IRAM Certification (Argentina)

9.1.2 Product EMC Compliance – Class A Compliance

ƒ FCC /ICES-003 - Emissions (USA/Canada) Verification ƒ CISPR 22 – Emissions (International) ƒ EN55022 - Emissions (Europe) ƒ EN55024 - Immunity (Europe) ƒ CE – EMC Directive 89/336/EEC (Europe) ƒ VCCI Emissions (Japan) ƒ AS/NZS 3548 Emissions (Australia / New Zealand) ƒ BSMI CNS13438 Emissions (Taiwan) ƒ GOST R 29216-91 Emissions - Listed on one System License (Russia) ƒ GOST R 50628-95 Immunity –Listed on one System License (Russia) ƒ Belarus License – Listed on one System License (Belarus)

Intel® Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Revision 1.4 ƒ RRL MIC Notice No. 1997-41 (EMC) & 1997-42 (EMI) (Korea)

9.1.3 Certifications / Regi strations / Declarations

ƒ UL Certification or NRTL (US/Canada) ƒ CB Certifications (International) ƒ CE Declaration of Conformity (CENELEC Europe) ƒ FCC/ICES-003 Class A Attestation (USA/Canada) ƒ C-Tick Declaration of Conformity (Australia) ƒ MED Declaration of Conformity (New Zealand) ƒ BSMI Certification (Taiwan) ƒ RRL Certification (Korea) ƒ Ecology Declaration (International)

9.2 Product Regulatory Compliance Markings

The Intel® Server Board bears the following regulatory marks. Regulatory Compliance Region Marking UL Mark USA/Canada CE Mark Europe EMC Marking (Class A) Canada CANADA ICES-003 CLASS A CANADA NMB-003 CLASSE A Intel order number: D41763-005 BSMI Marking (Class A) Taiwan C-tick Marking Australia / New Zealand RRL MIC Mark Korea Country of Origin Exporting Requirements Made in xxxxx (Provided by label, not silkscreen) Model Designation Regulatory Identification Examples (Server Board S5000PSL) for boxed type boards; or Board PB number for non-boxed boards (typically high-end boards)

Design and Environmental Specifications Intel® Server Boards S5000PSL and S5000XSL TPS Revision 1.4 Intel order number: D41763-005

9.3 Electromagnetic Compatibility Notices

9.3.1 FCC Verification Statement (USA)

This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Intel Corporation 5200 N.E. Elam Young Parkway Hillsboro, OR 97124-6497 Phone: 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: ƒ Reorient or relocate the receiving antenna. ƒ Increase the separation between the equipment and the receiver. ƒ Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. ƒ Consult the dealer or an experienced radio/TV technician for help. Any changes or modifications not expressly approved by the grantee of this device could void the user’s authority to operate the equipment. The customer is responsible for ensuring compliance of the modified product. All cables used to connect to peripherals must be shielded and grounded. Operation with cables, connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception.

9.3.2 ICES-003 (Canada)

Cet appareil numérique respecte les limites bruits radioélectriques applicables aux appareils numériques de Classe B prescrites dans la norme sur le matériel brouilleur: “Appareils Numériques”, NMB-003 édictée par le Ministre Canadian des Communications. English translation of the notice above: This digital apparatus does not exceed the Class B limits for radio noise emissions from digital apparatus set out in the interference-causing equipment standard entitled “Digital Apparatus,” ICES-003 of the Canadian Department of Communications.

Intel® Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications Revision 1.4

9.3.3 Europe (CE Declaration of Conformity)

This product has been tested in accordance too, and complies with the Low Voltage Directive (73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark to illustrate its compliance.

9.3.4 VCCI (Japan)

English translation of the notice above: This is a Class B product based on the standard of the Voluntary Control Council for Interference (VCCI) from Information Technology Equipment. If this is used near a radio or television receiver in a domestic environment, it may cause radio interference. Install and use the equipment according to the instruction manual.

9.3.5 BSMI (Taiwan)

The BSMI Certification Marking and EMC warning is located on the outside rear area of the product.

9.3.6 RRL (Korea)

Following is the RRL certification information for Korea. English translation of the notice above: 1. Type of Equipment (Model Name): On License and Product 2. Certification No.: On RRL certificate. Obta in certificate from local Intel representative 3. Name of Certification Recipient: Intel Corporation 4. Date of Manufacturer: Refer to date code on product 5. Manufacturer/Nation: Intel Corporation/Re fer to country of origin marked on product Intel order number: D41763-005

Design and Environmental Specifications Intel® Server Boards S5000PSL and S5000XSL TPS Revision 1.4 Intel order number: D41763-005

9.3.7 CNCA (CCC-China)

The CCC Certification Marking and EMC warning is located on the outside rear area of the product. A

9.4 Restriction of Hazardous Substances (RoHS)

Intel has a system in place to restrict the use of banned substances in accordance with the European Directive 2002/95/EC. Compliance is based on declaration that materials banned in the RoHS Directive are either (1) below all applicable substance threshold limits or (2) an approved/pending RoHS exemption applies. Note: RoHS implementation details are not fully defined and may change. Threshold limits and banned substances are noted below. ƒ Quantity limit of 0.1% by mass (1000 PPM) for: - Lead - Mercury - Hexavalent Chromium - Polybrominated Biphenyls Diphenyl Ethers (PBDE) ƒ Quantity limit of 0.01% by mass (100 PPM) for: - Cadmium

Intel® Server Boards S5000PSL and S5000XSL TPS Appendix A: Integration and Usage Tips Appendix A: Integration and Usage Tips ƒ When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-volt standby is still present even though the server board is powered off. ƒ Processors must be installed in order. CPU 1 is located near the edge of the server board and must be populated to operate the board. ƒ On the back edge of the server board are four diagnostic LEDs that display a sequence of red, green, or amber POST codes during the boot process. If the server board hangs during POST, the LEDs will display the last POST event run before the hang. ƒ Only Fully Buffered DIMMs (FBDIMMs) are supported on this server board. For a list of supported memory for this server board, see the Intel® S5000PSL, S5000XSL, S5000XVN, and Server System SC5400RA Tested Memory List. ƒ For a list of Intel supported operating systems, add-in cards, and peripherals for this server board, see the Intel ® S5000PSL, S5000XSL, S5000XVN, and Server System SC5400RA Tested Hardware and OS List. ƒ For a list of Intel supported hard disk drives for this workstation board, see the Intel® Server Board/Systems Tested Hard Drive List. ƒ Only Multi-Core Intel® Xeon® processors with system bus speeds of 667 (Intel® Xeon® processors 5000 series only), 1066, or 1333 MHz are supported on this server board. Previous generation Intel ® Xeon® processors are not supported. ƒ For the best performance, the number of FBDIMMs installed should be balanced across both memory branches. For example: a four-DIMM configuration will perform better than a two DIMM configuration. In a four-DIMM configuration, FBDIMMs should be installed in DIMM sockets A1, B1, C1, and D1. An eight-DIMM configuration will perform better then a six DIMM configuration. ƒ The Intel® RMM connector is not compatible with the Intel® Server Management Module Professional Edition (Product Code AXXIMMPRO) or with the Intel® Server Management Module Advanced Edition (Product Code AXXIMMADV) ƒ Removing AC power before performing the CMOS Clear operation will cause the system to automatically power up and immediately power down after the CMOS Clear procedure is followed and AC power is re-applied. If this happens, remove the AC power cord, wait 30 seconds, and then re-connect the AC power cord. Power up the system and proceed to the <F2> BIOS Setup Utility to reset the desired settings. ƒ Normal BMC functionality is disabled with the force BMC update jumper set to the “enabled” position (pins 2-3). The server should never be run with the BMC force update jumper set in this position and should only be used when the standard firmware update process fails. This jumper should remain in the default (disabled) position (pins 1-2) when the server is running normally. ƒ When performing a BIOS update procedure, the BIOS select jumper must be set to its default position (pins 2-3). Revision 1.4 Intel order number: D41763-005

Appendix B: BMC Sensor Tables Intel® Server Boards S5000PSL and S5000XSL TPS Appendix B: BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0, for sensor and event/reading-type table information. ƒ Sensor Type The Sensor Type is the values enumerated in the Sensor Type Codes table in the IPMI specification. The Sensor Type provides the context in which to interpret the sensor, such as the physical entity or characteristic that is represented by this sensor. ƒ Event / Reading Type The Event/Reading Type values are from the Event/Reading Type Code Ranges and Generic Event/Reading Type Codes tables in the IPMI specification. Digital sensors are a specific type of discrete sensor, which have only two states. ƒ Event Offset/Triggers Event Thresholds are event-generating thresholds for threshold types of sensors. - [u,l][nr,c,nc]: upper nonrecoverable, upper critical, upper noncritical, lower nonrecoverable, lower critical, lower noncritical - uc, lc: upper critical, lower critical Event Triggers are supported event-generating offsets for discrete type sensors. The offsets can be found in the Generic Event/Reading Type Codes or Sensor Type Codes tables in the IPMI specification, depending on whether the sensor event/reading type is generic or a sensor-specific response. ƒ Assertion / De-assertion Enables Assertion and de-assertion indicators reveal the type of events the sensor generates: - As: Assertions - De: De-assertion ƒ Readable Value / Offsets - Readable Value indicates the type of value returned for threshold and other non- discrete type sensors. - Readable Offsets indicate the offsets for discrete sensors that are readable with the Get Sensor Reading command. Unless otherwise indicated, all event triggers are readable; Readable Offsets consist of the reading type offsets that do not generate events. ƒ Event Data Event data is the data that is included in an event message generated by the sensor. For threshold-based sensors, the following abbreviations are used: - R: Reading value - T: Threshold value Revision 1.4 Intel order number: D41763-005

Intel® Server Boards S5000PSL and S5000XSL TPS Appendix B: BMC Sensor Tables Revision 1.4 Intel order number: D41763-005 ƒ Rearm Sensors The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. This column indicates the type supported by the sensor. The following abbreviations are used in the comment column to describe a sensor: - A: Auto-rearm - M: Manual rearm ƒ Default Hysteresis The hysteresis setting applies to all thresholds of the sensor. This column provides the count of hysterisis for the sensor, which can be 1 or 2 (positive or negative hysteresis). ƒ Criticality Criticality is a classification of the severity and nature of the condition. It also controls the behavior of the Control Panel Status LED ƒ Standby Some sensors operate on standby power. These sensors may be accessed and / or generate events when the main (system) power is off, but AC power is present.

Table 45. BMC Sensors

Intel® Server Boards S5000PSL and S5000XSL TPS Appendix B: BMC Sensor Tables Sensor Name[1] Sensor Number System Applica- bility Sensor Type Event / Reading Type Event Offset Triggers Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby Platform Security Violation 04h All Platform Security Violation Attempt 06h Sensor Specific 6Fh Secure mode violation attempt Out-of-band access password violation OK As and De – Trig Offset A, I X Chassis intrusion OK Physical Security 05h Chassis Intrusion is chassis- specific Physical Security 05h Sensor Specific 6Fh LAN leash lost [2] Degraded As and De – Trig Offset A X FP Diag Interrupt (NMI) 07h All Critical Interrupt 13h Sensor Specific 6Fh Front panel NMI / diagnostic interrupt Bus uncorrectable error OK As – Trig Offset A, I – System Event Log 09h All Event Logging Disabled 10h Sensor Specific 6Fh Log area reset / cleared OK As – Trig Offset A, I X Session Audit 0Ah All Session Audit 2Ah Sensor Specific 6Fh 00h – Session activation 01h – Session deactivation OK – As defined by IPMI A, I X System Event ('System Event') 0Bh All System Event 12h Sensor Specific 6Fh 00 – System reconfigured 04 – PEF action OK As – Trig Offset A, I X BB +1.2V Vtt 10h All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I – BB+1.8V NIC Core 11h All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I X – BB +1.5V AUX 12h All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I BB +1.5V 13h All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I – Revision 1.4 Intel order number: D41763-005

Appendix B: BMC Sensor Tables Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Name[1] Sensor Number System Applica- bility Sensor Type Event / Reading Type Event Offset Triggers Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby BB +1.8V 14h All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I – BB +3.3V 15h All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I – BB +3.3V STB 16h All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I X BB +1.5V ESB 17h All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I X BB +5V 18h All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I – BB +1.2V NIC 19h All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I – BB +12V AUX 1Ah All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I – BB 0.9V 1Bh All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I – BB Vbat 1Eh All Voltage 02h Digital Discrete 05h 01h – Limit exceeded Critical As and De – R, T A, I X BB Temp 30h All Temperature 01h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I X Front Panel Temp 32h All Temperature 01h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I X FBDIMM Aggregate [3] 48h All Temperature 01h Threshold 01h CPU 1 FAN 50h Chassis- specific Fan 04h Threshold 01h [l] [c,nc] [4] Threshold defined As and De Analog R, T M, I – CPU 2 FAN 51h Chassis- specific Fan 04h Threshold 01h [l] [c,nc] [4] Threshold defined As and De Analog R, T M, I – SYS FAN 1 TACH 52h Chassis- specific Fan 04h Threshold 01h [l] [c,nc] [4] Threshold defined As and De Analog R, T M, I – Revision 1.4 Intel order number: D41763-005

Intel® Server Boards S5000PSL and S5000XSL TPS Appendix B: BMC Sensor Tables Sensor Name[1] Sensor Number System Applica- bility Sensor Type Event / Reading Type Event Offset Triggers Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby SYS FAN 2 TACH 53h Chassis- specific Fan 04h Threshold 01h [l] [c,nc] [4] Threshold defined As and De Analog R, T M, I – SYS FAN 3 TACH' 54h Chassis- specific Fan 04h Threshold 01h [l] [c,nc] [4] Threshold defined As and De Analog R, T M, I – SYS FAN 4 TACH 55h Chassis- specific Fan 04h Threshold 01h [l] [c,nc] [4] Threshold defined As and De Analog R, T M, I – SYS FAN 5 TACH' 56h Chassis- specific Fan 04h Threshold 01h [l] [c,nc] [4] Threshold defined As and De Analog R, T M, I – SYS FAN 6 TACH 57h Chassis- specific Fan 04h Threshold 01h [l] [c,nc] [4] Threshold defined As and De Analog R, T M, I – Tach Fan (Not used on this server) 58h Chassis- specific Fan 04h Threshold 01h [l] [c,nc] [4] Threshold defined As and De Analog R, T M, I – Tach Fan (Not used on this server) 59h Chassis- specific Fan 04h Threshold 01h [l] [c,nc] [4] Threshold defined As and De Analog R, T M, I – Tach Fan (Not used on this server) 5Ah Chassis- specific Fan 04h Threshold 01h [l] [c,nc] [4] Threshold defined As and De Analog R, T M, I – Fan 1 Present 60h Chassis- specific Fan 04h Generic 08h Device present OK As and De – T A – Fan 2 Present 61h Chassis- specific Fan 04h Generic 08h Device present OK As and De – T A – Fan 3 Present 62h Chassis- specific Fan 04h Generic 08h Device present OK As and De – T A – Fan 4 Present 63h Chassis- specific Fan 04h Generic 08h Device present OK As and De – T A – Fan 5 Present 64h Chassis- specific Fan 04h Generic 08h Device present OK As and De – T A – Fan 6 Present 65h Chassis- specific Fan 04h Generic 08h Device present OK As and De – T A – Revision 1.4 Intel order number: D41763-005

Appendix B: BMC Sensor Tables Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Name[1] Sensor Number System Applica- bility Sensor Type Event / Reading Type Event Offset Triggers Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby Fan 7 Present 66h Chassis- specific Fan Generic 08h Device present OK As and De 04h – T A – Fan 8 Present 67h Chassis- specific Fan Generic 08h Device present OK As and De 04h – T A – Fan 9 Present 68h Chassis- specific Fan Generic 08h Device present OK As and De 04h – T A – Fan 10 Present 69h Chassis- specific Fan Generic Device present OK As and De – A – T 04h 08h Full redundant OK Redundancy lost Degraded Fan Redun- dancy [5] 6Fh Chassis- specific Fan Generic 0Bh As and De – Trig Offset A X 04h Redundancy degraded Degraded Non-red: suff res from redund Degraded Non-red: suff from insuff Degraded Non-red: insufficient Non Critical Redun degrade from full Degraded Degraded Redun degrade from non- redundant Presence OK Failure Degraded Predictive fail Degraded Power Supply Status [5] 1 70h Chassis- specific Power Supply 08h Sensor Specific 6Fh As and De – Trig Offset A X A/C lost Degraded Configuration error OK Presence OK Failure Degraded Predictive fail Degraded Power Supply Status [5] 2 71h Chassis- specific Power Supply Sensor Specific 6Fh As and De – Trig Offset A 08h A/C lost Degraded X Revision 1.4 Intel order number: D41763-005 100

Intel® Server Boards S5000PSL and S5000XSL TPS Appendix B: BMC Sensor Tables Sensor Name[1] Sensor Number System Applica- bility Sensor Type Event / Reading Type Event Offset Triggers Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby Configuration error OK Power Nozzle Power Supply 1 78h Chassis- specific Current 03h Threshold [u] [c,nc] Threshold defined As and De Analog R, T A, I – 01h Power Nozzle Power Supply 2 79h Chassis- specific Current Threshold 01h [u] [c,nc] Threshold defined As and De Analog R, T A, I – 03h 7Ah Chassis- specific Current 03h Threshold [u] [c,nc] Threshold defined As and De Analog R, T A, I – Power Gauge V1 rail (+12v) 01h Power Supply 1 Power Gauge V1 rail (+12v) Power Supply 2 7Bh Chassis- specific Current 03h Threshold 01h [u] [c,nc] Threshold defined As and De Analog R, T A, I – Power Gauge (aggre-gate power) Power Supply 1 7Ch Chassis- specific Other Units Threshold 01h [u] [c,nc] Threshold defined As and De Analog R, T A, I – 0Bh Power Gauge (aggregate power) Power Supply 2 7Dh Chassis- specific Other Units Threshold 01h [u] [c,nc] Threshold defined As and De 0Bh Analog R, T A, I – Revision 1.4 Intel order number: D41763-005 101

Appendix B: BMC Sensor Tables Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Name[1] Sensor Number System Applica- bility Sensor Type Event / Reading Type Event Offset Triggers Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby System ACPI Power State 82h All System ACPI Power State Sensor Specific 6Fh S0 / G0 22h S3 S5 / G2 G3 mechanical off OK As – Trig Offset A, I X Button 84h All Button Sensor Specific 6Fh Power button Reset button OK As – Trig Offset A, I X 14h SMI Timeout 85h All SMI Timeout F3h Digital Discrete 03h 01h – State asserted Critical As and De – Trig Offset A, I – Sensor Failure 86h All Sensor Failure F6h OEM Sensor Specific 73h I2C device not found I2C device error detected I2C bus timeout OK As – Trig Offset A X NMI Signal State 87h All OEM C0h Digital Discrete 01h – State asserted OK – 01h – A, I – 03h SMI Signal State 88h All OEM C0h Digital Discrete 03h 01h – State asserted OK – 01h – A, I – IERR Critical Thermal trip Critical Config error Critical Presence OK Proc 1 Status 90h All Processor 07h Sensor Specific As and De – 6Fh Disabled Degraded Trig Offset M X IERR Critical Thermal trip Critical Proc 2 Status 91h All Processor Config error Critical 07h Sensor Specific 6Fh As and De – Trig Offset M Presence OK X Revision 1.4 Intel order number: D41763-005 102

Intel® Server Boards S5000PSL and S5000XSL TPS Appendix B: BMC Sensor Tables Sensor Name[1] Sensor Number System Applica- bility Sensor Type Event / Reading Type Event Offset Triggers Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby Disabled Degraded Proc 1 Temp[6] 98h All Temperature 01h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I – P1 Therm Margin [7] 99h All Temperature 01h Threshold 01h Proc 2 Temp [6] 9Ah All Temperature 01h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I – P2 Therm Margin [7] 9Bh All Temperature 01h Threshold 01h P1B Therm Margin [8] 9Ch All Temperature 01h Threshold 01h P2B Therm Margin [8] 9Dh All Temperature 01h Threshold 01h Bus correctable error OK PCIe Link0 A0h All Sensor Specific 6Fh PCIe Link0 Bus uncorrectable error Degraded As – See the BIOS EPS A, i – Bus correctable error OK PCIe Link1 A1h All Sensor Specific 6Fh Sensor Specific 6Fh Bus uncorrectable error Degraded As – See the BIOS EPS A, I – Bus correctable error OK PCIe Link2 A2h All Sensor Specific 6Fh Sensor Specific 6Fh Bus uncorrectable error Degraded As – See the BIOS EPS A, I – Bus correctable error OK PCIe Link3 A3h All Sensor Specific 6Fh Sensor Specific 6Fh Bus uncorrectable error Degraded As – See the BIOS EPS A, I – Bus correctable error OK PCIe Link4 A4h All Sensor Specific 6Fh Sensor Specific 6Fh Bus uncorrectable error Degraded As – See the BIOS EPS A, I – Revision 1.4 Intel order number: D41763-005 103

Appendix B: BMC Sensor Tables Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Name[1] Sensor Number System Applica- bility Sensor Type Event / Reading Type Event Offset Triggers Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby Bus correctable error OK PCIe Link5 A5h All Sensor Specific 6Fh Sensor Specific 6Fh Bus uncorrectable error Degraded As – See the BIOS EPS A, I – Bus correctable error OK PCIe Link6 A6h All Sensor Specific 6Fh Sensor Specific 6Fh Bus uncorrectable error Degraded As – See the BIOS EPS A, I – Bus correctable error OK PCIe Link7 A7h All Sensor Specific 6Fh Sensor Specific 6Fh Bus uncorrectable error Degraded As – See the BIOS EPS A, I – Bus correctable error OK PCIe Link8 A8h All Sensor Specific 6Fh Sensor Specific 6Fh Bus uncorrectable error Degraded As – See the BIOS EPS A, I – Bus correctable error OK PCIe Link9 A9h All Sensor Specific 6Fh Sensor Specific 6Fh Bus uncorrectable error Degraded As – See the BIOS EPS A, I – Bus correctable error OK PCIe Link10 AAh All Sensor Specific 6Fh Sensor Specific 6Fh Bus uncorrectable error Degraded As – See the BIOS EPS A, I – Bus correctable error OK PCIe Link11 ABh All Sensor Specific 6Fh Sensor Specific 6Fh Bus uncorrectable error Degraded As – See the BIOS EPS A, I – Bus correctable error OK PCIe Link12 ACh All Sensor Specific 6Fh Sensor Specific 6Fh Bus uncorrectable error Degraded As – See the BIOS EPS A, I – PCIe Link13 ADh All Sensor Specific Sensor Specific Bus correctable error OK As – See the BIOS EPS A, I – Revision 1.4 Intel order number: D41763-005 104

Intel® Server Boards S5000PSL and S5000XSL TPS Appendix B: BMC Sensor Tables Sensor Name[1] Sensor Number System Applica- bility Sensor Type Event / Reading Type Event Offset Triggers Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby 6Fh 6Fh Bus uncorrectable error Degraded Proc 1 Thermal Control C0h All Temperature 01h Threshold 01h [u] [c] Non- Critical As and De Analog Trig Offset M – Proc 2 Thermal Control C1h All Temperature 01h Threshold 01h [u] [c] Non- Critical As and De Analog Trig Offset M – Proc 1 VRD Over Temp C8h All Temperature 01h Digital Discrete 05h 01h – Limit exceeded Non- Critical As and De – Trig Offset M – Proc 2 VRD Over Temp C9h All Temperature 01h Digital Discrete 05h 01h – Limit exceeded Non- Critical As and De – Trig Offset M – Proc 1 Vcc D0h All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A – Proc 2 Vcc D1h All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A – Proc 1 Vcc Out-of- Range D2h All Voltage 02h Digital Discrete 05h 01h – Limit exceeded Non- Critical As and De Discrete R, T A – Proc 2 Vcc Out-of- Range D3h All Voltage 02h Digital Discrete 05h 01h – Limit exceeded Non- Critical As and De Discrete R, T A – CPU Population Error D8h All Processor 07h Generic 03h 01h –- State asserted Critical As and De – R, T A – Fault status asserted Degraded Device installed OK Disabled Degraded DIMM A1 E0h All Slot Connector 21h Sensor Specific 6Fh Sparing OK As – Trig Offset A – DIMM A2 E1h All Slot Connector Sensor Specific Fault status asserted Degraded As – Trig Offset A – Revision 1.4 Intel order number: D41763-005 105

Appendix B: BMC Sensor Tables Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Name[1] Sensor Number System Applica- bility Sensor Type Event / Reading Type Event Offset Triggers Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby Device installed OK Disabled Degraded 21h 6Fh Sparing OK Fault status asserted Degraded Device installed OK Disabled Degraded DIMM B1 E2h All Slot Connector 21h Sensor Specific 6Fh Sparing OK As – Trig Offset A – Fault status asserted Degraded Device installed OK Disabled Degraded DIMM B2 E3h All Slot Connector 21h Sensor Specific 6Fh Sparing OK As – Trig Offset A – Fault status asserted Degraded Device installed OK Disabled Degraded DIMM C1 E4h All Slot Connector 21h Sensor Specific 6Fh Sparing OK As – Trig Offset A – Fault status asserted Degraded Device installed OK Disabled Degraded DIMM C2 E5h All Slot Connector 21h Sensor Specific 6Fh Sparing OK As – Trig Offset A – Fault status asserted Degraded Device installed OK Disabled Degraded DIMM D1 E6h All Slot Connector 21h Sensor Specific 6Fh Sparing OK As – Trig Offset A – Fault status asserted Degraded Device installed OK DIMM D2 E7h All Slot Connector 21h Sensor Specific 6Fh Disabled Degraded As – Trig Offset A – Revision 1.4 Intel order number: D41763-005 106

Intel® Server Boards S5000PSL and S5000XSL TPS Appendix B: BMC Sensor Tables Sensor Name[1] Sensor Number System Applica- bility Sensor Type Event / Reading Type Event Offset Triggers Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby Sparing OK Memory A Error ECh All Memory 0Ch Sensor Specific 6Fh Correctable ECC Uncorrectable ECC OK As – Trig Offset A – Memory B Error EDh All Memory 0Ch Sensor Specific 6Fh Correctable ECC Uncorrectable ECC OK As – Trig Offset A – Memory C Error EEh All Memory 0Ch Sensor Specific 6Fh Correctable ECC Uncorrectable ECC OK As – Trig Offset A – Memory D Error EFh All Memory 0Ch Sensor Specific 6Fh Correctable ECC Uncorrectable ECC OK As – Trig Offset A – B0 DIMM Sparing Enabled F0h All Entity Presence 25h Sensor Specific 6Fh Entity present OK As – Trig Offset A – Fully redundant OK Non-red: suff res from redund Non-red: suff res from insuff res Degraded B0 DIMM Sparing Redun- dancy F1h All Memory 0Ch Discrete 0Bh Non-red: Insuff res Crtical As – Trig Offset A – B1 DIMM Sparing Enabled F2h All Entity Presence 25h Sensor Specific 6Fh Entity present OK As – Trig Offset A – Fully redundant OK Non-red: suff res from redund Non-red: suff res from insuff res Degraded B1 DIMM Sparing Redun- dancy F3h All Memory 0Ch Discrete 0Bh Non-red: insuff res Crtical As – Trig Offset A – Revision 1.4 Intel order number: D41763-005 107

Intel® Server Boards S5000PSL and S5000XSL TPS Revision 1.4 Intel order number: D41763-005 108 Sensor Name[1] Sensor Number System Applica- bility Sensor Type Event / Reading Type Event Offset Triggers Criticality Assert / De-assert Readable Value / Offsets Event Data Rearm Standby B01 DIMM Mirroring Enabled F4h All Entity Presence 25h Sensor Specific 6Fh Entity present OK As – Trig Offset A – Fully redundant OK Non-red:suff res from redund Non-red:suff res from insuff res Degraded B01 DIMM Mirroring Redun- dancy F5h All Memory 0Ch Discrete 0Bh Non-red: insuff res Crtical As – Trig Offset A – Note 4: For system with redundant cooling capability, the contribution to system status is determined by the fan redundancy sensor. Note 1: Actual sensor name strings in SDR may vary from the names in this table, according to platform-specific usage. Note 8: Applicable with Intle® Xeon® Processor 5300 series and 45nm 2P Quad-Core Intel® Xeon® Processor Note 7: Applicable with Intel® Xeon® Processor 5100 series and 45nm 2P Dual-Core Intel® Xeon® Processor Note 5: Sensor only presents on systems that have applicable redundancy 9for instance, fan or power supply) Note 3: FBDIMM Aggregate sensor will only have effect when CLTT enabled. Note 6: Applicable with Intel® Xeon® Processor 5000 series Note 2: Not supported except for ESB2 embedded NICs. Appendix B: BMC Sensor Tables

process, the Diagnostic LEDs can be used to identify the last POST process that was executed. both bits are clear, then the LED is off. Figure 27. Diagnostic LED Placement Diagram

Appendix C: POST Code Diagnostic LED DecoderIntel® Server Boards S5000PSL and S5000XSL TPS In the below example, BIOS sends a value of ACh to the diagnostic LED decoder. The LEDs are decoded as follows: ƒ Red bits = 1010b = Ah ƒ Green bits = 1100b = Ch Since the red bits correspond to the upper nibble and the green bits correspond to the lower nibble, the two are concatenated as ACh. Table 46. POST Progress Code LED Example Table 47. Diagnostic LED POST Code Decoder

Description

0x10h Off Off Off R Power-on initialization of the host processor (bootstrap processor) 0x11h Off Off Off A Host processor cache initialization (including AP) 0x12h Off Off G R Starting application processor initialization 0x13h Off Off G A SMM initialization Chipset 0x21h Off Off R G Initializing a chipset component Memory 0x22h Off Off A Off Reading configuration data from memory (SPD on DIMM) 0x23h Off Off A G Detecting presence of memory 0x24h Off G R Off Programming timing parameters in the memory controller 0x25h Off G R G Configuring memory parameters in the memory controller 0x26h Off G A Off Optimizing memory controller settings 0x27h Off G A G Initializing memory, such as ECC init 0x28h G Off R Off Testing memory PCI Bus 0x50h Off R Off R Enumerating PCI busses 0x51h Off R Off A Allocating resources to PCI busses 0x52h Off R G R Hot Plug PCI controller initialization 0x53h Off R G A Reserved for PCI bus 0x54h Off A Off R Reserved for PCI bus 0x55h Off A Off A Reserved for PCI bus 0x56h Off A G R Reserved for PCI bus Revision 1.4 Intel order number: D41763-005 110

Intel® Server Boards S5000PSL and S5000XSL TPSAppendix C: POST Code Diagnostic LED Decoder Diagnostic LED Decoder G=Green, R=Red, A=Amber 0x57h Off A G A Reserved for PCI bus USB 0x58h G R Off R Resetting USB bus 0x59h G R Off A Reserved for USB devices ATA / ATAPI / SATA 0x5Ah G R G R Resetting PATA / SATA bus and all devices 0x5Bh G R G A Reserved for ATA SMBUS 0x5Ch G A Off R Resetting SMBUS 0x5Dh G A Off A Reserved for SMBUS Local Console 0x70h Off R R R Resetting the video controller (VGA) 0x71h Off R R A Disabling the video controller (VGA) 0x72h Off R A R Enabling the video controller (VGA) Remote Console 0x78h G R R R Resetting the console controller 0x79h G R R A Disabling the console controller 0x7Ah G R A R Enabling the console controller Keyboard (PS2 or USB) 0x90h R Off Off R Resetting the keyboard 0x91h R Off Off A Disabling the keyboard 0x92h R Off G R Detecting the presence of the keyboard 0x93h R Off G A Enabling the keyboard 0x94h R G Off R Clearing keyboard input buffer 0x95h R G Off A Instructing keyboard controller to run Self Test (PS2 only) Mouse (PS2 or USB) 0x98h A Off Off R Resetting the mouse 0x99h A Off Off A Detecting the mouse 0x9Ah A Off G R Detecting the presence of mouse 0x9Bh A Off G A Enabling the mouse Fixed Media 0xB0h R Off R R Resetting fixed media device 0xB1h R Off R A Disabling fixed media device 0xB2h R Off A R Detecting presence of a fixed media device (IDE hard drive detection, etc.) 0xB3h R Off A A Enabling / configuring a fixed media device Removable Media 0xB8h A Off R R Resetting removable media device 0xB9h A Off R A Disabling removable media device 0xBAh A Off A R Detecting presence of a removable media device (IDE CDROM detection, etc.) 0xBCh A G R R Enabling / configuring a removable media device Boot Device Selection Revision 1.4 Intel order number: D41763-005 111

Appendix C: POST Code Diagnostic LED DecoderIntel® Server Boards S5000PSL and S5000XSL TPS Diagnostic LED Decoder G=Green, R=Red, A=Amber 0xD0 R R Off R Trying boot device selection 0xD1 R R Off A Trying boot device selection 0xD2 R R G R Trying boot device selection 0xD3 R R G A Trying boot device selection 0xD4 R A Off R Trying boot device selection 0xD5 R A Off A Trying boot device selection 0xD6 R A G R Trying boot device selection 0xD7 R A G A Trying boot device selection 0xD8 A R Off R Trying boot device selection 0xD9 A R Off A Trying boot device selection 0XDA A R G R Trying boot device selection 0xDB A R G A Trying boot device selection 0xDC A A Off R Trying boot device selection 0xDE A A G R Trying boot device selection 0xDF A A G A Trying boot device selection Pre-EFI Initialization (PEI) Core 0xE0h R R R Off Started dispatching early initialization modules (PEIM) 0xE2h R R A Off Initial memory found, configured, and installed correctly 0xE1h R R R G Reserved for initialization module use (PEIM) 0xE3h R R A G Reserved for initialization module use (PEIM) Driver Execution Environment (DXE) Core 0xE4h R A R Off Entered EFI driver execution phase (DXE) 0xE5h R A R G Started dispatching drivers 0xE6h R A A Off Started connecting drivers DXE Drivers 0xE7h R A A G Waiting for user input 0xE8h A R R Off Checking password 0xE9h A R R G Entering BIOS setup 0xEAh A R A Off Flash Update 0xEEh A A A Off Calling Int 19. One beep unless silent boot is enabled. 0xEFh A A A G Unrecoverable boot failure / S3 resume failure Runtime Phase / EFI Operating System Boot 0xF4h R A R R Entering Sleep state 0xF5h R A R A Exiting Sleep state 0xF8h A R R R Operating system has requested EFI to close boot services (ExitBootServices ( ) has been called) 0xF9h A R R A Operating system has switched to virtual address mode (SetVirtualAddressMap ( ) has been called) 0xFAh A R A R Operating system has requested the system to reset (ResetSystem () has been called) Pre-EFI Initialization Module (PEIM) / Recovery 0x30h Off Off R R Crisis recovery has been initiated because of a user request 0x31h Off Off R A Crisis recovery has been initiated by software (corrupt flash) Revision 1.4 Intel order number: D41763-005 112

Intel® Server Boards S5000PSL and S5000XSL TPSAppendix C: POST Code Diagnostic LED Decoder Diagnostic LED Decoder G=Green, R=Red, A=Amber 0x34h Off G R R Loading crisis recovery capsule 0x35h Off G R A Handing off control to the crisis recovery capsule 0x3Fh G G A A Unable to complete crisis recovery. Revision 1.4 Intel order number: D41763-005 113

Whenever possible, the BIOS will output the current boot progress codes on the video screen. the progress port. The progress codes may be reported by the system BIOS or option ROMs. action or choose to continue booting. the faulty part and restart the system. Table 48. POST Error Messages and Handling

0012 CMOS date / time not set Pause

5220 Configuration cleared by jumper Pause

5221 Passwords cleared by jumper Pause

5223 Configuration default loaded Pause

0048 Password check failed Halt

0141 PCI resource conflict Pause

0146 Insufficient memory to shadow PCI ROM Pause

8110 Processor 01 internal error (IERR) on last boot Pause

8111 Processor 02 internal error (IERR) on last boot Pause

8120 Processor 01 thermal trip error on last boot Pause

8121 Processor 02 thermal trip error on last boot Pause

8130 Processor 01 disabled Pause

8131 Processor 02 disabled Pause

8160 Processor 01 unable to apply BIOS update Pause

8161 Processor 02 unable to apply BIOS update Pause

8190 Watchdog timer failed on last boot Pause

8198 Operating system boot watchdog timer expired on last boot Pause

0192 L3 cache size mismatch Halt

0194 CPUID, processor family are different Halt

0195 Front side bus mismatch Pause

0197 Processor speeds mismatched Pause

8300 Baseboard management controller failed self-test Pause

8306 Front panel controller locked Pause

8305 Hotswap controller failed Pause

Intel® Server Boards S5000PSL and S5000XSL TPS Appendix D: POST Code Errors Error Code Error Message Response 84F2 Baseboard management controller failed to respond Pause 84F3 Baseboard management controller in update mode Pause 84F4 Sensor data record empty Pause 84FF System event log full Pause 8500 Memory Component could not be configured in the selected RAS mode. Pause 8520 DIMM_A1 failed Self Test (BIST). Pause 8521 DIMM_A2 failed Self Test (BIST). Pause 8522 DIMM_A3 failed Self Test (BIST). Pause 8523 DIMM_A4 failed Self Test (BIST). Pause 8524 DIMM_B1 failed Self Test (BIST). Pause 8525 DIMM_B2 failed Self Test (BIST). Pause 8526 DIMM_B3 failed Self Test (BIST). Pause 8527 DIMM_B4 failed Self Test (BIST). Pause 8528 DIMM_C1 failed Self Test (BIST). Pause 8529 DIMM_C2 failed Self Test (BIST). Pause 852A DIMM_C3 failed Self Test (BIST). Pause 852B DIMM_C4 failed Self Test (BIST). Pause 852C DIMM_D1 failed Self Test (BIST). Pause 852D DIMM_D2 failed Self Test (BIST). Pause 852E DIMM_D3 failed Self Test (BIST). Pause 852F DIMM_D4 failed Self Test (BIST). Pause 8540 Memory component lost redundancy during the last boot. Pause 8580 DIMM_A1 correctable ECC error encountered. Pause 8581 DIMM_A2 correctable ECC error encountered. Pause 8582 DIMM_A3 correctable ECC error encountered. Pause 8583 DIMM_A4 correctable ECC error encountered. Pause 8584 DIMM_B1 correctable ECC error encountered. Pause 8585 DIMM_B2 correctable ECC error encountered. Pause 8586 DIMM_B3 correctable ECC error encountered. Pause 8587 DIMM_B4 correctable ECC error encountered. Pause 8588 DIMM_C1 correctable ECC error encountered. Pause 8589 DIMM_C2 correctable ECC error encountered. Pause 858A DIMM_C3 correctable ECC error encountered. Pause 858B DIMM_C4 correctable ECC error encountered. Pause 858C DIMM_D1 correctable ECC error encountered. Pause 858D DIMM_D2 correctable ECC error encountered. Pause 858E DIMM_D3 correctable ECC error encountered. Pause 858F DIMM_D4 correctable ECC error encountered. Pause 8600 Primary and secondary BIOS IDs do not match. Pause

8601 Override jumper is set to force boot from lower alternate BIOS bank of flash ROM Pause

8602 Watchdog timer expired (secondary BIOS may be bad!) Pause

8603 Secondary BIOS checksum fail Pause

Revision 1.4 Intel order number: D41763-005 115

visible code on POST Progress LEDs. Table 49. POST Error Beep Codes

3 Memory error System halted because a fatal error related to the memory

6 BIOS rolling back

part, and is rolling back to the last good BIOS. by a sequence of beeps whose count is equal to the digit. Table 50. BMC Beep Codes

Intel® Server Boards S5000PSL and S5000XSL TPS Appendix D: POST Code Errors Appendix E: Supported Intel® Server Chassis The Intel® Server Boards S5000PSL and S5000XSL are supported in the following Intel® pedestal server chassis: ƒ Intel® Server Chassis SC5400 BASE ƒ Intel® Server Chassis SC5400 BRP ƒ Intel® Server Chassis SC5400 LX ƒ Intel® Server Chassis SC5400 LXi ƒ Intel® Entry Server Chassis SC5299-E DP ƒ Intel® Entry Server Chassis SC5299-E BRP Revision 1.4 Intel order number: D41763-005 117

Glossary Intel® Server Boards S5000PSL and S5000XSL TPS Glossary This appendix contains important terms used in the preceding chapters. For ease of use, Acronyms are then entered in their respective place, with non-acronyms following. Term Definition ACPI Advanced Configuration and Power Interface APIC Advanced Programmable Interrupt Control ASMI Advanced Server Management Interface BIOS Basic Input / Output System BIST Built-In Self Test BMC Baseboard Management Controller Bridge Circuitry connecting one computer bus to another, allowing an agent on one to access the other BSP Bootstrap Processor byte 8-bit quantity. CBC Chassis Bridge Controller (A microcontroller connected to one or more other CBCs, together they bridge the IPMB buses of multiple chassis. CEK Common Enabling Kit CHAP Challenge Handshake Authentication Protocol CMOS In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytes of memory, which normally resides on the server board. DPC Direct Platform Control EEPROM Electrically Erasable Programmable Read-Only Memory EHCI Enhanced Host Controller Interface EMP Emergency Management Port EPS External Product Specification ESB2 Enterprise South Bridge 2 FBD Fully Buffered DIMM F MB Flexible Mother Board FRB Fault Resilient Booting FRU Field Replaceable Unit FSB Front Side Bus GB 1024 MB GPIO General Purpose I/O GTL Gunning Transceiver Logic HSC Hot-Swap Controller Hz Hertz (1 cycle / second) I2C Inter-Integrated Circuit Bus IA Intel® Architecture IBF Input Buffer ICH I/O Controller Hub IC MB Intelligent Chassis Management Bus IERR Internal Error Revision 1.4 Intel order number: D41763-005 118

Intel® Server Boards S5000PSL and S5000XSL TPS Glossary Term Definition IFB I/O and Firmware Bridge INTR Interrupt IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface IR Infrared ITP In-Target Probe KB 1024 bytes KCS Keyboard Controller Style LAN Local Area Network LCD Liquid Crystal Display LED Light Emitting Diode LPC Low Pin Count LUN Logical Unit Number MAC Media Access Control MB 1024KB MCH Memory Controller Hub MD2 Message Digest 2 – Hashing Algorithm MD5 Message Digest 5 – Hashing Algorithm – Higher Security ms milliseconds MTTR Memory Type Range Register Mux Multiplexor NIC Network Interface Controller NMI Nonmaskable Interrupt OBF Output Buffer OEM Original Equipment Manufacturer Ohm Unit of electrical resistance PEF Platform Event Filtering PEP Platform Event Paging PIA Platform Information Area (This feature configures the firmware for the platform hardware) PLD Programmable Logic Device PMI Platform Management Interrupt POST Power-On Self Test PSMI Power Supply Management Interface PWM Pulse-Width Modulation RAM Random Access Memory RASUM Reliability, Availability, Serviceability, Usability, and Manageability RISC Reduced Instruction Set Computing ROM Read Only Memory RTC Real-Time Clock (Component of ICH peripheral chip on the server board) SDR Sensor Data Record SECC Single Edge Connector Cartridge SEEPROM Serial Electrically Erasable Programmable Read-Only Memory SEL System Event Log Revision 1.4 Intel order number: D41763-005 119

Glossary Intel® Server Boards S5000PSL and S5000XSL TPS Term Definition SIO Server Input / Output SMI Server Management Interrupt (SMI is the highest priority nonmaskable interrupt) SMM Server Management Mode SMS Server Management Software SNMP Simple Network Management Protocol TBD To Be Determined TIM Thermal Interface Material UART Universal Asynchronous Receiver / Transmitter UDP User Datagram Protocol UHCI Universal Host Controller Interface UTC Universal time coordinare VID Voltage Identification VRD Voltage Regulator Down Word 16-bit quantity ZIF Zero Insertion Force Revision 1.4 Intel order number: D41763-005 120

Intel® Server Boards S5000PSL and S5000XSL TPS Reference Documents Reference Documents See the following documents for additional information: ƒ Intel® S5000 Server Board Family Datasheet ƒ Intel Server Boards S5000PSL and S5000XSL Specification Update ƒ Intel 5000 Series Chipset Memory Controller Hub Datasheet. ƒ Intel 631xESB/632xESB I/O Controller Hub Datasheet. Revision 1.4 Intel order number: D41763-005 121