CPC7232 IXYS | Alldatasheet
Document overview
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- PDF pages: 12
Technical content
Features
- Processed with BCDMOS on SOI (Silicon on Insulator)
- Flexible High Voltage Supplies up to VPP-VNN=200V
- Internal Output Bleeder Resistors
- DC to 10MHz Analog Signal Frequency
- -60dB Minimum Output-Off Isolation at 5MHz
- Low Quiescent Power Dissipation (< 1A Typical)
- Output Switch On-Resistance Typically 20
- TTL I/Os for 3.3V Interface
- Surface Mount Package
Applications
- Ultrasound Imaging
- Printers
- Industrial Controls and Measurement
- Piezoelectric Transducer Drivers
Figure 1. Block Diagram
Description
The CPC7232 is a low charge injection 8-channel high-voltage analog switch integrated circuit (IC) for use in applications requiring high voltage switching. Bleeder resistors are incorporated into both terminals of each output switch. Control of the high voltage switching is via low voltage TTL logic level compatible inputs for direct connectivity to the system controller. Switch manipulation is managed by an 8-bit serial to parallel shift register whose outputs are buffered and stored by an 8-bit transparent latch. Level shifters buffer the latch outputs and operate the high voltage switches. Because the CPC7232 is capable of switching high load voltages and has a flexible load voltage range, e.g. V PP/VNN: +40V/160V or +100V/100V, it is well suited for many medical and industrial applications such as medical ultrasound imaging, printers, and industrial measurement equipment. The bleeder resistors enable the discharge of capacitive loads, such as piezoelectric transducers, connected to the output switches of the CPC7232. Construction of the high voltage switches using IXYS Integrated Circuits’ reliable BCDMOS process technology on SOI (Silicon On Insulator) allow the switches to be organized as solid state switches with direct gate drive.
Ordering Information
8 BIT
D LE SW1 CL D LE SW2 CL D LE SW3 CL D LE SW4 CL D LE SW5 CL D LE SW6 CL D LE SW7 CL D LE LEVEL SHIFTERS Part Number Description CPC7232K 48-Lead LQFP in T rays (250/T ray) CPC7232KTR 48-Lead LQFP T ape & Reel (2000/Reel) CPC7232 8-Channel HV Analog Switch with Built-in Bleeder Resistors
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INTEGRATED CIRCUITS DIVISION CPC7232 R03 www.ixysic.com 3 1. Specifications
1.1 Package Pinout
1.2 Pin Description
2 N/C No connection
4 N/C No connection
6 N/C No connection
7 N/C No connection
9 N/C No connection
10 SW3 SW3 Output
11 N/C No connection
12 SW2 SW2 Output
13 N/C No connection
14 SW2 SW2 Output
15 N/C No connection
16 SW1 SW1 Output
17 N/C No connection
18 SW1 SW1 Output
19 N/C No connection
20 SW0 SW0 Output
21 N/C No connection
22 SW0 SW0 Output
23 N/C No connection
PP Switch positive high voltage supply
25 VNN Switch negative high voltage supply
26 N/C No connection
27 RGND Ground for bleed resistors
28 GND Ground
29 VDD Logic positive supply voltage
30 N/C No connection
31 N/C No connection
32 N/C No connection
34 CLK Clock input, positive edge trigger
35 LE Latch enable, active low
36 CL Latch clear, active high clears latches and
37 DOUT Serial data output
38 N/C No connection
39 SW7 SW7 Output
40 N/C No connection
41 SW7 SW7 Output
42 N/C No connection
43 SW6 SW6 Output
44 N/C No connection
45 SW6 SW6 Output
46 N/C No connection
47 SW5 SW5 Output
48 N/C No connection
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1.3 Absolute Maximum Ratings
Absolute maximum electrical ratings are at 25C. Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. Typical values are characteristic of the device at +25°C, and are the result of engineering evaluations. They are provided for information purposes only, and are not part of the manufacturing testing requirements.
1.4 Operating Conditions
1 Power up/down sequence is arbitrary except that GND must be powered-up first and powered-down last. 2 VSW must be VNN VSW VPP or floating during power up/down transition. 3 Rise and fall times of power supplies, VDD , VPP , and VNN , should not be less than 1ms. Parameter Min Max Units VDD Logic Power Supply Voltage -0.5 6 V VPP - VNN Supply Voltage -2 2 0 V VPP Positive High Voltage Supply -0.5 VNN+200 V VNN Negative High Voltage Supply -0.5 VPP-200 V Logic input voltages -0.5 VDD+0.3 V Analog signal range VNN VPP V Peak analog signal current per channel - 1 A Power dissipation - 2.3 W Thermal Impedance, Junction to Ambient - 53 C/W Storage temperature -60 +150 C Parameter Symbol Value Logic power supply voltage 1, 3 VDD 4.5V to 6V Positive high voltage supply 1, 3 VPP 40V to VNN + 200V Negative high voltage supply 1, 3 VNN -40V to -160V Analog signal voltage, peak-to-peak 2 VSW VNN+10V to VPP-10V Operating temperature TA 0°C to 70°C
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1.5 Electrical Characteristics
1.5.1 Switch Characteristics (over recommended operating conditions unless otherwise noted)
Parameter Symbol Test Conditions 0°C +25°C +70°C Units min max min typ max min max Small signal switch on-resistance RONS VPP=40V , VNN=-160V , ISW=5mA - 30 - 21 38 - 48 VPP=40V , VNN=-160V , ISW=200mA -2 5- -2 7-3 2 VPP=100V , VNN=-100V , ISW=5mA - 25 - 21 27 - 30 VPP=100V , VNN=-100V , ISW=200mA - 18 - 16 24 - 27 VPP=160V , VNN=-40V , ISW=5mA - 23 - 21 25 - 30 VPP=160V , VNN=-40V , ISW=200mA -2 2- -2 5-2 7 Small signal switch on-resistance matching RONS ISW=5mA, VPP=100V , VNN=-100V -2 0- 42 0-2 0 % Large signal switch on-resistance RONL VSW=VPP-10V , ISW=0.8A --- 1 6 --- Output bleed resistors RINT Output switch to RGND, IRINT=0.5mA - - 20 28 50 - - k Switch off leakage per switch ISOL VSW=VPP-10V and VNN+10V -5- 0 . 4 1 0 - 1 5 A DC offset, switch off - RL=100k - 100 - 0.2 100 - 100 mV DC offset, switch on - RL=100k - 100 - 0.2 100 - 100 Switch output peak current - VSW duty cycle = 0.1% ---- 0 . 8 -- A Output switch frequency fSW Duty cycle = 50% ---- 5 0 -- k H z Maximum VSW slew rate dV/dt VPP=160V , VNN=-40V -2 0- -2 0-2 0 V / n sVPP=100V , VNN=-100V VPP=40V , VNN=-160V Off isolation KO f=5MHz, 1k/15pF load -30 - -30 - - -30 - dBf=5MHz, 50 load -58 - -58 - - -58 - Switch crosstalk KCR f=5MHz, 50 load -60 - -60 - - -60 - dB Output switch isolation diode current IID 300ns pulse width, 2.0% duty cycle - 300 - - 300 - 300 mA Off capacitance, SW to GND CSG(OFF) VSW=0V , 1MHz 51 75 -2 552 0 pF On capacitance, SW to GND CSG(ON) VSW=0V , 1MHz 25 40 20 - 40 25 50 Output voltage spike +VSPK VPP=40V , VNN=-160V , RL=50 --- 150 - - mV -VSPK 93 +VSPK VPP=100V , VNN=-100V , RL=50 --- 150 - --VSPK 80 +VSPK VPP=160V , VNN=-40V , RL=50 --- 150 - --VSPK 72 Charge injection Q VPP=100V , VNN=-100V , VSW=0V -8 8 0- p C
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1.5.2 Logic DC Characteristics (over recomm ended operating conditions unless otherwise noted)
1.5.3 Logic Timing Characteristics (over reco mmended operating conditions unless otherwise noted)
Parameter Symbol Test Conditions 0°C +25°C +70°C Units min max min typ max min max DOUT source capability VOH IOUT= -400A -- VDD-0.7 V DD-0.1 --- VDOUT sink capability VOL IOUT= +400A - - - 0.04 0.7 - - Logic input capacitance CIN - - 10 - - 10 - 10 pF Logic input high VIH 4.75V < VDD < 5.25V 2-2--2- V Parameter Symbol Test Conditions 0°C +25°C 70°C Units min max min typ max min max Setup time before LE rises tSD - 150 - 150 - - 150 - ns Time width of LE tWLE - 150 - 150 - - 150 - Clock delay time to Data Out tDO - - 150 - 62 150 - 150 Time width of CL tWCL - 150 - 150 - - 150 - Setup time, data to clock tSU - 15 - 15 8 - 20 - Hold time, data from clock tH - 35 - 35 - - 35 - Clock frequency fCLK 50% duty cycle, fDATA=fCLK/2 -5--5-5 M H z Clock rise and fall times tR, tF - - 50 - - 50 - 50 ns Tu r n - o n t i m e tON VSW=VPP-10V , RL=10k -5- 5-5 s T urn-off time tOFF 3
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1.5.4 Supply DC Characteristics (over recomm ended operating conditions unless otherwise noted)
Parameter Symbol Test Conditions 0°C +25°C +70°C Units min max min typ max min max VPP quiescent supply current I PPQ All switches off --- 0 . 1 1 0 -- All switches on, ISW=5mA VNN quiescent supply current I NNQ All switches off --- - 0 . 1 - 1 0 --All switches on, ISW=5mA VPP operating supply current I PP VPP=40V , VNN=-160V 50kHz output switching frequency with no load -6 . 5- - 7 - 8 mAVPP=100V , VPP=160V , VNN operating supply current I NN VPP=40V , VNN=-160V 50kHz output switching frequency with no load -6 . 5- - 7 - 8 mAVPP=100V , VPP=160V , VDD average supply current IDD fCLK=5MHz, VDD=5V -4--4-4 m A VDD quiescent supply current I DDQ - - 10 - 0.03 10 - 10 A
INTEGRATED CIRCUITS DIVISION 8 www.ixysic.com R03 CPC7232 2. Functional Description The CPC7232 takes a serial stream of input data along with a synchronous clock signal. As the clock transits from low to high, the data at the input of each shift register is shifted through from SR(n) to SR(n+1). A high data bit, a "1," represents an ON switch; a low data bit, a "0," represents an OFF switch. Data is input and shifted through the internal shift register until all eight shift register positions, SR0 through SR7, are in the desired state. D IN: The data-in line presents data bits to the CPC7232 to be shifted through the internal shift register. CLK: The clock signal's rising edge is associated only with shifting data into and through the shift register. CL: The clear line overrides all other inputs. When CL is high, the shift register is cleared to all 0s and all latches are set low, which causes all output switches to be turned OFF immediately. When CL is low, all output switches remain in whatever state they are in, ON or OFF , in response to CLK, latch inputs, and the LE signal. LE : latch enable controls the state of the latches and thus the state of the eight switches. If LE is high, then the latches do not change states, but retain their most recent status: either ON or OFF . With LE high, input data and CLK have no effect on the state of the output switches. If LE is low, then all latch outputs and their switch states follow the inputs from the shift register. LE is overridden by CL: no matter what state LE is in, CL clears the latches. See “Truth Table” on page 9. D OUT: The data-out pin is the output of SR7. After eight clock pulses, the first bit of eight input data bits is shifted to SR7 and appears on D OUT. SW0 - SW7: The CPC7232 provides eight high-voltage SPST output switches with a typical on-resistance of 20. The two connections of each switch are not polarity-sensitive. V PP and VNN: Voltage inputs to the level shifters for each switch channel that translate the voltage level of the latch output signals to an appropriate level for the voltages being switched. The high-voltage output switches are turned on and off in response to the data sent into the latches from the shift register: data 0 turns a switch OFF , data 1 turns a switch ON. Two or more CPC7232 devices can be cascaded to form an n-switch arrangement. The D OUT pin of the first is connected to the DIN pin of the next in the series. All devices are connected to the same clock (CLK) signal. LE of all devices would normally be connected, as would CL, but this is not necessary. The first data bit applied to D IN of the CPC7232, whether it's a single device or several cascaded devices, ripples through to the last switch output in line after the application of a full clocking sequence of 8 clock pulses per CPC7232. Setting the serial I/O device to output the most significant bit (MSB) first, results in the MSB appearing on SW7 of the last device in line after a full clocking sequence. CL DIN CLK LE SW0 SW7 SW0 SW7 SW0 SW7 DOUT LE CL DIN CLK DOUT LE CL DIN CLK DOUT LE CL DIN CLK CPC7232 CPC7232 CPC7232
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2.1 Truth Table
Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the rising edge of the CLOCK signal. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is lo w the shift register data flows through the latch. 4. D OUT is high when switch 7 is on. 5. Shift register clocking has no effect on the s witch states if LE is H. 6. The clear input overrides all other inputs. D0 D1 D2 D3 D4 D5 D6 D7 LE CL SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HL L ON L L L OFF HLL ON X X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X X H OFF OFF OF F OFF OFF OFF OFF OFF
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2.2 Logic Timing Waveforms
50% 50% 50%50% DIN LE tWLE tSD 50% 50%CLK tSU tHtDO 50%DOUT tOFF tON 90% 10% OFF ON CL 50% 50% tWCL VOUT (TYP)
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3 Manufacturing Information
3.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits classifies its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) classification as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
3.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard JESD-625.
3.3 Soldering Profile
Provided in the table below is the Classification Temperature (TC) of this product and the maximum dwell time the body temperature of this device may be (TC - 5)ºC or greater. The classification temperature sets the Maximum Body Temperature allowed for this device during lead-free reflow processes. For through-hole devices, and any other processes, the guidelines of J-STD-020 must be observed.
3.4 Board Wash
IXYS Integrated Circuits recommends the use of no-clean flux formulations. Board washing to reduce or remove flux residue following the solder reflow process is acceptable provided proper precautions are taken to prevent damage to the device. These precautions include but are not limited to: using a low pressure wash and providing a follow up bake cycle sufficient to remove any moisture trapped within the device due to the washing process. Due to the variability of the wash parameters used to clean the board, determination of the bake temperature and duration necessary to remove the moisture trapped within the package is the responsibility of the user (assembler). Cleaning or drying methods that employ ultrasonic energy may damage the device and should not be used. Additionally, the device must not be exposed to flux or solvents that are Chlorine- or Fluorine-based. Device Moisture Sensitivity Level (MSL) Classification CPC7232K MSL 3 Device Classification Temperature (TC) Dwell Time (tp) Max Reflow Cycles CPC7232K 260°C 30 seconds 3
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3.5 Mechanical Dimensions
3.5.1 CPC7232K 48-Pin LQFP Package
3.6 Tape and Reel Specifications
3.6.1 CPC7232KTR LQFP-48 T ape & Reel
(inches) 0.60, +0.15/-0.10
1.60 Max
(0.063Max) 1.40 ± 0.05 (0.055 ± 0.002) 0.05 Min / 0.15 Max (0.002 Min - 0.006 Max) 0.50 (0.020) PCB Land Pattern 8.40 (0.331) 0.50 (0.020) 0.30 (0.012) 1.50 (0.059) 8.40 (0.331) Pin 48 Pin 1 0.22 ± 0.05 (0.009 ± 0.002) 7.00 ± 0.10 (0.276 ± 0.004) 9.00 ± 0.20 (0.354 ± 0.008) 9.00 ± 0.20 (0.354 ± 0.008) 7.00 ± 0.10 (0.276 ± 0.004) Dimensions mm (inches) K0=2.20 (0.087) K1=1.60 (0.063) 16.0±0.3 (0.63±0.012) P1=12.00 (0.472) A0=9.30 (0.366) B0=9.30 (0.366) Embossment Embossed Carrier Top Cover Tape Thickness 0.102 MAX. (0.004 MAX.) 330.2 DIA. (13.00 DIA.) NOTE: Unless otherwise specified, tolerance ±0.1 (0.004) Direction of Feed For additional information please visit www.ixysic.com IXYS Integrated Circuits makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits’ Standard Terms and Conditions of Sale, IXYS Integrated Circuits assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits’ product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS-DS-CPC7232-R03 © Copyright 2018, IXYS Integrated Circuits All rights reserved. Printed in USA. 6/14/2018