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Quad-Serial Configuration (EPCQ) Devices Datasheet Subscribe Send Feedback CF52012 | 2018.06.01 Latest document on the web: PDF | HTML
- Quad-Serial Configuration (EPCQ) Devices Datasheet
system programmable NOR flash memory. Table 1. Supported Intel EPCQ Devices
- PDN1708 Product discontinuance notification.
- PDN1802 Product discontinuance notification.
- AN822: Intel Configuration Device Migration Guideline Provides more information about migrating EPCQ to EPCQ-A devices.
- Quad-Serial Configuration (EPCQ-A) Devices Datasheet (1) EPCQ512/A is shown in the Intel Quartus® Prime software as EPCQ512. CF52012 | 2018.06.01 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered
- Serial or quad-serial FPGA configuration in devices that support active serial (AS) x1 or AS x4 configuration schemes(2)
- Low cost, low pin count, and non-volatile memory
- 2.7-V to 3.6-V operation
- Available in 8- or 16- small-outline integrated circuit (SOIC) package
- Reprogrammable memory with up to 100,000 erase or program cycles
- Write protection support for memory sectors using status register bits
- Fast read, extended dual input fast read, and extended quad input fast read of the entire memory using a single operation code
- Write bytes, extended dual input fast write bytes, and extended quad input fast write bytes of the entire memory using a single operation code
- Reprogrammable with an external microprocessor using the SRunner software driver
- In-system programming (ISP) support with the SRunner software driver
- ISP support with Intel FPGA Download CableIntel FPGA Download Cable II, Intel FPGA Ethernet Cable
- By default, the memory array is erased and the bits are set to 1
- More than 20 years data retention Related Information Errata Sheet for EPCQ Devices 1.3. Operating Conditions Tables in this section list information about the absolute maximum ratings, recommended operating conditions, DC operating conditions, ICC supply current, and capacitance for EPCQ devices. Note: The values of the tables in this section are finalized for EPCQ16, EPCQ32, EPCQ64, EPCQ128, EPCQ256, and EPCQ512/A devices. The operating conditions for all of these devices are the same unless indicated otherwise. 1.3.1. Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Table 3. Recommended Operating Conditions Provides more information about EPCQ thermal resistance. Table 4. DC Operating Conditions (4) The maximum VCC rise time is 100 ms. temperatures up to 100°C as long as the ambient temperature does not exceed 85°C. (6) The IOH parameter refers to the high-level TTL or CMOS output current.
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Table 5. ICC Supply Current Table 6. Capacitance Capacitance is sample-tested only at TA = 25 x C and at a 54 MHz frequency. Table 7. Supported Memory Array Organization in EPCQ Devices (7) The IOL parameter refers to the low-level TTL or CMOS output current. (1,024 x 16) subsectors for the EPCQ512/A device.
- Quad-Serial Configuration (EPCQ) Devices Datasheet
14 E000 EFFF
0 H'0000000 H'0000FFF
- Quad-Serial Configuration (EPCQ) Devices Datasheet
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Sector Subsector Address Range (Byte Addresses in HEX) Start End 2034 7F2000 7F2FFF 2033 7F1000 7F1FFF 2032 7F0000 7F0FFF 64 1039 40F000 40FFFF 1038 40E000 40EFFF . . . 1026 402000 402FFF 1025 401000 401FFF 1024 400000 400FFF 63 1023 3FF000 3FFFFF 1022 3FE000 3FEFFF . . . 1010 3F2000 3F2FFF 1009 3F1000 3F1FFF 1008 3F0000 3F0FFF 62 1007 3EF000 3EFFFF 1006 3EE000 3EEFFF . . . 994 3E2000 3E2FFF 993 3E1000 3E1FFF 992 3E0000 3E0FFF 1 31 1F000 1FFFF 30 1E000 1EFFF . . . 18 12000 12FFF 17 11000 11FFF 16 10000 10FFF 0 15 F000 FFFF . . . 2 2000 2FFF 1 1000 1FFF
- Quad-Serial Configuration (EPCQ) Devices Datasheet CF52012 | 2018.06.01 Quad-Serial Configuration (EPCQ) Devices Datasheet
4094 FFE000 FFEFFF
4082 FF2000 FF2FFF
4081 FF1000 FF1FFF
4080 FF0000 FF0FFF
4078 FEE000 FEEFFF
4066 FE2000 FE2FFF
4065 FE1000 FE1FFF
4064 FE0000 FE0FFF
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Sector Subsector Address Range (Byte Addresses in HEX) Start End 64 1039 40F000 40FFFF 1038 40E000 40EFFF . . . 1026 402000 402FFF 1025 401000 401FFF 1024 400000 400FFF 63 1023 3FF000 3FFFFF 1022 3FE000 3FEFFF . . . 1010 3F2000 3F2FFF 1009 3F1000 3F1FFF 1008 3F0000 3F0FFF 62 1007 3EF000 3EFFFF 1006 3EE000 3EEFFF . . . 994 3E2000 3E2FFF 993 3E1000 3E1FFF 992 3E0000 3E0FFF 1 31 1F000 1FFFF 30 1E000 1EFFF . . . 18 12000 12FFF 17 11000 11FFF 16 10000 10FFF 0 15 F000 FFFF . . . 2 2000 2FFF 1 1000 1FFF
- Quad-Serial Configuration (EPCQ) Devices Datasheet CF52012 | 2018.06.01 Quad-Serial Configuration (EPCQ) Devices Datasheet
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Sector Subsector Address Range (Byte Addresses in HEX) Start End 254 4079 FEF000 FEFFFF . . . . . . 2066 812000 812FFF 2065 811000 811FFF 2064 810000 810FFF 128 2063 80F000 80FFFF 2062 80E000 80EFFF . . . 2050 802000 802FFF 2049 801000 801FFF 2048 800000 800FFF 127 2047 7FF000 7FFFFF 2046 7FE000 7FEFFF . . . 2034 7F2000 7F2FFF 2033 7F1000 7F1FFF 2032 7F0000 7F0FFF 64 1039 40F000 40FFFF 1038 40E000 40EFFF . . . 1026 402000 402FFF 1025 401000 401FFF 1024 400000 400FFF 63 1023 3FF000 3FFFFF 1022 3FE000 3FEFFF . . . continued... 1. Quad-Serial Configuration (EPCQ) Devices Datasheet CF52012 | 2018.06.01 Quad-Serial Configuration (EPCQ) Devices Datasheet
Sector Subsector Address Range (Byte Addresses in HEX) Start End 1010 3F2000 3F2FFF 1009 3F1000 3F1FFF 1008 3F0000 3F0FFF 62 1007 3EF000 3EFFFF 1006 3EE000 3EEFFF . . . 994 3E2000 3E2FFF 993 3E1000 3E1FFF 992 3E0000 3E0FFF 1 31 1F000 1FFFF 30 1E000 1EFFF . . . 18 12000 12FFF 17 11000 11FFF 16 10000 10FFF 0 15 F000 FFFF . . . 2 2000 2FFF 1 1000 1FFF
- Quad-Serial Configuration (EPCQ) Devices Datasheet CF52012 | 2018.06.01 Quad-Serial Configuration (EPCQ) Devices Datasheet
8176 FF0000 1FF0FFF
the device serially, with the MSB first.
- Quad-Serial Configuration (EPCQ) Devices Datasheet
1.5.1. Timing Requirements When the active low chip select (nCS) signal is driven low, shift in the operation code into the EPCQ device using the serial data (DATA) pin. Each operation code bit is latched into the EPCQ device on the rising edge of the DCLK. While executing an operation, shift in the desired operation code, followed by the address or data bytes. See related information for more information about the address and data bytes. The device must drive the nCS pin high after the last bit of the operation sequence is shifted in. For read operations, the data read is shifted out on the DATA pin. You can drive the nCS pin high when any bit of the data is shifted out. For write and erase operations, drive the nCS pin high at a byte boundary, that is in a multiple of eight clock pulses. Otherwise, the operation is rejected and not executed. All attempts to access the memory contents while a write or erase cycle is in progress are rejected, and the write or erase cycle continues unaffected. 1.5.2. Addressing Mode The 3-byte addressing mode is enabled by default. To access the EPCQ256 or EPCQ512/A memory, you must use the 4-byte addressing mode. In 4-byte addressing mode, the address width is 32-bit address. To enable the 4-byte addressing mode, you must execute the 4BYTEADDREN operation. This addressing mode takes effect immediately after you execute the 4BYTEADDREN operation and remains active in the subsequent power-ups. To disable the 4-byte addressing mode, you must execute the 4BYTEADDREX operation. Note: If you are using the Intel Quartus Prime software or the SRunner software to program the EPCQ256 or EPCQ512/A device, you do not need to execute the 4BYTEADDREN operation. The Intel Quartus Prime software enables the 4-byte addressing mode when programming the device automatically. 1.6. Registers 1.6.1. Status Register 1. Quad-Serial Configuration (EPCQ) Devices Datasheet CF52012 | 2018.06.01 Quad-Serial Configuration (EPCQ) Devices Datasheet
Table 14. Status Register Bits
7 R/W 0 None
6 R/W 0 BP3 (Block
5 R/W 0 TB (Top/Bottom
- 1=Protected area starts from the bottom of the memory array.
- 0=Protected area starts from the top of the memory array. Determine that the protected area starts from the top or bottom of the memory array.
4 R/W 0 BP2(9) Table 15 on page 19 through Table 26 on page
3 BP1(9)
2 BP0(9)
1 R 0 WEL (Write
- 1=Allows the following operation to run: — Write Bytes — Write Status Register — Erase Bulk — Erase Die — Erase Sector
- 0=Rejects the above mentioned operations. Allows or rejects certain operation to run.
0 R 0 WIP (Write in
- 1=One of the following operation is in progress: — Write Status Register — Write NVCR — Write Bytes — Erase
- 0=no write or erase cycle in progress Indicates if there is a command in progress. 1.6.1.1. Read Status Register Operation (05h)
Figure 1. Read Status Operation Timing Diagram written by a write bytes operation or erased by an erase sector operation. (10) Applicable for EPCQ64, EPCQ128, EPCQ256, and EPCQ512/A devices only.
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Table 15. Block Protection Bits in EPCQ16 when TB Bit is Set to 0 Table 16. Block Protection Bits in EPCQ16 when TB Bit is Set to 1 Table 17. Block Protection Bits in EPCQ32 when TB Bit is Set to 0
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Table 18. Block Protection Bits in EPCQ32 when TB Bit is Set to 1 Table 19. Block Protection Bits in EPCQ64 when TB Bit is Set to 0
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Table 20. Block Protection Bits in EPCQ64 when TB Bit is Set to 1 Table 21. Block Protection Bits in EPCQ128 when TB Bit is Set to 0
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Table 22. Block Protection Bits in EPCQ128 when TB Bit is Set to 1
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Table 23. Block Protection Bits in EPCQ256 when TB Bit is Set to 0 Table 24. Block Protection Bits in EPCQ256 when TB Bit is Set to 1
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Table 25. Block Protection Bits in EPCQ512/A when TB Bit is Set to 0 Table 26. Block Protection Bits in EPCQ512/A when TB Bit is Set to 1
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Figure 2. Write Status Operation Timing Diagram the self-timed write status cycle and 0 when it is complete. The Write Operation Parameters provides more information about tWS, tES and tWB.
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Table 27. Flag Status Register Bits
7 Write or Erase
- 1=Ready
- 0=Busy Indicates whether one of the following operation is in progress:
- Write Status Register
- Write NVCR
- Write Bytes
- Erase
6 Erase suspend • 1=In effect
- 0=Not in effect Indicates whether an Erase operation has been or is going to be suspended. Note: Status bits are reset automatically
5 Erase • 1=Failure or protection
- 0=Clear Indicates whether an Erase operation has succeeded or failed.
4 Write • 1=Failure or protection
- 0=Clear Indicates whether a Write Bytes operation has succeeded or failed; also an attempt to write a 0 to a 1 when VPP = VPPH and the data pattern is a multiple of 64 bits.
3 Reserved
2 Write suspend • 1=In effect
- 0=Not in effect Indicates whether a Write Bytes operation has been or will be suspended.
1 Protection • 1=Failure or protection
- 0=Clear Indicates whether an Erase or Write Bytes operation has attempted to modify the protected array sector.
0 Addressing • 1=4-bytes addressing
- 0=3-bytes addressing Indicates the addressing mode used. 1.6.2.1. Read Flag Status Register Operation(70h) The Read flag status register can be read continuously and at any time, including during a write or erase operation. You must read the Read flag status register every time a write or erase command is issued.
Figure 3. Read Flag Status Register Operation Timing Diagram (11) Write or erase controller bit = NOT write in progress bit.
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Table 28. Dummy Clock Cycles and Address Bytes for the Non-Volatile Configuration
- Arria ® GX
- Arria II
- Cyclone ®
- Cyclone II
- Cyclone III
- Cyclone IV
- Stratix ®
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Intel Cyclone 10 LP 8 —
Table 29. Dummy Clock Cycles and Address Bytes for the Non-Volatile Configuration
- Arria V
- Cyclone V
- Stratix V 3-byte addressing 12 12 4-byte addressing 4 10
Table 30. Non-Volatile Configuration Register Operation Bit Definition dummy clock cycles is from 1 to 14.
- 0—4-byte addressing
- 1—3-byte addressing (12) The 4-byte addressing mode is used for EPCQ256 and EPCQ512/A devices. (13) The default dummy clock cycles is 10 for extended quad input fast read and 8 for extended dual input fast and standard fast read. 1. Quad-Serial Configuration (EPCQ) Devices Datasheet CF52012 | 2018.06.01 Quad-Serial Configuration (EPCQ) Devices Datasheet
register have been read, a 0 is output. Figure 4. Read Non-Volatile Configuration Register Operation Timing Diagram
- Execute the write enable operation.
- Execute the write non-volatile configuration register operation.
- Set the 16-bit register value.
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Figure 5. Write Non-Volatile Configuration Register Operation Timing Diagram Table 31. Summary of Operation Codes (14) List MSB first and LSB last. Register on page 27 for more information. device, only the last 256 bytes are written to the memory.
- Quad-Serial Configuration (EPCQ) Devices Datasheet
driving the nCS signal low, followed by shifting in the operation code through DATA0. Figure 6. 4BYTEADDREN Timing Diagram (14) List MSB first and LSB last. (18) This operation is applicable for EPCQ256 and EPCQ512/A devices only.
- Quad-Serial Configuration (EPCQ) Devices Datasheet
100 MHz during the falling edge of the DCLK signal. Figure 11. Fast Read Operation Timing Diagram mode, the address width is 32-bit address.
8 Dummy Clock Cycles
read sequence to continue indefinitely. program, or write cycle in progress. are shifted in and out on the DATA0 and DATA1 pins.
- Quad-Serial Configuration (EPCQ) Devices Datasheet
addresses are shifted in on the DATA0 and DATA1 pins. Figure 16. Extended Dual Input Fast Write Bytes Timing Diagram mode, the address width is 32-bit address.
- Quad-Serial Configuration (EPCQ) Devices Datasheet
before the self-timed erase cycle is complete. The Write Operation Parameters provides more information about tWS, tES and tWB. high after the eighth bit of the erase subsector operation code has been latched in. Figure 21. Erase Subsector Operation Timing Diagram mode, the address width is 32-bit address. is set to 0 before the self-timed erase cycle is complete.
- Write Operation Timing on page 40 1. Quad-Serial Configuration (EPCQ) Devices Datasheet CF52012 | 2018.06.01 Quad-Serial Configuration (EPCQ) Devices Datasheet
- Memory Array Organization on page 7 1.8. Power Mode EPCQ devices support active and standby power modes. When the nCS signal is low, the device is enabled and is in active power mode. The FPGA is configured while the EPCQ device is in active power mode. When the nCS signal is high, the device is disabled but remains in active power mode until all internal cycles are completed, such as write or erase operations. The EPCQ device then goes into standby power mode. The ICC1 and ICC0 parameters list the VCC supply current when the device is in active and standby power modes. 1.9. Timing Information Note: The values in the following tables are finalized for EPCQ16, EPCQ32, EPCQ64, EPCQ128, EPCQ256, and EPCQ512/A devices. Related Information Summary of Operation Codes on page 29 1.9.1. Write Operation Timing
Figure 22. Write Operation Timing Diagram Table 33. Write Operation Parameters
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Symbol Parameter Min Typical Max Unit DCLK high time for EPCQ512/A 3.375 — — ns tCL(19) DCLK low time for all devices except EPCQ512/A 4 — — ns DCLK low time for EPCQ512/A 3.375 — — ns tNCSSU Chip select (nCS) setup time for all devices except EPCQ512/A 4 — — ns DCLK low time for EPCQ512/A 3.375 — — ns tNCSH Chip select (nCS) hold time for all devices except EPCQ512/A 4 — — ns Chip select (nCS) hold time for EPCQ512/A 3.375 — — ns tDSU DATA[] in setup time before the rising edge on DCLK for all devices except EPCQ512/A 2 — — ns DATA[] in setup time before the rising edge on DCLK for EPCQ512/A 1.75 — — ns tDH DATA[] hold time after the rising edge on DCLK for all devices except EPCQ512/A 3 — — ns DATA[] hold time after the rising edge on DCLK for EPCQ512/A 2.5 — — ns tCSH Chip select (nCS) high time 50 — — ns tWB(20) Write bytes cycle time — 0.6 5 ms tWS(20) Write status cycle time — 1.3 8 ms tEB(20) Erase bulk cycle time for EPCQ16 — 30 60 s Erase bulk cycle time for EPCQ32 30 60 Erase bulk cycle time for EPCQ64 60 250 Erase bulk cycle time for EPCQ128 170 250 Erase bulk cycle time for EPCQ256 240 480 Erase bulk cycle time for EPCQ512/A 153 460 tES(20) Erase sector cycle time for all devices except EPCQ512/A — 0.7 3 s Erase sector cycle time for EPCQ512/A 0.15 1 tESS (20) Erase subsector cycle time for all devices except EPCQ512/A — 0.3 1.5 s Erase subsector cycle time for EPCQ512/A 0.05 0.4 (19) The value must be larger /than or equal to 1/f WCLK. (20) The Write Operation Timing Diagram does not show these parameters. 1. Quad-Serial Configuration (EPCQ) Devices Datasheet CF52012 | 2018.06.01 Quad-Serial Configuration (EPCQ) Devices Datasheet
Figure 23. Read Operation Timing Diagram Table 34. Read Operation Parameters The Intel Quartus Prime software provides programming support for EPCQ devices. the configuration data for the selected FPGA. systems. The SRunner software driver reads .rpd files and writes to the EPCQ devices. bytes operation and shifted in first during the write bytes operation. other data and address bytes. pulses the nCONFIG signal to start the configuration process.
- Quad-Serial Configuration (EPCQ) Devices Datasheet
JTAG interface that is used to configure the FPGA.
- Using the Intel FPGA Serial Flash Loader IP Core with the Quartus Prime Software
- Intel FPGA ASMI Parallel IP Core User Guide
- Intel FPGA Download Cable II User Guide
- Intel FPGA Ethernet Cable
- Configuration, Design Security, and Remote System Upgrades in Arria V Devices
- Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
- Configuration, Design Security, and Remote System Upgrades in Stratix V Devices 1.11. Pin Information The following lists the control pins on the EPCQ device:
- Serial data 3 (DATA3)
- Serial data 2 (DATA2)
- Serial data 1 (DATA1)
- Serial data 0 (DATA0)
- Serial clock (DCLK)
- Chip select (nCS) Related Information
- Configuration, Design Security, and Remote System Upgrades in Arria V Devices
- Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
- Configuration, Design Security, and Remote System Upgrades in Stratix V Devices 1.11.1. Pin-Out Diagram for EPCQ16 and EPCQ32 Devices
Figure 24. AS x1 and AS x4 Pin-Out Diagrams for EPCQ16 and EPCQ32 Devices
- Quad-Serial Configuration (EPCQ) Devices Datasheet
Figure 25. AS x1 and AS x4 Pin-Out Diagrams for EPCQ64, EPCQ128, EPCQ256, and N.C pins must be left unconnected. Table 35. EPCQ Device Pin Description input pin that serially transfers data into the EPCQ device. The data is latched on the rising edge of the DCLK signal.
- Quad-Serial Configuration (EPCQ) Devices Datasheet
e AS x1 Pin-Out Diagram AS x4 Pin-Out Diagram Pin Type Description Pin Number in 8-Pin SOIC Package Pin Number in 16- Pin SOIC Package Pin Number in 8-Pin SOIC Package Pin Number in 16- Pin SOIC Package that serially transfers data out of the EPCQ device to the FPGA. The data is shifted out on the falling edge of the DCLK signal. DAT 2 8 2 8 I/O For AS x1 and x4 modes, use this pin as an output signal pin that serially transfers data out of the EPCQ device to the FPGA during read or configuration operations. The transition of the signal is on the falling edge of the DCLK signal. During the extended dual input fast write bytes or extended quad input fast write bytes operation, this pin acts as an input signal pin that serially transfers data into the EPCQ device. The data is latched on the rising edge of the DCLK signal. During extended dual input fast read or extended quad input fast read operations, this pin acts as an output signal pin that serially transfer data out of the EPCQ device to the FPGA. The data is shifted out on the falling edge of the DCLK signal. During read, configuration, or program operations, you can enable the EPCQ device by pulling the nCS signal low. DAT — — 3 9 I/O For AS x1 mode, extended dual input fast write bytes operation and extended dual input fast read operation, this pin must connect to a 3.3-V power supply. For AS x4 mode, use this pin as an output signal that serially transfers data out of the EPCQ device to the FPGA during read or configuration operations. The transition of the signal is on the falling edge of the DCLK signal. During the extended quad input fast write bytes operation, this pin acts as an input pin that serially transfers data into the EPCQ device. The data is latched on the rising edge of the DCLK signal. During the extended quad input fast read operation, this pin acts as an output signal pin that serially transfers data out of the EPCQ device to the FPGA. The data is shifted out on the falling edge of the DCLK signal. DAT — — 7 1 I/O For AS x1 mode, extended dual input fast write bytes operation and extended dual input fast read operation, this pin must connect to a 3.3-V power supply. For AS x4 mode, use this pin as an output signal that serially transfers data out of the EPCQ device to the FPGA during read or configuration operations. The transition of the signal is on the falling edge of the DCLK signal. During the extended quad input fast write bytes operation, this pin acts as an input pin that serially transfers data into the EPCQ device. The data is latched on the rising edge of the DCLK signal. During the extended quad input fast read operation, this pin acts as an output signal pin that serially transfers data out of the EPCQ device to the FPGA. The data is shifted out on the falling edge of the DCLK signal. nCS 1 7 1 7 Input The active low nCS input signal toggles at the beginning and end of a valid operation. When this signal is high, the device is deselected and the DATA pin is tri-stated. When this signal is low, the device is enabled and is in active mode. After power up, the EPCQ device requires a falling edge on the nCS signal before you begin any operation. continued... 1. Quad-Serial Configuration (EPCQ) Devices Datasheet CF52012 | 2018.06.01 Quad-Serial Configuration (EPCQ) Devices Datasheet
FPGA on the next falling edge of the DCLK signal. VCC 8 2 8 2 Power Connect the power pins to a 3.3-V power supply. 4 10 4 10 Ground Ground pin. EPCQ128, EPCQ256, and EPCQ512/A devices are available in 16-pin SOIC packages. EPCQ256 or EPCQ512/A device, and EPCQ256 device to EPCQ512/A device. Table 36. EPCQ Device Ordering Codes (21) N indicates that the device is lead free.
- Quad-Serial Configuration (EPCQ) Devices Datasheet
1.13. Document Revision History for Quad-Serial Configuration (EPCQ) Devices Datasheet Document Version Changes 2018.06.01 • Updated the description for t DSU parameter.
- Added data retention feature information.
- Added information about the read flag status register operation.
- Added a note to Absolute Maximum Ratings to state the maximum undershoot and overshoot for VI.
- Updated the product obsolescence note in Supported Intel EPCQ Devices table.
- Added a link to PDN1802. Date Version Changes November 2017 2017.11.06 • Updated operation code from binary to hexadecimal value in Summary of Operation Codes table.
- Added operation code in hex value in each operation timing diagrams.
- Updated operation timing diagrams to improve operation code and DLCK alignment accuracy.
- Added Registers section and included read status, write status, read non-volatile configuration, and read non- volatile configuration registers.
- Added note stating EPCQ16, EPCQ32, EPCQ64, and EPCQ128 are scheduled for product obsolescence.
- Added Extended Quad Input Fast Write Bytes Operation Timing Diagram for EPCQ512/A figure.
- Added extended quad input fast write bytes operation code for EPCQ512/A in Summary of Operation Codes table.
- Removed ambient temperature in Absolute Maximum Ratings.
- Added note to EPCQ512/A device is shown as EPCQ512 inIntel Quartus Prime software.
- Updated Write Operation Timing for EPCQ512/A devices.
- Updated Recommended Operating Conditions and ICC Supply Current for EPCQ512/A devices.
- Updated capacitance is sample-tested at a 54 MHz frequency. May 2016 2016.05.30 • Removed instances of 'Preliminary' and notes about pending characterization.
- Replaced EPCQ512 instances with EPCQ512/A.
- Updated ordering code for EPCQ512/A.
- Updated AS x1 and AS x4 Pin-Out Diagrams for EPCQ64, EPCQ128, EPCQ256, and EPCQ512/A Devices figure.
- Updated Power dissipation and Joint temperature in the Absolute Maximum Ratings table. January 2015 2015.01.23 • Updated non-volatile configuration register operation code.
- Added erase subsector operation.
- Added read non-volatile configuration register operation.
- Updated AS x1 dummy clock cycles for non-volatile configuration registers.
- Updated the erase and program cycle to up to 100,000 cycles.
- Updated write non-volatile configuration register 16-bit register value. continued... 1. Quad-Serial Configuration (EPCQ) Devices Datasheet CF52012 | 2018.06.01 Quad-Serial Configuration (EPCQ) Devices Datasheet
- Added Non-volatile Configuration Register Operation Bit Definition table.
- Added read status operation timing diagram.
- Updated EPCQ Device Pin Description table.
- Added a link to the Packaging Specifications and Dimensions page. January 2014 2014.01.10 • Added EPCQ512 device support.
- Added the write non-volatile configuration register operation.
- Added a link to the ALTASMI_PARALLEL IP Core User Guide.
- Removed preliminary for EPCQ16, EPCQ32, EPCQ64, EPCQ128, and EPCQ256 devices.
- Updated block protection bits for EPCQ16, EPCQ32, EPCQ64, EPCQ128, and EPCQ256 devices.
- Updated the dummy byte term to dummy cycle.
- Updated the dummy cycles for the read device identification operation in the Operation Codes for EPCQ Devices.
- Updated the t CL and tCH parameters in the write operation timing diagram.
- Updated the Package section.
- Updated the erase bulk cycle time for EPCQ16 and EPCQ32 devices.
- Updated the operating temperature in the Recommended Operating Conditions. July 2012 3.0 • Added Table 3, Table 4, and Table 5 to include the address range for EPCQ16, EPCQ32, and EPCQ64 devices.
- Added Table 9, Table 10, Table 11, Table 12, Table 13, and Table 14 to include the block protection bits for EPCQ16, EPCQ32, and EPCQ64 devices.
- Added Figure 5, Figure 20 and Figure 21 to include EPCQ16 and EPCQ32 devices.
- Updated the “Device Package and Ordering Code” section.
- Updated Table 1, Table 2, Table 19, Table 20, Table 27, and Table 28 to include EPCQ16, EPCQ32, and EPCQ64 devices.
- Updated the address bytes for the extended quad input fast write bytes operation in Table 8.
- Updated Figure 22 and Figure 23 to include EPCQ64 devices. January 2012 2.0 • Added Figure 2.
- Updated “Read Bytes Operation” and “Fast Read Operation” sections.
- Updated Figure 1, Figure 3, Figure 4, Figure 7, and Figure 13.
- Updated Table 5, Table 11, Table 12, and Table 14.
- Minor text edits. June 2011 1.0 Initial release. 1. Quad-Serial Configuration (EPCQ) Devices Datasheet CF52012 | 2018.06.01 Quad-Serial Configuration (EPCQ) Devices Datasheet