82586 INTEL | Alldatasheet
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Technical content
Figure 1. 82586 Functional Block Diagram *IBM is a trademark of International Business Machines Corporation.
14 Order Number: 231246-007
The symbols in parentheses correspond to minimum mode. Figure 2. 82586 Pinout Diagrams
critical functions independently of the host proces- _head for a given worst case bus latency. destination address checking, CRC generation and —_main reflectometry for locating faults in the cable. nels transparently to the user. Buffers containing er- _ured for either the IEEE 802.3/Ethernet or HDLC. ered. The 82586 can be configured for 8-bit or 16-bit CRCs are supported. Table 1. 82586 Pin Description
48 Pin DIP | 68 Pin PLCC
Vss. Vss 26, 27,41, System Ground. begin the initialization sequence. TTL | when not transmitting. 25 1 | Received Data Input Signal. pin is sampled on the HIGH to LOW clock transition.
Table 1. 82586 Pin Description (Continued)
48 Pin DIP | 68 Pin PLCC| Type
within, at most, two TxC cycles.
1 Active LOW Carrier Sense input used to notify the 82586
preamble transmission has begun. INT 0 | Active HIGH Interrupt request signal. symmetrical clock generator. static during 82586 operation. 49, 50, 53, bus, the high byte will output the address only during T1.
54 ADO-AD15 are floated after a RESET or when the bus is
to that of ADO-AD15 during write operation.
48 Pin DIP| 68 Pin PLCC| Type
‘Command Blocks. The CA signal is synchronized. LOW edge and then detected by the 82586. 82586 is configured to 8-bit bus. is a logical OR between READY and SRDY/ARDY. ‘setup and hold time specifications, when in ARDY mode. following RESET, this pin assumes ARDY mode.
48 Pin DIP | 68 Pin PLCC | Type
controls the direction of data flow through the Transceiver. RESET or when the bus is not acquired. *8288 does not support 10 MHz operation.
interface the iAPX 186, but due to the small number Block. ory. CPU intervention is only required after the CU PENDED, NO RECEIVE RESOURCES), interrupts. @ sequence of frames. ready, RU not ready), and statistics (see Figure 4). The only hardware signals that connect the CPU and = The Command List serves as a program for the CU.
82586 SYSTEM MEMORY A specific command, Transmit, causes transmission
Figure 3. 82586/Host CPU interaction
intel. 82586 varuzanon nogt rerau conrnot euocx cm [come | | Fm 4 | Sea | i 7 L Toy ey . ace raed Than — _-— Orr Creel _- [ee]: ——[-ee,! mn 70) jem) | oe ores = | = = | ee iy J (2) in) | recewe | [ ecene | [ necene ac a | ae | Figure 4, 82586 Shared Memory Structure out the CPU intervention, the DMA of each buffer Receive buffer chaining (i.e. storing incoming frames and the prefetching of references to new buffers in _in a linked list of buffers) improves memory utiliza- parallel. The CPU is notified only after successful tion significantly. Without buffer chaining, the user transmission or retransmission. must allocate consecutive blocks of the maximum frame size (1518 bytes in Ethernet) for each frame. The Receive Frame Area is a list of Free Frame De- Taking into account that a typical frame size may be scriptors (Descriptors not yet used) and a list of buff- about 100 bytes, this practice is very inefficient. With ers prepared by the user. It is conceptually distinct buffer chaining, the user can allocate smail buffers from the Command List. Frames arrive without being and the 82586 uses only as many as needed. solicited by the 82586. The 82586 must be prepared to receive them even if it is engaged in other activi- In the past, the drawback of buffer chaining was the ties and to store them in the Free Frame Area. The CPU processing overhead and the time involved in Receive Unit fills the buffers upon frame reception the buffer switching (especially at 10 Mb/s). The and reformats the Free Buffer List into received 82586 overcomes this drawback by performing buff- frame structures. The frame structure is virtually er management on its own for both transmission and identical to the format of the frame to be transmitted. reception (completely transparent to the user). The first frame descriptor is referenced by SCB. A Frame Descriptor and the associated Buffer De- © The 82586 has a 22-bit memory address range in ‘scriptor wasted upon receiving a Bad Frame (CRC minimum mode and 24-bit memory address range in or Alignment errored, Receive DMA overrun errored, maximum mode. All memory structures, the System or Collision fragmented frame) are automatically re- Control Block, Command List, Receive Descriptor claimed and returned to the Free Buffer List, unless List, and alt buffer descriptors must reside within one the chip is configured to Save Bad Frames. 64K-byte memory segment. The Data Buffers can be located anywhere in the memory space. 1-8
Figure 8. Receive Frame Area Diagram
intel. 82586 * Fetches the address of the next free Receive NETWORK PLANNING AND Frame Descriptor. MAINTENANCE * Writes the address of the next free Buffer De- scriptor into the next free Receive Frame De- —_—_To perform proper planning, operation, and mainte- scriptor. nance of a communication network, the network e wed? it in Management entity must accumulate information on * FOStS_2, Frame Received’ interrupt status Bit in network behavior. The 82586 provides a rich set of . network-wide diagnostics that can serve as the ba- © Interrupts the CPU. sis for a network management entity. In the event of a frame error, such as a CRC error, Network Activity information is provided in the status the 82586 automatically reinitializes its DMA point- —_of each frame transmitted. The activity indicators ers and reclaims any data butters containing the bad are: frame. As long as Receive Frame Descriptors and Number of collisions: number of colisions the [aL data buffers are available, the 82586 will continue to 02500 expen $ receive frames without further CPU help. $2588 experienced in attempting to transmit this * Deferred transmission: indicates if the 82586 had
82586 NETWORK MANAGEMENT AND to defer to traffic on the link during the first trans-
DIAGNOSTIC FUNCTIONS mission attempt. The behavior of data communication networks is Statistics registers are updated after each received typically very complex due to their distributed and _frame that passes the address filtering, and is longer asynchronous nature. it is particularly difficult to pin- than the Minimum Frame Length configuration pa- point a failure when it occurs. The 82586 was de- —_rameter. signed in anticipation of these problems and — CRC errors: number of frames that experienced a includes a set of features for improving reliability and CRC error and were property aligned. testability. © Alignment errors: number of frames that experi- ‘The 82586 reports on the following events after enced a CRC error and were misaligned. each frame transmitted: * No-resources: number of correct frames lost due © Transmission successtul. to lack of memory resources. © Transmission unsuccesstul lost Carrier Sense. Overrun errors: number of frame sequences lost q ‘ due to DMA overrun. © Transmission unsuccessful; lost Clear-to-Send. * Transmission unsuccessful; DMA underrun be- The 82586 can be configured to Promiscuous Mode. cause the system bus did not keep up with the _In this mode it captures all frames transmitted on the transmission, Network without checking the Destination Address. ssi . isi This is useful in implementing a monitoring station to oT ful; f coll a Transmission unsuccess number of collisions capture all frames for analysis. a . The 82586 is capable of determining if there is a ‘The 82586 checks each incoming frame and reports capa " i i “ short or open circuit anywhere in the Network using Pharma y nowing erors, GF configured to "Save Bed the builtin Time Domain Retlectometer (TDR) mech- anism. * CRC error: incorrect CRC in a well aligned frame. * Alignment error: incorrect CRC in a misaligned frame. STATION DIAGNOSTICS * Frame too short: the frame is shorter than the i 3 The chip can be configured to External Loopback. configured value for minimum frame length. - The transmitter to receiver interconnection can be ‘* Overrun: the frame was not completely placed in —_ placed anywhere between the 82586 and the link to memory because the system bus did not keep up _locate faults, for example: the 82586 output pins, the with incoming data. Serial Interface Unit, the Transceiver cable, or in the ‘© Out of buffers: no memory resources to store the ‘Transceiver. frame, so part of the frame was discarded. 4-14
82586 SELF TESTING but (different from IDLE) is associated with a CB
The 82586 can be configured to Internal Loopback. on the list. and any frame transmitted is received immediately. Command, and points to its CB. COMMAND word of the Action Command. 100 bytes of its internal registers to memory.
- frames and stores them in memory.
The Command Unit is the logical unit that executes discard. associated with each Action Command. way. Figure 10. System Control Block (SCB) Format
intel ° 82586 * READY—RU has free memory resources and © COMMAND word: Specifies the action to be per- stores incoming frames. formed as a result of the CA. This word is set by the CPU and cleared by the 82586. Defined bits are: The CPU may affect RU operation in three ways: issuing an AU Control Command, setting bits in [ACK-OX ](Bit 15) | © Acknowledges the Frame Descriptor, FD, COMMAND word of the . ‘command executed event. frame currently being received, or setting EL bit of |ACK-FR |(Bit14) | « Acknowledges the frame Butter Descriptor, BD, of the butfer currently being [ac cna @it13) | « Acmowlodes that the led. Command Unit became not a ready. ACK-RNR| (Bit 12) | * Acknowledges that the SYSTEM CONTROL BLOCK (SCB) Recelve Unt became not The System Control Block is the communication | ¢, its 8-10)| © oa thi i mail-box between the 82586 and the host CPU. The UC | (Bits 8-10)] » (3 bits) this field contains 1 SCB format is shown in Figure 10. Command Unit. 0 # NOP (doesn’t affect current The host CPU issues Control Commands to the state of the unit). 82586 via the SCB. These commands may appear 1 * Start execution of the first at any time during routine operation, as determined command on the Cat Wa by the host CPU. After the required Control Com- then complete t before.” mand is setup, the CPU sends a CA signal to the starting the new CBL. The 82586. beginning of the CBL is in ; ; CBL OFFSET. SCB is also used by the 82586 to return status infor- 2 * Resume the operation of mation to the host CPU. After inserting the required the command unit by status bits into SCB, the 82586 issues an Interrupt to executing the next command. This operation the CPU. assumes that the . command unit has been The format is as follows: 3 Brows suspanded. * Suspend execution o STATUS word: Indicates the status of the 82586. commands on CBL after This word is modified only by the 82586. Defined bits current command is are: complete. 4 * Abort ti of cx | (it 15) ‘© A command in the CBL. commands immaciatoly. having its ‘I’ (interrupt) bit 5-7 * Reserved, illegal for use. set has been executed. RUC (Bits 4-6) | © (9 bits) This field contains FR | (Bit 14) © A frame has been received. the command to the CNR | (Bit 13) © The Command Unit left the receive unit. Valid values. Active state. are RNR | (Bit 12) © The Receive Unit left the ° ° datestun attr curont Ready state. 1 reception of frames. CUS | (Bits 8-10) | © (3 bits) this field contains * Stamens oing revolved, " the status of the Command then complete reception Unit. before starting. The Valid values are: beginning of the RFA is 0 —Idle contained in the RFA = OFFSET. 3 puspended 2 ‘© Resume frame receiving Activ (only when in suspended 3-7 —Not Used state) RUS | (Bits 4—6) | + (3 bits) this field contains 3 '* Suspend frame receiving. it the status of the Receive a frame is being received, Unit. Valid values are: then complete its reception 0 —Iidle before suspending. 1 —Suspended 4 ‘* Abort receiver operation 2 —No Resources immediately. 3 _NotUsed 5-7 ‘* Reserved, illegal for use. RESET | (Bit 7) * Reset chip (logically the 4 _ —Ready same as hardware 5-7 —Not Used RESET). 4-13
ed following CU-START. Thus, the 82586 reads this mand Block. aligned frames received with a CRC error. ligned frames received with a CRC error. tion. Figure 11. The NOP Command Block
15 ODD BYTE EVEN BYTE 0
Figure 12. The |A-SETUP Command Block OK | (Bit13) | * Error Free Completion . rameter must be zero for IEEE 802.3/Ethernet. However, no enforcement of 0 is provided by the .
- Thus, an Individual Address with least signifi. Byte 6-7:
Figure 13. The CONFIGURE Command Block frames are not saved] | EXT-LPBCK| (Bit 15) _| External Loopback. frames are saved in Internal Loopback.
intel. 82586 INTER (Bits 8-15) | * Number indicating COTF @its * Collision Detect FRAME the Interframe 12-14 Filter in Bit Times SPACING Spacing in TxC CDT-SRC | (Bit15) | © Collision Detect period units. Source Byte 12-13: 0 © External
1 Internal
SLOT- (Bits 0-7) | © Slot Time Number, TIME (L) Low Byte Byte 16: SLT-TM (H) | Bits 8-10) | * Slot Time Number, (Bits 0-7) | * Minimum Number of High Bits Bytes in a Frame RETRY- | @its * Maximum Number of NUM 12-15) Transmission Retries on Collisions CONFIGURATION DEFAULTS 1 Byte 14-15: vt - - The default values of the configuration parameters PRM (Bit 0) * Promiscuous Mode are compatible with the IEEE 802.3/Ethernet Stan- BC-DIS | (Bit 1) * Broadcast Disable dards. RESET configures the 82586 according to MANCH/ | (Bit 2) * Manchester or NRZ the defaults shown in Table 2. NRZ * Encoding/Decoding 0 °NRZ Table 2. 82586 Default Values 1 * Manchester Preamble Length (Bytes) = 8 TONO-CRS | (Bit 3) * Transmit on No Address Length (Bytes) = 6 0 gamer. ‘Fonse _. Broadcast Disable = 0 * Cease Transmission CRC-16/CRC-32 = 0 WGRS Goes Inactive No CRC insertion = 0 1 * Continue Padding = 0 Transmission Even if Min-Frame-Length (Bytes) = 64 no Carter Sense Interframe Spacing (Bits) = 96 NCRC-INS | (Bit 4) * No CRC insertion Slot Time (Bits) | = 512 CRC-16 — | (Bit'5) © CRC Type: Number of Retries = 15 t) © 32 bit Autodin Il CRC Linear Priority : = 0 Polynomial Accelerated Contention Resolution = 0 1 * 16 bit CCITT. CRC Exponential Backoff Method = 0 Polynomial Manchester/NRZ = 0 BT-STF | Bite) © Bitstuffing: Internal CRS = 0 0 © End of Carrier Mode CRS Fitter = 0 (Ethernet) Internal CDT = 0 1 * HOLC like Bitstufting COT Filter = 0 : Mode Transmit On No CRS = 0 PAD (@Bit7) * Padding FIFO THRESHOLD = 8 t) * No Padding SRDY/ARDY = 0 1 . Labial tings by Save Bad Frame = 0 ransmitting Flags A /Length Locati = for Romainr of Actrs/ Length Location = 8 cRSF Bits 8-9) | * Carer Sonso Fite EXT Loopback = 8 Bits 8 eines ne Promiscuous Mode = 0 CRS-SRC |(Bit11) | * Carrier Sense Source 0 * External 1 ¢ Internal 1-17
Figure 14. The MC-SETUP Command Block This command sets up the 82586 with a set of Multi-_ticast Address. B | @it14) | © Busy Executing during reception. COMMAND word: ble to become all zeros. the nearest multiple of Address Length (in bytes).
Figure 15. The Transmit Command Block TRANSMIT CB includes the following fields: fro Collision Dotect om. B | (Bit14) | © Busy Executing retries. during transmission there were 16 collisions. s7 | @t7 | «transmssonhad io cates that there is no Information field. LENGTH FIELD: Length field of the frame.
the case of a Transceiver| contents. The length of the buffer is 170 bytes. one exists) in transmit fiade are av follows. 82586 CONFIGURE command field. dred bytes of internal registers to be placed inmem- cant byte. Figure 18. The DUMP Command Block
Figure 19. The DUMP Area
intel. 82586 Bytes 18H to 1BH: Contents of Receive CRC — CUR-RB-EBC: Current Receive Buffer Empty Byte Checker. RXCRCRO is the least significant byte. Count Let N be the currently used Receive Buffer. The contents are dependent on the activity per- Then CUR-RB-EBC indicates the Empty part of the formed before the DUMP command: buffer, ie. the ACT-COUNT of buffer N is given by the difference between its SIZE and the CUR-RB- After RESET - ‘All Ones." EBC. After good frame reception— NXT-FD-ADR: Next Frame Descriptor Address. De- ’ . fine N as the last Receive Frame Descriptor with bits 1. For GRC-CCITT - OIDOFH C = 1 andB = 0, then NXT-FD-ADR is the address 2. For CRC-Autodin-Il - C704DD7BH of N + 2 Receive Frame Descriptor (with B = C = ; 0) and is equal to the LINK-ADDRESS field in N + 1 After Bad Frame reception - corresponds to the re- Receive Frame Descriptor. ceived information. 1 CUR-FD-ADR: Current Frame Descriptor Address. After reception attempt, i.e. unsuccessful check for Similar to next NXT-FD-ADR but refers to N + 1 address match, corresponds to the CRC performed Receive Frame Descriptor (with B = 1, C = 0). on the frame address. Bytes 54H to SSH: Temporary register. NOTE: Any frame on the serial link modifies this register. NXT-TB-CNT: Next Transmit Butfer Count. Let N be contents. the last transmitted butter of the TRANSMIT com- mand executed recently, the NXT-TB-CNT is the Bytes 1CH to 21H: Temporary Registers. ACT-COUNT field in the Nth Transmit Butter De- scriptor. EOF - Corresponds to the EOF bit of the Bytes 22H to 23H: Receive Status Register. Bits 6, Nth Transmit Buffer Descriptor. EOF = 1 indicates 7, 8, 10, 11 and 13 assume the same meaning as _that the last buffer accessed by the 82586 during corresponding bits in the Receive Frame Descriptor Transmit was the last Transmit Buffer in the data Status field. butfer chain associated with the Transmit Com- mand. Bytes 24H to 2BH: HASH TABLE. BUF-ADR: Buffer Address. The BUF-PTR field in the Bytes 2CH to 2DH: Status bits of the last time TDR | DUMP-STATUS Command Block. id that . Commend that was performed NXT-TB-AD-L: Next Transmit Butfer Address Low. NXT-RB-SIZE: Let N be the last butfer of the last Let N be the last Transmit Butfer in the transmit butt- received frame, then NXT-AB-SIZE is the number of @& chain of the TRANSMIT Command performed bytes of available in the N + 1 butfer. EL- The EL recently, then NXT-TB-AD-L are the two least signifi- bit of the Receive Butter Descriptor. cant bytes of the Nth buffer address. NXT-RB-ADR: Let N be the last Receive Buffer LA-TB-ADR: Look Ahead Transmit Buffer Descrip- , tor Address. Let N be the last Transmit Butfor in the used, then NXT-RB-ADR is the BUFFER-ADDRESS 4 o ‘eld | 4 transmit buffer chain of the TRANSMIT Command field in the N + 1 Receive-Bufter Descriptor, i.e. the r pointer to the N+ 1 Receive Butter. performed recently, then LA-TBD-ADR is the NEXT- BD-ADDRESS field of the Nth Buffer Descriptor. CUR-RB-SIZE: The number of bytes in the last butt- XT-TBD-ADR: Next Transmit Buffer Descriptor er of the last received frame. EL - The EL bit of the Agdrass, Similar in function to LA-TBD-ADR but last buffer in the last received frame. ress. Similar in function to LA- Te lated to Transmit Buffer Descriptor N-1. Actually, itis LA-RBD-ADR: Look Ahead Butfer Descriptor, ie. _'n@ address of Transmit Butter Descriptor N. the pointer to N + 2 Receiver Buffer Descriptor. Bytes 60H, 61H: This is a copy of the 2nd word in the DUMP-ST/ ing. NXT-RBD-ADR: Next Receive Buffer Descriptor Ad- e ‘ATUS command presently executing, dress. Similar to LA-RBD-ADR but points toN + 1 NXT-CB-ADR: Next Command Block Address. The Receive Buffer Descriptor. LINK-ADDRESS field in the DUMP Command Block - presently executing. Points to the next command. CUR-RBD-ADR: Current Receive Buffer Descriptor Address. Similar to LA-RBD-ADR, but point to Nth GUR-CB-ADR: Current Command Block Address. Receive Buffer Descriptor. The address of the DUMP Command Block currently executing. 1-23
intel. 82586 SCB-ADR: Offset of the System Control Block 1. If AL-LOCation = 0 then RCV-DMA-BC = (2 (sce). times ADDR-LEN plus 2) if the next Receive Frame Descriptor has already been fetched. H, 7FH: 2. If AL-LOCation = 1 then it contains the size of Bytes 7E the next Receive Butter. RU-SUS-RQ (Bit 4) - Receive Unit Suspend Re- quest. BR+ BUF —PTR+96H - Sum of Base Address plus BUF — PTR field and 96H. Bytes 80H, 81H: RCV-DMA-ADR - Receive DMA absolute Address. This is the next RCV-DMA start address. The value cususra (Bit 4) - Command Unit Suspend Re- —_gepends on AL-LOCation configuration bit. 1. If AL-LOCation = 0, then RCV-DMA-ADR is the END-OF-CBL (Bit 5) - End of Command Block List. If Destination Address field located in the next Re- “4" indicates that DUMP-STATUS is the last com- ceive Frame Descriptor. mand in the command chain. 2. If AL-LOCation = 1, then RCV-DMA-ADR is the next Receive Data Buffer Address. ABRT-IN-PROG (Bit 6) - Command Unit Abort Re- quest. The following nomenclature has been used in the RU-SUS-FD (Bit 12) - Receive Unit Suspend Fi PUMP table: Goociptor Ba: Aneonw Wi tw Rovelee Frome Des 0 | © The 82586 writes zer0 in this location. scriptor used recently, then RU-SUS-FD is equiva- 1 | ¢ The 82586 writes one in this location. lent to the S bit of N + 1 Receive Frame Descriptor. X | © The 82586 writes zero or one in this location. /11 | @ The 82586 copies this location from the Bytes 82H, 83H: corresponding position in the memory RU-SUS (Bit 4) - Receive Unit in SUSPENDED state. structure. AU-NRSRG (Bt 5)- Receive Unitin NO RESOURC- bi pqnose . ee The DIAGNOSE Command triggers an internal self RU-RDY (Bit 6) - Receive Unit in READY state. test procedure of backoff related registers and coun- RU-IDL (Bit 7) - Receive Unit in IDLE state. ters. , ae The DIAGNOSE command includes the following RNR (Bit 12) - RNR Interrupt in Service bit. CNA (it 13) - CNA Interrupt in Service bit. STATUS word (written by 82586): ; c (Bit 15) | © Command Completed FR (Bit 14) - FR Interrupt in Service bit. B (Bit 14) | © Busy Executing ; - ; Command OX (Bit 15) - CX Interrupt in Service bit. OK | (Bit13) | © Error Free Completion . FAIL (Bit 11) © Indicates that the Self Bytes 90H to 93H: Test Procedured Failed BUF-ADR-PTR - Buffer pointer is the absolute ad- dress of the bytes following the DUMP Command § COMMAND word: block. EL | @it15) | © End of Command List s (Bit 14) | © Suspend After Bytes 94H to 95H: Completion 1 (Bit 13) | Interrupt After RCV-DMA-BC - Receive DMA Byte Count. This field Completion contains number of bytes to be transferred during | CMD | (Bits0-2) | * DIAGNOSE = 7 the next Receive DMA operation. The value de- pends on AL-LOCation configuration bit. LINK OFFSET: Address of next Command Block. 1-24
Figure 20. The DIAGNOSE Command Block
1 Lfefacrent] faTacren |: <fo[scren] fo[acren |r-[o [acter]
Figure 21. The Receive Frame Area points to the first FD of the chain; the last FD is Frame.
Figure 22. The Frame Descriptor (FD) Format OK | (Bit13) | © Frame received LINK OFFSET: Address of next FD in list. S11 | (Bit11) | © Received Frame . S10 | (Bit10) | © Received Frame Contains Destination Address of received frame. Alignment Error. Length configuration parameter. s8 | (Bits) | *RCV-DMA Overrun. same as DESTINATION ADDRESS. configured Minimum byte Length or Type Field of received frame. EL | (Bit 15) Last FD in the List. end-of-frame indication). ater receiving this frame. The Butter Descriptor contains the following fields.
Figure 23. The Receive Buffer Descriptor (RBD) Format ACT | (Bits 0-13)} * Number of bytes in the EL | @IT15) | © LasteDinist.
intel. 22506 eee ABSOLUTE MAXIMUM RATINGS* “WARNING: Stressing the device beyond the “Absolute Voltage on Any Pin with These are stress ratings only. Operation beyond the D.C. CHARACTERISTICS Ta = 0°C to 70°C, Te = 0°C to 105°C, Vog = SV +10%, CLK has MOS levels (See Vit, Viti: VMOL: Vmou). TxC and RxC have 82C501 compatible levels (Vii. Vii. Vain). All other signals have TTL levels (see Vit: Vins Vou, OH). [symbor | __ Parameter [Min [Max | Unite | TeatConditions _| [ Vu___| imputtowVotagemy [os | oe [ov [| [vii | inputHigh vortagoTmy [20 | vectos |v | | Vor__| Outputtowvoragecrmy [| ows [vf ig = 25ma | | Vou | OutputHigh Votagecrmy [24 |Tv | ton 400A | [ Vux__| imputtowvonagewmos) | -os [os [ov [| [Yum | inputhigh Votage mos) [39 | voctost v |_| [_vrn | inputigh Voltage Te) [aa | voctos| v [| [ Van | InputHigh Vottage eC) [30 | Vec+os| v [| | Vwo.__| Outputtowvotageos) | | ows [| 25m | Von | OutputrighVotagemos) | Voc-os | | Vv | ton 400nA | [ui | tmputLoakagecurent || eto [uA | Ove Veo | [uo | OutputLeakage Curent [| st0 Twa | 048 = Vour < Veo | [cm | Capacitance of nputButter |" [10 |r | FO= tM | Cour | Capacitance of Outputsuter || 20 pr [C= tM ce Ta = 70°C 1-28
Figure 24. TTL input/Output Voltage Levels for Timing Measurements
1 VARY WITH VCC
Figure 25. System Clock CMOS Input Voltage Levels for Timing Measurements
intel. 82586 a INPUT TIMING REQUIREMENTS* eee | soe | eas | [ win [wax | min | Fi [ares Hs a oe J [72 |ctktowtimeattav | 73 | 1000] 55 | 1000] «« | 1000] | [ta [eiktowtimeatoov [|__| 425 | 1000 42s | 1000 | | [te eixriontineattsv [=f fs | [«][ |_| [75 [ctktignTimeatsev | | [ws] [ws] |_| [te [ciKrisetime Tis [is [ae | notes [7 feukrartime Tas | is Pe | nate | [te | Datainseuptime 20 [fo | as TT [710 [AsmneROV Actve SoupTime | 20 | | 20 | | | | woes _| [111 [AsyneROY inactive SeupTime [a6 [| 36 | [a5 [| Notes | [Ti [Aemenoviodtime [is | | 5 | | 16 | | Nota | [113 __[ Synchronous Ready/Actve Setup | 96 | [35 [| 20 [| [t14 | Synchronous Ready HoidTime [0 [To | fo fT [t17__[Resetseuptime | 20 || ao | 20 [| News| [t1¢__[ResetHodtime To [To [Po [| notes | [ti [caPusewin fae fate [a |t20__[oasewptime [20 | [a0 [| 20 [noes | [ta1__[cawogtime [10 [to [0 | Notes | OUTPUT TIMINGS** [Symboi [Parameter [in [ wax | win [ Max [ win | Max | Comments | [r22_[ormvaiddey To [oo | o [oo fo fa [| [120 [WR.DENAcivedeay [0 | 7 | o [7 | o | [| [724 | WR.DENinactwe Dey [10 [es | 10 [os [to | as [| [725 [ime Actve delay [0 [es | 0 [65 | 0 [70 | Notes | [726 int inactive Delay [0 [as [0 [es | 0 [70 [Noes | [127 __[WoidActweDelay | | es | 0 [as | 0 | 70 | Notes | [72e_[HoiinaciveDelay fo [es | 0 [as | 0 | 70 | Notes | [129 | Address vaiiDelay | 0 [ss | 0 [ss | o [| so | | | 790__[ Address FioatDelay [0 | 60 | o [so |e [oo [| [71 [Oatavaidooey | o | ss] 0 | 55] 0 | so | Now? | [72 [oatanowtine | of [of [e|[ |_| [128 [SuusAcivensay ‘| 0 | ow) ealwls| | 1-30
intel. 82586 SERIAL INTERFACE A.C. TIMING for Manchester: CHARACTERISTICS f min = 500 kHz + 100 ppm fmax = 10 MHz + 100 ppm CLOCK SPECIFICATION Applies for TxC, FxC for NRZ: for Manchester, symmetry is needed: f min = 100 kHz + 100 ppm 1 f max = 10 MHz + 100 ppm 151, 152 = 9, #5% A.C. CHARACTERISTICS TRANSMIT AND RECEIVE TIMING PARAMETER SPECIFICATION® [_symbot | Parameter Min [Max [Comments | [me | Teoee CT t00 1000 Notes 14.2 | [te | Tote t00 Notes 8.2 | | te | TiCrisetime TT Notes | t50 | Trcrantime TT Noto ta [351 | TrCrigntimeesov | ao | 1000 | Notore | | tse | TrCtowtimeeooy || Notes 14 | [153 | teDrisetime TT 10 Notes 5,13 | [tse | toraitime 10 Notes 10 | i cia = 152) ~7 | 56 | TrClowtoTeDvais | Ta Notes 8.5 | | 157 | TrClowtoTeD Transition || 90 | Notes 25 | | 158 | TeCHightoTxDTransiton || 90 | Notes 2.5 | | 159 | TrCLowtoTsDHighattheTranemissionend || 40 | Notes | | to | _THCLowtoRTSLow.TimetoAcivatoATS [| 40 [Notes | | ter | CTSvaidtoTClow.cTSseuptine | 4s | | tee | TCLowtoCTSinvaid. CTSHodTime | 20 || Note? | | 163 | TiCLowtoRTSHigh tmetoDesctvatoATS [| 40 | Notes | | tee | FC oocKoyto Tt Nets 15.9 | | tes | FxCricotime TT Notts | | tes | FCravtime TT Notts | | ter | PxCHightimeea7v | a6 | 1000 | Notes | [tee | Fit Lowtine soo ro Nos | “Ail units are in ns. 1-34
intel. 82586 A.C. CHARACTERISTICS (Continued) TRANSMIT AND RECEIVE TIMING PARAMETER SPECIFICATION’ (Continued) RECEIVE DATA PARAMETERS. : xD Sotup Time [so | | Noter | RxD Hold Time [30 [| Noter | x0 Fall Timo [ | 0 | Noto | { CARRIER SENSE/COLLISION DETECT PARAMETERS 173 CDT Valid to Tx High Ext. Collision Detect Setup Time CDT Low to Jamming Start ee ee GRE Valid to TxC High Ext. Carrier Sense Setup Time | 30 | | Note12 | TiC High to CRS Inactive. CRS Hold Time [ 2 | | Noter2 | GR Low to Jamming Start PT Notes | Jamming Period [fT Note 10 | Tso * GRE Inactive Setup Time to RxC High End of Receive Frame INTERFRAME SPACING PARAMETER Inter Frame Delay [fT Noto | *All units are in ns. NOTES: 1. TTL levels: 2. Manchester only 3. NRZ only 4, Manchester requires 50% duty cycle 5.1 TTL load + 50 pF.
6.1 TTL load + 100 pF
- Abnormal end of transmission. CTS expires before RTS 8. Programmable value: 175 = NCDF x T48 + (12.5 to 23.5) x T48 if collision occurs after preamble NCDF—The collision detection filter configuration value 9. Programmable value: 178 = NCSF x T48 + (12.5 to 23.5) x T48 NCSF—The carrier sense filter configuration value TBD is a function of internal/external carrier sense bit 10. 179 = 32 x T48 11. Programmable value: T82 = NIFS x T48 NIFS—the IFS configuration value "12. To guarantee recognition on the next clock 13. Applies to TTL levels 14. 82C501 compatible levels, see Figure 34 15. 82C501 compatible levels, see Figure 35 1-35