80C186EA INTEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 50
Technical content
*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. October 1995 COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 272432-003 80C186EA/80C188EA AND 80L186EA/80L188EA 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS Y 80C186 Upgrade for Power Critical Applications Y Fully Static Operation Y True CMOS Inputs and Outputs Y Integrated Feature Set Ð Static 186 CPU Core Ð Power Save, Idle and Powerdown Modes Ð Clock Generator Ð 2 Independent DMA Channels Ð 3 Programmable 16-Bit Timers Ð Dynamic RAM Refresh Control Unit Ð Programmable Memory and Peripheral Chip Select Logic Ð Programmable Wait State Generator Ð Local Bus Controller Ð System-Level Testing Support (High Impedance Test Mode) Y Speed Versions Available (5V): Ð 25 MHz (80C186EA25/80C188EA25) Ð 20 MHz (80C186EA20/80C188EA20) Ð 13 MHz (80C186EA13/80C188EA13) Y Speed Versions Available (3V): Ð 13 MHz (80L186EA13/80L188EA13) Ð 8 MHz (80L186EA8/80L188EA8) Y Direct Addressing Capability to
1 Mbyte Memory and 64 Kbyte I/O
Y Supports 80C187 Numeric Coprocessor Interface (80C186EA only) Y Available in the Following Packages: Ð 68-Pin Plastic Leaded Chip Carrier (PLCC) Ð 80-Pin EIAJ Quad Flat Pack (QFP) Ð 80-Pin Shrink Quad Flat Pack (SQFP) Y Available in Extended Temperature Range ( b40§Ct o a85§C) The 80C186EA is a CHMOS high integration embedded microprocessor. The 80C186EA includes all of the features of an ‘‘Enhanced Mode’’ 80C186 while adding the additional capabilities of Idle and Powerdown Modes. In Numerics Mode, the 80C186EA interfaces directly with an 80C187 Numerics Coprocessor. 272432–1
80C186EA/80C188EA, 80L186EA/80L188EA 80C186EA/80C188EA AND 80L186EA/80L188EA 16-Bit High Integration Embedded Processor CONTENTS PAGE INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 80C186EA CORE ARCHITECTURE ÀÀÀÀÀÀÀ 4 Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 80C186EA PERIPHERAL ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5 Interrupt Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5 Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5 DMA Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Chip-Select Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Power Management ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 80C187 Interface (80C186EA Only) ÀÀÀÀÀÀÀÀÀ 8 ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 DIFFERENCES BETWEEN THE 80C186XL AND THE 80C186EA ÀÀÀÀÀÀÀÀ 8 Pinout Compatibility ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 Operating Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 TTL vs CMOS Inputs ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 Timing Specifications ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 Prefix Identification ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 80C186EA Pinout ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15 CONTENTS PAGE PACKAGE THERMAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 21 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21 Recommended Connections ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21 DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 ICC versus Frequency and Voltage ÀÀÀÀÀÀÀÀÀ 24 PDTMR Pin Delay Calculation ÀÀÀÀÀÀÀÀÀÀÀÀÀ 24 AC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25 AC CharacteristicsÐ80C186EA20/13 ÀÀÀÀÀ 25 AC CharacteristicsÐ80L186EA13/8 ÀÀÀÀÀÀÀ 27 Relative Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29 AC TEST CONDITIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30 AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30 DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33 RESET ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33 BUS CYCLE WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36 EXECUTION TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43 INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 44 REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 50 ERRATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 50
Figure 1. 80C186EA/80C188EA Block Diagram
80C186EA/80C188EA, 80L186EA/80L188EA INTRODUCTION Unless specifically noted, all references to the 80C186EA apply to the 80C188EA, 80L186EA, and 80L188EA. References to pins that differ between the 80C186EA/80L186EA and the 80C188EA/ 80L188EA are given in parentheses. The ‘‘L’’ in the part number denotes low voltage operation. Physi- cally and functionally, the ‘‘C’’ and ‘‘L’’ devices are identical. The 80C186EA is the second product in a new gen- eration of low-power, high-integration microproces- sors. It enhances the existing 80C186XL family by offering new features and operating modes. The 80C186EA is object code compatible with the 80C186XL embedded processor. The 80L186EA is the 3V version of the 80C186EA. The 80L186EA is functionally identical to the 80C186EA embedded processor. Current 80C186EA customers can easily upgrade their de- signs to use the 80L186EA and benefit from the re- duced power consumption inherent in 3V operation. The feature set of the 80C186EA/80L186EA meets the needs of low-power, space-critical applications. Low-power applications benefit from the static de- sign of the CPU core and the integrated peripherals as well as low voltage operation. Minimum current consumption is achieved by providing a Powerdown Mode that halts operation of the device, and freezes the clock circuits. Peripheral design enhancements ensure that non-initialized peripherals consume little current. Space-critical applications benefit from the inte- gration of commonly used system peripherals. Two flexible DMA channels perform CPU-independent data transfers. A flexible chip select unit simplifies memory and peripheral interfacing. The interrupt unit provides sources for up to 128 external interrupts and will prioritize these interrupts with those generat- ed from the on-chip peripherals. Three general pur- pose timer/counters round out the feature set of the 80C186EA. Figure 1 shows a block diagram of the 80C186EA/ 80C188EA. The Execution Unit (EU) is an enhanced
8086 CPU core that includes: dedicated hardware to
speed up effective address calculations, enhance execution speed for multiple-bit shift and rotate in- structions and for multiply and divide instructions, string move instructions that operate at full bus bandwidth, ten new instructions, and static opera- tion. The Bus Interface Unit (BIU) is the same as that found on the original 80C186 family products. An independent internal bus is used to allow communi- cation between the BIU and internal peripherals. 80C186EA CORE ARCHITECTURE Bus Interface Unit The 80C186EA core incorporates a bus controller that generates local bus control signals. In addition, it employs a HOLD/HLDA protocol to share the local bus with other bus masters. The bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle status information and data (for write operations) in- formation. It is also responsible for reading data off the local bus during a read operation. SRDY and ARDY input pins are provided to extend a bus cycle beyond the minimum four states (clocks). The local bus controller also generates two control signals (DEN and DT/R ) when interfacing to exter- nal transceiver chips. This capability allows the addi- tion of transceivers for simple buffering of the mulit- plexed address/data bus. Clock Generator The processor provides an on-chip clock generator for both internal and external clock generation. The clock generator features a crystal oscillator, a divide- by-two counter, and two low-power operating modes. The oscillator circuit is designed to be used with ei- ther a parallel resonant fundamental or third-over- tone mode crystal network. Alternatively, the oscilla- tor circuit may be driven from an external clock source. Figure 2 shows the various operating modes of the oscillator circuit. The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter. This counter is used to drive all internal phase clocks and the exter- nal CLKOUT signal. CLKOUT is a 50% duty cycle processor clock and can be used to drive other sys- tem components. All AC timings are referenced to CLKOUT. The following parameters are recommended when choosing a crystal: Temperature Range: Application Specific ESR (Equivalent Series Resistance): 60 X max C0 (Shunt Capacitance of Crystal): 7.0 pF max C L (Load Capacitance): 20 pF g 2p F Drive Level: 2 mW max
Figure 3. Peripheral Control Block Registers
30 Interrupt Status
32 TMR0 Interrupt Control
34 DMA0 Interrupt Control
36 DMA1 Interrupt Control
38 TMR1 Interrupt Control
Figure 4. 80C186EA Slave Mode Peripheral even-aligned word transfers proceed at a faster rate. priority than general processor execution cycles. CPU, the DMA unit, or the Refresh Control Unit. dress block to be located on any 8 Kbyte boundary. 80C186EA to exit Power Save Mode. all peripherals operate normally.
80C186EA/80C188EA, 80L186EA/80L188EA 80C187 Interface (80C186EA Only) The 80C187 Numerics Coprocessor may be used to extend the 80C186EA instruction set to include floating point and advanced integer instructions. Connecting the 80C186EA RESOUT and TEST BUSY pins to the 80C187 enables Numerics Mode operation. In Numerics Mode, three of the four Mid- Range Chip Select (MCS ) pins become handshaking pins for the interface. The exchange of data and control information proceeds through four dedicated I/O ports. If an 80C187 is not present, the 80C186EA config- ures itself for regular operation at reset. NOTE: The 80C187 is not specified for 3V operation and therefore does not interface directly to the 80L186EA. ONCE Test Mode To facilitate testing and inspection of devices when fixed into a target system, the 80C186EA has a test mode available which forces all output and input/ output pins to be placed in the high-impedance state. ONCE stands for ‘‘ON Circuit Emulation’’. The ONCE mode is selected by forcing the UCS and LCS pins LOW (0) during a processor reset (these pins are weakly held to a HIGH (1) level) while RESIN is active. DIFFERENCES BETWEEN THE 80C186XL AND THE 80C186EA The 80C186EA is intended as a direct functional up- grade for 80C186XL designs. In many cases, it will be possible to replace an existing 80C186XL with little or no hardware redesign. The following sections describe differences in pinout, operating modes, and AC and DC specifications to keep in mind. Pinout Compatibility The 80C186EA requires a PDTMR pin to time the processor’s exit from Powerdown Mode. The original pin arrangement for the 80C186XL in the PLCC package did not have any spare leads to use for PDTMR, so the DT/R pin was sacrificed. The ar- rangement of all the other leads in the 68-lead PLCC is identical between the 80C186XL and the 80C186EA. DT/R may be synthesized by latching the S1 status output. Therefore, upgrading a PLCC 80C186XL to PLCC 80C186EA is straightforward. The 80-lead QFP (EIAJ) pinouts are different be- tween the 80C186XL and the 80C186EA. In addition to the PDTMR pin, the 80C186EA has more power and ground pins and the overall arrangement of pins was shifted. A new circuit board layout for the 80C186EA is required. Operating Modes The 80C186XL has two operating modes, Compati- ble and Enhanced. Compatible Mode is a pin-to-pin replacement for the NMOS 80186, except for nu- merics coprocessing. In Enhanced Mode, the proc- essor has a Refresh Control Unit, the Power-Save feature and an interface to the 80C187 Numerics Coprocessor. The MCS0 , MCS1 , and MCS3 pins change their functions to constitute handshaking pins for the 80C187. The 80C186EA allows all non-80C187 users to use all the MCS pins for chip-selects. In regular opera- tion, all 80C186EA features (including those of the Enhanced Mode 80C186) are present except for the interface to the 80C187. Numerics Mode disables the three chip-select pins and reconfigures them for connection to the 80C187. TTL vs CMOS Inputs The inputs of the 80C186EA are rated for CMOS switching levels for improved noise immunity, but the 80C186XL inputs are rated for TTL switching levels. In particular, the 80C186EA requires a minimum V IH of 3.5V to recognize a logic one while the 80C186XL requires a minimum V IH of only 1.9V (assuming 5.0V operation). The solution is to drive the 80C186EA with true CMOS devices, such as those from the HC and AC logic families, or to use pullup resistors where the added current draw is not a problem. Timing Specifications 80C186EA timing relationships are expressed in a simplified format over the 80C186XL. The AC per- formance of an 80C186EA at a specified frequency will be very close to that of an 80C186XL at the same frequency. Check the timings applicable to your design prior to replacing the 80C186XL.
80C186EA/80C188EA, 80L186EA/80L188EA
PACKAGE INFORMATION
This section describes the pins, pinouts, and thermal characteristics for the 80C186EA in the Plastic Leaded Chip Carrier (PLCC) package, Shrink Quad Flat Pack (SQFP), and Quad Flat Pack (QFP) pack- age. For complete package specifications and infor- mation, see the Intel Packaging Outlines and Dimen- sions Guide (Order Number: 231369). With the extended temperature range operational characteristics are guaranteed over a temperature range corresponding to b40§Ct o a85§C ambient. Package types are identified by a two-letter prefix to the part number. The prefixes are listed in Table 1. Table 1. Prefix Identification
- The 25 MHz version is only available in commercial tem-
perature range corresponding to 0 §Ct o a70§C ambient.
- There are three columns for each entry in the Pin
3 lists all the possible symbols for this column. (asynchronous or synchronous). istics for input pins are S(E), S(L), A(E) and A(L). state as a function of the device operating mode. ble characteristics in Table 2.
Table 2. Pin Description Nomenclature
Table 3. Pin Descriptions externally to a V CC board plane. externally to a V SS board plane. driven to a known state, and RESOUT will also be driven active. 80C186EA into Numerics Mode. characteristics of the crystal oscillator. serviced by the CPU. NMI is latched internally. 80C186EA of 80C187 Numerics Coprocessor activity. transferred during the data phase of the bus cycle. Pin names in parentheses apply to the 80C188EA and 80L188EA.
Table 3. Pin Descriptions (Continued) queue status information along with QS1. indicate a Refresh bus cycle. Pin names in parentheses apply to the 80C188EA and 80L188EA.
ARDY I A(L) Asychronous ReaDY is an input to signal for the end of a bus cycle. SRDY I S(L) Synchronous ReaDY is an input to signal for the end of a bus cycle. held high input while RESIN is active and must not be driven low. another bus master to drive the signals directly. LCS are used to enable ONCE Mode. are used to enable ONCE Mode. Pin names in parentheses apply to the 80C188EA and 80L188EA.
the processor accesses the 80C187. programmed to provide latched Address A2:1 signals. SELECT when the ICU is configured for Slave Mode. ICU is configured for Slave Mode. Pin names in parentheses apply to the 80C188EA and 80L188EA.
(i.e., contacts facing down). Table 4. PLCC Pin Names with Package Location Pin names in parentheses apply to the 80C188EA/80L188EA.
Table 5. PLCC Package Location with Pin Names
1 AD15 (A15)
2 AD7
3 AD14 (A14)
4 AD6
5 AD13 (A13)
6 AD5
7 AD12 (A12)
8 AD4
10 AD11 (A11)
11 AD3
12 AD10 (A10)
13 AD2
14 AD9 (A9)
15 AD1
16 AD8 (A8)
17 AD0
18 DRQ0
19 DRQ1
20 T0IN
21 T1IN
22 T0OUT
23 T1OUT
24 RESIN
25 PCS0
26 V SS
27 PCS1
28 PCS2
29 PCS3
30 PCS4
31 PCS5 /A1
32 PCS6 /A2
33 LCS
34 UCS
35 MCS3 /NCS
36 MCS2
37 MCS1 /ERROR
38 MCS0 /PEREQ
39 DEN
40 PDTMR
41 INT3/INTA1
42 INT2/INTA0
43 V CC
44 INT1/SELECT
45 INT0
46 NMI
47 TEST
48 LOCK
49 SRDY
50 HOLD
51 HLDA
55 ARDY
56 CLKOUT
57 RESOUT
58 OSCOUT
59 CLKIN
61 ALE/QS0
63 WR /QS1
64 BHE (RFSH)
65 A19/S6
66 A18
67 A17
68 A16
Pin names in parentheses apply to the 80C186EA/80L188EA.
- The nine-character alphanumeric code (XXXXXXXXD) underneath the product number is the Intel FPO number.
- Pin names in parentheses apply to the 80C186EA/80L188EA.
Figure 5. 68-Lead PLCC Pinout Diagram
Table 6. QFP (EIAJ) Pin Names with Package Location Pin names in parentheses apply to the 80C186EA/80L188EA.
Table 7. QFP (EIAJ) Package Location with Pin Names
1 AD15 (A15) 21 S2 41 MCS1 /ERROR 61 DRQ0
4 A17 24 V SS 44 V CC 64 AD0
5 A18 25 HLDA 45 UCS 65 AD8 (A8)
6 A19/S6 26 HOLD 46 LCS 66 AD1
7 BHE (RFSH) 27 SRDY 47 PCS6 /A2 67 AD9 (A9)
10 ALE/QS0 30 NMI 50 PCS3 70 AD3
12 V SS 32 INT1/SELECT 52 PCS1 72 V CC
13 V SS 33 V CC 53 V SS 73 V CC
16 CLKIN 36 INT3/INTA1 / 56 T1OUT 76 AD5
17 OSCOUT IRQ 57 T0OUT 77 AD13 (A13)
18 RESOUT 37 DT/R
58 T1IN 78 AD6
19 CLKOUT 38 PDTMR 59 T0IN 79 AD14 (A14)
20 ARDY 39 DEN
60 DRQ1 80 AD7
40 MCS0 /PEREQ
Pin names in parentheses apply to the 80C186EA/80L188EA.
- The nine-character alphanumeric code (XXXXXXXXD) underneath the product number is the Intel FPO number.
- Pin names in parentheses apply to the 80C186EA/80L188EA.
Figure 6. Quad Flat Pack (EIAJ) Pinout Diagram
Table 8. SQFP Pin Functions with Package Location Pin names in parentheses apply to the 80C186EA/80L188EA. Table 9. SQFP Pin Locations with Pin Names
1 AD0
2 AD8 (A8)
3 AD1
5 AD9 (A9)
6 AD2
7 AD10 (A10)
8 AD3
9 AD11 (A11)
11 V CC
12 AD4
13 AD12 (A12)
14 AD5
15 AD13 (A13)
16 AD6
17 AD14 (A14)
18 AD7
19 AD15 (A15)
21 A16/S3
22 A17/S4
23 A18/S5
24 A19/S6
26 BHE
27 WR /QS1
28 RD/QSMD
29 ALE/QS0
31 V SS
34 RESET
36 CLKOUT
37 ARDY
41 V SS
42 HLDA
43 HOLD
44 SRDY
45 LOCK
46 TEST /BUSY
47 NMI
48 INT0
49 INT1/SELECT
50 V CC
51 V CC
52 INT2/INTA0
53 INT3/INTA1
54 DT/R
55 PDTMR
56 DEN
57 MCS0 /PEREQ
58 MCS1 /ERROR
59 MCS2
60 MCS3 /NPS
61 V CC
62 UCS
63 LCS
64 PCS6 /A2
65 PCS5 /A1
66 PCS4
67 PCS3
68 PCS2
69 PCS1
70 V SS
71 PCS0
73 RES
74 TMR OUT 1
75 TMR OUT 0
76 TMR IN 1
77 TMR IN 0
78 DRQ1
79 DRQ0
Pin names in parentheses apply to the 80C186EA/80L188EA.
Figure 7. Shrink Quad Flat Pack (SQFP) Pinout Diagram
- XXXXXXXXD indicates the Intel FPO number.
- Pin names in parentheses apply to the 80C188EA.
Table 10. Thermal Resistance ( iCA) at Various Airflows (in §C/Watt)
80C186EA/80C188EA, 80L186EA/80L188EA ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings * Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Case Temperature under Bias ÀÀÀ b65§Ct o a150§C Supply Voltage with Respect to V SS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀb0.5V to a6.5V Voltage on Other Pins with Respect to V SS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀb0.5V to V CC a 0.5V NOTICE: This data sheet contains preliminary infor- mation on new products in production. It is valid for the devices indicated in the revision history. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. Recommended Connections Power and ground connections must be made to multiple V CC and V SS pins. Every 80C186EA based circuit board should contain separate power (V CC) and ground (V SS) planes. All V CC and V SS pins must be connected to the appropriate plane. Pins identi- fied as ‘‘N.C.’’ must not be connected in the system. Decoupling capacitors should be placed near the processor. The value and type of decoupling capac- itors is application and board layout dependent. The processor can cause transient power surges when its output buffers transition, particularly when con- nected to large capacitive loads. Always connect any unused input pins to an appro- priate signal level. In particular, unused interrupt pins (NMI, INT3:0) should be connected to V SS to avoid unwanted interrupts. Leave any unused output pin or any ‘‘N.C.’’ pin unconnected.
80C186EA/80C188EA, 80L186EA/80L188EA DC SPECIFICATIONS (80C186EA/80C188EA) Symbol Parameter Min Max Units Conditions VCC Supply Voltage 4.5 5.5 V VIL Input Low Voltage for All Pins b0.5 0.3 V CC V VIH Input High Voltage for All Pins 0.7 V CC VCC a 0.5 V VOL Output Low Voltage 0.45 V I OL e 3 mA (min) VOH Output High Voltage V CC b 0.5 V I OH eb 2 mA (min) VHYR Input Hysterisis on RESIN 0.30 V IIL1 Input Leakage Current (except g10 mA0 V s VIN s VCC RD/QSMD, UCS , LCS , MCS0 /PEREQ, MCS1/ERROR, LOCK and TEST /BUSY) IIL2 Input Leakage Current b275 mAV IN e 0.7 V CC (RD/QSMD, UCS , LCS , MCS0 /PEREQ, (Note 1) MCS1, ERROR , LOCK and TEST /BUSY IOL Output Leakage Current g10 mA 0.45 s VOUT s VCC (Note 2) ICC Supply Current Cold (RESET) 80C186EA25/80C188EA25 105 mA (Notes 3, 5) 80C186EA20/80C188EA20 90 mA 80C186EA13/80C188EA13 65 mA IID Supply Current In Idle Mode 80C186EA25/80C188EA25 90 mA (Note 5) 80C186EA20/80C188EA20 70 mA 80C186EA13/80C188EA13 46 mA IPD Supply Current In Powerdown Mode 80C186EA25/80C188EA25 100 mA (Note 5) 80C186EA20/80C188EA20 100 mA 80C186EA13/80C188EA13 100 mA COUT Output Pin Capacitance 0 15 pF T F e 1 MHz (Note 4) CIN Input Pin Capacitance 0 15 pF T F e 1 MHz NOTES: 1. RD /QSMD, UCS , LCS , MCS0 /PEREQ, MCS1 /ERROR, LOCK and TEST /BUSY have internal pullups that are only acti- vated during RESET. Loading these pins above I OL eb 275 mA will cause the processor to enter alternate modes of operation. 2. Output pins are floated using HOLD or ONCE Mode. 3. Measured at worst case temperature and V CC with all outputs loaded as specified in the AC Test Conditions, and with the device in RESET (RESIN held low). RESET is worst case for I CC. 4. Output capacitance is the capacitive load of a floating output pin. 5. Operating conditions for 25 MHz are 0 §Ct o a70§C, V CC e 5.0V g10%.
80C186EA/80C188EA, 80L186EA/80L188EA DC SPECIFICATIONS (80L186EA/80L188EA) Symbol Parameter Min Max Units Conditions VCC Supply Voltage 2.7 5.5 V VIL Input Low Voltage for All Pins b0.5 0.3 V CC V VIH Input High Voltage for All Pins 0.7 V CC VCC a 0.5 V VOL Output Low Voltage 0.45 V I OL e 1.6 mA (min) VOH Output High Voltage V CC b 0.5 V I OH eb 1 mA (min) VHYR Input Hysterisis on RESIN 0.30 V IIL1 Input Leakage Current (except g10 mA0 V s VIN s VCC RD/QSMD, UCS , LCS , MCS0 /PEREQ, MCS1, LOCK and TEST ) IIL2 Input Leakage Current b275 mAV IN e 0.7 V CC (RD/QSMD, UCS , LCS , MCS0 , (Note 1) MCS1, LOCK and TEST ) IOL Output Leakage Current g10 mA 0.45 s VOUT s VCC (Note 2) ICC5 Supply Current (RESET, 5.5V) 80L186EA-13 65 mA (Note 3) 80L186EA-8 40 mA (Note 3) ICC3 Supply Current (RESET, 2.7V) 80L186EA-13 34 mA (Note 3) 80L186EA-8 20 mA (Note 3) IID5 Supply Current Idle (5.5V) 80L186EA-13 46 mA 80L186EA-8 28 mA IID5 Supply Current Idle (2.7V) 80L186EA-13 24 mA 80L186EA-8 14 mA IPD5 Supply Current Powerdown (5.5V) 80L186EA-13 100 mA 80L186EA-8 100 mA IPD3 Supply Current Powerdown (2.7V) 80L186EA-13 50 mA 80L186EA-8 50 mA COUT Output Pin Capacitance 0 15 pF T F e 1 MHz (Note 4) CIN Input Pin Capacitance 0 15 pF T F e 1 MHz NOTES: 1. RD /QSMD, UCS , LCS , MCS0 , MCS1 , LOCK and TEST have internal pullups that are only activated during RESET. Loading these pins above I OL eb 275 mA will cause the processor to enter alternate modes of operation. 2. Output pins are floated using HOLD or ONCE Mode. 3. Measured at worst case temperature and V CC with all outputs loaded as specified in the AC Test Conditions, and with the device in RESET (RESIN held low). 4. Output capacitance is the capacitive load of a floating output pin.
and is typically less than 50 mA. quency within the specified operating range. crystal or resonator circuit time to stabilize. and/or higher temperature will increase delay time. Table 11. C DEV Values
- Max C DEV is calculated at b40§C, all floating outputs driven to V CC or GND, and all
outputs loaded to 50 pF (including CLKOUT and OSCOUT). OSCOUT, which are not loaded.
80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS AC CharacteristicsÐ80C186EA25/80C186EA20/80C186EA13 Symbol Parameter Min Max Min Max Min Max Units Notes INPUT CLOCK 25 MHz (12) 20 MHz 13 MHz TF CLKIN Frequency 0 50 0 40 0 26 MHz 1 TC CLKIN Period 20 % 25 % 38.5 % ns 1 TCH CLKIN High Time 10 % 10 % 12 % ns 1, 2 TCL CLKIN Low Time 10 % 10 % 12 % ns 1, 2 TCR CLKIN Rise Time 1 8 1 8 1 8 ns 1, 3 TCF CLKIN Fall Time 1 8 1 8 1 8 ns 1, 3 OUTPUT CLOCK TCD CLKIN to CLKOUT Delay 0 15 0 17 0 23 ns 1, 4 T CLKOUT Period 2T C 2*TC 2*TC ns 1 TPH CLKOUT High Time (T/2) b 5 (T/2) b 5 (T/2) b 5n s 1 TPL CLKOUT Low Time (T/2) b 5 (T/2) b 5 (T/2) b 5n s 1 TPR CLKOUT Rise Time 1 6 1 6 1 6 ns 1, 5 TPF CLKOUT Fall Time 1 6 1 6 1 6 ns 1, 5 OUTPUT DELAYS TCHOV1 ALE, S2:0 , DEN , DT/R , 3 20 3 22 3 25 ns 1, 4, 6, 7 BHE, (RFSH ), LOCK , A19:16 TCHOV2 MCS3:0, LCS , UCS , PCS6:0 , 3 25 3 27 3 30 ns 1, 4, 6, 8 NCS,R D ,W R TCLOV1 BHE (RFSH), DEN , LOCK , 3 20 3 22 3 25 ns 1, 4, 6 RESOUT, HLDA, T0OUT, T1OUT, A19:16 TCLOV2 RD,W R , MCS3:0 , LCS , 3 25 3 27 3 30 ns 1, 4, 6 UCS, PCS6:0 , AD15:0 (A15:8, AD7:0), NCS, INTA1:0 , S2:0 TCHOF RD,W R , BHE (RFSH), DT/R , 0 25 0 25 0 25 ns 1 LOCK, S2:0 , A19:16 TCLOF DEN, AD15:0 (A15:8, AD7:0) 0 25 0 25 0 25 ns 1
80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS (Continued) AC CharacteristicsÐ80C186EA25/80C186EA20/80C186EA13 Symbol Parameter Min Max Min Max Min Max Units Notes SYNCHRONOUS INPUTS 25 MHz (12) 20 MHz 13 MHz TCHIS TEST, NMI, INT3:0, 8 10 10 ns 1, 9 T1:0IN, ARDY TCHIH TEST, NMI, INT3:0, 3 3 3 ns 1, 9 T1:0IN, ARDY TCLIS AD15:0 (AD7:0), ARDY, 10 10 10 ns 1, 10 SRDY, DRQ1:0 TCLIH AD15:0 (AD7:0), ARDY, 3 3 3 ns 1, 10 SRDY, DRQ1:0 TCLIS HOLD, PEREQ, ERROR 10 10 10 ns 1, 9 (80C186EA Only) TCLIH HOLD, PEREQ, ERROR 333 n s 1 , 9 (80C186EA Only) TCLIS RESIN (to CLKIN) 10 10 10 ns 1, 9 TCLIH RESIN (from CLKIN) 3 3 3 ns 1, 9 NOTES: 1. See AC Timing Waveforms , for waveforms and definition. 2. Measured at V IH for high time, V IL for low time. 3. Only required to guarantee I CC. Maximum limits are bounded by T C,T CH and T CL. 4. Specified for a 50 pF load, see Figure 13 for capacitive derating information. 5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF. 6. See Figure 14 for rise and fall times. 7. T CHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release. 8. T CHOV2 applies to RD and WR only after a HOLD release. 9. Setup and Hold are required to guarantee recognition. 10. Setup and Hold are required for proper operation. 11. T CHOVS applies to BHE (RFSH) and A19:16 only after a HOLD release. 12. Operating conditions for 25 MHz are 0 §Ct o a70§C, V CC e 5.0V g10%. Pin names in parentheses apply to the 80C188EA/80L188EA.
80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS AC CharacteristicsÐ80L186EA13/80L186EA8 Symbol Parameter Min Max Min Max Units Notes INPUT CLOCK 13 MHz 8 MHz TF CLKIN Frequency 0 26 0 16 MHz 1 TC CLKIN Period 38.5 % 62.5 % ns 1 TCH CLKIN High Time 12 % 12 % ns 1, 2 TCL CLKIN Low Time 12 % 12 % ns 1, 2 TCR CLKIN Rise Time 1 8 1 8 ns 1, 3 TCF CLKIN Fall Time 1 8 1 8 ns 1, 3 OUTPUT CLOCK TCD CLKIN to CLKOUT Delay 0 45 0 95 ns 1, 4 T CLKOUT Period 2 *TC 2*TC ns 1 TPH CLKOUT High Time (T/2) b 5 (T/2) b 5n s 1 TPL CLKOUT Low Time (T/2) b 5 (T/2) b 5n s 1 TPR CLKOUT Rise Time 1 12 1 12 ns 1, 5 TPF CLKOUT Fall Time 1 12 1 12 ns 1, 5 OUTPUT DELAYS TCHOV1 ALE, LOCK 3 2 7 3 2 7 n s 1 ,4 ,6 ,7 TCHOV2 MCS3:0, LCS , UCS , 33 233 2 n s 1 , 4 , PCS6:0,R D ,W R 6, 8 TCHOV3 S2:0 (DEN), DT/R , 33 033 0 n s 1 BHE (RFSH), A19:16 TCLOV1 LOCK, RESOUT, HLDA, 3 27 3 27 ns 1, 4, 6 T0OUT, T1OUT TCLOV2 RD,W R , MCS3:0 , LCS , 3 3 2 3 3 5 n s 1 ,4 ,6 UCS, PCS6:0 , INTA1:0 TCLOV3 BHE (RFSH), DEN , A19:16 3 30 3 30 ns 1, 4, 6 TCLOV4 AD15:0 (A15:8, AD7:0) 3 34 3 35 ns 1, 4, 6 TCLOV5 S2:0 3 3 8 3 4 0 n s 1 ,4 ,6 TCHOF RD,W R , BHE (RFSH) , 02 702 7 n s 1 DT/R, LOCK , S2:0, A19:16 TCLOF DEN, AD15:0 (A15:8, AD7:0) 0 27 0 27 ns 1 NOTES: 1. See AC Timing Waveforms , for waveforms and definition. 2. Measured at V IH for high time, V IL for low time. 3. Only required to guarantee I CC. Maximum limits are bounded by T C,T CH and T CL. 4. Specified for a 50 pF load, see Figure 13 for capacitive derating information. 5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF. 6. See Figure 14 for rise and fall times. 7. T CHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release. 8. T CHOV2 applies to RD and WR only after a HOLD release. 9. Setup and Hold are required to guarantee recognition. 10. Setup and Hold are required for proper operation. 11. T CHOVS applies to BHE (RFSH) and A19:16 only after a HOLD release. 12. Pin names in parentheses apply to the 80C188EA/80L188EA.
80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS AC CharacteristicsÐ80L186EA13/80L186EA8 Symbol Parameter Min Max Min Max Units Notes SYNCHRONOUS INPUTS 13 MHz 8 MHz TCHIS TEST, NMI, INT3:0, T1:0IN, ARDY 22 22 ns 1, 9 TCHIH TEST, NMI, INT3:0, T1:0IN, ARDY 3 3 ns 1, 9 TCLIS AD15:0 (AD7:0), ARDY, SRDY, DRQ1:0 22 22 ns 1, 10 TCLIH AD15:0 (AD7:0), ARDY, SRDY, DRQ1:0 3 3 ns 1, 10 TCLIS HOLD 22 22 ns 1, 9 TCLIH HOLD 3 3 ns 1, 9 TCLIS RESIN (to CLKIN) 22 22 ns 1, 9 TCLIH RESIN (from CLKIN) 3 3 ns 1, 9 NOTES: 1. See AC Timing Waveforms , for waveforms and definition. 2. Measured at V IH for high time, V IL for low time. 3. Only required to guarantee I CC. Maximum limits are bounded by T C,T CH and T CL. 4. Specified for a 50 pF load, see Figure 13 for capacitive derating information. 5. Specified for a 50 pF load, see Figure 14 for rise and fall times outside 50 pF. 6. See Figure 14 for rise and fall times. 7. T CHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release. 8. T CHOV2 applies to RD and WR only after a HOLD release. 9. Setup and Hold are required to guarantee recognition. 10. Setup and Hold are required for proper operation. 11. T CHOVS applies to BHE (RFSH) and A19:16 only after a HOLD release. 12. Pin names in parentheses apply to the 80C188EA/80L188EA.
80C186EA/80C188EA, 80L186EA/80L188EA AC SPECIFICATIONS (Continued) Relative Timings (80C186EA25/20/13, 80L186EA13/8) Symbol Parameter Min Max Unit Notes RELATIVE TIMINGS TLHLL ALE Rising to ALE Falling T b 15 ns TAVLL Address Valid to ALE Falling (/2T b 10 ns TPLLL Chip Selects Valid to ALE Falling (/2T b 10 ns 1 TLLAX Address Hold from ALE Falling (/2T b 10 ns TLLWL ALE Falling to WR Falling (/2T b 15 ns 1 TLLRL ALE Falling to RD Falling (/2T b 15 ns 1 TRHLH RD Rising to ALE Rising (/2T b 10 ns 1 TWHLH WR Rising to ALE Rising (/2T b 10 ns 1 TAFRL Address Float to RD Falling 0 ns TRLRH RD Falling to RD Rising (2 *T) b 5n s 2 TWLWH WR Falling to WR Rising (2 *T) b 5n s 2 TRHAV RD Rising to Address Active T b 15 ns TWHDX Output Data Hold after WR Rising T b 15 ns TWHDEX WR Rising to DEN Rising (/2T b 10 ns 1 TWHPH WR Rising to Chip Select Rising (/2T b 10 ns 1, 4 TRHPH RD Rising to Chip Select Rising (/2T b 10 ns 1, 4 TPHPL CS Inactive to CS Active (/2T b 10 ns 1 TDXDL DEN Inactive to DT/R Low 0 ns 5 TOVRH ONCE (UCS , LCS ) Active to RESIN Rising T ns 3 TRHOX ONCE (UCS , LCS ) to RESIN Rising T ns 3 NOTES: 1. Assumes equal loading on both pins. 2. Can be extended using wait states. 3. Not tested. 4. Not applicable to latched A2:1. These signals change only on falling T 5. For write cycle followed by read cycle. 6. Operating conditions for 25 MHz are 0 §Ct o a70§C, V CC e 5.0V g10%.
- T DXDL for write cycle followed by read cycle.
- Pin names in parentheses apply to tthe 80C188EA.
Figure 12. Relative Signal Waveform
Figure 15. Powerup Reset Waveforms
- CLKOUT synchronization occurs approximately 1 (/2 CLKIN periods after RESIN is sampled low.
- Pin names in parentheses apply to the 80C188EA.
Figure 16. Warm Reset Waveforms
- CLKOUT resynchronization occurs approximately 1 (/2 CLKIN periods after RESIN is sampled low. If RESIN is sampled low while CLKOUT is transitioning high,
then CLKOUT will remain high for two CLKIN periods. If RESIN is sampled low while CLKOUT is transitioning high, then CLKOUT will not be affected.
- Pin names in parentheses apply to the 80C188EA.
- During the data phase of the bus cycle, A19/S6 is driven high for a DMA or refresh cycle.
- Pin names in parentheses apply to the 80C188EA.
Figure 17. Read, Fetch and Refresh Cycle Waveform
- During the data phase of the bus cycle, A19/S6 is driven high for a DMA cycle.
- Pin names in parentheses apply to the 80C188EA.
Figure 18. Write Cycle Waveform
- The processor drives these pins to 0 during Idle and Powerdown Modes.
- Pin names in parentheses apply to the 80C188EA.
Figure 19. Halt Cycle Waveform
- INTA occurs one clock later in Slave Mode.
- Pin names in parentheses apply to the 80C188EA.
Figure 20. INTA Cycle Waveform
- Pin names in parentheses apply to the 80C188EA.
Figure 21. HOLD/HLDA Waveform
- Pin names in parentheses apply to the 80C188EA.
Figure 22. DRAM Refresh Cycle During Hold Acknowledge
- Generalized diagram for READ or WRITE.
- ARDY low by either edge causes a wait state. Only rising ARDY is fully synchronized.
- SRDY low causes a wait state. SRDY must meet setup and hold times to ensure correct device operation.
- Either ARDY or SRDY active high will terminate a bus cycle.
- Pin names in parentheses apply to the 80C188EA.
Figure 23. Ready Waveform
80C186EA/80C188EA, 80L186EA/80L188EA 80C186EA/80C188EA EXECUTION TIMINGS A determination of program exeuction timing must consider the bus cycles necessary to prefetch in- structions as well as the number of execution unit cycles necessary to execute instructions. The fol- lowing instruction timings represent the minimum execution time in clock cycle for each instruction. The timings given are based on the following as- sumptions: # The opcode, along with any data or displacement required for execution of a particular instruction, has been prefetched and resides in the queue at the time it is needed. # No wait states or bus HOLDs occur. # All word-data is located on even-address bound- aries. (80C186EA only) All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address. All instructions which involve memory accesses can require one or two additional clocks above the mini- mum timings shown due to the asynchronous hand- shake between the bus interface unit (BIU) and exe- cution unit. With a 16-bit BIU, the 80C186EA has sufficient bus performance to endure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time. Therefore, actual program exeuc- tion time will not be substanially greater than that derived from adding the instruction timings shown. The 80C188EA 8-bit BIU is limited in its performance relative to the execution unit. A sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time. Therefore, actual program execution time will be substantially greater than that derived from adding the instruction timings shown.
80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY Function Format 80C186EA 80C188EA CommentsClock Clock Cycles Cycles DATA TRANSFER MOV e Move: Register to Register/Memory 1000100w m o dr e g r / m 2/12 2/12 * Register/memory to register 1000101w m o dr e g r / m 2 / 9 2 / 9 Immediate to register/memory 1100011w m o d0 0 0 r / m data data if w e1 12–13 12–13 8/16-bit Immediate to register 1011w r e g data data if w e1 3–4 3–4 8/16-bit Memory to accumulator 1010000w addr-low addr-high 8 8 * Accumulator to memory 1010001w addr-low addr-high 9 9 * Register/memory to segment register 10001110 m o d0r e g r / m 2 / 9 2/13 Segment register to register/memory 10001100 m o d0r e g r / m 2/11 2/15 PUSH e Push: Memory 11111111 m o d110 r / m 1 6 2 0 Register 01010 r e g 1 0 1 4 Segment register 000r e g110 9 1 3 Immediate 011010s0 data data if s e01 0 1 4 PUSHA e Push All 01100000 3 6 6 8 POP e Pop: Memory 10001111 m o d000 r / m 2 0 2 4 Register 01011 r e g 1 0 1 4 Segment register 000r e g111 (regi01) 8 12 POPA e P o pA l l 01100001 5 1 8 3 XCHG e Exchange: Register/memory with register 1000011w m o dr e g r / m 4/17 4/17 * Register with accumulator 10010 r e g 3 3 IN e Input from: Fixed port 1110010w port 10 10 * Variable port 1110110w 8 7 * OUT e Output to: Fixed port 1110011w port 9 9 * Variable port 1110111w 7 7 * XLAT e Translate byte to AL 11010111 1 1 1 5 LEA e Load EA to register 10001101 m o dr e g r / m 6 6 LDS e Load pointer to DS 11000101 m o dr e g r / m (modi11) 18 26 LES e Load pointer to ES 11000100 m o dr e g r / m (modi11) 18 26 LAHF e Load AH with flags 10011111 2 2 SAHF e Store AH into flags 10011110 3 3 PUSHF e Push flags 10011100 9 1 3 POPF e Pop flags 10011101 8 1 2 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA CommentsClock Clock Cycles Cycles DATA TRANSFER (Continued) SEGMENT e Segment Override: CS 00101110 2 2 SS 00110110 2 2 DS 00111110 2 2 ES 00100110 2 2 ARITHMETIC ADD e Add: Reg/memory with register to either 000000dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 100000sw m o d000 r / m data data if s w e01 4/16 4/16 * Immediate to accumulator 0000010w data data if w e1 3/4 3/4 8/16-bit ADC e Add with carry: Reg/memory with register to either 000100dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 100000sw m o d010 r / m data data if s w e01 4/16 4/16 * Immediate to accumulator 0001010w data data if w e1 3/4 3/4 8/16-bit INC e Increment: Register/memory 1111111w m o d000 r / m 3/15 3/15 * Register 01000 r e g 3 3 SUB e Subtract: Reg/memory and register to either 001010dw m o dr e g r / m 3/10 3/10 * Immediate from register/memory 100000sw m o d101 r / m data data if s w e01 4/16 4/16 * Immediate from accumulator 0010110w data data if w e1 3/4 3/4 8/16-bit SBB e Subtract with borrow: Reg/memory and register to either 000110dw m o dr e g r / m 3/10 3/10 * Immediate from register/memory 100000sw m o d011 r / m data data if s w e01 4/16 4/16 * Immediate from accumulator 0001110w data data if w e1 3/4 3/4 * 8/16-bit DEC e Decrement Register/memory 1111111w m o d001 r / m 3/15 3/15 * Register 01001 r e g 3 3 CMP e Compare: Register/memory with register 0011101w m o dr e g r / m 3/10 3/10 * Register with register/memory 0011100w m o dr e g r / m 3/10 3/10 * Immediate with register/memory 100000sw m o d111 r / m data data if s w e01 3/10 3/10 * Immediate with accumulator 0011110w data data if w e1 3/4 3/4 8/16-bit NEG e Change sign register/memory 1111011w m o d011 r / m 3/10* 3/10* AAA e ASCII adjust for add 00110111 8 8 DAA e Decimal adjust for add 00100111 4 4 AAS e ASCII adjust for subtract 00111111 7 7 DAS e Decimal adjust for subtract 00101111 4 4 MUL e Multiply (unsigned): 1111011w m o d1 0 0 r / m Register-Byte 26–28 26–28 Register-Word 35–37 35–37 Memory-Byte 32–34 32–34 Memory-Word 41–43 41–48 * Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA CommentsClock Clock Cycles Cycles ARITHMETIC (Continued) IMUL e Integer multiply (signed): 1111011w m o d101 r / m Register-Byte 25–28 25–28 Register-Word 34–37 34–37 Memory-Byte 31–34 32–34 Memory-Word 40–43 40–43 * IMUL e Integer Immediate multiply 011010s1 m o dr e g r / m data data if s e0 22–25 22-25 (signed) 29–32 29–32 DIV e Divide (unsigned): 1111011w m o d110 r / m Register-Byte 29 29 Register-Word 38 38 Memory-Byte 35 35 Memory-Word 44 44 * IDIV e Integer divide (signed): 1111011w m o d111 r / m Register-Byte 44–52 44–52 Register-Word 53–61 53–61 Memory-Byte 50–58 50–58 Memory-Word 59–67 59–67 * AAM e ASCII adjust for multiply 11010100 00001010 1 9 1 9 AAD e ASCII adjust for divide 11010101 00001010 1 5 1 5 CBW e Convert byte to word 10011000 2 2 CWD e Convert word to double word 10011001 4 4 LOGIC Shift/Rotate Instructions: Register/Memory by 1 1101000w m o dT T Tr / m 2/15 2/15 Register/Memory by CL 1101001w m o dT T Tr / m 5 an/17an5 an/17an Register/Memory by Count 1100000w m o dT T Tr / m count 5 an/17an5 an/17an TTT Instruction
000 R O L
001 R O R
010 R C L
011 R C R
101 S H R
111 S A R
AND e And: Reg/memory and register to either 001000dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d100 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0010010w data data if w e1 3/4 3/4 * 8/16-bit TESTeAnd function to flags, no result: Register/memory and register 1000010w m o dr e g r / m 3/10 3/10 * Immediate data and register/memory 1111011w m o d000 r / m data data if w e1 4/10 4/10 * Immediate data and accumulator 1010100w data data if w e1 3/4 3/4 8/16-bit OReOr: Reg/memory and register to either 000010dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d001 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0000110w data data if w e1 3/4 3/4 * 8/16-bit Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA CommentsClock Clock Cycles Cycles LOGIC (Continued) XOR e Exclusive or: Reg/memory and register to either 001100dw m o dr e g r / m 3/10 3/10 * Immediate to register/memory 1000000w m o d110 r / m data data if w e1 4/16 4/16 * Immediate to accumulator 0011010w data data if w e1 3/4 3/4 8/16-bit NOT e Invert register/memory 1111011w m o d010 r / m 3/10 3/10 * STRING MANIPULATION MOVS e Move byte/word 1010010w 1 4 1 4 * CMPS e Compare byte/word 1010011w 2 2 2 2 * SCAS e Scan byte/word 1010111w 1 5 1 5 * LODS e Load byte/wd to AL/AX 1010110w 1 2 1 2 * STOS e Store byte/wd from AL/AX 1010101w 1 0 1 0 * INS e Input byte/wd from DX port 0110110w 1 4 1 4 OUTS e Output byte/wd to DX port 0110111w 1 4 1 4 Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ) MOVS e Move string 11110010 1010010w 8 a8n 8 a8n* CMPS e Compare string 1111001z 1010011w 5 a22n 5 a22n SCAS e Scan string 1111001z 1010111w 5 a15n 5 a15n* LODS e Load string 11110010 1010110w 6 a11n 6 a11n* STOS e Store string 11110010 1010101w 6 a9n 6 a9n* INS e Input string 11110010 0110110w 8 a8n 8 a8n* OUTS e Output string 11110010 0110111w 8 a8n 8 a8n* CONTROL TRANSFER CALL e Call: Direct within segment 11101000 disp-low disp-high 15 19 Register/memory 11111111 m o d010 r / m 13/19 17/27 indirect within segment Direct intersegment 10011010 segment offset 23 31 segment selector Indirect intersegment 11111111 m o d011 r / m (mod i 11) 38 54 JMP e Unconditional jump: Short/long 11101011 disp-low 14 14 Direct within segment 11101001 disp-low disp-high 14 14 Register/memory 11111111 m o d100 r / m 11/17 11/21 indirect within segment Direct intersegment 11101010 segment offset 14 14 segment selector Indirect intersegment 11111111 m o d101 r / m (mod i 11) 26 34 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA CommentsClock Clock Cycles Cycles CONTROL TRANSFER (Continued) RET e Return from CALL: Within segment 11000011 1 6 2 0 Within seg adding immed to SP 11000010 data-low data-high 18 22 Intersegment 11001011 2 2 3 0 Intersegment adding immediate to SP 11001010 data-low data-high 25 33 JE/JZ e Jump on equal/zero 01110100 disp 4/13 4/13 JMP not JL/JNGE e Jump on less/not greater or equal 01111100 disp 4/13 4/13 taken/JMP JLE/JNG e Jump on less or equal/not greater 01111110 disp 4/13 4/13 taken JB/JNAE e Jump on below/not above or equal 01110010 disp 4/13 4/13 JBE/JNA e Jump on below or equal/not above 01110110 disp 4/13 4/13 JP/JPE e Jump on parity/parity even 01111010 disp 4/13 4/13 JO e Jump on overflow 01110 000 disp 4/13 4/13 JS e Jump on sign 01111000 disp 4/13 4/13 JNE/JNZ e Jump on not equal/not zero 01110101 disp 4/13 4/13 JNL/JGE e Jump on not less/greater or equal 01111101 disp 4/13 4/13 JNLE/JG e Jump on not less or equal/greater 01111111 disp 4/13 4/13 JNB/JAE e Jump on not below/above or equal 01110011 disp 4/13 4/13 JNBE/JA e Jump on not below or equal/above 01110111 disp 4/13 4/13 JNP/JPO e Jump on not par/par odd 01111011 disp 4/13 4/13 JNO e Jump on not overflow 01110001 disp 4/13 4/13 JNS e Jump on not sign 01111001 disp 4/13 4/13 JCXZ e Jump on CX zero 11100011 disp 5/15 5/15 LOOP e Loop CX times 11100010 disp 6/16 6/16 LOOP not LOOPZ/LOOPE e Loop while zero/equal 11100001 disp 6/16 6/16 taken/LOOP LOOPNZ/LOOPNE e Loop while not zero/equal 11100000 disp 6/16 6/16 taken ENTER e Enter Procedure 11001000 data-low data-high L L e 0 15 19 L e 1 25 29 L l 1 22a16(nb1) 26 a20(nb1) LEAVE e Leave Procedure 11001001 8 8 INT e Interrupt: Type specified 11001101 type 47 47 Type 3 11001100 4 5 4 5 i f INT. taken/ INTO e Interrupt on overflow 11001110 48/4 48/4 if INT. not taken IRET e Interrupt return 11001111 2 8 2 8 BOUND e Detect value out of range 01100010 m o dr e g r / m 3 3 – 3 5 3 3 – 3 5 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers.
80C186EA/80C188EA, 80L186EA/80L188EA INSTRUCTION SET SUMMARY (Continued) Function Format 80C186EA 80C188EA CommentsClock Clock Cycles Cycles PROCESSOR CONTROL CLC e Clear carry 11111000 2 2 CMC e Complement carry 11110101 2 2 STC e Set carry 11111001 2 2 CLD e Clear direction 11111100 2 2 STD e Set direction 11111101 2 2 CLI e Clear interrupt 11111010 2 2 STI e Set interrupt 11111011 2 2 HLT e Halt 11110100 2 2 WAIT e Wait 10011011 6 6 i f TEST e 0 LOCK e Bus lock prefix 11110000 2 2 NOP e No Operation 10010000 3 3 (TTT LLL are opcode to processor extension) Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers. The Effective Address (EA) of the memory operand is computed according to the mod and r/m fields: if mod e 11 then r/m is treated as a REG field if mod e 00 then DISP e 0*, disp-low and disp- high are absent if mod e 01 then DISP e disp-low sign-ex- tended to 16-bits, disp-high is absent if mod e 10 then DISP e disp-high: disp-low if r/m e 000 then EA e (BX) a (SI) a DISP if r/m e 001 then EA e (BX) a (DI) a DISP if r/m e 010 then EA e (BP) a (SI) a DISP if r/m e 011 then EA e (BP) a (DI) a DISP if r/m e 100 then EA e (SI) a DISP if r/m e 101 then EA e (DI) a DISP if r/m e 110 then EA e (BP) a DISP* if r/m e 111 then EA e (BX) a DISP DISP follows 2nd byte of instruction (before data if required) *except if mod e 00 and r/m e 110 then EA e disp-high: disp-low. EA calculation time is 4 clock cycles for all modes, and is included in the execution times given whenev- er appropriate. Segment Override Prefix 0 0 1 reg 1 1 0 reg is assigned according to the following: Segment reg Register 00 ES 01 CS 10 SS 11 DS REG is assigned according to the following table: 16-Bit (w e 1) 8-Bit (w e 0)
000 AX 000 AL
001 CX 001 CL
010 DX 010 DL
011 BX 011 BL
100 SP 100 AH
101 BP 101 CH
110 SI 110 DH
111 DI 111 BH
The physical addresses of all operands addressed by the BP register are computed using the SS seg- ment register. The physical addresses of the desti- nation operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment, which may not be overridden.