C10GX51002

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Intel® Cyclone® 10 GX Device Datasheet 2022.02.14

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Intel® Cyclone® 10 GX Device Datasheet Online Version Send Feedback C10GX51002 ID: 683828 Version: 2022.02.14

Intel® Cyclone® 10 GX Device Datasheet This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Intel® Cyclone® 10 GX devices. Intel Cyclone 10 GX devices are offered in extended and industrial grades. Extended devices are offered in –E5 (fastest) and – E6 speed grades. Industrial grade devices are offered in the –I5 and –I6 speed grades. Related Information Intel Cyclone 10 GX Device Overview Provides more information about the densities and packages in the Intel Cyclone 10 GX devices.

Electrical Characteristics

The following sections describe the operating conditions and power consumption of Intel Cyclone 10 GX devices. Operating Conditions Intel Cyclone 10 GX devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Intel Cyclone 10 GX devices, you must consider the operating requirements described in this section. Absolute Maximum Ratings This section defines the maximum operating conditions for Intel Cyclone 10 GX devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions. Caution: Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. 683828 | 2022.02.14 Send Feedback Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered

Table 1. Absolute Maximum Ratings for Intel Cyclone 10 GX Devices (1) The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.

Symbol Description Condition Minimum Maximum Unit IOUT DC output current per pin — –25 (2)(3)(4)(5) (6) 25 mA TJ Operating junction temperature — –55 125 °C TSTG Storage temperature (no bias) — –65 150 °C Related Information

AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 Devices Provides the power sequencing requirements for Intel Cyclone 10 GX devices.
Power-Up and Power-Down Sequences, Power Management in Intel Cyclone 10 GX Devices chapter Provides the power sequencing requirements for Intel Cyclone 10 GX devices. Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 2.70 V for LVDS I/O can only be at 2.70 V for ~4% over the lifetime of the device. (2) The maximum current allowed through any LVDS I/O bank pin when the device is not turned on or during power-up/power-down conditions is 10 mA. (3) Total current per LVDS I/O bank must not exceed 100 mA. (4) Voltage level must not exceed 1.89 V. (5) Applies to all I/O standards and settings supported by LVDS I/O banks, including single-ended and differential I/Os. (6) Applies only to LVDS I/O banks. 3 V I/O banks are not covered under this specification and must be implemented as per the power sequencing requirement. For more details, refer to AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria® 10, and Intel Stratix® 10 Devices and Power Management in Intel Cyclone 10 GX Devices chapter. Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Send Feedback Intel® Cyclone® 10 GX Device Datasheet

Table 2. Maximum Allowed Overshoot During Transitions for Intel Cyclone 10 GX Devices are applicable to the VREFP_ADC and VREFN_ADC I/O pins. For an overshoot of 2.5 V, the percentage of high time for the overshoot can be as high as 100% over a 10-year period. with 100% I/O toggle rate and 50% duty cycle signal. (7) The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.

Figure 1. Intel Cyclone 10 GX Devices Overshoot Duration This section lists the functional operation limits for the AC and DC parameters for Intel Cyclone 10 GX devices. Table 3. Recommended Operating Conditions for Intel Cyclone 10 GX Devices This table lists the steady-state voltage values expected from Intel Cyclone 10 GX devices. Power supply ramps must all be strictly monotonic, without plateaus. (8) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

Symbol Description Condition Minimum (8) Typical Maximum (8) Unit 1.2 V 1.14 1.2 1.26 V VCCERAM Embedded memory power supply 0.9 V 0.87 0.9 0.93 V VCCBAT (9) Battery back-up power supply (For design security volatile key register) — 1.14 — 1.89 V VCCPT Power supply for programmable power technology and I/O pre-driver 1.8 V 1.71 1.8 1.89 V VCCIO I/O buffers power supply 3.0 V (for 3 V I/O only) 2.85 3.0 3.15 V 2.5 V (for 3 V I/O only) 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V 1.5 V 1.425 1.5 1.575 V 1.25 V 1.19 1.25 1.31 V VCCA_PLL PLL analog voltage regulator power supply — 1.71 1.8 1.89 V VREFP_ADC Precision voltage reference for voltage sensor — 1.2475 1.25 1.2525 V VI (11)(12) DC input voltage 3 V I/O –0.3 — 3.3 V continued... (8) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (9) If you do not use the design security feature in Intel Cyclone 10 GX devices, connect VCCBAT to a 1.5-V to 1.8-V power supply. Intel Cyclone 10 GX power-on reset (POR) circuitry monitors VCCBAT. Intel Cyclone 10 GX devices do not exit POR if VCCBAT is not powered up. (10) For minimum and maximum voltage values, refer to the I/O Standard Specifications section. (11) The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os. Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Intel® Cyclone® 10 GX Device Datasheet Send Feedback

Table 4. Transceiver Power Supply Operating Conditions for Intel Cyclone 10 GX Devices

12.5 Gbps

(8) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (13) tramp is the ramp time of each individual power supply, not the ramp time of all combined power supplies. (14) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

Symbol Description Condition Minimum (14) Typical Maximum (14) Unit Backplane ≤

6.6 Gbps

Chip-to-chip ≤

11.3 Gbps

0.92 0.95 0.98 V VCCR_GXB[L1][C,D] Receiver power supply Chip-to-chip ≤ Backplane ≤ 1.0 1.03 1.06 V Chip-to-chip ≤ 0.92 0.95 0.98 V VCCH_GXBL Transceiver output buffer power supply — 1.710 1.8 1.890 V Related Information

Transceiver Performance for Intel Cyclone 10 GX Devices on page 21
Intel Cyclone 10 GX Pin Connection Guidelines DC Characteristics Supply Current and Power Consumption Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel Quartus® Prime Power Analyzer feature. Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources. The Intel Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates. (14) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Intel® Cyclone® 10 GX Device Datasheet Send Feedback

Early Power Estimator User Guide Provides more information about power estimation tools.
Power Analysis and Optimization User Guide: Intel Quartus Prime Pro Edition Provides more information about power estimation tools. I/O Pin Leakage Current

Table 5. I/O Pin Leakage Current for Intel Cyclone 10 GX Devices The bus-hold trip points are based on calculated input voltages from the JEDEC standard. Table 6. Bus Hold Parameters for Intel Cyclone 10 GX Devices (15) This value is only applicable for LVDS I/O bank. (16) This value is only applicable for 3 V I/O bank.

Table 7. OCT Calibration Accuracy Specifications for Intel Cyclone 10 GX Devices Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.

Table 8. OCT Without Calibration Resistance Tolerance Specifications for Intel Cyclone 10 GX Devices This table lists the Intel Cyclone 10 GX OCT without calibration resistance tolerance to PVT changes. (17) Only applicable to POD12 I/O standard.

Table 9. Pin Capacitance for Intel Cyclone 10 GX Devices only available for the pins as described in the Internal Weak Pull-Down Resistor Values for Intel Cyclone 10 GX Devices table. Table 10. Internal Weak Pull-Up Resistor Values for Intel Cyclone 10 GX Devices (18) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. (19) Valid with ±25% tolerances to cover changes over PVT.

Table 11. Internal Weak Pull-Down Resistor Values for Intel Cyclone 10 GX Devices user I/O pins and dual-purpose I/O pins. Provides more information about the pins that support internal weak pull-up and internal weak pull-down features. and IOL) for various I/O standards supported by Intel Cyclone 10 GX devices. For minimum voltage values, use the minimum VCCIO values. For maximum voltage values, use the maximum VCCIO values. You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.

Table 12. Single-Ended I/O Standards Specifications for Intel Cyclone 10 GX Devices Table 13. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Intel Cyclone 10 GX Devices and IOH specifications in the datasheet.

Table 14. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Intel Cyclone 10 GX Devices and IOH specifications in the datasheet.

Table 15. Differential SSTL I/O Standards Specifications for Intel Cyclone 10 GX Devices and IOH specifications in the datasheet.

Table 16. Differential HSTL and HSUL I/O Standards Specifications for Intel Cyclone 10 GX Devices

0.3 VCCIO +

limits (VIH(DC) and VIL(DC)).

Table 17. Differential I/O Standards Specifications for Intel Cyclone 10 GX Devices Differential inputs are powered by VCCPT which requires 1.8 V.

1 DMAX

Provides the specifications for transmitter, receiver, and reference clock I/O pin. (23) The minimum VID value is applicable over the entire common mode range, VCM. Mbps and 0 V to 1.85 V for data rates below 700 Mbps. (26) For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V. (27) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.1 V to 1.625 V. 700 Mbps and 0.45 V to 1.95 V for data rates below 700 Mbps.

Table 18. Transmitter and Receiver Data Rate Performance Table 19. ATX PLL and Fractional PLL (fPLL) Performance (29) Chip-to-chip links are applications with short reach channels.

Table 20. CMU PLL Performance Table 21. High-Speed Serial Transceiver-Fabric Interface Performance for Intel Cyclone 10 GX Devices The frequencies listed are the maximum frequencies. Table 22. Reference Clock Specifications (31) HCSL is only supported for PCIe.

Symbol/Description Condition Min Typ Max Unit Input Reference Clock Frequency (CMU PLL) 61 — 800 MHz Input Reference Clock Frequency (ATX PLL) 100 — 800 MHz Input Reference Clock Frequency (fPLL PLL) 25 (32) / 50 — 800 MHz Rise time 20% to 80% — — 400 ps Fall time 80% to 20% — — 400 ps Duty cycle — 45 — 55 % Spread-spectrum modulating clock frequency PCIe 30 — 33 kHz Spread-spectrum downspread PCIe — 0 to –0.5 — % On-chip termination resistors — — 100 — Ω Absolute VMAX Dedicated reference clock pin — — 1.6 V RX pin as a reference clock — — 1.2 V Absolute VMIN — –0.4 — — V Peak-to-peak differential input voltage — 200 — 1600 mV VICM (AC coupled) VCCR_GXB = 0.95 V — 0.95 — V VCCR_GXB = 1.03 V — 1.03 — V VICM (DC coupled) HCSL I/O standard for PCIe reference clock 250 — 550 mV Transmitter REFCLK Phase Noise (622 MHz) (33) 100 Hz — — –70 dBc/Hz 1 kHz — — –90 dBc/Hz continued... (32) 25 MHz is for HDMI applications only. (33) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 622 MHz + 20*log(f/622). Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Send Feedback Intel® Cyclone® 10 GX Device Datasheet

Table 23. Transceiver Clocks Specifications Table 24. Transceiver Clock Network Maximum Data Rate Specifications (34) Defined for worst case spread spectrum clock (SSC) modulation profile, such as Lexmark.

Table 25. Receiver Specifications (35) CML, Differential LVPECL, and LVDS are only used on AC coupled links. (36) The device cannot tolerate prolonged operation at this absolute maximum. (37) The device cannot tolerate prolonged operation at this absolute minimum. Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. matching common mode voltage.

Table 26. Transmitter Specifications (40) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset. (41) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high. when the CDR is functioning in the manual mode. high when the CDR is functioning in the manual mode. (44) High Speed Differential I/O is the dedicated I/O standard for the transmitter in Intel Cyclone 10 GX transceivers.

Table 27. Typical Transmitter VOD Settings (45) The Intel Quartus Prime software automatically selects the appropriate slew rate depending on the design configurations. (46) SLEW_R1 is the slowest and SLEW_R5 is the fastest. SLEW_R6 and SLEW_R7 are not used.

Table 28. Transmitter Channel-to-channel Skew Specifications (47) refclk is set to 125 MHz during the test. (48) You can reduce the lane-to-lane skew by increasing the reference clock frequency.

Table 29. Clock Tree Performance for Intel Cyclone 10 GX Devices Table 30. Fractional PLL Specifications for Intel Cyclone 10 GX Devices simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

Symbol Parameter Condition Min Typ Max Unit tLOCK Time required to lock from end-of-device configuration or deassertion of pll_powerdown — — — 1 ms tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post- scale counters/delays) — — — 1 ms fCLBW PLL closed-loop bandwidth — 0.3 — 4 MHz tPLL_PSERR Accuracy of PLL phase shift — — — 50 ps tARESET Minimum pulse width on the pll_powerdown signal — 10 — — ns tINCCJ (50)(51) Input clock cycle-to-cycle jitter FREF ≥ 100 MHz — — 0.13 UI (p-p) FREF < 100 MHz — — 650 ps (p-p) tOUTPJ (52) Period jitter for clock output FOUT ≥ 100 MHz — — 600 ps (p-p) FOUT < 100 MHz — — 60 mUI (p-p) tOUTCCJ (52) Cycle-to-cycle jitter for clock output FOUT ≥ 100 MHz — — 600 ps (p-p) FOUT < 100 MHz — — 60 mUI (p-p) dKBIT Bit number of Delta Sigma Modulator (DSM) — — 32 — bit Related Information Memory Output Clock Jitter Specifications on page 43 Provides more information about the external memory interface clock output jitter specifications. (50) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps. (51) FREF is fIN/N, specification applies when N = 1. (52) External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Intel Cyclone 10 GX Devices table. Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Intel® Cyclone® 10 GX Device Datasheet Send Feedback

Table 31. I/O PLL Specifications for Intel Cyclone 10 GX Devices simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

Symbol Parameter Condition Min Typ Max Unit tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) — — — 1 ms tPLL_PSERR Accuracy of PLL phase shift — — — ±50 ps tARESET Minimum pulse width on the areset signal — 10 — — ns tINCCJ (54)(55) Input clock cycle-to-cycle jitter FREF ≥ 100 MHz — — 0.15 UI (p-p) FREF < 100 MHz — — 750 ps (p-p) tOUTPJ_DC Period jitter for dedicated clock output FOUT ≥ 100 MHz — — 175 ps (p-p) FOUT < 100 MHz — — 17.5 mUI (p-p) tOUTCCJ_DC Cycle-to-cycle jitter for dedicated clock output FOUT ≥ 100 MHz — — 175 ps (p-p) FOUT < 100 MHz — — 17.5 mUI (p-p) tOUTPJ_IO (56) Period jitter for clock output on the regular I/O FOUT ≥ 100 MHz — — 600 ps (p-p) FOUT < 100 MHz — — 60 mUI (p-p) tOUTCCJ_IO (56) Cycle-to-cycle jitter for clock output on the regular I/O FOUT ≥ 100 MHz — — 600 ps (p-p) FOUT < 100 MHz — — 60 mUI (p-p) tCASC_OUTPJ_DC Period jitter for dedicated clock output in cascaded PLLs FOUT ≥ 100 MHz — — 175 ps (p-p) FOUT < 100 MHz — — 17.5 mUI (p-p) Related Information Memory Output Clock Jitter Specifications on page 43 Provides more information about the external memory interface clock output jitter specifications. (54) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps. (55) FREF is fIN/N, specification applies when N = 1. (56) External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Intel Cyclone 10 GX Devices table. Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Intel® Cyclone® 10 GX Device Datasheet Send Feedback

Table 32. DSP Block Performance Specifications for Intel Cyclone 10 GX Devices When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.

Table 33. Memory Block Performance Specifications for Intel Cyclone 10 GX Devices Table 34. Internal Temperature Sensing Diode Specifications for Intel Cyclone 10 GX Devices Provides the transfer function for the internal TSD.

Table 35. External Temperature Sensing Diode Specifications for Intel Cyclone 10 GX Devices

The typical value is at 25°C.
Diode accuracy improves with lower injection current.
Absolute accuracy is dependent on third party external diode ADC and integration specifics. Description Min Typ Max Unit Ibias, diode source current 10 — 100 μA Vbias, voltage across diode 0.3 — 0.9 V Series resistance — — < 1 Ω Diode ideality factor — 1.03 — — Internal Voltage Sensor Specifications

Table 36. Internal Voltage Sensor Specifications for Intel Cyclone 10 GX Devices

This section describes the periphery performance, high-speed I/O, and external memory interface. Table 37. High-Speed I/O Specifications for Intel Cyclone 10 GX Devices When serializer/deserializer (SERDES) factor J = 3 to 10, use the SERDES block. For LVDS applications, you must use the PLLs in integer PLL mode. channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

True RSDS output standard with data rates of up to 360 Mbps
True mini-LVDS output standard with data rates of up to 400 Mbps Symbol Condition –E5, –I5 –E6, –I6 Unit Min Typ Max Min Typ Max fHSCLK_in (input clock frequency) True Differential I/O Standards Clock boost factor W = 1 to 40 (57) 10 — 700 10 — 625 MHz fHSCLK_in (input clock frequency) Single Ended I/O Standards Clock boost factor W = 1 to 40 (57) 10 — 625 10 — 525 MHz fHSCLK_OUT (output clock frequency) — — — 700 (58) — — 625 (58) MHz continued... (57) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate. (58) This is achieved by using the PHY clock network. Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Intel® Cyclone® 10 GX Device Datasheet Send Feedback

Symbol Condition –E5, –I5 –E6, –I6 Unit Min Typ Max Min Typ Max Transmitter True Differential I/O Standards - fHSDR (data rate) (59) SERDES factor J = 4 to 10 (60)(61)(62) (62) — 1434 (62) — 1250 Mbps SERDES factor J = 3 (60)(61)(62) (62) — 1076 (62) — 938 Mbps SERDES factor J = 2, uses DDR registers SERDES factor J = 1, uses DDR registers tx Jitter - True Differential I/O Standards Total jitter for data rate, 600 Mbps – 1.6 Gbps — — 200 — — 250 ps Total jitter for data rate, < 600 Mbps tDUTY (64) TX output clock duty cycle for Differential I/O Standards 45 50 55 45 50 55 % tRISE & & tFALL (61) (65) True Differential I/O Standards — — 180 — — 200 ps continued... (59) Requires package skew compensation with PCB trace length. (60) The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis. (61) The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface. (62) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and serializer do not have a minimum toggle rate. (63) The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal integrity meets the interface requirements. (64) Not applicable for DIVCLK = 1. Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Send Feedback Intel® Cyclone® 10 GX Device Datasheet

Symbol Condition –E5, –I5 –E6, –I6 Unit Min Typ Max Min Typ Max TCCS (64)(59) True Differential I/O Standards — — 150 — — 150 ps Receiver True Differential I/O Standards - fHSDRDPA (data rate) SERDES factor 150 — 1434 150 — 1250 Mbps SERDES factor J = 3 (60)(61)(62) 150 — 1076 150 — 938 Mbps fHSDR (data rate) (without DPA) (59) SERDES factor J = 3 to 10 (62) — (66) (62) — (66) Mbps SERDES factor J = 2, uses DDR registers SERDES factor J = 1, uses DDR registers DPA (FIFO mode) DPA run length — — — 10000 — — 10000 UI DPA (soft CDR mode) DPA run length SGMII/GbE protocol — — 5 — — 5 UI All other protocols — — 50 data transition per 208 UI — — 50 data transition per 208 UI Soft CDR mode Soft-CDR ppm tolerance Non DPA mode Sampling Window — — — 300 — — 300 ps (65) This applies to default pre-emphasis and VOD settings only. (66) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported. Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Intel® Cyclone® 10 GX Device Datasheet Send Feedback

Table 38. DPA Lock Time Specifications for Intel Cyclone 10 GX Devices (67) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions. (68) This is the maximum data transition consumed by DPA to lock.

Figure 2. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.4 Gbps Table 39. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.4 Gbps

Figure 3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.4 Gbps

0.1 UI P-P

Table 40. Memory Standards Supported by the Hard Memory Controller for Intel Cyclone 10 GX Devices This table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator.

Provides the specific details of the memory standards supported. Table 41. DLL Frequency Range Specifications for Intel Cyclone 10 GX Devices 600 MHz. To support interfaces below 600 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported range.

Table 42. DQS Phase Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) for Intel Cyclone 10 GX Devices This error specification is the absolute maximum and minimum error. Table 43. Memory Output Clock Jitter Specifications for Intel Cyclone 10 GX Devices circuits clocked by a PLL output routed on a PHY clock network as specified. Intel recommends using PHY clock networks for better jitter performance. The memory output clock jitter is applicable when an input jitter of 10 ps peak-to-peak is applied with bit error rate (BER) 10–12, equivalent to 14 sigma. Table 44. OCT Calibration Block Specifications for Intel Cyclone 10 GX Devices

Figure 4. Timing Diagram for on oe and dyn_term_ctrl Signals This section provides configuration specifications and timing for Intel Cyclone 10 GX devices. is ready to begin configuration. Table 45. Fast and Standard POR Delay Specification for Intel Cyclone 10 GX Devices Provides more information about POR delay based on MSEL pin settings for each configuration scheme. (69) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip.

Table 46. JTAG Timing Parameters and Values for Intel Cyclone 10 GX Devices (70) The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming.

Table 47. DCLK-to-DATA[] Ratio for Intel Cyclone 10 GX Devices You cannot turn on encryption and compression at the same time for Intel Cyclone 10 GX devices. FPP ×32. For the respective DCLK-to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Intel Cyclone 10 GX Devices table. Table 48. FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Intel Cyclone 10 GX Devices Use these timing parameters when the decompression and design security features are disabled. (71) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.

Symbol Parameter Minimum Maximum Unit tCF2CK (73) nCONFIG high to first rising edge on DCLK 3,010 — μs tST2CK (73) nSTATUS high to first rising edge of DCLK 10 — μs tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns tDH DATA[] hold time after rising edge on DCLK 0 — ns tCH DCLK high time 0.45 × 1/fMAX — s tCL DCLK low time 0.45 × 1/fMAX — s tCLK DCLK period 1/fMAX — s fMAX DCLK frequency (FPP ×8/×16/×32) — 100 MHz tCD2UM CONF_DONE high to user mode (74) 175 830 μs tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (600 × CLKUSR period) — — Related Information FPP Configuration Timing Provides the FPP configuration timing waveforms. (72) This value is applicable if you do not delay configuration by externally holding the nSTATUS low. (73) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. (74) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Send Feedback Intel® Cyclone® 10 GX Device Datasheet

Table 49. FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Intel Cyclone 10 GX Devices Use these timing parameters when you use the decompression and design security features. (75) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (76) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. (77) N is the DCLK-to-DATA ratio and fDCLK is the DCLK frequency the system is operating.

Provides the FPP configuration timing waveforms. Table 50. AS Timing Parameters for AS ×1 and AS ×4 Configurations in Intel Cyclone 10 GX Devices The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device. for Intel Cyclone 10 GX Devices table. (78) The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device.

PS Configuration Timing on page 50
AS Configuration Timing Provides the AS configuration timing waveform. DCLK Frequency Specification in the AS Configuration Scheme

Table 51. DCLK Frequency Specification in the AS Configuration Scheme This table lists the internal clock frequency specification for the AS configuration scheme. The DCLK frequency specification applies when you use the internal oscillator as the configuration clock source. The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz. You can only set 12.5, 25, 50, and 100 MHz in the Intel Quartus Prime software. Table 52. PS Timing Parameters for Intel Cyclone 10 GX Devices

Symbol Parameter Minimum Maximum Unit tCF2CK (81) nCONFIG high to first rising edge on DCLK 3,010 — μs tST2CK (81) nSTATUS high to first rising edge of DCLK 10 — μs tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns tDH DATA[] hold time after rising edge on DCLK 0 — ns tCH DCLK high time 0.45 × 1/fMAX — s tCL DCLK low time 0.45 × 1/fMAX — s tCLK DCLK period 1/fMAX — s fMAX DCLK frequency — 125 MHz tCD2UM CONF_DONE high to user mode (82) 175 830 μs tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (600 × CLKUSR period) — — Related Information PS Configuration Timing Provides the PS configuration timing waveform. (79) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (80) This value is applicable if you do not delay configuration by externally holding the nSTATUS low. (81) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. (82) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device. Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Send Feedback Intel® Cyclone® 10 GX Device Datasheet

Table 53. Initialization Clock Source Option and the Maximum Frequency for Intel Cyclone 10 GX Devices

PS and FPP—Raw Binary File (.rbf)
AS—Raw Programming Data File (.rpd) The .rpd file size follows the Intel configuration devices capacity. However, the actual configuration bit stream size for .rpd file is the same as .rbf file. (83) To enable CLKUSR as the initialization clock source, in the Intel Quartus Prime software, select Device and Pin Options ➤ General ➤ Device initialization clock source ➤ CLKUSR pin. (84) If you use the CLKUSR pin for AS and transceiver calibration simultaneously, the only allowed frequency is 100 MHz. Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Intel® Cyclone® 10 GX Device Datasheet Send Feedback

Table 54. Configuration Bit Stream Sizes for Intel Cyclone 10 GX Devices format, have different file sizes. software, any design targeted for the same device has the same uncompressed configuration file size. configuration bit stream, and it is specifically for the Configuration via Protocol (CvP) feature. estimated configuration bit stream sizes. Refer to the .rbf file generated in the Intel Quartus Prime software for the actual bit stream size.

Table 55. Minimum Configuration Time Estimation for Intel Cyclone 10 GX Devices The estimated values are based on the uncompressed configuration bit stream sizes in the Configuration Bit Stream Sizes for Intel Cyclone 10 GX Devices table.

Configuration Files on page 52
DCLK Frequency Specification in the AS Configuration Scheme on page 50 Provides the DCLK frequency using internal oscillator. (85) The minimum configuration time is calculated based on DCLK frequency of 100 MHz. Only external CLKUSR may guarantee the frequency accuracy of 100 MHz. If you use internal oscillator of 100 MHz, you may not get the actual frequency of 100 MHz. For the DCLK frequency using internal oscillator, refer to the DCLK Frequency Specification in the AS Configuration Scheme table. (86) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic. Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Intel® Cyclone® 10 GX Device Datasheet Send Feedback

Table 56. Remote System Upgrade Circuitry Timing Specifications for Intel Cyclone 10 GX Devices

Remote System Upgrade State Machine Provides more information about configuration reset (RU_CONFIG) signal.
User Watchdog Timer Provides more information about reset_timer (RU_nRSTIMER) signal. User Watchdog Internal Circuitry Timing Specifications

Table 57. User Watchdog Internal Oscillator Frequency Specifications for Intel Cyclone 10 GX Devices analysis. You may generate the I/O timing report manually using the Timing Analyzer or using the automated script. user-supplied to the Remote Update Intel FPGA IP core must meet this specification.

design after you complete place-and-route. Provides the techniques to generate I/O timing information using the Intel Quartus Prime software. Table 58. IOE Programmable Delay for Intel Cyclone 10 GX Devices delay chain with maximum offset settings after excluding the intrinsic delay (delay at minimum offset settings). Table 59. Glossary in the Assignment Name column. (91) Minimum offset does not include the intrinsic delay.

Positive Channel (p) = VIH Negative Channel (n) = VIL Ground VID VID VID p - n = 0 V VCM Transmitter Output Waveforms Single-Ended Waveform Differential Waveform Positive Channel (p) = VOH Negative Channel (n) = VOL Ground VOD VOD VOD p - n = 0 V VCM fHSCLK I/O PLL input clock frequency. fHSDR High-speed I/O block—Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA. fHSDRDPA High-speed I/O block—Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA. J High-speed I/O block—Deserialization factor (width of parallel data bus). JTAG Timing Specifications JTAG Timing Specifications: continued... Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Send Feedback Intel® Cyclone® 10 GX Device Datasheet

RL Receiver differential input discrete resistor (external to the Intel Cyclone 10 GX device). Sampling window (SW) Timing Diagram—the period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window, as shown: Bit Time 0.5 x TCCS RSKM Sampling Window (SW) RSKM 0.5 x TCCS Single-ended voltage referenced I/O standard The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. Single-Ended Voltage Referenced I/O Standard continued... Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Intel® Cyclone® 10 GX Device Datasheet Send Feedback

VIH(DC)VREF VOH VOL VCCIO VSS VIL(DC) VIH(AC) VIL(AC) tC High-speed receiver/transmitter input and output clock period. TCCS (channel-to-channel-skew) The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table). tDUTY High-speed I/O block—Duty cycle on high-speed transmitter output clock. tFALL Signal high-to-low transition time (80–20%) tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input tOUTPJ_IO Period jitter on the GPIO driven by a PLL tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL tRISE Signal low-to-high transition time (20–80%) Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w). VCM(DC) DC Common mode input voltage. VICM Input Common mode voltage—The common mode of the differential signal at the receiver. VID Input differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. VDIF(AC) AC differential input voltage—Minimum AC input differential voltage required for switching. VDIF(DC) DC differential input voltage— Minimum DC input differential voltage required for switching. VIH Voltage input high—The minimum positive voltage applied to the input which is accepted by the device as a logic high. continued... Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Send Feedback Intel® Cyclone® 10 GX Device Datasheet

VIH(AC) High-level AC input voltage VIH(DC) High-level DC input voltage VIL Voltage input low—The maximum positive voltage applied to the input which is accepted by the device as a logic low. VIL(AC) Low-level AC input voltage VIL(DC) Low-level DC input voltage VOCM Output Common mode voltage—The common mode of the differential signal at the transmitter. VOD Output differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter. VSWING Differential input voltage VIX Input differential cross point voltage VOX Output differential cross point voltage W High-speed I/O block—Clock Boost Factor Document Revision History for the Intel Cyclone 10 GX Device Datasheet Document Version Changes 2022.02.14 • Updated V CCBAT specifications in the Recommended Operating Conditions for Intel Cyclone 10 GX Devices table.

Removed table description from the I/O Pin Leakage Current for Intel Cyclone 10 GX Devices table.
Updated the Differential I/O Standards Specifications for Intel Cyclone 10 GX Devices table. — Changed I/O standard from RSDS (HIO) to RSDS. — Changed I/O standard from Mini-LVDS (HIO) to Mini-LVDS and updated footnote.
Removed diagram: DPA Lock Time Specifications with DPA PLL Calibration Enabled
Added footnote to Maximum Data Transition in the DPA Lock Time Specifications for Intel Cyclone 10 GX Devices table.
Updated t CF2CD and tCF2ST0 minimum specifications in the FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Intel Cyclone 10 GX Devices table.
Updated the FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Intel Cyclone 10 GX Devices table. — Updated tCF2CD and tCF2ST0 minimum specifications. — Removed tR and tF specifications. continued... Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Intel® Cyclone® 10 GX Device Datasheet Send Feedback

Updated t CF2CD and tCF2ST0 minimum specifications in the PS Timing Parameters for Intel Cyclone 10 GX Devices table.
Updated the Configuration Bit Stream Sizes for Intel Cyclone 10 GX Devices table. — Updated table description. — Updated Uncompressed Configuration Bit Stream Size and IOCSR Bit Stream Size.
Updated Minimum Configuration Time in the Minimum Configuration Time Estimation for Intel Cyclone 10 GX Devices table. 2018.06.15 • Added Intel Cyclone 10 GX Devices Overshoot Duration figure and description.
Added a link in the OCT Calibration Accuracy Specifications section.
Removed Equation for OCT Variation Without Recalibration.
Updated the note to CLKUSR in the Initialization Clock Source Option and the Maximum Frequency for Intel Cyclone 10 GX Devices table.
Updated the I/O Timing section on the I/O timing information generation guidelines.
Updated the description and maximum offset values in the IOE Programmable Delay for Intel Cyclone 10 GX Devices table. 2018.04.06 Added notes to IOUT specification in the Absolute Maximum Ratings for Intel Cyclone 10 GX Devices table. Date Version Changes November 2017 2017.11.10 • Changed the full symbol names for V CCR_GXB and VCCT_GXB, and changed the description for VCCH_GXB in the Transceiver Power Supply Operating Conditions for Intel Cyclone 10 GX Devices table.
Removed note from the Transceiver Power Supply Operating Conditions section.
Added a footnote in the Reference Clock Specifications table.
Removed the "Programmable AC Gain at High Gain mode and Data Rate ≤ 12.5 Gbps" parameter from the Receiver Specifications table.
Changed the channel span descriptions for the x1 and x6 clock networks in the Transceiver Clock Network Maximum Data Rate Specifications table.
Changed the description of the VOD ratio in the Typical Transmitter VOD Settings table.
Changed the specifications for CDR PPM deviation limit in the Receiver Specifications table.
Updated the description for V CCT_GXB, VCCR_GXB, and VCCH_GXB.
Added note to V I in the Recommended Operating Conditions for Intel Cyclone 10 GX Devices table.
Updated notes to RSDS and Mini-LVDS in the Differential I/O Standards Specifications for Intel Cyclone 10 GX Devices table.
Updated f VCO specifications in the Fractional PLL Specifications for Intel Cyclone 10 GX Devices table.
Updated temperature range from "–40 to 125°C" to "–40 to 100°C" in the Internal Temperature Sensing Diode Specifications for Intel Cyclone 10 GX Devices table.
Updated the description for the Memory Output Clock Jitter Specifications for Intel Cyclone 10 GX Devices table. continued... Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Send Feedback Intel® Cyclone® 10 GX Device Datasheet

Updated the following IP cores name: — Remote Update Intel FPGA — PHYLite for Parallel Interfaces Intel Cyclone 10 FPGA
Removed automotive-grade information.
Removed Preliminary tags. May 2017 2017.05.08 Initial release. Intel® Cyclone® 10 GX Device Datasheet 683828 | 2022.02.14 Intel® Cyclone® 10 GX Device Datasheet Send Feedback

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C10GX51002 specifications and overview.

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Intel® Cyclone® 10 GX Device Datasheet 2022.02.14

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Intel® Cyclone® 10 GX Device Datasheet 2022.02.14

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