BP0C51BH

80C31BH INTEL | Alldatasheet

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*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. January 1995COPYRIGHT © INTEL CORPORATION, 1995 Order Number: 270419-007 80C31BH/80C51BH/87C51 MCSÉ 51 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Automotive Y Extended Automotive Temperature Range ( b40§Ct o a125§C Ambient) Y High Performance CHMOS Process Y Power Control Modes Y 4 Kbyte On-Chip ROM/EPROM Y 128 x 8-bit RAM Y 32 Programmable I/O Lines Y Two 16-Bit Timer/Counters Y 5 Interrupt Sources Y Quick-Pulse EPROM Programming Y 2-Level Program Memory Lock EPROM Y Boolean Processor Y Programmable Serial Port Y TTL- and CMOS-Compatible Logic Levels Y 64K External Program Memory Space Y 64K External Data Memory Space Y IDLE and POWER DOWN Modes Y ONCE Mode Facilitates System Testing Y Available in 12 MHz and 16 MHz Versions Y Available in PLCC and DIP Packages (See Packaging Specification, Order Ý231369) The MCS É 51 CHMOS microcontroller products are fabricated on Intel’s reliable CHMOS process and are functionally compatible with the standard MCS 51 HMOS microcontroller products. This technology combines the high speed and density characteristics of HMOS with the low power attributes of CHMOS. This combina- tion expands the effectiveness of the powerful MCS 51 microcontroller architecture and instruction set. Like the MCS 51 HMOS microcontroller versions, the MCS 51 CHMOS microcontroller products have the following features: 4 Kbytes of EPROM/ROM (87C51/80C51BH respectively); 128 bytes of RAM; 32 I/O lines; two 16-bit timer/counters; a five-source two-level interrupt structure; a full duplex serial port; and on-chip oscillator and clock circuitry. In addition, the MCS 51 CHMOS microcontroller products exhibit low operating power, along with two software selectable modes of reduced activity for further power reductionÐIdle and Power Down. The Idle mode freezes the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. The 87C51 is the EPROM version of the 80C51BH. It contains 4 Kbytes of on-chip program memory that can be electrically programmed, and can be erased by exposure to ultraviolet light. The 87C51 EPROM array uses a modified Quick-Pulse Programming algorithm, by which the entire 4 Kbyte array can be programmed in about 12 seconds. NOTICE: This datasheet contains information on products in full production. Specifications within this datasheet are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

Figure 1. MCS É 51 Microcontroller Architectural Block Diagram

Figure 2. MCS É 51 Microcontroller Product Family Nomenclature Table 1. Temperature Options

Diagrams are for pin reference only. Package sizes are not to scale. Figure 3. Pin Connections prove power supply bypassing. during program verification. strong internal pullups when emitting 1s. tents of the P2 Special Function Register.

Table 2. Status of the External Pins During Idle and Power Down the Power Down mode is terminated. The only exit from Power Down is a hardware reset. tor to restart and stabilize. come up at the same time for a proper start-up. tents of the Carry Bit and B.7 must be equal. tance will not exceed 20 pF.

AUTOMOTIVE 80C31BH/80C51BH/87C51 PROGRAM MEMORY LOCK (EPROM Only) The 87C51 contains two program memory lock schemes: Encrypted Verify and Lock Bits. Encrypted Verify: The 87C51 implements a 32- byte EPROM array that can be programmed by the customer, and which can then be used to encrypt the program code bytes during EPROM verification. The EPROM verification procedure is performed as usual, except that each code byte comes out logical- ly X-NORed with one of the 32 key bytes. The key bytes are gone through in sequence. Therefore, to read the ROM code, one has to know the 32 key bytes in their proper sequence. Lock Bits: Also on the chip are two Lock Bits which can be left unprogrammed (U) or can be pro- grammed (P) to obtain the following additional fea- tures: Bit 1 Bit 2 Additional Features U U none PU # Externally fetched code can not access internal Program Memory. # Further programming disabled. U P (Reserved for Future definition.) PP # Externally fetched code can not access internal Program Memory. # Further programming disabled. # Program verification is disabled. When Lock Bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to func- tion properly. ONCE MODE The ONCE (‘‘on-circuit emulation’’) mode facilitates testing and debugging of systems using the 87C51 without the 87C51 having to be removed from the circuit. The ONCE mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator cir- cuit remains active. While the 87C51 is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.

AUTOMOTIVE 80C31BH/80C51BH/87C51 ABSOLUTE MAXIMUM RATINGS * Ambient Temperature Under Bias b40§Ct o a125§C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b65§Ct o a150§C Voltage on EA /VPP Pin to V SS ÀÀÀÀÀÀÀ0V to a13.0V Voltage on Any Other Pin to V SS ÀÀb0.5V to a6.5V IOL per I/O pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W (Based on package heat transfer limitations, not de- vice power consumption). Typical Junction Temperature (T J) ÀÀÀÀÀÀÀÀ a135§C (Based upon ambient temperature at a125§C) Typical Thermal Resistance Junction-to-Ambient (iJA): PDIP ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ75 §C/W PLCCÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ46§C/W NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and ex- tended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. DC CHARACTERISTICS: (TA eb 40§Ct o a125§C; V CC e 5V g10% (5V g20% EPROM Only); V SS e 0V) Symbol Parameter Min Typ(1) Max Unit Test (87C51/80C51BH) Conditions VIL Input Low Voltage (Except EA ) b0.5 0.2 V CCb0.25 V VIL1 Input Low Voltage to EA 0 0.2 V CCb0.45 V VIH Input High Voltage (Except XTAL1, RST) 0.2V CCa1.0 V CCa0.5 V VIH1 Input High Voltage (XTAL1, RST) 0.7 V CCa0.1 V CCa0.5 V VOL Output Low Voltage (Ports 1, 2, 3) 0.45 (7) VI OL e 1.6 mA (2) VOL1 Output Low Voltage (Port 0, ALE, PSEN ) 0.45 (7) VI OL e 3.2 mA (2) VOH Output High Voltage 2.4 V I OH eb 60 mA (Ports 1, 2, 3, ALE, PSEN ) 0.9 V CC VI OH eb 10 mA VOH1 Output High Voltage (Port 0 in 2.4 V I OH eb 800 mA External Bus Mode) 0.9 V CC VI OH eb 80 mA(3) IIL Logical 0 Input Current (Ports 1, 2, 3) b75 mAV IN e 0.45 V ITL Logical 1-to-0 transition current b750 mA (4) (Ports 1, 2, 3) ILI Input Leakage Current (Port 0) g10 mAV IN e VIL or V IH ICC Power Supply Current: Active Mode @ 12 MHz (5) 11.5 25/20 mA Idle Mode @ 12 MHz (5) 1.3 6/5 mA (6) Power Down Mode 3 100/75 mAV CC e 2.2V to 5.5V RRST Internal Reset Pulldown Resistor 50 300 K X CIO Pin Capacitance 10 pF NOTES: 1. ‘‘Typicals’’ are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The values listed are at room temp, 5V. 2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V OLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1- to-0 transitions during bus operations. In the worst cases (capacitive loading l 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 3. Capacitive loading on Ports 0 and 2 may cause the V OH on ALE and PSEN to momentarily fall below the 0.9 V CC specification when the address bits are stabilizing.

AUTOMOTIVE 80C31BH/80C51BH/87C51 EXPLANATION OF THE AC SYMBOLS Each timing symbol has 5 characters. The first char- acter is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A:Address. C:Clock. D:Input data. H:Logic level HIGH. I:Instruction (program memory contents). L:Logic level LOW, or ALE. P:PSEN Q:Output data. R:RD signal. T:Time. V:Valid. W:WR signal. X:No longer a valid logic level. Z:Float. For example, T AVLL e Time from Address Valid to ALE Low. TLLPL e Time from ALE Low to PSEN Low. AC CHARACTERISTICS: (TA eb 40§Ct o a125§C; V CC e 5V g10% (5V g20% EPROM Only); VSS e 0V; Load Capacitance for Port 0, ALE, and PSEN e 100 pF; Load Capacitance for All Other Outputs e 80 pF) EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS Symbol Parameter 12 MHz Osc Variable Oscillator Units Min Max Min Max 1/TCLCL Oscillator Frequency MHz 87C51/80C51BH/80C31BH 3.5 12–16 TLHLL ALE Pulse Width 127 2T CLCLb40 ns TAVLL Address Valid to ALE Low 28 T CLCLb55 ns TLLAX Address Hold After ALE Low 48 T CLCLb35 ns TLLIV ALE Low to Valid Instr In 224 4T CLCLb110 ns TLLPL ALE Low to PSEN Low 43 T CLCLb40 ns TPLPH PSEN Pulse Width 205 3T CLCLb45 ns TPLIV PSEN Low to Valid Instr In 135 3T CLCLb115 ns TPXIX Input Instr Hold After PSEN 00 n s TPXIZ Input Instr Float After PSEN 59 T CLCLb25 ns TAVIV Address Valid to Valid Instr In 312 5T CLCLb105 ns TPLAZ PSEN Low to Address Float 10 10 ns TRLRH RD Pulse Width 400 6T CLCLb100 ns TWLWH WR Pulse Width 400 6T CLCLb100 ns TRLDV RD Low to Valid Data In 252 5T CLCLb165 ns TRHDX Data Hold After RD High 0 0 ns TRHDZ Data Float After RD High 97 2T CLCLb70 ns TLLDV ALE Low to Valid Data In 517 8T CLCLb150 ns TAVDV Address Valid to Valid Data In 585 9T CLCLb165 ns TLLWL ALE Low to RD or WR Low 200 300 3T CLCLb50 3T CLCLa50 ns TAVWL Address Valid to RD or WR Low 203 4T CLCLb130 ns TQVWX Data Valid to WR Transition 23 T CLCLb60 ns TWHQX Data Hold After WR High 33 T CLCLb50 ns TRLAZ RD Low to Address Float 0 0 ns TWHLH RD or WR High to ALE High 43 123 T CLCLb40 T CLCLa40 ns

AUTOMOTIVE 80C31BH/80C51BH/87C51 EXTERNAL PROGRAM MEMORY READ CYCLE 270419–12 EXTERNAL DATA MEMORY READ CYCLE 270419–13 EXTERNAL DATA MEMORY WRITE CYCLE 270419–14

AUTOMOTIVE 80C31BH/80C51BH/87C51 EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1/TCLCL Oscillator Frequency 3.5 12 MHz 3.5 16 TCHCX High Time 20 ns TCLCX Low Time 20 ns TCLCH Rise Time 20 ns TCHCL Fall Time 20 ns EXTERNAL CLOCK DRIVE WAVEFORM 270419–17 SERIAL PORT TIMINGÐSHIFT REGISTER MODE

12 MHz Variable

Symbol Parameter Oscillator Oscillator Units Min Max Min Max TXLXL Serial Port Clock Cycle Time 1.0 12T CLCL ms TQVXH Output Data Setup to Clock Rising Edge 700 10T CLCLb133 ns TXHQX Output Data Hold After Clock Rising Edge 50 2T CLCLb117 ns TXHDX Input Data Hold After Clock Rising Edge 0 0 ns TXHDV Clock Rising Edge to Input Data Valid 700 10T CLCLb133 ns SHIFT REGISTER MODE TIMING WAVEFORMS 270419–15 AC TESTING INPUT, OUTPUT WAVEFORMS 270419–16 AC inputs during testing are driven at V CC b 0.5 for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0.’’ Timing measurements are made at V IH min for a Logic ‘‘1’’ and V IL max for a Logic ‘‘0’’. FLOAT WAVEFORMS 270419–18 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV change from the loaded V OH/VOL level occurs. I OL/IOH t g20 mA.

the device as an 87C51 manufactured by Intel. Program Memory verification. Table 3. EPROM Programming Modes (g10 ms) and high for a minimum of 10 ms. Figure 11. Programming Configuration

Figure 13. The other pins are held at the ‘‘Verify shown in later sections of this datasheet. of the program byte with one of the encryption bytes. label be placed over the window. Erasure leaves the array in an all 1s state.

AUTOMOTIVE 80C31BH/80C51BH/87C51 EPROM PROGRAMMING AND VERIFICATION WAVEFORMS 270419–22 *FOR PROGRAMMING CONDITIONS SEE FIGURE 11. FOR VERIFICATION CONDITIONS SEE FIGURE 13. DATASHEET REVISION SUMMARY The following are the key differences between this datasheet and the -006 version: 1. The ‘‘preliminary’’ status was removed and replaced with production status (no label). 2. Trademark was updated. The following are the key differences between the -005 and the -006 version of the datasheet: 1. Preliminary notice added to Title page. 2. Figure 3 Pin Connections the NC pins are now Reserved pins. 3. Figure 3 Pin Connections RST pin is now RESET pin. 4. RST pin description is now RESET pin description. 5. Figure 4 the capacitor values have been removed. 6. CERDIP part reference in the D.C. Characteristics section has been removed. 7. I CC Max characteristics have been corrected to reflect test program conditions. 8. T AVIV and T RLDV formulas changed to correlate 12 MHz timings. The following are the key differences between the -004 and the -005 version of this datasheet: 1. Removed references to burn-in options in Table 1 and added explanation of burn-in offered. Removed references to commercial temperatures. 2. Deleted reference to ‘‘ b1’’ designation 16 MHz. 3. Differentiated V CC for ROM/ROMless and EPROM. The following are the key differences between the -002 and the -003 version of this datasheet: 1. Changed the title to 80C31BH/80C51BH/87C51 CHMOS Single-Chip 8-Bit Microcontroller. 2. Added the pin count for each package version in Figure 2. 3. Removed references to burn-in options in Table 1. 4. Added external oscillator start-up design considerations. The following are the key differences between the -002 and the -001 version of the 80C51BH datasheet: 1. Maximum I OL per I/O pin added. 2. Note 7 on Maximum Current Specifications added to DC Characterstics. 3. Datasheet Revision Summary added.