BD82HM55-SLGZS INTEL | Alldatasheet
Document overview
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- PDF pages: 956
Technical content
Datasheet sections
- 1.1 About This Manual
- 1.2 Overview
- 1.2.1 Capability Overview
- 1.3 Intel ® 5 Series Chipset and Intel® 3400 Series Chipset SKU Definition
- 1.4 Reference Documents
- 2 Signal Description
- 2.1 Direct Media Interface (DMI) to Host Controller
- 2.2 PCI Express*
- 2.3 Firmware Hub Interface
- 2.4 PCI Interface
- 2.5 Serial ATA Interface
- 2.6 LPC Interface
- 2.7 Interrupt Interface
- 2.8 USB Interface
- 2.9 Power Management Interface
- 2.10 Processor Interface
- 2.11 SMBus Interface
- 2.12 System Management Interface
- 2.13 Real Time Clock Interface
- 2.14 Miscellaneous Signals
- 2.15 Intel
- 2.16 Controller Link
- 2.17 Serial Peripheral Interface (SPI)
- 2.18 Intel
- 2.19 JTAG Signals
- 2.20 Clock Signals
- 2.21 LVDS Signals (Mobile only)
- 2.22 Analog Display /CRT DAC Signals
- 2.23 Intel
- 2.24 Digital Display Signals
- 2.25 General Purpose I/O Signals
- 2.26 Manageability Signals
- 2.27 Power and Ground Signals
- 2.28 Pin Straps
- 2.28.1 Functional Straps
- 2.28.2 External RTC Circuitry
- 3.1 Integrated Pull-Ups and Pull-Downs
- 3.2 Output and I/O Signals Planes and States
- 3.3 Power Planes for Input Signals
- 5 Functional Description
- 5.1 DMI-to-PCI Bridge (D30:F0)
- 5.1.1 PCI Bus Interface
- 5.1.2 PCI Bridge As an Initiator
- 5.1.2.1 Memory Reads and Writes
- 5.1.2.2 I/O Reads and Writes
- 5.1.2.3 Configuration Reads and Writes
- 5.1.2.4 Locked Cycles
- 5.1.2.5 Target / Master Aborts
- 5.1.2.6 Secondary Master Latency Timer
- 5.1.2.7 Dual Address Cycle (DAC)
- 5.1.2.8 Memory and I/O Decode to PCI
- 5.1.3 Parity Error Detection and Generation
- 5.1.4 PCIRST#
- 5.1.5 Peer Cycles
- 5.1.6 PCI-to-PCI Bridge Model
- 5.1.7 IDSEL to Device Number Mapping
Document Number: 322169-004 Intel® 5 Series Chipset and Intel® 3400 Series Chipset Datasheet January 2012
2 Datasheet
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained at http:// www.intel.com/design/literature.htm. Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user. Intel ® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM). Functionality, performance or other benefits will vary depending on hardware and software configurations. Software applications may not be compatible with all Intel® Active Management Technology requires activation and a system with a corporate network connection, an Intel® AMT-enabled chipset, network hardware and software. For notebooks, Intel AMT may be unavailable or limited over a host OS-based VPN, when connecting wirelessly, on battery power, sleeping, hibernating or powered off. Results dependent upon hardware, setup & configuration. For more information, visit http:// www.intel.com/technology/platform-technology/intel-amt. Intel® High Definition Audio (Intel® HD Audio) requires an Intel® HD Audio enabled system. Consult your PC manufacturer for more information. Sound quality will depend on equipment and actual implementation. For more information about Intel HD Audio, refer to http://www.intel.com/design/ chipsets/hdaudio.htm. The original equipment manufacturer must provide TPM functionality, which requires a TPM-supported BIOS. TPM functionality must be initialized and may not be available in all countries. Intel® Anti-Theft Technology-PC Protection (Intel® AT-p). No computer system can provide absolute security under all conditions. Intel® Anti-Theft Technology (Intel® AT-p) requires the computer system to have an Intel® AT-enabled chipset, BIOS, firmware release, software and an Intel AT-capable Service Provider/ISV application and service subscription. The detection (triggers), response (actions), and recovery mechanisms only work after the Intel® AT functionality has been activated and configured. Certain functionality may not be offered by some ISVs or service providers and may not be available in all countries. Intel assumes no liability for lost or stolen data and/or systems or any other damages resulting thereof. Systems using Client Initiated Remote Access require wired LAN connectivity and may not be available in public hot spots or "click to accept" locations. For more information, refer to http://software.intel.com/en-us/blogs/2008/10/09/new-with-intel-amt-4050-fast-call-for-help-and-remote-pc-assist-aka- cira/ Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2012, Intel Corporation. All rights reserved.
4 Datasheet
5.3.3.1 Intel
® 5 Series Chipset and Intel® 3400 Series Chipset
5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count
6 Datasheet
5.13.10.1 Power Plane Control with SLP_S3#,
5.16.6 Intel
5.21.2 Thermal Reporting Over System Mana gement Link 1 Interface (SMLink1) . 241 5.21.2.2 I
8 Datasheet
5.22.1.7 Interaction Between Dock/Undock and Power Management
5.23 Intel
5.24.4.3 Intel
® Management Engine Firmware SPI Flash Requirements ...265
5.25 Intel
5.27 PCH Display Interfaces and Intel
5.27.6 Intel
5.28.3 Support for Function Level Reset (FLR) in Intel® 5 Series
5.29 Intel
10.1.15 RPFN—Root Port Function Number and Hide for PCI
10 Datasheet
11.1.7 PMLT—Primary Master Latency Timer Register
11.1.10 SMLT—Secondary Master Latency Timer Register
11.1.11 IOBASE_LIMIT—I/O Base and Limit Register
11.1.13 MEMBASE_LIMIT—Memory Base and Limit Register
11.1.14 PREF_MEM_BASE_LIMIT—Prefetchable Memory Base
11.1.15 PMBU32—Prefetchable Memory Base Upper 32 Bits
11.1.16 PMLU32—Prefetchable Memory Limit Upper 32 Bits
11.1.20 SPDH—Secondary PCI Device Hiding Register
11.1.21 DTC—Delayed Transaction Control Register
11.1.22 BPS—Bridge Proprietary Status Register
11.1.23 BPC—Bridge Policy Configuration Register
11.1.24 SVCAP—Subsystem Vend or Capability Register
12.1 Gigabit LAN Configuration Registers
12.1.1 VID—Vendor Identification Register
12.1.2 DID—Device Identification Register
12.1.3 PCICMD—PCI Command Register
12.1.4 PCISTS—PCI Status Register
12.1.5 RID—Revision Identification Register
12.1.6 CC—Class Code Register
12.1.7 CLS—Cache Line Size Register
12.1.8 PLT—Primary Latency Timer Register
12.1.9 HT—Header Type Register
12.1.10 MBARA—Memory Base Address Register A
12.1.11 MBARB—Memory Base Address Register B
12.1.12 MBARC—Memory Base Address Register C
12.1.13 SVID—Subsystem Vendor ID Register
12.1.14 SID—Subsystem ID Register
12.1.15 ERBA—Expansion ROM Base Address Register
12.1.16 CAPP—Capabilities List Pointer Register
12.1.17 INTR—Interrupt Information Register
12.1.18 MLMG—Maximum Latency/Minimum Grant Register
12.1.19 CLIST 1—Capabilities List Register 1
12.1.20 PMC—PCI Power Management Capabilities Register
12.1.21 PMCS—PCI Power Management Control and Status
12 Datasheet
12.1.22 DR—Data Register
12.1.23 CLIST 2—Capabilities List Register 2
12.1.24 MCTL—Message Control Register
12.1.25 MADDL—Message Address Low Register
12.1.26 MADDH—Message Address High Register
12.1.27 MDAT—Message Data Register
12.1.28 FLRCAP—Function Level Reset Capability
12.1.29 FLRCLV—Function Level Rese t Capability Length and Version
13.1.15 GPIOBASE—GPIO Base Address Register
13.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register
13.1.18 SIRQ_CNTL—Serial IRQ Control Register
13.1.19 PIRQ[n]_ROUT—PIRQ[E,F,G, H] Routing Control Register
13.1.20 LPC_IBDF—IOxAPIC Bus:Device:Function Register
13.1.21 LPC_HnBDF—HPET n Bus:Device:Function Register
13.1.22 LPC_I/O_DEC—I/O Decode Ranges Register
13.1.24 GEN1_DEC—LPC I/F Generic Decode Range 1 Register
13.1.25 GEN2_DEC—LPC I/F Generic Decode Range 2 Register
13.1.26 GEN3_DEC—LPC I/F Generic Decode Range 3 Register
13.1.27 GEN4_DEC—LPC I/F Generic Decode Range 4 Register
13.1.28 ULKMC—USB Legacy Keyboard / Mouse Control
13.1.29 LGMR—LPC I/F Generic Memory Range Register
13.1.30 FWH_SEL1—Firmware Hub Select 1 Register
13.1.31 FWH_SEL2—Firmware Hub Select 2 Register
13.1.32 FWH_DEC_EN1—Firmware Hub Decode Enable
13.1.33 BIOS_CNTL—BIOS Control Register
13.1.34 FDCAP—Feature Detection Capability ID
13.1.35 FDLEN—Feature Detection Capability Length
13.1.36 FDVER—Feature Detection Version
13.1.37 FDVCT—Feature Vector Register
13.1.38 RCBA—Root Complex Base Address Register
13.4.4 ICW3—Master Controller Initialization Command
13.4.5 ICW3—Slave Controlle r Initialization Command
13.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)
13.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)
14 Datasheet
13.8.1 Power Management PCI Configuration Registers
13.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register
13.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register
13.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register
13.8.1.4 GEN_PMCON_LOCK—General Power Management Configuration
13.8.1.7 PMIR—Power Management Initialization Register (PM—D31:F0) .531
13.8.1.8 GPIO_ROUT—GPIO Routing Control Register
13.8.2.1 APM_CNT—Advanced Power Management Control Port Register .532
13.10.6 GP_SB_CMDSTS—GP Serial Blink Command
14.1.8 BCC—Base Class Code Register
14.1.9 PMLT—Primary Master Latency Timer Register
14.1.10 HTYPE—Header Type Register
14.1.11 PCMD_BAR—Primary Command Block Base Address
14.1.12 PCNL_BAR—Primary Control Block Base Address
14.1.13 SCMD_BAR—Secondary Command Block Base Address
14.1.14 SCNL_BAR—Secondary Control Block Base Address
14.1.15 BAR—Legacy Bus Master Base Address Register
14.1.16 ABAR/SIDPBA1—AHCI Base Address Register/Serial ATA
14.1.17 SVID—Subsystem Vendor Identification Register
14.1.24 SDMA_CNT—Synchronous DMA Control Register
14.1.25 SDMA_TIM—Synchronous DMA Timing Register
14.1.26 IDE_CONFIG—IDE I/O Configuration Register
14.1.27 PID—PCI Power Management Capability Identification
14.1.28 PC—PCI Power Management Capabilities Register
14.1.29 PMCS—PCI Power Management Control and Status
14.1.30 MSICI—Message Signaled Interrupt Capability
14.1.31 MSIMC—Message Signaled Interrupt Message
14.1.32 MSIMA—Message Signaled Interrupt Message
14.1.33 MSIMD—Message Signaled Interrupt Message
16 Datasheet
14.1.40 FLRCLV—FLR Capability Length and Version
14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
14.4.1.6 CCC_CTL—Command Completion Coalescing Control
14.4.1.7 CCC_Ports—Command Completion Coalescing Ports
14.4.1.12 RSTF—Intel
14.4.2.1 PxCLB—Port [5:0] Command List Base Address Register
14.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper
14.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits
15.1.8 BCC—Base Class Code Register
15.1.9 PMLT—Primary Master Latency Timer Register
15.1.10 PCMD_BAR—Primary Command Block Base Address
15.1.11 PCNL_BAR—Primary Control Block Base Address Register
15.1.12 SCMD_BAR—Secondary Command Block Base Address
15.1.13 SCNL_BAR—Secondary Control Block Base Address
15.1.14 BAR—Legacy Bus Master Base Address Register
15.1.15 SIDPBA—SATA Index/Data Pair Base Address Register
15.1.16 SVID—Subsystem Vendor Identification Register
15.1.22 SDMA_CNT—Synchronous DMA Control Register
15.1.23 SDMA_TIM—Synchronous DMA Timing Register
15.1.24 IDE_CONFIG—IDE I/O Configuration Register
15.1.25 PID—PCI Power Management Capability Identification
15.1.26 PC—PCI Power Management Capabilities Register
15.1.27 PMCS—PCI Power Management Control and Status
15.1.33 FLRCLV—FLR Capab ility Length and Value
15.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
16.1 USB EHCI Configuration Registers
16.1.1 VID—Vendor Identification Register
16.1.2 DID—Device Identification Register
16.1.3 PCICMD—PCI Command Register
18 Datasheet
16.1.4 PCISTS—PCI Status Register
16.1.5 RID—Revision Identification Register
16.1.6 PI—Programming Interface Register
16.1.7 SCC—Sub Class Code Register
16.1.8 BCC—Base Class Code Register
16.1.9 PMLT—Primary Master Latency Timer Register
16.1.10 HEADTYP—Header Type Register
16.1.11 MEM_BASE—Memory Base Address Register
16.1.12 SVID—USB EHCI Subsystem Vendor ID Register
16.1.13 SID—USB EHCI Subsystem ID Register
16.1.14 CAP_PTR—Capabilities Pointer Register
16.1.15 INT_LN—Interrupt Line Register
16.1.16 INT_PN—Interrupt Pin Register
16.1.17 PWR_CAPID—PCI Power Management Capability ID
16.1.18 NXT_PTR1—Next Item Pointer #1 Register
16.1.19 PWR_CAP—Power Management Capabilities Register
16.1.20 PWR_CNTL_STS—Power Management Control/
16.1.21 DEBUG_CAPID—Debug Port Capability ID Register
16.1.22 NXT_PTR2—Next Item Pointer #2 Register
16.1.23 DEBUG_BASE—Debug Port Base Offset Register
16.1.24 USB_RELNUM—USB Release Number Register
16.1.25 FL_ADJ—Frame Length Adjustment Register
16.1.26 PWAKE_CAP—Port Wake Capability Register
16.1.27 LEG_EXT_CAP—USB EHCI Legacy Support Extended
16.1.28 LEG_EXT_CS—USB EHCI Legacy Support Extended
16.1.29 SPECIAL_SMI—Intel Specific USB 2.0 SMI Register
16.1.30 ACCESS_CNTL—Access Control Register
16.1.31 EHCIIR1—EHCI Initialization Register 1
16.1.33 FLR_CID—Function Level Reset Capability ID
16.1.34 FLR_NEXT—Function Level Reset Next Capability Pointer
16.1.35 FLR_CLV—Function Level Reset Capability Length and
16.1.36 FLR_CTRL—Function Level Reset Control Register
16.1.37 FLR_STS—Function Level Reset Status Register
16.2.1.2 HCIVERSION—Host Controller Interface Version Number
16.2.1.4 HCCPARAMS—Host Controller Capability Parameters
16.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment
16.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address
16.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address
17.1 Intel ® High Definition Audio PCI Configuration
17.1.1 VID—Vendor Identification Register
17.1.2 DID—Device Identification Register
17.1.3 PCICMD—PCI Command Register
17.1.4 PCISTS—PCI Status Register
17.1.5 RID—Revision Identification Register
17.1.6 PI—Programming Interface Register
17.1.7 SCC—Sub Class Code Register
17.1.8 BCC—Base Class Code Register
17.1.9 CLS—Cache Line Size Register
17.1.10 LT—Latency Timer Register
17.1.11 HEADTYP—Header Type Register
17.1.12 HDBARL—Intel ® High Definition Audio Lower Base Address
17.1.13 HDBARU—Intel ® High Definition Audio Upper Base Address Register
17.1.14 SVID—Subsystem Vendor Identification Register
17.1.15 SID—Subsystem Identification Register
17.1.16 CAPPTR—Capabilities Pointer Register
17.1.17 INTLN—Interrupt Line Register
20 Datasheet
17.1.18 INTPN—Interrupt Pin Register
17.1.19 HDCTL—Intel ® High Definition Audio Control Register
17.1.20 HDINIT1—Intel ® High Definition Audio Initialization
Register 1 (Intel® High Definition
17.1.21 TCSEL—Traffic Class Select Register
17.1.22 DCKCTL—Docking Control Register (Mobile Only)
17.1.23 DCKSTS—Docking Status Register (Mobile Only)
17.1.24 PID—PCI Power Management Capability ID Register
17.1.25 PC—Power Management Capabilities Register
17.1.26 PCS—Power Management Control and Status Register
17.1.27 MID—MSI Capab ility ID Register
17.1.28 MMC—MSI Message Control Register
17.1.29 MMLA—MSI Message Lower Address Register
17.1.30 MMUA—MSI Message Upper Address Register
17.1.31 MMD—MSI Message Data Register
17.1.32 PXID—PCI Express* Capability ID Register
17.1.33 PXC—PCI Express* Capabilities Register
17.1.34 DEVCAP—Device Capabilities Register
17.1.35 DEVC—Device Control Register
17.1.36 DEVS—Device Status Register
17.1.37 VCCAP—Virtual Channel Enhanced Capability Header
17.1.38 PVCCAP1—Port VC Capability Register 1
17.1.39 PVCCAP2—Port VC Capability Register 2
17.1.40 PVCCTL—Port VC Control Register
17.1.41 PVCSTS—Port VC Status Register
17.1.42 VC0CAP—VC0 Resource Capability Register
17.1.43 VC0CTL—VC0 Resource Control Register
17.1.44 VC0STS—VC0 Resource Status Register
17.1.45 VCiCAP—VCi Resour ce Capability Register
17.1.46 VCiCTL—VCi Resource Control Register
17.1.47 VCiSTS—VCi Resource Status Register
17.1.48 RCCAP—Root Complex Link Declaration Enhanced
Capability Header Register
17.1.49 ESD—Element Self Description Register
17.1.50 L1DESC—Link 1 Description Register
17.1.51 L1ADDL—Link 1 Lower Address Register
17.1.52 L1ADDU—Link 1 Upper Address Register
17.2 Intel ® High Definition Audio Memory Mapped Configuration Registers
17.2.1 GCAP—Global Capabilities Register
17.2.2 VMIN—Minor Version Register
17.2.3 VMAJ—Major Version Register
17.2.4 OUTPAY—Output Payload Capability Register
17.2.5 INPAY—Input Payload Capability Register
17.2.6 GCTL—Global Control Register
17.2.7 WAKEEN—Wake Enable Register
17.2.8 STATESTS—State Change Status Register
17.2.9 GSTS—Global Status Register
17.2.10 OUTSTRMPAY—Output Stream Payload Capability
17.2.11 INSTRMPAY—Input St ream Payload Capability
17.2.12 INTCTL—Interrupt Control Register
17.2.13 INTSTS—Interrupt Status Register
17.2.14 WALCLK—Wall Clock Counter Register
17.2.15 SSYNC—Stream Synchronization Register
17.2.16 CORBLBASE—CORB Lower Base Address Register
17.2.17 CORBUBASE—CORB Upper Base Address Register
17.2.18 CORBWP—CORB Write Pointer Register
17.2.19 CORBRP—CORB Read Pointer Register
17.2.20 CORBCTL—CORB Control Register
17.2.21 CORBST—CORB Status Register
17.2.22 CORBSIZE—CORB Size Register
17.2.23 RIRBLBASE—RIRB Lower Base Address Register
17.2.24 RIRBUBASE—RIRB Uppe r Base Address Register
17.2.25 RIRBWP—RIRB Write Pointer Register
17.2.26 RINTCNT—Response Interrupt Count Register
17.2.27 RIRBCTL—RIRB Control Register
17.2.28 RIRBSTS—RIRB Status Register
17.2.29 RIRBSIZE—RIRB Size Register
22 Datasheet
17.2.30 IC—Immediate Command Register
17.2.31 IR—Immediate Response Register
17.2.32 ICS—Immediate Command Status Register
17.2.33 DPLBASE—DMA Position Lower Base Address Register
17.2.34 DPUBASE—DMA Position Up per Base Address Register
17.2.35 SDCTL—Stream Descriptor Control Register
17.2.36 SDSTS—Stream Descriptor Status Register
17.2.37 SDLPIB—Stream Descriptor Link Position in Buffer
17.2.38 SDCBL—Stream Descriptor Cyclic Buffer Length Register
17.2.39 SDLVI—Stream Descriptor Last Valid Index Register
17.2.40 SDFIFOW—Stream Descriptor FIFO Watermark Register
17.2.41 SDFIFOS—Stream Descriptor FIFO Size Register
17.2.42 SDFMT—Stream Descriptor Format Register
17.2.43 SDBDPL—Stream Descripto r Buffer Descriptor List
Pointer Lower Base Address Register
17.2.44 SDBDPU—Stream Descripto r Buffer Descriptor List
Pointer Upper Base Address Register
18.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0
18.1.10 SMBMBAR1—D31_F3_SMBus Memory Base Address 1
18.1.11 SMB_BASE—SMBus Base Address Register
18.1.12 SVID—Subsystem Vendor Identification Register
18.1.13 SID—Subsystem Identification Register
18.2.4 XMIT_SLVA—Transmit Slave Address Register
18.2.7 Host_BLOCK_DB—Host Block Data Byte Register
18.2.8 PEC—Packet Error Check (PEC) Register
18.2.9 RCV_SLVA—Receive Slave Address Register
18.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register
18.2.14 SMBus_PIN_CTL—SMBus Pin Control Register
18.2.17 NOTIFY_DADDR—Notify Device Address Register
18.2.18 NOTIFY_DLOW—Notify Data Low Byte Register
18.2.19 NOTIFY_DHIGH—Notify Data High Byte Register
19.1 PCI Express* Configuration Registers
19.1.1 VID—Vendor Identification Register
19.1.2 DID—Device Identification Register
19.1.3 PCICMD—PCI Command Register
19.1.4 PCISTS—PCI Status Register
19.1.5 RID—Revision Identification Register
19.1.6 PI—Programming Interface Register
19.1.7 SCC—Sub Class Code Register
19.1.8 BCC—Base Class Code Register
19.1.9 CLS—Cache Line Size Register
19.1.10 PLT—Primary Latency Timer Register
19.1.11 HEADTYP—Header Type Register
19.1.12 BNUM—Bus Number Register
19.1.13 SLT—Secondary Latency Timer
19.1.14 IOBL—I/O Base and Limit Register
19.1.15 SSTS—Secondary Status Register
19.1.16 MBL—Memory Base and Limit Register
19.1.17 PMBL—Prefetchable Memory Base and Limit Register
19.1.18 PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/
19.1.19 PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/
19.1.20 CAPP—Capabilities List Pointer Register
19.1.21 INTR—Interrupt Information Register
24 Datasheet
19.1.22 BCTRL—Bridge Control Register
19.1.23 CLIST—Capabilities List Register
19.1.24 XCAP—PCI Express* Capabilities Register
19.1.25 DCAP—Device Capabilities Register
19.1.26 DCTL—Device Control Register
19.1.27 DSTS—Device Status Register
19.1.28 LCAP—Link Capabilities Register
19.1.29 LCTL—Link Control Register
19.1.30 LSTS—Link Status Register
19.1.31 SLCAP—Slot Capabilities Register
19.1.32 SLCTL—Slot Control Register
19.1.33 SLSTS—Slot Status Register
19.1.34 RCTL—Root Control Register
19.1.35 RSTS—Root Status Register
19.1.36 DCAP2—Device Capabilities 2 Register
19.1.37 DCTL2—Device Control 2 Register
19.1.38 LCTL2—Link Control 2 Register
19.1.39 MID—Message Signaled Interrupt Identifiers Register
19.1.40 MC—Message Signaled Interrupt Message Control Register
19.1.41 MA—Message Signaled Interrupt Message Address
19.1.42 MD—Message Signaled Interrupt Message Data Register
19.1.43 SVCAP—Subsystem Vendor Capability Register
19.1.44 SVID—Subsystem Vendor Identification Register
19.1.45 PMCAP—Power Management Capability Register
19.1.46 PMC—PCI Power Management Capabilities Register
19.1.47 PMCS—PCI Power Management Control and Status
19.1.48 MPC2—Miscellaneous Port Configuration Register 2
19.1.49 MPC—Miscellaneous Port Configuration Register
19.1.50 SMSCS—SMI/SCI Status Register
19.1.51 RPDCGEN—Root Port Dynamic Clock Gating Enable
19.1.52 PECR1—PCI Express* Configuration Register 1
19.1.53 UES—Uncorrectable Error Status Register
19.1.54 UEM—Uncorrectable Error Mask
19.1.55 UEV—Uncorrectable Error Severity
19.1.56 CES—Correctable Error Status Register
19.1.57 CEM—Correctable Error Mask Register
19.1.58 AECC—Advanced Error Capa bilities and Control Register
19.1.59 RES—Root Error Status Register
19.1.60 PECR2—PCI Express* Configuration Register 2
19.1.61 PEETM—PCI Express* Extended Test Mode Register
19.1.62 PEC1—PCI Express* Configuration Register 1
21.1.1 BFPR –BIOS Flash Primary Region Register
21.1.2 HSFS—Hardware Sequencing Flash Status Register
21.1.3 HSFC—Hardware Sequencing Flash Control Register
21.1.4 FADDR—Flash Address Register
21.1.5 FDATA0—Flash Data 0 Register
21.1.6 FDATAN—Flash Data [N] Register
21.1.7 FRAP—Flash Regions Access Permissions Register
21.1.8 FREG0—Flash Region 0 (F lash Descriptor) Register
21.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register
21.1.10 FREG2—Flash Region 2 (Intel® ME) Register
21.1.11 FREG3—Flash Region 3 (GbE) Register
21.1.12 FREG4—Flash Region 4 (Platform Data) Register
21.1.13 PR0—Protected Range 0 Register
21.1.14 PR1—Protected Range 1 Register
21.1.15 PR2—Protected Range 2 Register
21.1.16 PR3—Protected Range 3 Register
21.1.17 PR4—Protected Range 4 Register
21.1.18 SSFS—Software Sequencing Flash Status Register
21.1.19 SSFC—Software Sequencing Flash Control Register
26 Datasheet
21.1.20 PREOP—Prefix Opcode Configuration Register
21.1.21 OPTYPE—Opcode Type Configuration Register
21.1.22 OPMENU—Opcode Menu Configuration Register
21.1.23 BBAR—BIOS Base Address Configuration Register
21.1.24 FDOC—Flash Descriptor Observability Control Register
21.1.25 FDOD—Flash Descriptor Observability Data Register
21.1.26 AFC—Additional Flash Control Register
21.1.27 LVSCC—Host Lower Vendor Specific Component
21.1.28 UVSCC—Host Upper Vendor Specific Component
21.1.29 FPB—Flash Partition Boundary Register
21.4.1 GLFPR –Gigabit LAN Flash Primary Region Register
21.4.2 HSFS—Hardware Sequencing Flash Status Register
21.4.3 HSFC—Hardware Sequencing Flash Control Register
21.4.4 FADDR—Flash Address Register
21.4.5 FDATA0—Flash Data 0 Register
21.4.6 FRAP—Flash Regions Access Permissions Register
21.4.7 FREG0—Flash Region 0 (Flash Descriptor) Register
21.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register
21.4.9 FREG2—Flash Region 2 (Intel® ME) Register
21.4.10 FREG3—Flash Region 3 (GbE) Register
21.4.11 PR0—Protected Range 0 Register
21.4.12 PR1—Protected Range 1 Register
21.4.13 SSFS—Software Sequencing Flash Status Register
21.4.14 SSFC—Software Sequencing Flash Control Register
21.4.15 PREOP—Prefix Opcode Configuration Register
21.4.16 OPTYPE—Opcode Type Configuration Register
21.4.17 OPMENU—Opcode Menu Configuration Register
22.1.20 TBARBH—BIOS Assigned Thermal Base High DWord
22.2 Thermal Memory Mapped Configuration Registers
22.2.8 TSGPEN—Thermal Sensor General Purpose Event
22.2.10 PPEC—Processor Power Error Correction Register
22.2.13 MGTA—Memory Controller/Graphics Temperature
22.2.24 MGTV—Memory Controller/Graphics Temperature
22.2.26 MMGPC—Max Memory Controller/Graphics Power Clamp
22.2.28 MPCPC—Max Processor Core Power Clamp Register
28 Datasheet
23.1 First Intel ® Management Engine Interface (Intel® MEI) Configuration Registers
23.1.1 VID—Vendor Identification Register
23.1.2 DID—Device Identification Register
23.1.3 PCICMD—PCI Command Register
23.1.4 PCISTS—PCI Status Register
23.1.5 RID—Revision Identification Register
23.1.6 CC—Class Code Register
23.1.7 HTYPE—Header Type Register
23.1.8 MEI0_MBAR—MEI0 MMIO Base Address Register
23.1.9 SVID—Subsystem Vendor ID Register
23.1.10 SID—Subsystem ID Register
23.1.11 CAPP—Capabilities List Pointer Register
23.1.12 INTR—Interrupt Information Register
23.1.13 HFS—Host Firmware Status Register
23.1.14 ME_UMA—Management Engine UMA Register
23.1.15 GMES—General ME Status Register
23.1.16 H_GS—Host General Status Register
23.1.17 PID—PCI Power Management Capability ID Register
23.1.18 PC—PCI Power Management Capabilities Register
23.1.19 PMCS—PCI Power Management Control and Status
23.1.20 MID—Message Signaled Interrupt Identifiers Register
23.1.21 MC—Message Signaled Interrupt Message Control Register
23.1.22 MA—Message Signaled Interrupt Message Address
23.1.23 MUA—Message Signaled Interrupt Upper Address Register
23.1.24 MD—Message Signaled Interrupt Message Data Register
23.1.25 HIDM—MEI Interrupt Delivery Mode Register
23.1.26 HERES—MEI Extend Register Status
23.1.27 HERX—MEI Extend Register DWX
23.2 Second Management Engine Inte rface(MEI1) Configuration Registers
23.2.1 VID—Vendor Identification Register
23.2.2 DID—Device Identification Register
23.2.3 PCICMD—PCI Command Register
23.2.4 PCISTS—PCI Status Register
23.2.5 RID—Revision Identification Register
23.2.6 CC—Class Code Register
23.2.7 HTYPE—Header Type Register
23.2.8 MEI_MBAR—MEI MMIO Base Address Register
23.2.9 SVID—Subsystem Vendor ID Register
23.2.10 SID—Subsystem ID Register
23.2.11 CAPP—Capabilities List Pointer Register
23.2.12 INTR—Interrupt Information Register
23.2.13 HFS—Host Firmware Status Register
23.2.14 GMES—General ME Status Register
23.2.15 H_GS—Host General Status Register
23.2.16 PID—PCI Power Management Capability ID Register
23.2.17 PC—PCI Power Management Capabilities Register
23.2.18 PMCS—PCI Power Management Control and Status
23.2.19 MID—Message Signaled Interrupt Identifiers Register
23.2.20 MC—Message Signaled Interrupt Message Control Register
23.2.21 MA—Message Signaled Interrupt Message Address
23.2.22 MUA—Message Signaled Interrupt Upper Address Register
23.2.23 MD—Message Signaled Interrupt Message Data Register
23.2.24 HIDM—MEI Interrupt Delivery Mode Register
23.2.25 HERES—MEI Extend Register Status
23.2.26 HERX—MEI Extend Register DWX
23.3.1 H_CB_WW—Host Circular Buffer Write Window Register
23.3.2 H_CSR—Host Control Status Register
23.3.3 ME_CB_RW—ME Circular Buffer Read Window Register
23.3.4 ME CSR_HA—ME Control St atus Host Access Register
23.4.1 H_CB_WW—Host Circular Buffer Write Window Register
23.4.2 H_CSR—Host Control Status Register
23.4.3 ME_CB_RW—ME Circular Buffer Read Window Register
23.4.4 ME CSR_HA—ME Control St atus Host Access Register
23.5 IDE Function for Remote Boot and Installations
30 Datasheet
23.5.8 PCMDBA—Primary Command Block IO Bar Register
23.5.9 PCTLBA—Primary Control Block Base Address Register
23.5.10 SCMDBA—Secondary Command Block Base Address
23.5.11 SCTLBA—Secondary Control Block base Address
23.5.12 LBAR—Legacy Bus Master Base Address Register
23.5.15 CAPP—Capabilities List Pointer Register
23.5.16 INTR—Interrupt Information Register
23.5.17 PID—PCI Power Management Capability ID Register
23.5.18 PC—PCI Power Management Capabilities Register
23.5.19 PMCS—PCI Power Management Control and Status
23.5.20 MID—Message Signaled Interrupt Capability ID
23.5.21 MC—Message Signaled Interrupt Message Control
23.5.22 MA—Message Signaled Interrupt Message Address
23.5.23 MAU—Message Signaled Interrupt Message Upper
23.5.24 MD—Message Signaled Interrupt Message Data
23.6.2 IDEERD1—IDE Error Register DEV1
23.6.3 IDEERD0—IDE Error Register DEV0
23.6.4 IDEFR—IDE Features Register
23.6.5 IDESCIR—IDE Sector Count In Register
23.6.6 IDESCOR1—IDE Sector Count Out Register Device 1
23.6.7 IDESCOR0—IDE Sector Count Out Register Device
23.6.8 IDESNOR0—IDE Sector Number Out Register
23.6.9 IDESNOR1—IDE Sector Number Out Register
23.6.10 IDESNIR—IDE Sector Number In Register Register
23.6.11 IDECLIR—IDE Cylinder Low In Register Register
23.6.12 IDCLOR1—IDE Cylinder Low Out Register Device 1
23.6.13 IDCLOR0—IDE Cylinder Low Out Register Device 0
23.6.14 IDCHOR0—IDE Cylinder High Out Register Device 0
23.6.15 IDCHOR1—IDE Cylinder High Out Register Device 1
23.6.16 IDECHIR—IDE Cylinder High In Register
23.6.17 IDEDHIR—IDE Drive/Head In Register
23.6.18 IDDHOR1—IDE Drive Head Out Register Device 1
23.6.19 IDDHOR0—IDE Drive Head Out Register Device 0
23.6.20 IDESD0R—IDE Status Device 0 Register
23.6.21 IDESD1R—IDE Status Device 1 Register
23.8.1 IDEPBMCR—IDE Primary Bus Master Command
23.8.2 IDEPBMDS0R—IDE Prim ary Bus Master Device
23.8.3 IDEPBMSR—IDE Primary Bus Master Status
23.8.4 IDEPBMDS1R—IDE Prim ary Bus Master Device
23.8.5 IDEPBMDTPR0—IDE Primary Bus Master Descriptor
23.8.6 IDEPBMDTPR1—IDE Primary Bus Master Descriptor
23.8.7 IDEPBMDTPR2—IDE Primary Bus Master Descriptor
23.8.8 IDEPBMDTPR3—IDE Primary Bus Master Descriptor
23.8.9 IDESBMCR—IDE Secondary Bus Master Command
23.8.10 IDESBMDS0R—IDE Secondary Bus Master Device
23.8.11 IDESBMSR—IDE Secondary Bus Master Status
23.8.12 IDESBMDS1R—IDE Secondary Bus Master Device
23.8.13 IDESBMDTPR0—IDE Second ary Bus Master Descriptor
23.8.14 IDESBMDTPR1—IDE Second ary Bus Master Descriptor
23.8.15 IDESBMDTPR2—IDE Second ary Bus Master Descriptor
23.8.16 IDESBMDTPR3—IDE Second ary Bus Master Descriptor
23.9 Serial Port for Remote Keyboard and Text (KT)
23.9.8 KTIBA—KT IO Block Base Address Register
23.9.9 KTMBA—KT Memory Block Base Address Register
32 Datasheet
23.9.14 PID—PCI Power Management Capability ID Register
23.9.15 PC—PCI Power Management Capabilities ID Register
23.9.16 MID—Message Signaled Interrupt Capability ID
23.9.17 MC—Message Signaled Interrupt Message Control
23.9.18 MA—Message Signaled Interrupt Message Address
23.9.19 MAU—Message Signaled Interrupt Message Upper
23.9.20 MD—Message Signaled Interrupt Message Data
23.10.6 KTIIR—KT Interrupt Identification Register
34 Datasheet
8-14 CRT DAC Signal Group DC Characteristics: Functional Operating Range 8-22 DDC Characteristics DDC Signals: CRT_DDC_CLK, CRT_DDC_DATA, L_DDC_CLK, L_DDC_DATA, SDVO_CTRLCLK, SDVO_CTRLDATA, DDP[D:C]_CTRLCLK, 8-30 Intel 9-2 Fixed I/O Ranges Decoded by Intel 12-1 Gigabit LAN Configuration Registers Address Map
36 Datasheet
® High Definition Audio PCI Register Address Map 17-2 Intel ® High Definition Audio PCI Register Address Map 19-1 PCI Express* Configuration Registers Address Map 21-1 Serial Peripheral Interface (SPI) Register Address Map 21-2 Gigabit LAN SPI Flash Program Register Address Map 23-1 Intel ® MEI Configuration Registers Address Map 23-1 MEI1 Configuration Registers Address Map 23-7 Serial Port for Remote Keyboard and Text (KT) Redirection Register
Revision History
Number Description Revision Date 001 • Initial release. September 2009 002
- SATA Port Multiplier Removal
- 1.5V On-Die PLL Voltage Regulator Support Removal
- Update on Note 9 for Table 2-25, “General Purpose I/O Signal”
- Updated GPIO15 and GPIO27 in Table 2-28, “Functional Strap Definition”
- Added Measure Icc for SFF Table
- Updated Measured Icc for Desktop and Mobile Tables
- Updated Table 2-20 CLKOUTFLEX0 type
- Updated PCIe Port Configurations
- Updated PME_B0_S5_DIS Bit Discription
- Updated Section 5.14.2.2 Advanced TCO Mode
- Updated Table 9-9 Other DC Characteristics
- Updated GCAP_ID Default Value
- Updated t240 and t218 Power Sequencing and Reset Signal Timings
- Added XTAL25 DC and AC Characteristics
- Added CEV1 Core Energy Valu e 1 Register to Section 22.2
- Updated Section 14.4.1.11 VSP - Vendor Specific Default Value
- Updated Desktop SKUs Definitions
- Added BCLK Input to AC Characteristics
- Updated MPC2- Miscellaneous Port Configuration Register 2
- Updated DMIC - DMI Control Register Description
- Updated NV_CLE Nomical pull- down in Table 3-1. Integrated Pull-ups and Pull-Downs
- Updated Section 10.1.62 BUC - Backed Up Control Register January 2010 003
- Addeed Intel ® B55 Express Chipset
- Updated bit description for USBIRA—USB Initialization Register A
- Updated Table 2-29. Intel ® 5 Series Chipset and Intel® 3400 Series Chipset Device and Revision ID Table.
- Updated bit description for GP_RST_SEL1 — GPIO Reset Select register
- Updated bit description for GP_RST_SEL2 — GPIO Reset Select register
- Updated bit description for GP_RST_SEL3 — GPIO Reset Select register
- Update Table 3-1 to include SPI_CS0#
- Updated Table 8-1, Storage Conditions
- Updated Table 8-14, PCI Express* Interface Timings
- Updated Section 21.1.2, HSFS—Hardwar e Sequencing Flash Status Register June 2010
38 Datasheet
- Updated Table 1-1, Industry Standards
- Updated Section 1.2, Overview — Updated the initial set of bullets —U p d a t e d I n t e l® Active Management Technology Section — Updated Serial Over Lan (SOL) Function Section —A d d e d K V M S e c t i o n — Updated IDE-R Function Section — Added PCH Display Interface Section —A d d e d I n t e l ® Flexible Display Interconnect (FDI) Section
- Updated Table 2-5, Serial ATA Interface Signals — Added TEMP_ALERT# to the SATA5G P /GPIO49 / TEMP_ALERT# Signals — SCLOCK/GPIO22 Signal
- Added note under Table 2-7, “Interrupt Signals”
- Updated Table 2-8, “USB Interface Signals” Overcurrent Indicators description.
- Updated Table 2-9, “Power Management In terface Signals” description for SLP_LAN#/ GPIO29.
- Update Table 2-15, “Intel High Definition Audio LInk Signals” description for HDA_DOCK_RST#/GPIO13.
- Added Note 12 to Table 2-25, “General Purpose I/O SIgnals”.
- Updated Table 2-27, “Power and Ground Signals” description for DcpSusByp.
- Updated Table 2-28, “Functional Strap Definitions” Comment column for GNT3#/ GPIO55.
- Updated Table 2-29, “Intel 5 Series Chip set and Intel 3400 Series Chipset Device and Revision ID Table”.
- Added Note to Section 5.2, “PCI Express* Root Ports (D28:F0, F1,F2,F3,F4,F5,F6,F7)”.
- Added note on wake up settings to Section 5.3.4.1.1, “Advanced Power Management
- Updated Table 5-27, “Causes of Wake Events”. and SRTCRST#”.
- Updated Section 5.13.13, “Reset Behavior”.
- Updated Section 5.14.2. 2, “Advanced TCO Mode”.
- Updated Section 5.16. 11, “SGPIO Signals”.
- Added note to Block Read/Write command in Section 5.20.1.1, “Command Protocols” for the SMBus Host Controller.
- Updated Section 5.27, “P CH Display Interfaces”.
- Updated Section 8.2, “Absolute Maximum and Minimum Ratings”.
- Updated VOL3 and VOH3 in Table 8-10, “DC Output Characteristics”.
- Updated VccVRM in Table 8-11, “Other DC Characteristics”. Also, Added Note 3 to the table.
- Added notes to Table 8-16, “PCI Express* Interface Timings”, Table 8-17, “HDMI Interface Timings”, and Table 8-18, “SDVO Interface Timings“.
- Added SMLink0 Clock timings to Table 8-24, “Clock Timings”.
- Updated Table 8-28, “SMBus Timing”.
- Updated Table 8-37, “Controller Link Receive Timings”.
- Added Note 18 to Table 8-18, “Power Se quencing and Reset Signal Timings” for LAN_RST# timing.
- Added Figure 8-30, “Controller Link Receive Timings” and Figure 8-31, “Controller Link Receive Slew Rate”. January 2012 Revision Number Description Revision Date
- Chapter 9, “Register and Memory Mapping” — Added R/WL register access attribute de finition and updated the definition for “Default”. — Added notes to Table 9-1, “PCI Devices and Functions”. — Updated Table 9-2, “Fixed I/O Ranges Decoded by Intel PCH”. — Updated Table 9-3, “Variable I/O Decode Ranges”. — Updated Table 9-4, “Memory Decode Ranges from Processor Perspective”. — Updated Section 9.4.1, “Boot-Block Update Scheme”.
- Updated Section 10.1.9, “LCAP—Link Capab ilities Register” Bits 17:15 L1 Exit Latency (EL1).
- Updated Section 10.1.10, “LCTL—Link Control Register”.
- Updated Section 10.1.15, “RPFN—Root Port Function Number and Hide for PCI Express* Root Ports” for bits 30:28 and 26:24.
- Updated Section 10.1.43, “OIC— Other Interrupt Control Register” note below table.
- Updated Section 10.1.62, “BUC—Backed Up control Register” bit 5 and bit 0.
- Updated Section 10.1.64, “CG—Clock Gating Register” bits 29:28.
- Updated Section 10.1.69, “USBOCM2 —Overcurrent MAP Register 2”.
- Added Section 13.1.12, “CAPP—Capability Li st Pointer Register (LPC I/F—D31:Fo)
- Updated Section 14.1.22, “IDE_TIM—IDE Timing Register (SATA–D31:F2)”.
- Added Section 14.1.23, “SIDETIM—Slave IDE Timing Register”, Section 14.1.24, “SDMA_CNT—Synchronous DMA Control Register”, Section 14.1.25, “SDMA_TIM—Synchronous DMA Timing Register”, and Section 14.1.26, “IDE_CONFIG—IDE I/O COnfiguration Register”.
- Updated Section 14.1.37, “SCLKGC—SATA Clock General Configuration Register”.
- Updated Section 14.3.2.3, “PxSERR—Serial ATA Error Register (B31:F2)” bit 23.
- Updated Section 14.4.1.10, “RSTF—RST Feature Capabilities Register” bit 7.
- Updated Section 14.4.1.12, “Intel ® RST Feature Capabilities”.
- Updated Section 14.4.2.5, “P xIS—Port [5:0] Interrupt Status Register (D31:F2)” and Section 14.4.2.6, “PxIE—Port [5:0] Interrupt Enable Register 9D31:F2)”
- Updated Section 15.1.21, “IDE_TIM—I DE Timing Register (SATA–D31:F5)”
- Added Section 15.1.22, “SDMA_CNT—Synchronous DMA Control Register”, Section 15.1.23, “SDMB_TIM—Synchronous DMA Timing Register”, and Section 15.1.24, “IDE_CONFIG—IDE I/O COnfiguration Register”.
- Added note to Section 16.1, “USB EHCI Configuration Registers (USB EHCI—D29:F0, D26:F0)”.
- Updated Section 16.1.20, “PWR_CNTL_STS—Power Managment Control/Status Register” bits 1:0.
- Updated Section 16.1.31, “EHCIR1—EHCI Initialization Register 1”
- Added Section 16.1.32, “EHCIIR2—EHCI Init ialization Register 2, Section 16.1.38, “EHCIIR3—EHCI Initialization Register 3”, and Section 16.1.39, “EHCIIR4—EHCI Initialization Register 4”.
- Added Section 17.1.20, “HDINIT1—Intel High Definition Audio Initialization Register 1”.
- Updated Section 17.2.15, “SSYNC—S tream Synchronization Register”.
- Added note to Section 19.1, “PCI Express Configuration Registers (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)”.
- Updated Section 21.1.2, “H SFS—Hardware Sequencing Flash Status Register” bit 13 and Section 21.4.2, “HSFS— Hardware Sequencing Flash Status Register” bit 13
- Updated Section 22.1.3, “CMD—Command” bit 2.
- Updated Section 22.2.5, “TSTTP—Thermal Sens or Temperature Trip Point Register” bits 23:16.
- Updated Section 22.2.12, “P TA—PCH Temperature Adjust”. January 2012 Revision Number Description Revision Date
40 Datasheet
Platform Controller Hub (PCH)
Features
Direct Media Interface — 10 Gb/s each dire ction, full duplex — Transparent to software PCI Express* — NEW: 8 PCI Express root ports — NEW: PCI Express 2.0 specification running at 2.5 GT/s. — NEW: Ports 1–4 or Ports 5–8 can independently be configured to support four x1s, two x2s, one x2 and 2 x1s, or one x4 port widths. — Support for full 2.5 Gb /s bandwidth in each direction per x1 lane — Module based Hot-Plug supported (such as, ExpressCard*) PCI Bus Interface — Supports PCI Rev 2.3 Specification at 33 MHz — Four available PCI REQ/GNT pairs — Support for 64-bit addressing on PCI using DAC protocol Integrated Serial ATA Host Controller — Up to six SATA ports — Data transfer rates up to 3.0 Gb/s (300 MB/s). — Integrated AHCI controller External SATA support — NEW: Port Disable Capability Intel® Rapid Storage Technology — Configures the PCH SATA controller as a RAID controller supporting RAID 0/1/5/10 Intel® High Definition Audio Interface — PCI Express endpoint — Independent Bus Master logic for eight general purpose streams: four input and four output — Support four external Codecs — Supports variable length stream slots — Supports multichannel, 32-bit sample depth, 192 kHz sample rate output — Provides mic array support — Allows for non-48 kHz sampling output — Support for ACPI Device States —L o w V o l t a g e M o d e Intel® Quiet System Technology — Four TACH signals and Four PWM signals Simple Serial Transport (SST) 1.0 Bus and Platform Environmental Control Interface (PECI) USB 2.0 — Two EHCI Host Controllers, supporting up to fourteen external ports —P e r - P o r t - D i s able Capability — Includes up to two USB 2.0 High-speed Debug Ports — Supports wake-up from sleeping states S1–S4 — Supports legacy Keyboard/Mouse software Integrated Gigabit LAN Controller — NEW: PCI Express* connection — Integrated ASF Management Controller — Network security wi th System Defense — Supports IEEE 802.3 — 10/100/1000 Mbps Ethernet Support — Jumbo Frame Support Intel® Active Management Technology with System Defense — NEW: Network Outbreak Containment Heuristics Intel® I/O Virtualization (VT-d) Support Intel® Trusted Execution Technology Support Power Management Logic — Supports ACPI 4.0a — ACPI-defined power states (system level S0, S1, S3, S4, and S5 states, various internal device levels of Dx states, and processor driven C states) — ACPI Power Management Timer —S M I # g e n e r a t i o n — All registers readable/restorable for proper resume from 0 V suspend states — Support for A-based le gacy power management for non-ACPI implementations External Glue Integration — Integrated Pull-up, Pull-down and Series Termination resistors on processor interface — Integrated Pull-down and Series resistors on USB Enhanced DMA Controller — Two cascaded 8237 DMA controllers — Supports LPC DMA
Note: Not all features are available on all PCH SKUs. See Section 1.3 for more details. § § SMBus — Faster speed, up to 100 kbps — Flexible SMBus/SMLink ar chitecture to optimize for ASF — Provides independent ma nageability bus through SMLink interface — Supports SMBus 2.0 Specification — Host interface allows pr ocessor to communicate using SMBus — Slave interface allows an internal or external Microcontroller to access system resources — Compatible with most two-wire components that are also I2C compatible High Precision Event Timers — Advanced operating syst em interrupt scheduling Timers Based on 8254 — System timer, Refresh request, Speaker tone output Real-Time Clock — 256-byte battery-backed CMOS RAM — Integrated oscillator components — Lower Power DC/DC Converter implementation System TCO Reduction Circuits — Timers to generate SMI# and Reset upon detection of system hang — Timers to detect impr oper processor reset — Integrated processor frequency strap logic — Supports ability to di sable external devices Serial Peripheral Interface (SPI) — Supports up to two SPI devices — Supports 20 MHz, 33 MHz, and 50 MHz SPI devices — Support up to two diffe rent erase granularities Interrupt Controller — Supports up to eigh t PCI interrupt pins — Supports PCI 2.3 Message Signaled Interrupts — Two cascaded 8259 with 15 interrupts — Integrated I/O APIC capability with 24 interrupts — Supports Processor Sy stem Bus interrupt delivery 1.05 V operation with 1.5 V and 3.3 V I/O — 5 V tolerant buffers on PCI, USB and selected Legacy signals 1.05 V Core Voltage Five Integrated Voltage Regulators for different power rails Firmware Hub Interface supports BIOS Memory size up to 8 MB Low Pin Count (LPC) I/F — Supports two Master/DMA devices. — Support for Security De vice (Trusted Platform Module) connected to LPC. GPIO — TTL, Open-Drain, Inversion —G P I O l o c k d o w n Package — 27 mm x 27 mm FCBGA (Desktop Only) — 27 mm x 25 mm FCBGA (Mobile Only) — 22 mm x 20 mm FCBGA (Mobile SFF Only) Analog Display Port Digital Display — Three Digital Display ports capable of supporting HDMI/DVI and Display port — One Digital Display port supporting SDVO —L D V S ( M o b i l e O n l y ) Intel® Anti-Theft Technology JTAG — Boundary Scan for testing during board manufacturing
42 Datasheet
1 Introduction
1.1 About This Manual
This document is intended for Original Equipment Manufacturers and BIOS vendors creating Intel® 5 Series Chipset and Intel® 3400 Series Chipset based products. This document is for the following components:
- I n t e l® 5 Series Chipset —I n t e l® P55 Express Chipset —I n t e l® H55 Express Chipset —I n t e l® H57 Express Chipset —I n t e l® Q57 Express Chipset —I n t e l® B55 Express Chipset —I n t e l® PM55 Express Chipset —I n t e l® QM57 Express Chipset —I n t e l® HM55 Express Chipset —I n t e l® HM57 Express Chipset —I n t e l® QS57 Express Chipset
- I n t e l® 3400 Series Chipset —I n t e l® 3400 Chipset —I n t e l® 3420 Chipset —I n t e l® 3450 Chipset Section 1.3 provides high-level feature differences for the Intel® 5 Series Chipset and Intel® 3400 Series Chipset. Note: Throughout this document, PCH is used as a general term and refers to the Intel® 5 Series Chipset and Intel® 3400 Series Chipset, unless specifically noted otherwise. Note: Throughout this document, the term “Desktop” refers to information that is for the Intel® P55 Express Chipset, Intel® H55 Express Chipset, Intel® H57 Express Chipset, Intel® Q57 Express Chipset, Intel® B55 Express Chipset, Intel® 3400 Chipset, Intel® 3420 Chipset, Intel® 3450 Chipset, unless specifically noted otherwise. Throughout this document, the term “Mobile Only” refers to information that is for the Intel® PM55 Express Chipset, Intel® QM57 Express Chipset, Intel® HM55 Express Chipset, Intel® HM57 Express Chipset, and the Intel® QS57 Express Chipset, unless specifically noted otherwise. This manual assumes a working knowledge of the vocabulary and principles of PCI Express*, USB, AHCI, SATA, Intel® High Definition Audio (Intel® HD Audio), SMBus, PCI, ACPI, and LPC. Although some details of these features are described within this manual, see the individual industry specifications listed in Table 1-1 for the complete details.
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Table 1-1. Industry Specifications Specification Location PCI Express* Base Specification, Revision 1.1 http://www.pcisig.com/specifications PCI Express* Base Specification, Revision 2.0 http://www.pcisig.com/specifications Low Pin Count Interface Specification, Revision 1.1 (LPC) http://developer.intel.com/design/ chipsets/industry/lpc.htm System Management Bus Specification, Version 2.0 (SMBus) http://www.smbus.org/specs/ PCI Local Bus Specification, Revision 2.3 (PCI) http://www.pcisig.com/specifications PCI Power Management Specification, Revision 1.2 http://www.pcisig.com/specifications SFF-8485 Specification for Serial GPIO (SGPIO) Bus, Revision 0.7 ftp://ftp.seagate.com/sff/SFF-8485.PDF Advanced Host Controller Interface specification for Serial ATA, Revision 1.2 http://www.intel.com/technology/ serialata/ahci.htm Intel ® High Definition Audio Specification, Revision 1.0 http://www.intel.com/standards/ hdaudio/ Universal Serial Bus Specification (USB), Revision 2.0 http://www.usb.org/developers/docs Advanced Configuration and Power Interface, Version 3.0b (ACPI) http://www.acpi.info/spec.htm Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 (EHCI) http://developer.intel.com/technology/ usb/ehcispec.htm Serial ATA Specification, Revision 2.5 http://www.serialata.org/ Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0 http://www.serialata.org/ Serial ATA II Cables and Connectors Volume 2 Gold http://www.serialata.org/ Alert Standard Format Specification, Version 1.03 http://www.dmtf.org/standards/asf IEEE 802.3 Fast Ethernet http://standards.ieee.org/getieee802/ AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) http://T13.org (T13 1410D) IA-PC HPET (High Precision Event Timers) Specification, Revision 0.98a http://www.intel.com/hardwaredesign/ hpetspec.htm TPM Specification 1.02, Level 2 Revision 103 http://www.trustedcomputinggroup.org/ specs/TPM Intel ® Virtualization Technology http://www.intel.com/technology/ platform-technology/virtualization/ index.htm
Chapter 1. Introduction Chapter 1 introduces the PCH and provides information on manual organization and gives a general overview of the PCH. Chapter 2. Signal Description Chapter 2 provides a block diagram of the PCH and a detailed description of each signal. Signals are arranged according to interface and details are provided as to the drive characteristics (Input/Output, Open Drain, etc.) of all signals. Chapter 3. PCH Pin States Chapter 3 provides a complete list of signals, their associated power well, their logic level in each power state, and their logic level before and after reset. Chapter 4. PCH and System Clock Domains Chapter 4 provides a list of each clock domain associated with the PCH in an Intel® 5 Series Chipset or Intel® 3400 Series Chipset based system. Chapter 5. Functional Description Chapter 5 provides a detailed description of the functions in the PCH. All PCI buses, devices and functions in this manual are abbreviated using the following nomenclature; Bus:Device:Function. This manual abbreviates buses as B0 and B1, devices as D22, D25, D25, D26, D27, D28, D29, D30 and D31 and functions as F0, F1, F2, F3, F4, F5, F6 and F7. For example Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be considered to be Bus 0. Note that the PCH external PCI bus is typically Bus 1, but may be assigned a different number depending upon system configuration. Chapter 6. Ballout Definition Chapter 6 provides a table of each signal and its ball assignment in the package. Chapter 7. Package Information Chapter 7 provides drawings of the physical dimensions and characteristics of the package. Chapter 8. Electrical Characteristics Chapter 8 provides all AC and DC characteristics including detailed timing diagrams. Chapter 9. Register and Memory Mappings Chapter 9 provides an overview of the registers, fixed I/O ranges, variable I/O ranges and memory ranges decoded by the PCH. Chapter 10. Chipset Configuration Registers Chapter 10 provides a detailed description of all registers and base functionality that is related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI Express*). It contains the root complex register block, which describes the behavior of the upstream internal link. Chapter 11. PCI-to-PCI Bridge Registers Chapter 11 provides a detailed description of all registers that reside in the PCI-to-PCI bridge. This bridge resides at Device 30, Function 0 (D30:F0). Chapter 12. Integrated LAN Controller Registers Chapter 12 provides a detailed description of all registers that reside in the PCH’s integrated LAN controller. The integrated LAN Controller resides at Device 25, Function 0 (D25:F0). Chapter 13. LPC Bridge Registers Chapter 13 provides a detailed description of all registers that reside in the LPC bridge. This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers for many different units within the PCH including DMA, Timers, Interrupts, Processor Interface, GPIO, Power Management, System Management and RTC.
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Chapter 14. SATA Controller Registers Chapter 14 provides a detailed description of all registers that reside in the SATA controller #1. This controller resides at Device 31, Function 2 (D31:F2). Chapter 15. SATA Controller Registers Chapter 15 provides a detailed description of all registers that reside in the SATA controller #2. This controller resides at Device 31, Function 5 (D31:F5). Chapter 16. EHCI Controller Registers Chapter 16 provides a detailed description of all registers that reside in the two EHCI host controllers. These controllers reside at Device 29, Function 0 (D29:F0) and Device 26, Function 0 (D26:F0). Chapter 17. Intel® High Definition Audio Controller Registers Chapter 17 provides a detailed description of all registers that reside in the Intel® High Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0). Chapter 18. SMBus Controller Registers Chapter 18 provides a detailed description of all registers that reside in the SMBus controller. This controller resides at Device 31, Function 3 (D31:F3). Chapter 19. PCI Express* Port Controller Registers Chapter 19 provides a detailed description of all registers that reside in the PCI Express controller. This controller resides at Device 28, Functions 0 to 5 (D28:F0-F7). Chapter 20. High Precision Event Timers Registers Chapter 20 provides a detailed description of all registers that reside in the multimedia timer memory mapped register space. Chapter 21. Serial Peripheral Interface Registers Chapter 21 provides a detailed description of all registers that reside in the SPI memory mapped register space. Chapter 22. Thermal Sensors Chapter 22 provides a detailed description of all registers that reside in the thermal sensors PCI configuration space. The registers reside at Device 31, Function 6 (D31:F6). Chapter 23. Intel® Management Engine (Intel® ME) Chapter 23 provides a detailed description of all registers that reside in the Intel ME controller. The registers reside at Device 22, Function 0 (D22:F0).
1.2 Overview
The PCH provides extensive I/O support. Functions and capabilities include:
- PCI Express* Base Specification, Revision 2.0 support for up to eight ports
- PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations (supports up to four Req/Gnt pairs)
- ACPI Power Management Logic Support, Revision 3.0b
- Enhanced DMA controller, interrupt controller, and timer functions
- Integrated Serial ATA host controllers with independent DMA operation on up to six ports
- USB host interface with support for up to fourteen USB ports; two EHCI high-speed USB 2.0 Host controllers and 2 rate matching hubs
- Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense
- System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices
- Supports Intel ® High Definition Audio
- Supports Intel ® Rapid Storage Technology
- Supports Intel ® Active Management Technology
- Supports Intel ® Virtualization Technology for Directed I/O
- Supports Intel ® Trusted Execution Technology
- Supports Intel ® Flexible Display Interconnect (Intel® FDI)
- Supports buffered mode generating extra clocks from a clock chip
- Analog and Digital Display ports —A n a l o g C R T —H D M I —D V I —D i s p l a y P o r t 1 . 1 —S D V O — LVDS (Mobile Only) — Embedded DisplayPort
- Low Pin Count (LPC) interface
- Firmware Hub (FWH) interface support
- Serial Peripheral Interface (SPI) support
- I n t e l® Quiet System Technology (Desktop only)
- I n t e l® Anti-Theft Technology
- JTAG Boundary Scan support The PCH incorporates a variety of PCI devices and functions, as shown in Table 1-2. They are divided into eight logical devices. The first is the DMI-To-PCI bridge (Device 30). The second device (Device 31) contains most of the standard PCI functions that always existed in the PCI-to-ISA bridges (South Bridges), such as the Intel® PIIX4. The third and fourth (Device 29 and Device 26) are the USB host controller devices. The fifth (Device 28) is the PCI Express device. The sixth (Device 27) is the HD Audio controller device, and the seventh (Device 25) is the Gigabit Ethernet controller device. The eighth (Device 22) is the Intel ® Management Engine Interface Controller.
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NOTES: 1. The PCI-to-LPC bridge contai ns registers that control LPC, Power Management, System Management, GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA. 2. Device 26:Function 2 may be configured as Device 29:Function 3 during BIOS Post. 3. SATA Controller 2 is only visible when D31:F2 CC.SCC=01h. Table 1-2. PCI Devi ces and Functions Bus:Device:Function Function Description Bus 0:Device 30:Function 0 DMI-to-PCI Bridge Bus 0:Device 31:Function 0 LPC Controller 1 Bus 0:Device 31:Function 2 SATA Controller #1 Bus 0:Device 31:Function 5 SATA Controller #2 Bus 0:Device 31:Function 6 Thermal Subsystem Bus 0:Device 31:Function 3 SMBus Controller Bus 0:Device 29:Function 0 USB HS EHCI Controller #1 Bus 0:Device 26:Fucntion 0 USB HS EHCI Controller #2 Bus 0:Device 28:Function 0 PCI Express* Port 1 Bus 0:Device 28:Function 1 PCI Express Port 2 Bus 0:Device 28:Function 2 PCI Express Port 3 Bus 0:Device 28:Function 3 PCI Express Port 4 Bus 0:Device 28:Function 4 PCI Express Port 5 Bus 0:Device 28:Function 5 PCI Express Port 6 Bus 0:Device 28:Function 6 PCI Express Port 7 Bus 0:Device 28:Function 7 PCI Express Port 8 Bus 0:Device 27:Function 0 Intel ® High Definition Audio Controller Bus 0:Device 25:Function 0 Gigabit Ethernet Controller Bus 0:Device 22:Function 0 Intel ® Management Engine Interface (Intel® MEI) #1 Bus 0:Device 22:Function 1 Intel ® Management Engine Interface (Intel® MEI) #2 Bus 0:Device 22:Function 2 IDE-R Bus 0:Device 22:Function 3 KT
1.2.1 Capability Overview
The following sub-sections provide an overview of the PCH capabilities. Direct Media Interface (DMI) Direct Media Interface (DMI) is the chip-to-chip connection between the processor and PCH. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software-transparent, permitting current and legacy software to operate normally. PCI Express* Interface The PCH provides up to 8 PCI Express Root Ports, supporting the PCI Express Base Specification, Revision 2.0. Each Root Port supports 2.5 Gb/s bandwidth in each direction (5 Gb/s concurrent). PCI Express Root Ports 1-4 and Ports 5–8 can be independently configured as four x1s, two x2s, one x2 and 2 x1s, or one x4 port widths. Serial ATA (SATA) Controller The PCH has two integrated SATA host controllers that support independent DMA operation on up to six ports and supports data transfer rates of up to 3.0 GB/s (300 MB/s). The SATA controller contains two modes of operation—a legacy mode using I/O space, and an AHCI mode using memory space. Software that uses legacy mode will not have AHCI capabilities. The PCH supports the Serial ATA Specification, Revision 1.0a. The PCH also supports several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.0 (AHCI support is required for some elements). AHCI The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a new programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices—each device is treated as a master—and hardware-assisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires appropriate software support (such as an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware. See Section 1.3 for details on SKU feature availability. Intel® Rapid Storage Technology The PCH provides support for Intel® Rapid Storage Technology, providing both AHCI (see above for details on AHCI) and integrated RAID functionality. The industry-leading RAID capability provides high-performance RAID 0, 1, 5, and 10 functionality on up to 6 SATA ports of the PCH. Matrix RAID support is provided to allow multiple RAID levels to be combined on a single set of hard drives, such as RAID 0 and RAID 1 on two disks. Other RAID features include hot spare support, SMART alerting, and RAID 0 auto replace. Software components include an Option ROM for pre-boot configuration and boot functionality, a Microsoft Windows* compatible driver, and a user interface for configuration and management of the RAID capability of the PCH. See Section 1.3 for details on SKU feature availability.
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The PCH PCI interface provides a 33 MHz, Revision 2.3 implementation. The PCH integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internal PCH requests. This allows for combinations of up to four PCI down devices and PCI slots. Low Pin Count (LPC) Interface The PCH implements an LPC Interface as described in the LPC 1.1 Specification. The Low Pin Count (LPC) bridge function of the PCH resides in PCI Device 31:Function 0. In addition to the LPC bridge interface function, D31:F0 contains other functional units including DMA, interrupt controllers, timers, power management, system management, GPIO, and RTC. Serial Peripheral Interface (SPI) The PCH implements an SPI Interface as an alternative interface for the BIOS flash device. An SPI flash device can be used as a replacement for the FWH, and is required to support Gigabit Ethernet, Intel® Active Management Technology and integrated Intel® Quiet System Technology. The PCH supports up to two SPI flash devices with speeds of up to 50 MHz using two chip select pins. Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) The DMA controller incorporates the logic of two 8237 DMA controllers, with seven independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by- byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the seven DMA channels can be programmed to support fast Type-F transfers. Channel 4 is reserved as a generic bus master request. The PCH supports LPC DMA, which is similar to ISA DMA, through the PCH’s DMA controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. The timer/counter block contains three counters that are equivalent in function to those found in one 8254 programmable interval timer. These three counters are combined to provide the system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock source for these three counters. The PCH provides an ISA-Compatible Programmable Interrupt Controller (PIC) that incorporates the functionality of two 8259 interrupt controllers. The two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. In addition, the PCH supports a serial interrupt scheme. All of the registers in these modules can be read and restored. This is required to save and restore system state after power has been removed and restored to the platform. Advanced Programmable Interrupt Controller (APIC) In addition to the standard ISA compatible Programmable Interrupt controller (PIC) described in the previous section, the PCH incorporates the Advanced Programmable Interrupt Controller (APIC).
Universal Serial Bus (USB) Controllers The PCH contains up to two Enhanced Host Controller Interface (EHCI) host controllers that support USB high-speed signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/s. The PCH also contains two Rate Matching Hubs (RMH) that support USB full- speed and low-speed signaling. The PCH supports up to fourteen USB 2.0 ports. All fourteen ports are high-speed, full- speed, and low-speed capable. Gigabit Ethernet Controller The Gigabit Ethernet Controller provides a system interface using a PCI function. The controller provides a full memory-mapped or IO mapped interface along with a 64 bit address master support for systems using more than 4 GB of physical memory and DMA (Direct Memory Addressing) mechanisms for high performance data transfers. Its bus master capabilities enable the component to process high-level commands and perform multiple operations; this lowers processor utilization by off-loading communication tasks from the processor. Two large configurable transmit and receive FIFOs (up to 20 KB each) help prevent data underruns and overruns while waiting for bus accesses. This enables the integrated LAN controller to transmit data with minimum interframe spacing (IFS). The LAN controller can operate at multiple speeds (10/100/1000 MB/s) and in either full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a proprietary collision reduction mechanism. See Section 5.3 for details. RTC The PCH contains a Motorola* MC146818B-compatible real-time clock with 256 bytes of battery-backed RAM. The real-time clock performs two key functions: keeping track of the time of day and storing system data, even when the system is powered down. The RTC operates on a 32.768 KHz crystal and a 3 V battery. The RTC also supports two lockable memory ranges. By setting bits in the configuration space, two 8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of passwords or other system security information. The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in advance, rather than just 24 hours in advance. GPIO Various general purpose inputs and outputs are provided for custom system design. The number of inputs and outputs varies depending on the PCH’s configuration. Enhanced Power Management The PCH power management functions include enhanced clock control and various low- power (suspend) states (such as, Suspend-to-RAM and Suspend-to-Disk). A hardware- based thermal management circuit permits software-independent entrance to low- power states. The the PCH contains full support for the Advanced Configuration and Power Interface (ACPI) Specification, Revision 3.0a.
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Intel® Active Management Technology (Intel® AMT) (Not available on all the Intel® 5 Series Chipset or Intel® 3400 Series Chipset SKUs) Intel AMT is a fundamental component of Intel® vPro™ technology. Intel AMT is a set of advanced manageability features developed as a direct result of IT customer feedback gained through Intel market research. With the advent of powerful tools like the Intel® System Defense Utility, the extensive feature set of Intel AMT easily integrates into any network environment. See Section 1.3 for details on SKU feature availability. Manageability In addition to Intel® AMT, the PCH integrates several functions designed to manage the system and lower the total cost of ownership (TCO) of the system. These system management functions are designed to report errors, diagnose the system, and recover from system lockups without the aid of an external microcontroller.
- TCO Timer. The PCH’s integrated programmable TCO timer is used to detect system locks. The first expiration of the timer generates an SMI# that the system can use to recover from a software lock. The second expiration of the timer causes a system reset to recover from a hardware lock.
- Processor Present Indicator. The PCH looks for the processor to fetch the first instruction after reset. If the processor does not fetch the first instruction, the PCH will reboot the system.
- ECC Error Reporting. When detecting an ECC error, the host controller has the ability to send one of several messages to the PCH. The host controller can instruct the PCH to generate either an SMI#, NMI, SERR#, or TCO interrupt.
- Function Disable. The PCH provides the ability to disable the following integrated functions: LAN, USB, LPC, Intel® HD Audio, SATA, PCI Express or SMBus. Once disabled, these functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts or power management events are generated from the disabled functions.
- Intruder Detect. The PCH provides an input signal (INTRUDER#) that can be attached to a switch that is activated by the system case being opened. The PCH can be programmed to generate an SMI# or TCO interrupt due to an active INTRUDER# signal. System Management Bus (SMBus 2.0) The PCH contains an SMBus Host interface that allows the processor to communicate with SMBus slaves. This interface is compatible with most I 2C devices. Special I2C commands are implemented. The PCH’s SMBus host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). Also, the PCH supports slave functionality, including the Host Notify protocol. Hence, the host controller supports eight command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify. The PCH SMBus also implements hardware-based Packet Error Checking for data robustness and the Address Resolution Protocol (ARP) to dynamically provide address to all SMBus devices.
Intel® High Definition Audio Controller The Intel® High Definition Audio Specification defines a digital interface that can be used to attach different types of codecs, such as audio and modem codecs. The PCH’s Intel ® HD Audio controller supports up to 4 codecs. The link can operate at either 3.3 V or 1.5 V. With the support of multi-channel audio stream, 32-bit sample depth, and sample rate up to 192 kHz, the Intel® HD Audio controller provides audio quality that can deliver CE levels of audio experience. On the input side, the PCH adds support for an array of microphones. Intel® Quiet System Technology (Intel® QST) The PCH integrates four fan speed sensors (four TACH signals) and four fan speed controllers (three Pulse Width Modulator signals), which enables monitoring and controlling up to four fans on the system. With the new implementation of the single- wire Simple Serial Transport (SST) 1.0 bus and Platform Environmental Control Interface (PECI), the PCH provides an easy way to connect to SST-based thermal sensors and access the processor thermal data. In addition, coupled with the new sophisticated fan speed control algorithms, Intel ® QST provides effective thermal and acoustic management for the platform. Note: Intel® Quiet System Technology functionality requires a correctly configured system, including an appropriate processor, Intel® Management Engine firmware, and system BIOS support. Intel® Anti-Theft Technology (Not available on all the Intel® 5 Series Chipset or Intel® 3400 Series Chipset SKUs) The PCH introduces a new hardware-based security technology which encrypts data stored on any SATA compliant HDD in AHCI Mode. This feature gives the end-user the ability to restrict access to HDD data by unknown parties. Intel® Anti-Theft Technology can be used alone or can be combined with software encryption applications to add protection against data theft. Intel® Anti-Theft Technology functionality requires a correctly configured system, including an appropriate processor, Intel® Management Engine firmware, and system BIOS support. Intel® Virtualization Technology for Directed I/O (Intel® VT-d) The PCH provides hardware support for implementation of Intel® Virtualization Technology with Directed I/O (Intel® VT-d). Intel® VT-d Technology consists of technology components that support the virtualization of platforms based on Intel® Architecture Processors. Intel® VT-d Technology enables multiple operating systems and applications to run in independent partitions. A partition behaves like a virtual machine (VM) and provides isolation and protection across partitions. Each partition is allocated its own subset of host physical memory.
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The PCH adds the industry standard JTAG interface and enables Boundary-Scan in place of the XOR chains used in previous generations. Boundary-Scan can be used to ensure device connectivity during the board manufacturing process. The JTAG interface allows system manufacturers to improve efficiency by using industry available tools to test the PCH on an assembled board. Since JTAG is a serial interface, it eliminates the need to create probe points for every pin in an XOR chain. This eases pin breakout and trace routing and simplifies the interface between the system and a bed-of-nails tester. Note: Contact your local Intel Field Sales Representative for additional information about JTAG usage on the PCH. Serial Over Lan (SOL) Function This function supports redirection of keyboard and text screens to a terminal window on a remote console. The keyboard and text redirection enables the control of the client machine through the network without the need to be physically near that machine. Text and keyboard redirection allows the remote machine to control and configure a client system. The SOL function emulates a standard PCI device and redirects the data from the serial port to the management console using the integrated LAN. KVM KVM provides enhanced capabilities to its predecessor – SOL. In addition to the features set provided by SOL, KVM provides mouse and graphic redirection across the integrated LAN. Unlike SOL, KVM does not appear as a host accessible PCI device but is instead almost completely performed by Intel AMT Firmware with minimal BIOS interaction as described in the Intel ME BIOS Writer’s Guide. The KVM feature is only available with internal graphics. IDE-R Function The IDE-R function is an IDE Redirection interface that provides client connection to management console ATA/ATAPI devices such as hard disk drives and optical disk drives. A remote machine can setup a diagnostic SW or OS installation image and direct the client to boot an IDE-R session. The IDE-R interface is the same as the IDE interface although the device is not physically connected to the system and supports the ATA/ATAPI-6 specification. IDE-R does not conflict with any other type of boot and can instead be implemented as a boot device option. The Intel AMT solution will use IDE-R when remote boot is required. The device attached through IDE-R is only visible to software during a management boot session. During normal boot session, the IDE-R controller does not appear as a PCI present device. PCH Display Interface The PCH integrates latest display technologies such as HDMI*, DisplayPort*, Embedded DisplayPort (eDP*), SDVO, and DVI along with legacy display technologies: Analog Port (VGA) and LVDS (mobile only). The Analog Port and LVDS Port are dedicated ports on the PCH and the Digital Ports B, C and D can be configured to drive HDMI, DVI, or DisplayPort. Digital Port B can also be configured as SDVO while Digital Port D can be configured as eDP. The HDMI interface supports the HDMI* 1.3C specification while the DisplayPort interface supports the DisplayPort* 1.1a specification. The PCH supports High-bandwidth Digital Content Protection for high definition content playback over digital interfaces. The PCH also integrates audio codecs for audio support over HDMI and DisplayPort interfaces. The PCH receives the display data over the Intel ® FDI and transcodes the data as per the display technology protocol and sends the data through the display interface.
Intel® Flexible Display Interconnect (FDI) The Intel® FDI connects the display engine in the processor with the display interfaces on the PCH. The display data from the frame buffer is processed by the display engine and sent to the PCH where it is transcoded and driven out on the panel. Intel FDI involves two channels – A and B for display data transfer. Intel FDI Channel A has 4 lanes and Channel B supports 4 lanes depending on the display configuration. Each of the Intel FDI Channel lanes uses differential signal supporting 2.7 Gb/s. For two display configurations Intel FDI CH A maps to display pipe A while Intel CH B maps to the second display pipe B.
1.3 Intel ® 5 Series Chipset and Intel® 3400 Series
NOTES: 1. Contact your local Intel Field Sales Repres entative for currently available PCH SKUs. 2. Table above shows feature difference between the PCH skus. If a feature is not listed in the table it is considered a Base feature that is included in all SKUs. 3. The PCH provides hardware support for AHCI functionality when enabled by appropriate system configurations and software drivers. 4. USB ports 6 and 7 are disabled. 5. PCIe* ports 7 an d 8 are disabled. Table 1-3. Intel ® 5 Series Chipset Desktop SKUs Feature Set SKU Name(s) Q57 H57 H55 P55 B55 PCI Express* 2.0 Ports 88 6 5 86 5 USB* 2.0 Ports 14 14 12 4 14 12 4 SATA Ports 66 6 66 HDMI/DVI/VGA/SDVO/DisplayPort/eDP Yes Yes Yes No Yes LVDS No No No No No Integrated Graphics Support with PAVP 1.5 Yes Yes Yes No Yes Intel® Quiet System Technology Yes Yes Yes No Yes Intel® Rapid Storage Technology AHCI Yes Yes Yes Yes Yes Raid 0/1/5/10 Support Yes Yes No Yes No Intel® ME Ignition FW only No No No Yes No Intel® AT Yes No No No No Intel® AMT 6.0 Yes No No No No Intel® Remote PC Assist Technology for Business Yes No No No No Intel® Remote PC Assist Technology for Consumer No Yes Yes No No Intel® Remote Wake Technology No Yes Yes No No
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NOTES: 1. Contact your local Intel Field Sales Repres entative for currently available PCH SKUs. 2. Table above shows feature difference between th e PCH SKUs. If a feature is not listed in the table it is considered a Base feature that is included in all skus. 3. The PCH provides hardware support for AHCI functionality when enabled by appropriate system configurations and software drivers. 4. USB ports 6 and 7 are disabled. 5. PCIe* ports 7 and 8 are disabled. 6. SATA ports 2 and 3 are disabled. Table 1-4. Intel ® 5 Series Chipset Mobile SKUs Feature Set SKU Name(s) QM57 HM57 PM55 HM55 QS57 PCI Express* 2.0 Ports 8886 5 8 USB* 2.0 Ports 14 14 14 12 4 14 SATA Ports 6664 6 6 HDMI/DVI/VGA/SDVO/DisplayPort/eDP Yes Yes No Yes Yes LVDS Yes Yes No Yes Yes Graphics Support with PAVP 1.5 Yes Yes No Yes Yes Intel® Quiet System Technology No No No No No Intel® Rapid Storage Technology AHCI Yes Yes Yes Yes Yes Raid 0/1/5/10 Support Yes Yes Yes No Yes Intel® ME Ignition FW only No No Yes No No Intel® AT Yes Yes No Yes Yes Intel® Active Managment Technology (Intel AMT) 6.0 Yes No No No Yes Intel® Remote PC Assist Technology for Business Yes No No No Yes Intel® Remote PC Assist Technology for Consumer No Yes No No No Intel® Remote Wake Technology No No No No No
- Contact your local Intel Field Sales Repres entative for currently available PCH skus. 2. Table above shows feature difference between the PCH skus. If a feature is not listed in the table it is considered a Base feature that is included in all skus. 3. The PCH provides hardware support for AHCI functionality when enabled by appropriate system configurations and software drivers. 4. USB ports 6 and 7 are disabled. 5. USB ports 8, 9, 10, 11, 12 and 13 are disabled. 6. SATA ports 2 and 3 are disabled. 7. PCIe* ports 7 an d 8 are disabled.
1.4 Reference Documents
§ § Table 1-5. Intel ® 3400 Series Chipset Server SKUs Feature Set SKU Name(s) Intel® 3400 Chipset Intel® 3420 Chipset Intel® 3450 Chipset PCI Express* 2.0 Ports 67 88 USB* 2.0 Ports 85 124 14 SATA Ports 46 66 HDMI/DVI/VGA/SDVO/DisplayPort No No Yes LVDS No No No Graphics Support with PAVP 1.5 No No Yes Intel® Quiet System Technology No No Yes Intel® Rapid Storage Technology AHCI No3 Yes Yes Raid 0/1/5/10 Support No Yes Yes Intel® ME Ignition FW only Yes Yes No Intel® AT No No Yes Intel® AMT 6.0 No No Yes Intel® Remote PC Assist Technology for Business No No Yes Intel® Remote PC Assist Technology for Consumer No No No Intel® Remote Wake Technology No No Yes Document Document Number / Location Intel® 5 Series Chipset and Intel® 3400 Series Chipset Specification Update http://download.intel.com/ design/processor/ specupdt/322166.pdf Intel® 5 Series Chipset and Intel® 3400 Series Chipset Thermal Mechanical Specifications and Design Guidelines www.intel.com/Assets/ PDF/designguide/ 322171.pdf
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2 Signal Description
This chapter provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of the signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when at the high voltage level. The “†” symbol at the end of the signal name indicates that the signal is mobile only. The following notations are used to describe the signal type: I Input Pin O Output Pin OD O Open Drain Output Pin. I/OD Bi-directional Input/Open Drain Output Pin. I/O Bi-directional Input / Output Pin. CMOS CMOS buffers. 1.5 V tolerant. COD CMOS Open Drain buffers. 3.3 V tolerant. HVCMOS High Voltage CMOS buffers. 3.3 V tolerant. A Analog reference or output. The “Type” for each signal is indicative of the functional operating mode of the signal. Unless otherwise noted in Section 3.2 or Section 3.3, a signal is considered to be in the functional operating mode after RTCRST# de-asserts for signals in the RTC well, after RSMRST# de-asserts for signals in the suspend well, after PWROK asserts for signals in the core well, and after LAN_RST# de-asserts for signals in the LAN well.
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Figure 2-1. PCH Interfac e Signals Block Diagram TBD THRMTRIP# SYS_RESET# RSMRST# SLP_S3# SLP_S4# SLP_S5#/GPIO63 SLP_M# CLKRUN# †/GPIO32 PWROK MEPWROK PWRBTN# RI# WAKE# SUS_STAT#/GPIO61 SUSCLK/GPIO62 LAN_RST# BATLOW# †/GPIO72 PLTRST# STP_PCI#/GPIO34 ACPRESENT †/GPIO31 DRAMPWROK LAN_PHY_PWR_CTRL SLP_LAN#/GPIO29 PMSYNCH AD[31:0] C/BE[3:0]# DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# REQ0# REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54 GNT0# GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55 SERR# PME# CLKIN_PCILOOPBACK PCIRST# PLOCK# PCI Interface Power Mgnt. Interrupt Interface INIT3_3V# RCIN# A20GATE PROCPWRGD Processor Interface USB SERIRQ PIRQ[D:A]# PIRQ[H:E]#/GPIO[5:2] USB[13:0]P; USB[13:0]N OC0#/GPIO59; OC1#/GPIO40 OC2#/GPIO41; OC3#/GPIO42 OC4#/GPIO43; OC5#/GPIO9 OC6#/GPIO10; OC7#/GPIO14 USBRBIAS USBRBIAS# RTCX1 RTCX2 CLKIN_BCLK_P;CLKIN_BCLK_N CLKIN_DMI_P;CLKIN_DMI_N CLKIN_SATA_[P:N]/CKSSCD_[P:N] CLKIN_DOT96P;CLKIN_DOT96N XTAL25_IN REF14CLKIN PCIECLKRQ0#/GPIO73;PCIECLKRQ1#/GPIO18 PCIECLKRQ2#/GPIO20;PCIECLKRQ3#/GPIO25 PCIECLKRQ4#/GPIO26;PCIECLKRQ5#/GPIO44 PCIECLKRQ6#/GPIO45;PCIECLKRQ7#/GPIO46 PEG_A_CLKRQ#/GPIO47;PEG_B_CLKRQ#/GPIO56 XCLK_RCOMP RTC Clock Inputs Misc. Signals INTVRMEN SPKR SRTCRST# RTCRST# General Purpose I/O PWM[3:0]/TP[12:9] † TACH0/GPIO17; TACH1/GPIO1 TACH2/GPIO6; TACH3/GPIO7 SST PECI INTRUDER#; SML[0:1]DATA;SML[0:1]CLK; SML0ALERT#/GPIO60 SML1ALERT#/GPIO74 DMI[3:0]TXP, DMI[3:0]TXN DMI[3:0]RXP, DMI[3:0]RXN DMI_ZCOMP DMI_IRCOMP Direct Media Interface LPC / FWH Interface SMBus Interface HDA_RST# HDA_SYNC HDA_BCLK HDA_SDO HDA_SDIN[3:0] Intel® High Definition Audio System Mgnt. LAD[3:0]/FWH[3:0] LFRAME#/FWH4 LDRQ0#; LDRQ1#/GPIO23 SMBDATA; SMBCLK SMBALERT#/GPIO11 SATA[5:0]TXP, SATA[5:0]TXN SATA[5:0]RXP, SATA[5:0]RXN SATAICOMPO SATAICOMPI SATALED# SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37 SATA4GP/GPIO16 SATA5GP/GPIO49/TEMP_ALERT# SCLOCK/GPIO22 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 Serial ATA Interface PCI Express* Interface PETp[8:1], PETn[8:1] PERp[8:1], PERn[8:1] SPI SPI_CS0#; SPI_CS1# SPI_MISO SPI_MOSI SPI_CLK JTAG* Fan Speed Control DDPB_[3:0]P;DDPB_[3:0]N; DDPC_[3:0]P;DDPC_[3:0]N; DDPD_[3:0]P;DDPD_[3:0]N; DDP[B:D]_AUXP;DDP[B:D]_AUXN; DDP[B:D]_HPD SDVO_CTRLCLK; SDVO_CTRLDATA DDPC_CTRLCLK;DDPC_CTRLDATA DDPD_CTRLCLK;DDPD_CTRLDATA SDVO_INTP;SDVO_INTN SDVO_TVCLKINP;SDVO_TVCLKINN SDVO_STALLP;SDVO_STALLN Digital Display Interface Clock Outputs CLKOUT_DP_[P:N]/CLKOUT_BCLK1_[P:N] CLKIN_DMI_P;CLKIN_DMI_N XTAL25_OUT CLKOUT_PEG_A_[P:N];CLKOUT_PEG_B_[P:N] CLKOUT_PCIE[7:0]_P; CLKOUT_PCIE[7:0]_N CLKOUT_PCI[4:0] CLKOUTFLEX0/GPIO64;CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66;CLKOUTFLEX3/GPIO67 CRT_RED;CRT_GREEN;CRT_BLUE DAC_IREF CRT_HSYNC;CRT_VSYNC CRT_DDC_CLK;CRT_DDC_DATA CRT_IRTN Analog Display LVDS CLOCKOUT_BCLK0_[P:N]/CLKOUT_PCIE8_[P:N} JTAGTCK JTAGTMS JTAGTDI JTAGTDO CL_CLK1† CL_DATA1† CL_RST1#† Controller Link LVDS[A:B]_DATA[3:0] † LVDS[A:B]_DATA#[3:0] † LVDS[A:B]_CLK †:LVDS[A:B]_CLK# † LVD_VREFH†;LVD_VREFL †;LFV_VBG† LVD_IBG†
2.1 Direct Media Interface (DMI) to Host Controller
2.2 PCI Express*
Table 2-1. Direct Me dia Interface Signals Name Type Description DMI0TXP, DMI0TXN O Direct Media Interface Differential Transmit Pair 0 DMI0RXP, DMI0RXN I Direct Media Interface Differential Receive Pair 0 DMI1TXP, DMI1TXN O Direct Media Interface Differential Transmit Pair 1 DMI1RXP, DMI1RXN I Direct Media Interface Differential Receive Pair 1 DMI2TXP, DMI2TXN O Direct Media Interface Differential Transmit Pair 2 DMI2RXP, DMI2RXN I Direct Media Interface Differential Receive Pair 2 DMI3TXP, DMI3TXN O Direct Media Interface Differential Transmit Pair 3 DMI3RXP, DMI3RXN I Direct Media Interface Differential Receive Pair 3 DMI_ZCOMP I Impedance Compensation Input: Determines DMI input impedance. DMI_IRCOMP O Impedance/Current Compensation Output: Determines DMI output impedance and bias current. Table 2-2. PCI Express* Signals Name Type Description PETp1, PETn1 O PCI Express* Differential Transmit Pair 1 PERp1, PERn1 I PCI Express Differential Receive Pair 1 PETp2, PETn2 O PCI Express Differential Transmit Pair 2 PERp2, PERn2 I PCI Express Differential Receive Pair 2 PETp3, PETn3 O PCI Express Differential Transmit Pair 3 PERp3, PERn3 I PCI Express Differential Receive Pair 3 PETp4, PETn4 O PCI Express Differential Transmit Pair 4 PERp4, PERn4 I PCI Express Differential Receive Pair 4 PETp5, PETn5 O PCI Express Differential Transmit Pair 5 PERp5, PERn5 I PCI Express Differential Receive Pair 5 PETp6, PETn6 O PCI Express Differential Transmit Pair 6 PERp6, PERn6 I PCI Express Differential Receive Pair 6 PETp7, PETn7 O PCI Express Differential Transmit Pair 7 NOTE: Port 7 may not be available in all PCH SKUs. Please see Chapter 1.3 for more information.
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2.3 Firmware Hub Interface
PERp7, PERn7 I PCI Express Differential Receive Pair 7 NOTE: Port 7 may not be available in all PCH SKUs. Please see Chapter 1.3 for more information. PETp8, PETn8 O PCI Express Differential Transmit Pair 8 NOTE: Port 8 may not be available in all PCH SKUs. Please see Chapter 1.3 for more information. PERp8, PERn8 I PCI Express Differential Receive Pair 8 NOTE: Port 8 may not be available in all PCH SKUs. Please see Chapter 1.3 for more information. Table 2-3. Firmware Hub Interface Signals Name Type Description FWH[3:0] / LAD[3:0] I/O Firmware Hub Signals. These signals are multiplexed with the LPC address signals. FWH4 / LFRAME# O Firmware Hub Signals. This signal is multiplexed with the LPC LFRAME# signal. INIT3_3V# O Initialization 3.3 V: INIT3_3V# is asserted by the PCH for 16 PCI clocks to reset the processor. This signal is intended for Firmware Hub. Table 2-2. PCI Express* Signals Name Type Description
2.4 PCI Interface
Table 2-4. PCI Interface Signals (Sheet 1 of 3) Name Type Description AD[31:0] I/O PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction, AD[31:0] contain a physical address (32 bits). During subsequent clocks, AD[31:0] contain data. The PCH will drive all 0s on AD[31:0] during the address phase of all PCI Special Cycles. C/BE[3:0]# I/O Bus Command and Byte Enables: The command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# define the Byte Enables. All command encodings not shown are reserved. The PCH does not decode reserved values, and therefore will not respond if a PCI master generates a cycle using one of the reserved values. DEVSEL# I/O Device Select: The PCH asserts DEVSEL# to claim a PCI transaction. As an output, the PCH asserts DEVSEL# when a PCI master peripheral attempts an access to an internal PCH address or an address destined for DMI (main memory or graphics). As an input, DEVSEL# indicates the response to a PCH-initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of PLTRST#. DEVSEL# remains tri-stated by the PCH until driven by a target device. FRAME# I/O Cycle Frame: The current initiator drives FRAME# to indicate the beginning and duration of a PCI transaction. While the initiator asserts FRAME#, data transfers continue. When the initiator negates FRAME#, the transaction is in the final data phase. FRAME# is an input to the PCH when the PCH is the target, and FRAME# is an output from the PCH when the PCH is the initiator. FRAME# remains tri-stated by the PCH until driven by an initiator. IRDY# I/O Initiator Ready: IRDY# indicates the PCH ability, as an initiator, to complete the current data phase of the transaction. It is used in conjunction with TRDY#. A data phase is completed on any clock both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates the PCH has valid data present on AD[31:0]. During a read, it indicates the PCH is prepared to latch data. IRDY# is an input to the PCH when the PCH is the target and an output from the PCH when the PCH is an initiator. IRDY# remains tri-stated by the PCH until driven by an initiator. C/BE[3:0]# Command Type 0000b Interrupt Acknowledge 0001b Special Cycle 0010b I/O Read 0011b I/O Write 0110b Memory Read 0111b Memory Write 1010b Configuration Read 1011b Configuration Write 1100b Memory Read Multiple 1110b Memory Read Line 1111b Memory Write and Invalidate
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TRDY# I/O Target Ready: TRDY# indicates the PCH ability, as a target, to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is completed when both TRDY# and IRDY# are sampled asserted. During a read, TRDY# indicates that the PCH, as a target, has placed valid data on AD[31:0]. During a write, TRDY# indicates the PCH, as a target is prepared to latch data. TRDY# is an input to the PCH when the PCH is the initiator and an output from the PCH when the PCH is a target. TRDY# is tri-stated from the leading edge of PLTRST#. TRDY# remains tri-stated by the PCH until driven by a target. STOP# I/O Stop: STOP# indicates that the PCH, as a target, is requesting the initiator to stop the current transaction. STOP# causes the PCH, as an initiator, to stop the current transaction. STOP# is an output when the PCH is a target and an input when the PCH is an initiator. PAR I/O Calculated/Checked Parity: PAR uses “even” parity calculated on 36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the PCH counts the number of ones within the 36 bits plus PAR and the sum is always even. The PCH always calculates PAR on 36 bits regardless of the valid byte enables. The PCH generates PAR for address and data phases and only ensures PAR to be valid one PCI clock after the corresponding address or data phase. The PCH drives and tri-states PAR identically to the AD[31:0] lines except that the PCH delays PAR by exactly one PCI clock. PAR is an output during the address phase (delayed one clock) for all PCH initiated transactions. PAR is an output during the data phase (delayed one clock) when the PCH is the initiator of a PCI write transaction, and when it is the target of a read transaction. The PCH checks parity when it is the target of a PCI write transaction. If a parity error is detected, the PCH will set the appropriate internal status bits, and has the option to generate an NMI# or SMI#. PERR# I/O Parity Error: An external PCI device drives PERR# when it receives data that has a parity error. The PCH drives PERR# when it detects a parity error. The PCH can either generate an NMI# or SMI# upon detecting a parity error (either detected internally or reported using the PERR# signal). REQ0# REQ1#/ GPIO50 REQ2#/ GPIO52 REQ3#/GPIO54 I PCI Requests: The PCH supports up to 4 masters on the PCI bus. REQ[3:1]# pins can instead be used as GPIO. GNT0# GNT1#/ GPIO51 GNT2#/ GPIO53 GNT3#/GPIO55 O PCI Grants: The PCH supports up to 4 masters on the PCI bus. GNT[3:1]# pins can instead be used as GPIO. Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3 power rail. NOTE: GNT[3:0]# are sampled as a functional strap. See Section 2.28.1 for details. CLKIN_PCILOO PBACK I PCI Clock: This is a 33 MHz clock feedback input to reduce skew between PCH PCI clock and clock observed by connected PCI devices. This signal must be connected to one of the pins in the group CLKOUT_PCI[4:0] Table 2-4. PCI Interface Signals (Sheet 2 of 3) Name Type Description
2.5 Serial ATA Interface
PCIRST# O PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical OR of the primary interface PLTRST# signal and the state of the Secondary Bus Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6). PLOCK# I/O PCI Lock: This signal indicates an exclusive bus operation and may require multiple transactions to complete. The PCH asserts PLOCK# when it performs non-exclusive transactions on the PCI bus. PLOCK# is ignored when PCI masters are granted the bus. SERR# I/OD System Error: SERR# can be pulsed active by any PCI device that detects a system error condition. Upon sampling SERR# active, the PCH has the ability to generate an NMI, SMI#, or interrupt. PME# I/OD PCI Power Management Event: PCI peripherals drive PME# to wake the system from low-power states S1–S5. PME# assertion can also be enabled to generate an SCI from the S0 state. In some cases the PCH may drive PME# active due to an internal wake event. The PCH will not drive PME# high, but it will be pulled up to VccSus3_3 by an internal pull-up resistor. Table 2-5. Serial ATA Interf ace Signals (Sheet 1 of 3) Name Type Description SATA0TXP SATA0TXN O Serial ATA 0 Differential Transmit Pairs: These are outbound high-speed differential signals to Port 0. In compatible mode, SATA Port 0 is the primary master of SATA Controller 1. SATA0RXP SATA0RXN I Serial ATA 0 Differential Receive Pair: These are inbound high- speed differential signals from Port 0. In compatible mode, SATA Port 0 is the primary master of SATA Controller 1. SATA1TXP SATA1TXN O Serial ATA 1 Differential Transmit Pair: These are outbound high-speed differential signals to Port 1. In compatible mode, SATA Port 1 is the secondary master of SATA Controller 1. SATA1RXP SATA1RXN I Serial ATA 1 Differential Receive Pair: These are inbound high- speed differential signals from Port 1. In compatible mode, SATA Port 1 is the secondary master of SATA Controller 1. —S A T A 2 T X P SATA2TXN O Serial ATA 2 Differential Transmit Pair: These are outbound high-speed differential signals to Port 2. In compatible mode, SATA Port 2 is the primary slave of SATA Controller 1. NOTE: SATA Port 2 may not be available in all PCH SKUs. Table 2-4. PCI Interface Signals (Sheet 3 of 3) Name Type Description
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Serial ATA 2 Differential Receive Pair: These are inbound high- speed differential signals from Port 2. In compatible mode, SATA Port 2 is the primary slave of SATA Controller 1. NOTE: SATA Port 2 may not be available in all PCH SKUs. SATA3TXP SATA3TXN O Serial ATA 3 Differential Transmit Pair: These are outbound high-speed differential signals to Port 3 In compatible mode, SATA Port 3 is the secondary slave of SATA Controller 1. NOTE: SATA Port 3 may not be available in all PCH SKUs. SATA3RXP SATA3RXN I Serial ATA 3 Differential Receive Pair: These are inbound high- speed differential signals from Port 3 In compatible mode, SATA Port 3 is the secondary slave of SATA Controller 1. NOTE: SATA Port 3 may not be available in all PCH SKUs. SATA4TXP SATA4TXN O Serial ATA 4 Differential Transmit Pair: These are outbound high-speed differential signals to Port 4. In compatible mode, SATA Port 4 is the primary master of SATA Controller 2. SATA4RXP SATA4RXN I Serial ATA 4 Differential Receive Pair: These are inbound high- speed differential signals from Port 4. In compatible mode, SATA Port 4 is the primary master of SATA Controller 2. SATA5TXP SATA5TXN O Serial ATA 5 Differential Transmit Pair: These are outbound high-speed differential signals to Port 5. In compatible mode, SATA Port 5 is the secondary master of SATA Controller 2. SATA5RXP SATA5RXN I Serial ATA 5 Differential Receive Pair: These are inbound high- speed differential signals from Port 5. In compatible mode, SATA Port 5 is the secondary master of SATA Controller 2. SATAICOMPO O Serial ATA Compensation Output: Connected to the external precision resistor to VccCore. Must be connected to SATAICOMPI on the board. SATAICOMPI I Serial ATA Compensation Input: Connected to SATAICOMPO on the board. SATA0GP / GPIO21 I Serial ATA 0 General Purpose: This is an input pin which can be configured as an interlock switch corresponding to SATA Port 0. When used as an interlock switch status indication, this signal should be driven to ‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open. This signal can instead be used as GPIO21. SATA1GP / GPIO19 I Serial ATA 1 General Purpose: This is an input pin which can be configured as an interlock switch corresponding to SATA Port 1. When used as an interlock switch status indication, this signal should be driven to ‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open. This signal can instead be used as GPIO19. Table 2-5. Serial ATA Interf ace Signals (Sheet 2 of 3) Name Type Description
Serial ATA 2 General Purpose: This is an input pin which can be configured as an interlock switch corresponding to SATA Port 2. When used as an interlock switch status indication, this signal should be driven to ‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open. This signal can instead be used as GPIO36. SATA3GP / GPIO37 I Serial ATA 3 General Purpose: This is an input pin which can be configured as an interlock switch corresponding to SATA Port 3. When used as an interlock switch status indication, this signal should be driven to ‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open. This signal can instead be used as GPIO37. SATA4GP / GPIO16 I Serial ATA 4 General Purpose: This is an input pin which can be configured as an interlock switch corresponding to SATA Port 4. When used as an interlock switch status indication, this signal should be driven to ‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open. This signal can instead be used as GPIO16. SATA5GP / GPIO49 / TEMP_ALERT# I Serial ATA 5 General Purpose: This is an input pin which can be configured as an interlock switch corresponding to SATA Port 5. When used as an interlock switch status indication, this signal should be driven to ‘0’ to indicate that the switch is closed and to ‘1’ to indicate that the switch is open. This signal can instead be used as GPIO49. SATALED# OD O Serial ATA LED: This signal is an open-drain output pin driven during SATA command activity. It is to be connected to external circuitry that can provide the current to drive a platform LED. When active, the LED is on. When tri-stated, the LED is off. An external pull-up resistor to Vcc3_3 is required. SCLOCK/ GPIO22 OD O SGPIO Reference Clock: The SATA controller uses rising edges of this clock to transmit serial data, and the target uses the falling edge of this clock to latch data. The SCLOCK frequency supported is 32 kHz. This signal can instead be used as a GPIO22. SLOAD/GPIO38 OD O SGPIO Load: The controller drives a ‘1’ at the rising edge of SCLOCK to indicate either the start or end of a bit stream. A 4-bit vendor specific pattern will be transmitted right after the signal assertion. This signal can instead be used as a GPIO38. SDATAOUT0/ GPIO39 SDATAOUT1/ GPIO48 OD O SGPIO Dataout: Driven by the controller to indicate the drive status in the following sequence: drive 0, 1, 2, 3, 4, 5, 0, 1, 2... These signals can instead be used as GPIOs. Table 2-5. Serial ATA Interf ace Signals (Sheet 3 of 3) Name Type Description
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2.6 LPC Interface
2.7 Interrupt Interface
NOTE: PIRQ Interrupts can only be shared if it is configured as level sensitive. They cannot be shared if configured as edge triggered. Table 2-6. LPC Interface Signals Name Type Description LAD[3:0] / FWH[3:0] I/O LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull- ups are provided. LFRAME# / FWH4 O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort. LDRQ0#, LDRQ1# / GPIO23 I LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to request DMA or bus master access. These signals are typically connected to an external Super I/O device. An internal pull-up resistor is provided on these signal. This signal can instead be used as GPIO23. Table 2-7. Interrupt Signals Name Type Description SERIRQ I/OD Serial Interrupt Request: This pin implements the serial interrupt protocol. PIRQ[D:A]# I/OD PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in Section 5.8.6. Each PIRQx# line has a separate Route Control register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQA# is connected to IRQ16, PIRQB# to IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the legacy interrupts. PIRQ[H:E]# / GPIO[5:2] I/OD PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in Section 5.8.6. Each PIRQx# line has a separate Route Control register. In APIC mode, these signals are connected to the internal I/O APIC in the following fashion: PIRQE# is connected to IRQ20, PIRQF# to IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the legacy interrupts. These signals can instead be used as GPIOs.
2.8 USB Interface
Table 2-8. USB Interface Signals (Sheet 1 of 2) Name Type Description USBP0P, USBP0N I/O Universal Serial Bus Port [1:0] Differential: These differential pairs are used to transmit Data/Address/Command signals for port 0. NOTE: No external resistors are required on these signals. The PCH integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. USBP1P, USBP1N I/O Universal Serial Bus Port [1:0] Differential: These differential pairs are used to transmit Data/Address/Command signals for port 1. NOTE: No external resistors are required on these signals. The PCH integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. USBP2P, USBP2N I/O Universal Serial Bus Port [3:2] Differential: These differential pairs are used to transmit Data/Address/Command signals for port 2. NOTE: No external resistors are required on these signals. The PCH integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. USBP3P, USBP3N I/O Universal Serial Bus Port [3:2] Differential: These differential pairs are used to transmit Data/Address/Command signals for port 3. NOTE: No external resistors are required on these signals. The PCH integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. USBP4P, USBP4N I/O Universal Serial Bus Port [5:4] Differential: These differential pairs are used to transmit Data/Address/Command signals for port 4. NOTE: No external resistors are required on these signals. The PCH integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. USBP5P, USBP5N I/O Universal Serial Bus Port [5:4] Differential: These differential pairs are used to transmit Data/Address/Command signals for port 5. NOTE: No external resistors are required on these signals. The PCH integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. USBP6P, USBP6N I/O Universal Serial Bus Port [7:6] Differential: These differential pairs are used to transmit Data/Address/Command signals for port 6. NOTE: No external resistors are required on these signals. The PCH integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. USBP7P, USBP7N I/O Universal Serial Bus Port [7:6] Differential: These differential pairs are used to transmit Data/Address/Command signals for port 7. NOTE: No external resistors are required on these signals. The PCH integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor.
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USBP8P, USBP8N I/O Universal Serial Bus Port [9:8] Differential: These differential pairs are used to transmit Data/Address/Command signals for port 8. NOTE: No external resistors are required on these signals. The PCH integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. USBP9P, USBP9N I/O Universal Serial Bus Port [9:8] Differential: These differential pairs are used to transmit Data/Address/Command signals for port 9. NOTE: No external resistors are required on these signals. The PCH integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. USBP10P, USBP10N I/O Universal Serial Bus Port [11:10] Differential: These differential pairs are used to transmit Data/Address/Command signals for port 10. NOTE: No external resistors are required on these signals. The PCH integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. USBP11P, USBP11N I/O Universal Serial Bus Port [11:10] Differential: These differential pairs are used to transmit Data/Address/Command signals for port 11. NOTE: No external resistors are required on these signals. The PCH integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. USBP12P, USBP12N I/O Universal Serial Bus Port [13:12] Differential: These differential pairs are used to transmit Data/Address/Command signals for port 12. NOTE: No external resistors are required on these signals. The PCH integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. USBP13P, USBP13N I/O Universal Serial Bus Port [13:12] Differential: These differential pairs are used to transmit Data/Address/Command signals for port 13. NOTE: No external resistors are required on these signals. The PCH integrates 15 kΩ pull-downs and provides an output driver impedance of 45 Ω which requires no external series resistor. OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 I Overcurrent Indicators: These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred. These signals can instead be used as GPIOs. NOTES: 1. OC# pins are not 5 V tolerant. 2. Depending on platform configur ation, sharing of OC# pins may be required. 3. OC#[3:0] can only be used for EHCI controller #1 4. OC#[4:7] can only be used for EHCI controller #2 USBRBIAS O USB Resistor Bias: Analog connection point for an external resistor. Used to set transmit currents and internal load resistors. USBRBIAS# I USB Resistor Bias Complement: Analog connection point for an external resistor. Used to set transmit currents and internal load resistors. Table 2-8. USB Interface Signals (Sheet 2 of 2) Name Type Description
2.9 Power Management Interface
Table 2-9. Power Management In terface Signals (Sheet 1 of 3) Name Type Description PLTRST# O Platform Reset: The PCH asserts PLTRST# to reset devices on the platform (such as, SIO, FWH, LAN, processor, etc.). The PCH asserts PLTRST# during power-up and when software initiates a hard reset sequence through the Reset Control register (I/O Register CF9h). The PCH drives PLTRST# inactive a minimum of 1 ms after both PWROK and SYS_PWROK are driven high. The PCH drives PLTRST# active a minimum of 1 ms when initiated through the Reset Control register (I/O Register CF9h). NOTE: PLTRST# is in the VccSus3_3 well. THRMTRIP# I Thermal Trip: When low, this signal indicates that a thermal trip from the processor occurred, and the PCH will immediately transition to a S5 state. The PCH will not wait for the processor stop grant cycle since the processor has overheated. SLP_S3# O S3 Sleep Control: SLP_S3# is for power plane control. This signal shuts off power to all non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off) states. SLP_S4# O S4 Sleep Control: SLP_S4# is for power plane control. This signal shuts power to all non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state. NOTE: This pin must be used to control the DRAM power to use the PCH’s DRAM power-cycling feature. See Chapter 5.13.10.2 for details SLP_S5# / GPIO63 O S5 Sleep Control: SLP_S5# is for power plane control. This signal is used to shut power off to all non-critical systems when in the S5 (Soft Off) states. This signal can instead be used as GPIO63 SLP_M# O Manageability Sleep State Control: SLP_M# is for power plane control. If no Management Engine firmware is present, SLP_M# will have the same timings as SLP_S3#. SLP_LAN# / GPIO29 O LAN Sub-System Sleep Control: When SLP_LAN# is deasserted it indicates that the PHY device must be powered. When SLP_LAN# is asserted, power can be shut off to the PHY device. SLP_LAN# will always be deasserted in S0 and anytime SLP_A# is deasserted. A SLP_LAN#/GPIO Select Soft-Strap can be used for systems NOT using SLP_LAN# functionality to revert to GPIO29 usage. When soft- strap is 0 (default), pin function will be SLP_LAN#. When soft-strap is set to 1, the pin returns to its regular GPIO mode. The pin behavior is summarized in Section 5.13.10.5. PWROK I Power OK: When asserted, PWROK is an indication to the PCH that all of its core power rails are powered and stable. PWROK can be driven asynchronously. When PWROK is negated, the PCH asserts PLTRST#. NOTE: It is required that the power rails associated with PCI/PCIe typically the 3.3 V, 5 V, and 12 V core well rails) have been valid for 99 ms prior to PCH PWROK assertion to comply with the 100 ms PCI 2.3/PCIe 2.0 specification on PLTRST# de- assertion. PWROK must not glitch, even if RSMRST# is low.
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MEPWROK I Management Engine Power OK: When asserted, this signal indicates that power to the ME subsystem is stable. PWRBTN# I Power Button: The Power Button will cause SMI# or SCI to indicate a system request to go to a sleep state. If the system is already in a sleep state, this signal will cause a wake event. If PWRBTN# is pressed for more than 4 seconds, this will cause an unconditional transition (power button override) to the S5 state. Override will occur even if the system is in the S1–S4 states. This signal has an internal pull-up resistor and has an internal 16 ms de-bounce on the input. RI# I Ring Indicate: This signal is an input from a modem. It can be enabled as a wake event, and this is preserved across power failures. SYS_RESET# I System Reset: This pin forces an internal reset after being debounced. The PCH will reset immediately if the SMBus is idle; otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before forcing a reset on the system. RSMRST# I Resume Well Reset: This signal is used for resetting the resume power plane logic. This signal must be asserted for at least 10 ms after the suspend power wells are valid. When de-asserted, this signal is an indication that the suspend power wells are stable. LAN_RST# I LAN Reset: When asserted, the internal LAN controller is in reset. This signal must remain asserted until at least 1 ms after the LAN power well (VccLAN) and ME power well (VccME3_3) are valid. Also, LAN_RST# must assert a minimum of 40 ns before the LAN power rails become inactive. When de-asserted, this signal is an indication that LAN power wells are stable. NOTES: 1. If Intel LAN is enabled, LAN_ RST# must be connected to the same source as MEPWROK. 2. If Intel LAN is not used or disabled, LAN_RST# must be grounded through an external pull-down resistor. LAN_PHY_PW R_CTRL / GPIO12 O LAN PHY Power Control: LAN_PHY_PWR_CTRL should be connected to LAN_DISABLE_N on the Intel 82567 GbE PHY. The PCH will drive LAN_PHY_PWR_CTRL low to put the PHY into a low power state when functionality is not needed. NOTES: LAN_PHY_PWR_CTRL can only be driven low if SLP_LAN# is de- asserted. This signal can instead be used as GPIO12. WAKE# I PCI Express* Wake Event: Sideband wake signal on PCI Express asserted by components requesting wake up. SUS_STAT# / GPIO61 O Suspend Status: This signal is asserted by the PCH to indicate that the system will be entering a low power state soon. This can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode. It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered-off planes. This signal can instead be used as GPIO61. SUSCLK / GPIO62 O Suspend Clock: This clock is an output of the RTC generator circuit to use by other chips for refresh clock. This signal can instead be used as GPIO62. Table 2-9. Power Management Interface Signals (Sheet 2 of 3) Name Type Description
DRAM Power OK: This signal should connect to the Processor’s SM_DRAMPWROK pin. The PCH asserts this pin to indicate when DRAM power is on. NOTE: 1. This pin should have External pull-up to the an always on Voltage level of 1.05 V / 1.1 V PMSYNCH O Power Management Sync: Provides state information from the PCH to the processor relevant to C-state transitions. CLKRUN# (Mobile Only) / GPIO32 (Desktop Only) I/O PCI Clock Run: Mobile only signal used to support PCI CLKRUN protocol. Connects to peripherals that need to request clock restart or prevention of clock stopping. Mobile: Can be configured as CLKRUN# Desktop: GPIO mode only. BATLOW# (Mobile Only) / GPIO72 (Desktop Only) I Battery Low: Mobile only signal is an input from the battery to indicate that there is insufficient power to boot the system. Assertion will prevent wake from S3–S5 state. This signal can also be enabled to cause an SMI# when asserted. Mobile: Can be configured as BATLOW# Desktop: GPIO mode only. NOTE: Desktop requires a weak external pull-up SYS_PWROK I System Power OK: This generic power good input to the PCH is driven and used in a platform-specific manner. While PWROK always indicates that the CORE well of the PCH is stable, SYS_PWROK is used to inform the PCH that power is stable to some other system component(s) and the system is ready to start the exit from reset. The particular component(s) associated with SYS_PWROK can vary across platform types supported by the same generation of the PCH. Depending on the platform, the PCH may expect (and wait) for SYS_PWROK at different stages of the boot flow before continuing. STP_PCI# / GPIO34 O Stop PCI Clock: This signal is an output to the external clock generator for it to turn off the PCI clock. This signal can instead be used as GPIO34. Table 2-9. Power Management In terface Signals (Sheet 3 of 3) Name Type Description
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2.10 Processor Interface
2.11 SMBus Interface
Table 2-10. Processor Interface Signals Name Type Description RCIN# I Keyboard Controller Reset Processor: The keyboard controller can generate INIT# to the processor. This saves the external OR gate with the PCH’s other sources of INIT#. When the PCH detects the assertion of this signal, INIT# is generated for 16 PCI clocks. NOTE: The PCH will ignore RCIN# assertion during transitions to the S1, S3, S4, and S5 states. A20GATE I A20 Gate: A20GATE is from the keyboard controller. The signal acts as an alternative method to force the A20M# signal active. It saves the external OR gate needed with various other chipsets. PROCPWRGD O Processor Power Good: This signal should be connected to the processor’s VCCPWRGOOD_1 and VCCPWRGOOD_0 input to indicate when the processor power is valid. Table 2-11. SM Bus Interface Signals Name Type Description SMBDATA I/OD SMBus Data: External pull-up resistor is required. SMBCLK I/OD SMBus Clock: External pull-up resistor is required. SMBALERT# / GPIO11 I SMBus Alert: This signal is used to wake the system or generate SMI#. This signal can instead be used as GPIO11.
2.12 System Management Interface
2.13 Real Time Clock Interface
Table 2-12. System Management Interface Signals Name Type Description INTRUDER# I Intruder Detect: This signal can be set to disable system if box detected open. This signal’s status is readable, so it can be used like a GPI if the Intruder Detection is not needed. SML0DATA I/OD System Management Link 0 Data: SMBus link to external PHY. External pull-up is required. SML0CLK I/OD System Management Link 0 Clock: SMBus link to external PHY. External pull-up is required. SML0ALERT# / GPIO60 / O OD SMLink Alert 0: Output of the integrated LAN controller to external PHY. External pull-up resistor is required. This signal can instead be used as GPIO60. SML1ALERT# / GPIO74 O OD SMLink Alert 1: Alert for the Intel ME SMBus controller to optional Embedded Controller or BMC. External pull-up resistor is required. This signal can instead be used as GPIO74. SML1CLK / GPIO58 I/OD System Management Link 1 Clock: SMBus link to optional Embedded Controller or BMC. External pull-up resistor is required. This signal can instead be used as GPIO58. SML1DATA / GPIO75 I/OD System Management Link 1 Data: SMBus link to optional Embedded Controller or BMC. External pull-up resistor is required. This signal can instead be used as GPIO75. Table 2-13. Real Time Clock Interface Name Type Description RTCX1 Special Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If no external crystal is used, then RTCX1 can be driven with the desired clock rate. RTCX2 Special Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If no external crystal is used, then RTCX2 should be left floating.
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2.14 Miscellaneous Signals
Table 2-14. Miscellaneous Signals Name Type Description INTVRMEN I Internal Voltage Regulator Enable: This signal enables the internal 1.05 V regulators. This signal must be always pulled-up to VccRTC. SPKR O Speaker: The SPKR signal is the output of counter 2 and is internally “ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an external speaker driver device, which in turn drives the system speaker. Upon PLTRST#, its output state is 0. NOTE: SPKR is sampled as a functional strap. See Section 2.28.1 for more details. There is a weak integrated pull-down resistor on SPKR pin. RTCRST# I RTC Reset: When asserted, this signal resets register bits in the RTC well. NOTES: 1. Unless CMOS is be ing cleared (only to be done in the G3 power state), the RTCRST# input must always be high when all other RTC power planes are on. 2. In the case where the RTC battery is dead or missing on the platform, the RTCRST# pin must rise before the RSMRST# pin. SRTCRST# I Secondary RTC Reset: This signal resets the manageability register bits in the RTC well when the RTC battery is removed. NOTES: 1. The SRTCRST# input must always be high when all other RTC power planes are on. 2. In the case where the RTC battery is dead or missing on the platform, the SRTCRST# pin must rise before the RSMRST# pin.
2.15 Intel ® High Definition Audio Link
Table 2-15. Intel ® High Definition Audio Link Signals Name Type Description HDA_RST# O Intel® High Definition Audio Reset: Master hardware reset to external codec(s). HDA_SYNC O Intel® High Definition Audio Sync: 48 kHz fixed rate sample sync to the codec(s). Also used to encode the stream number. NOTE: This signal is sampled as a functional strap. See Section 2.28.1 for more details. There is a weak integrated pull-down resistor on this pin. HDA_BCLK O Intel® High Definition Audio Bit Clock Output: 24.000 MHz serial data clock generated by the Intel® High Definition Audio controller (the PCH). This signal has a weak internal pull-down resistor. HDA_SDO O Intel® High Definition Audio Serial Data Out: Serial TDM data output to the codec(s). This serial output is double-pumped for a bit rate of 48 Mb/s for Intel® High Definition Audio. NOTE: This signal is sampled as a functional strap. See Section 2.28.1 for more details. There is a weak integrated pull-down resistor on this pin. HDA_SDIN[3:0] I Intel® High Definition Audio Serial Data In [3:0]: Serial TDM data inputs from the codecs. The serial input is single- pumped for a bit rate of 24 Mb/s for Intel ® High Definition Audio. These signals have integrated pull-down resistors, which are always enabled. NOTE: During enumeration, the PCH will drive this signal. During normal operation, the CODEC will drive it. HDA_DOCK_EN# (Mobile Only) / GPIO33 O High Definition Audio Dock Enable: This mobile signal controls the external Intel® HD Audio docking isolation logic. This is an active low signal. When de-asserted the external docking switch is in isolate mode. When asserted the external docking switch electrically connects the Intel® HD Audio dock signals to the corresponding PCH signals. Mobile: Can be configured as HDA_DOCK_EN# Desktop: GPIO mode only. NOTE: This signal is sampled as a functional strap. See Section 2.28.1 for more details. HDA_DOCK_RST# / GPIO13 O Intel High Definition Audio Dock Reset: This signal is a dedicated HDA_RST# signal for the codec(s) in the docking station. Aside from operating independently from the normal HDA_RST# signal, it otherwise works similarly to the HDA_RST# signal. This signal is shared with GPIO13. This signal defaults to GPIO13 mode after PLTRST#. BIOS is responsible for configuring GPIO13 to HDA_DOCK_RST# mode.
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2.16 Controller Link
2.17 Serial Peripheral Interface (SPI)
Table 2-16. Controller Link Signals Signal Name Type Description CL_RST1# / TP20 (Desktop Only) O Controller Link Reset 1: Controller Link reset that connects to a Wireless LAN Device supporting Intel® Active Management Technology. CL_CLK1 / TP18 (Desktop Only) I/O Controller Link Clock 1: Bi-directional clock that connects to a Wireless LAN Device supporting Intel® Active Management Technology. CL_DATA1 / TP19 (Desktop Only) I/O Controller Link Data 1: Bi-directional data that connects to a Wireless LAN Device supporting Intel® Active Management Technology. Table 2-17. Serial Peripheral Interface (SPI) Signals Name Type Description SPI_CS0# O SPI Chip Select 0: Used as the SPI bus request signal. SPI_CS1# O SPI Chip Select 1: Used as the SPI bus request signal. SPI_MISO I SPI Master IN Slave OUT: Data input pin for the PCH. SPI_MOSI O SPI Master OUT Slave IN: Data output pin for the PCH. NOTE: This signal is sampled as a functional strap. See Section 2.28.1 for more details. There is a weak integrated pull-down resistor on this pin. SPI_CLK O SPI Clock: SPI clock signal, during idle the bus owner will drive the clock signal low. 17.86 MHz and 31.25 MHz.
2.18 Intel ® Quiet System Technology and Thermal
Table 2-18. Intel ® Quiet System Technology Signals Signal Name Type Description PWM[3:0] (Desktop Only) / TP[12:9] (Mobile Only) OD O Fan Pulse Width Modulation Outputs: Pulse Width Modulated duty cycle output signal that is used for Intel® Quiet System Technology. When controlling a 3-wire fan, this signal controls a power transistor that, in turn, controls power to the fan. When controlling a 4-wire fan, this signal is connected to the “Control” signal on the fan. The polarity of this signal is programmable. The output default is low. These signals are 5 V tolerant. TACH0 (Desktop Only) / GPIO17 TACH1 (Desktop Only) / GPIO1 TACH2 (Desktop Only) / GPIO6 TACH3 (Desktop Only) / GPIO7 I Fan Tachometer Inputs: Tachometer pulse input signal that is used to measure fan speed. This signal is connected to the “Sense” signal on the fan. These signals can instead be used as a GPIOs. SST I/O Simple Serial Transport: Single-wire, serial bus. Connect to SST compliant devices such as SST thermal sensors or voltage sensors. PECI I/O Platform Environment Control Interface: Single-wire, serial bus. Connect to corresponding pin of the processor for accessing processor digital thermometer.
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2.19 JTAG Signals
NOTE: JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std. 1149.1-2001).
2.20 Clock Signals
Table 2-19. JTAG Signals Name Type Description JTAG_TCK I Test Clock Input (TCK): The test clock input provides the clock for the JTAG test logic. JTAG_TMS I Test Mode Select (TMS): The signal is decoded by the Test Access Port (TAP) controller to control test operations. JTAG_TDI I Test Data Input (TDI): Serial test instructions and data are received by the test logic at TDI. JTAG_TDO OD Test Data Output (TDO): TDO is the serial output for test instructions and data from the test logic defined in this standard. TRST# I Test Reset (RST): RST is an active low asynchronous signal that can reset the Test Access Port (TAP) controller. NOTE: The RST signal is optional per the IEEE 1149.1 specification, and is not functional for Boundary Scan Testing. Table 2-20. Clock Interface Signals (Sheet 1 of 3) Name Type Description CLKIN_BCLK_P, CLKIN_BCLK_N I 133 MHz differential reference clock from a clock chip in Buffer-Through Mode. CLKOUT_BCLK0_P / CLKOUT_PCIE8_P, CLKOUT_BCLK0_N / CLKOUT_PCIE8_N O
133 MHz Differential output to Processor or 100 MHz
PCIe* Gen 1.1 specification differential output to PCI Express devices. CLKOUT_DP_P / CLKOUT_BCLK1_P, CLKOUT_DP_N / CLKOUT_BCLK1_N O 120 MHz Differential output for DisplayPort reference or
133 MHz Differential output to processor
CLKIN_DMI_P, CLKIN_DMI_N I
100 MHz differential reference clock from a clock chip in
Buffer-Through Mode. NOTE: This input clock is required to be PCIe 2.0 jitter spec compliant from a clock chip, for PCIe 2.0 discrete Graphics platforms. CLKOUT_DMI_P, CLKOUT_DMI_N O 100 MHz Gen2 specification jitter tolerant differential output to processor. CLKIN_SATA_P / CKSSCD_P, CLKIN_SATA_N / CKSSCD_N I
100 MHz differential reference clock from a clock chip,
provided separately from CLKIN_DMI, for use only as a 100 MHz source for SATA. CLKIN_DOT96P, CLKIN_DOT96N I 96 MHz differential referenc e clock from a clock chip.
XTAL25_IN I Connection for 25 MHz crystal to the PCH oscillator circuit. XTAL25_OUT O Connection for 25 MHz crystal to the PCH oscillator circuit. REFCLK14IN I Single-ended 14.31818 MHz reference clock driven by a clock chip. CLKOUT_PEG_A_P, CLKOUT_PEG_A_N O 100 MHz Gen2 specification differential output to PCI- Express Graphics device CLKOUT_PEG_B_P, CLKOUT_PEG_B_N O 100 MHz Gen2 specification differential output to a second PCI-Express Graphics device PEG_A_CLKRQ# / GPIO47, PEG_B_CLKRQ# / GPIO56 I Clock Request Signals for PEG SLOTS These signals can instead be used as GPIOs CLKOUT_PCIE[7:0]P, CLKOUT_PCIE[7:0]N O 100 MHz PCIe* Gen1.1 specification differential output to PCI Express* devices PCIECLKRQ0# / GPIO73, PCIECLKRQ1# / GPIO18, PCIECLKRQ2# / GPIO20, PCIECLKRQ3# / GPIO25, PCIECLKRQ4# / GPIO26, PCIECLKRQ5# / GPIO44, PCIECLKRQ6# / GPIO45, PCIECLKRQ7# / GPIO46 I Clock Request Signals for PCI Express 100 MHz Clocks These signals can instead be used as GPIOs NOTE: External Pull-up Resistor required if used for CLKREQ# functionality CLKOUT_PCI[4:0] O Single Ended 33.3 MHz outputs to PCI connectors/ devices. One of these signals must be connected to CLKIN_PCILOOPBACK to function as a PCI clock loopback. This allows skew control for variable lengths of CLKOUT_PCI[4:0]. CLKOUTFLEX0 / GPIO64 O Configurable as a GPIO or as an Intel ® Management Firmware programmable output clock, which can be configured as one of the following:
- 3 3 M H z
- 14.31818 MHz
- DC Output logic ‘0’ (Default) NOTE: Default clock setting requires no Intel ME FW configuration. CLKOUTFLEX1 / GPIO65 O Configurable as a GPIO or as an Intel ® Management Firmware programmable output clock, which can be configured as one of the following: Non functional and unsupported clock output value (Default)
- 3 3 M H z
- 14.31818 MHz output to SIO
- DC Output logic ‘0’ NOTE: Default clock setting requires no Intel ME FW configuration. Table 2-20. Clock Interface Signals (Sheet 2 of 3) Name Type Description
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2.21 LVDS Signals (Mobile only)
Configurable as a GPIO or as an Intel® Management Firmware programmable output clock which can be configured as one of the following:
- 33 MHz
- 14.31818 MHz (Default)
- DC Output logic ‘0’ NOTE: Default clock setting requires no Intel ME FW configuration. CLKOUTFLEX3 / GPIO67 O Configurable as a GPIO or as an Intel ® Management Firmware programmable output clock which can be configured as one of the following:
- 48 MHz (Default)
- 33 MHz
- 14.31818 MHz output to SIO
- DC Output logic ‘0’ NOTE: Default clock setting requires no Intel ME FW configuration. XCLK_RCOMP I/O Differential clock buffer Impedance Compensation: Connected to an external precision resistor (90.9 ohms ± 1%) to VccIO. Table 2-21. LVDS Interface Signals (Sheet 1 of 2) Name Type Description LVDSA_DATA[3:0] O LVDS Channel A differentia l data output – positive LVDSA_DATA#[3:0] O LVDS Channel A differential data output – negative LVDSA_CLK O LVDS Channel A differential clock output – positive LVDSA_CLK# O LVDS Channel A differential clock output – negative LVDSB_DATA[3:0] O LVDS Channel B differential data output – positive LVDSB_DATA#[3:0] O LVDS Channel B differential data output – negative LVDSB_CLK O LVDS Channel B differential clock output – positive LVDSB_CLK# O LVDS Channel B differential clock output – negative L_DDC_CLK I/O EDID support for flat panel display L_DDC_DATA I/O EDID support for flat panel display L_CTRL_CLK I/O Control signal (clock) for external SSC clock chip control – optional L_CTRL_DATA I/O Control signal (data) for external SSC clock chip control – optional L_VDD_EN O LVDS Panel Power Enable: Panel power control enable control for LVDS. This signal is also called VDD_DBL in the CPIS specification and is used to control the VDC source to the panel logic. Table 2-20. Clock Interface Signals (Sheet 3 of 3) Name Type Description
2.22 Analog Display /CRT DAC Signals
L_BKLTEN O LVDS Backlight Enable: Panel backlight enable control for LVDS. This signal is also called ENA_BL in the CPIS specification and is used to gate power into the backlight circuitry. L_BKLTCTL O Panel Backlight Brightness Control: Panel brightness control for LVDS. This signal is also called VARY_BL in the CPIS specification and is used as the PWM Clock input signal. LVDS_VREFH O Test mode voltage reference. LVDS_VREFL O Test mode voltage reference. LVD_IBG I LVDS reference current. LVD_VBG O Test mode voltage reference. Table 2-22. Analog Display Interface Signals Name Type Description CRT_RED O A RED Analog Video Output: This signal is a CRT Analog video output from the internal color palette DAC. CRT_GREEN O A GREEN Analog Video Output: This signal is a CRT Analog video output from the internal color palette DAC. CRT_BLUE O A BLUE Analog Video Output: This signal is a CRT Analog video output from the internal color palette DAC. DAC_IREF I/O A Resistor Set: Set point resistor for the internal color palette DAC. A 1 KOhm 1% resistor is required between DAC_IREF and motherboard ground. CRT_HSYNC O HVCMOS CRT Horizontal Synchronization: This signal is used as the horizontal sync (polarity is programmable) or “sync interval”.
2.5 V output
CRT_VSYNC O HVCMOS CRT Vertical Synchronization: This signal is used as the vertical sync (polarity is programmable). 2.5V output. CRT_DDC_CLK I/O COD Monitor Control Clock CRT_DDC_DATA I/O COD Monitor Control Data CRT_IRTN I/O COD Monitor Interrupt Return Table 2-21. LVDS Interface Signals (Sheet 2 of 2) Name Type Description
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2.23 Intel ® Flexible Display Interface (FDI)
2.24 Digital Display Signals
Table 2-23. Intel ® Flexible Display Interface Signals Signal Name Type Description FDI_RXP[3:0] I Display Link 1 positive data in FDI_RXN[3:0] I Display Link 1 negative data in FDI_FSYNC[0] O Display link 1 Frame sync FDI_LSYNC[0] O Display link 1 Line sync FDI_RXP[7:4] I Display Link 2 positive data in FDI_RXN[7:4] I Display Link 2 negative data in FDI_FSYNC[1] O Display link 2 Frame sync FDI_LSYNC[1] O Display link 2 Line sync FDI_INT O Used for Display interrupts from the PCH to processor. Table 2-24. Digital Display Inte rface Signals (Sheet 1 of 3) Name Type Description DDPB_[3:0]P O Port B: Capable of SDVO / HDMI / DVI / DisplayPort SDVO DDPB_[0]P: red DDPB_[1]P: green DDPB_[2]P: blue DDPB_[3]P: clock HDMI / DVI Port B Data and Clock Lines DDPB_[0]P: TMDSB_DATA2 DDPB_[1]P: TMDSB_DATA1 DDPB_[2]P: TMDSB_DATA0 DDPB_[3]P: TMDSB_CLK DisplayPort Port B DDPB_[0]P: Display Port Lane 0 DDPB_[1]P: Display Port Lane 1 DDPB_[2]P: Display Port Lane 2 DDPB_[3]P: Display Port Lane 3
DDPB_[3:0]N O Port B: Capable of SDVO / HDMI / DVI / DisplayPort SDVO DDPB_[0]N: red complement DDPB_[1]N: green complement DDPB_[2]N: blue complement DDPB_[3]N: clock complement HDMI / DVI Port B Data and Clock Line Complements DDPB_[0]N: TMDSB_DATA2B DDPB_[1]N: TMDSB_DATA1B DDPB_[2]N: TMDSB_DATA0B DDPB_[3]N: TMDSB_CLKB DisplayPort Port B DDPB_[0]N: Display Port Lane 0 complement DDPB_[1]N: Display Port Lane 1 complement DDPB_[2]N: Display Port Lane 2 complement DDPB_[3]N: Display Port Lane 3 complement DDPB_AUXP I/O Port B: Display Port Aux DDPB_AUXN I/O Port B: Display Port Aux Complement DDPB_HPD I Port B: TMDSB_HPD Hot Plug Detect SDVO_CRTLCLK I/O Port B: HDMI Control Clock. Shared with port B SDVO SDVO_CTRLDATA I/O Port B: HDMI Control Data. Shared with port B SDVO SDVO_INTP I SDVO_INTP: Serial Digital Video Input Interrupt SDVO_INTN I SDVO_INTN: Serial Digital Video Input Interrupt Complement. SDVO_TVCLKINP I SDVO_TVCLKINP: Serial Digital Video TVOUT Synchronization Clock. SDVO_TVCLKINN I SDVO_TVCLKINN: Serial Digital Video TVOUT Synchronization Clock Complement. SDVO_STALLP I SDVO_STALLP: Serial Digital Video Field Stall. SDVO_STALLN I SDVO_STALLN: Serial Digital Video Field Stall Complement. DDPC_[3:0]P O Port C: Capable of HDMI / DVI / DP HDMI / DVI Port C Data and Clock Lines DDPC_[0]P: TMDSC_DATA2 DDPC_[1]P: TMDSC_DATA1 DDPC_[2]P: TMDSC_DATA0 DDPC_[3]P: TMDSC_CLK DisplayPort Port C DDPC_[0]P: Display Port Lane 0 DDPC_[1]P: Display Port Lane 1 DDPC_[2]P: Display Port Lane 2 DDPC_[3]P: Display Port Lane 3 Table 2-24. Digital Display Inte rface Signals (Sheet 2 of 3) Name Type Description
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DDPC_[3:0]N O Port C: Capable of HDMI / DVI / DisplayPort HDMI / DVI Port C Data and Clock Line Complements DDPC_[0]N: TMDSC_DATA2B DDPC_[1]N: TMDSC_DATA1B DDPC_[2]N: TMDSC_DATA0B DDPC_[3]N: TMDSC_CLKB DisplayPort Port C Complements DDPC_[0]N: Lane 0 complement DDPC_[1]N: Lane 1 complement DDPC_[2]N: Lane 2 complement DDPC_[3]N: Lane 3 complement DDPC_AUXP I/O Port C: Display Port Aux DDPC_AUXN I/O Port C: Display Port Aux Complement DDPC_HPD I Port C: TMDSC_HPD Hot Plug Detect DDPC_CTRLCLK I/O HDMI port C Control Clock DDPC_CTRLDATA I/O HDMI port C Control Data DDPD_[3:0]P O Port D: Capable of HDMI / DVI / DP HDMI / DVI Port D Data and Clock Lines DDPD_[0]P: TMDSC_DATA2 DDPD_[1]P: TMDSC_DATA1 DDPD_[2]P: TMDSC_DATA0 DDPD_[3]P: TMDSC_CLK DisplayPort Port D DDPD_[0]P: Display Port Lane 0 DDPD_[1]P: Display Port Lane 1 DDPD_[2]P: Display Port Lane 2 DDPD_[3]P: Display Port Lane 3 DDPD_[3:0]N O Port D: Capable of HDMI / DVI / DisplayPort HDMI / DVI Port D Data and Clock Line Complements DDPD_[0]N: TMDSC_DATA2B DDPD_[1]N: TMDSC_DATA1B DDPD_[2]N: TMDSC_DATA0B DDPD_[3]N: TMDSC_CLKB DisplayPort Port D Complements DDPD_[0]N: Lane 0 complement DDPD_[1]N: Lane 1 complement DDPD_[2]N: Lane 2 complement DDPD_[3]N: Lane 3 complement DDPD_AUXP I/O Port D: Display Port Aux DDPD_AUXN I/O Port D: Display Port Aux Complement DDPD_HPD I Port D: TMDSD_HPD Hot Plug Detect DDPD_CTRLCLK I/O HDMI port D Control Clock DDPD_CTRLDATA I/O HDMI port D Control Data Table 2-24. Digital Display Inte rface Signals (Sheet 3 of 3) Name Type Description
2.25 General Purpose I/O Signals
NOTES: 1. GPIO Configuration registers within the Core Well are reset whenever PWROK is de- asserted. 2. GPIO Configuration registers within the Suspend Well are reset when RSMRST# is asserted, CF9h reset (06h or 0Eh) event occurs, or SYS_RST# is asserted. 3. GPIO24 is an exception to the other GPIO Signals in the Suspend Well and is not reset by CF9h reset (06h or 0Eh). Table 2-25. General Purpose I/O Signals (Sheet 1 of 3) Name Type Tolerance Power Well Default Blink Capability Description GPIO75 I/O 3.3 V Suspend Native No Multiplexed with SML1DATA. (Note 10) GPIO74 I/O 3.3 V Suspend Native No Multiplexed with SML1ALERT#. (Note 10) GPIO73 I/O 3.3 V Suspend Native No Multiplexed with PCIECLKRQ0# GPIO72 I/O 3.3 V Suspend Native (Mobile Only) No Mobile: Multiplexed with BATLOW#. Desktop: Unmultiplexed (Note 4) GPIO67 I/O 3.3 V Core Native No Multiplexed with CLKOUTFLEX3 GPIO66 I/O 3.3 V Core Native No Multiplexed with CLKOUTFLEX2 GPIO65 I/O 3.3 V Core Native No Multiplexed with CLKOUTFLEX1 GPIO64 I/O 3.3 V Core Native No Multiplexed with CLKOUTFLEX0 GPIO63 I/O 3.3 V Suspend Native No Multiplexed with SLP_S5# GPIO62 I/O 3.3 V Suspend Native No Multiplexed with SUSCLK GPIO61 I/O 3.3 V Suspend Native No Multiplexed with SUS_STAT# GPIO60 I/O 3.3 V Suspend Native No Multiplexed with SML0ALERT# GPIO59 I/O 3.3 V Suspend Native No Multiplexed with OC[0]#. (Note 10) GPIO58 I/O 3.3 V Suspend Native No Multiplexed with SML1CLK GPIO57 I/O 3.3 V Suspend GPI No Unmultiplexed GPIO56 I/O 3.3 V Suspend Native No Multiplexed with PEG_B_CLKRQ# GPIO55 I/O 3.3 V Core Native No Multiplexed with GNT3# GPIO54 I/O 5.0 V Core Native No Multi plexed with REQ3#. (Note 10) GPIO53 I/O 3.3 V Core Native No Multiplexed with GNT2# GPIO52 I/O 5.0 V Core Native No Multi plexed with REQ2#.(Note 10) GPIO51 I/O 3.3 V Core Native No Multiplexed with GNT1# GPIO50 I/O 5.0 V Core Native No Multi plexed with REQ1#.(Note 10) GPIO49 I/O 3.3V Core GPI No Multiplexed with SATA5GP. GPIO48 I/O 3.3 V Core GPI No Multiplexed with SDATAOUT1. GPIO47 I/O 3.3V Suspend Native No Multiplexed with PEG_A_CLKRQ# GPIO46 I/O 3.3V Suspend Native No Multiplexed with PCIECLKRQ7# GPIO45 I/O 3.3V Suspend Native No Multiplexed with PCIECLKRQ6#
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GPIO44 I/O 3.3V Suspend Native No Multiplexed with PCIECLKRQ5# GPIO[43:40] I/O 3.3 V Suspend Native No Multiplexed with OC[4:1]#. (Note 10) GPIO39 I/O 3.3 V Core GPI No Multiplexed with SDATAOUT0. GPIO38 I/O 3.3 V Core GPI No Multiplexed with SLOAD. GPIO37 I/O 3.3 V Core GPI No Multiplexed with SATA3GP. GPIO36 I/O 3.3 V Core GPI No Multiplexed with SATA2GP. GPIO35 I/O 3.3 V Core GPO No Unmultiplexed. GPIO34 I/O 3.3 V Core GPI No Multiplexed with STP_PCI# GPIO33 I/O 3.3 V Core GPO No Multiplexed with HDA_DOCK_EN# (Mobile Only) (Note 4) GPIO32 I/O 3.3 V Core GPO, Native (Mobile only) No Desktop Only: Unmultiplexed Mobile Only: Used as CLKRUN#, unavailable as GPIO. (Note 4) GPIO31 I/O 3.3 V Suspend GPI Yes Mult iplexed with ACPRESENT (Note 6) GPIO30 I/O 3.3 V Suspend GPI Yes Multiplexed with SUS_PWR_DN_ACK Desktop: Cannot be used for native function. Used as GPIO30 only. Mobile: Used as SUS_PWR_DN_ACK or GPIO30 GPIO29 I/O 3.3 V Suspend GPI No Multi plexed with SLP_LAN# (Note 9) GPIO28 I/O 3.3 V Suspend GPI Yes Unmultiplexed GPIO27 I/O 3.3 V Suspend GPO Yes Unmultiplexed GPIO26 I/O 3.3 V Suspend Native Yes M ultiplexed with PCIECLKRQ4# GPIO25 I/O 3.3 V Suspend Native Yes M ultiplexed with PCIECLKRQ3# GPIO24 I/O 3.3 V Suspend GPO Yes Unmultiplexed NOTE: GPIO24 configuration register bits are not cleared by CF9h reset event. GPIO23 I/O 3.3 V Core Native Yes Multiplexed with LDRQ1#. GPIO22 I/O 3.3 V Core GPI Yes Multiplexed with SCLOCK GPIO21 I/O 3.3 V Core GPI Yes Multiplexed with SATA0GP GPIO20 I/O 3.3 V Core Native Yes Mu ltiplexed with PCIECLKRQ2# GPIO19 I/O 3.3 V Core GPI Yes Multiplexed with SATA1GP GPIO18 I/O 3.3 V Core Native Yes (Note 7) Multiplexed with PCIECLKRQ1# GPIO17 I/O 3.3 V Core GPI Yes Multiplexed with TACH0. Mobile: Used as GPIO17 only. GPIO16 I/O 3.3 V Core GPI Yes Multiplexed with SATA4GP. GPIO15 I/O 3.3 V Suspend GPO Yes Unmultiplexed GPIO14 I/O 3.3 V Suspend Native Yes Multiplexed with OC7# Table 2-25. General Purpose I/O Signals (Sheet 2 of 3) Name Type Tolerance Power Well Default Blink Capability Description
NOTES: 1. All GPIOs can be configured as either input or output. 2. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an SMI# or an SCI, but not both. 3. Some GPIOs exist in the VccSus3_3 power plan e. Care must be taken to make sure GPIO signals are not driven high into powered-down planes. Also, external devices should not be driving powered down GPIOs high. Some GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button Override event will result in the PCH driving a pin to a logic 1 to another device that is powered down. 4. The functionality that is multiplexed with the GPIO may not be used in desktop configuration. 5. When this signal is configured as GP O, the output stage is an open drain. 6. In a ME disabled system, GPIO31 ma y be used as ACPRESENT from the EC. 7. GPIO18 will toggle at a frequency of approxim ately 1 Hz when the signal is programmed as a GPIO (when configured as an output) by BIOS. 9. For functional purposes of SLP_LAN# (the nati ve functionality of the pin), this pin always behaves as an output even if the GPIO defaults to an input. Therefore, this pin cannot be used as a true GPIO29 by system designers. If Host BIOS does not control SLP_LAN# control, SLP_LAN# behavior will be based on the setting of the RTC backed SLP_LAN# Default Bit (D31:F0:A4h:Bit 8). 10. When the multiplexed GPIO is used as GPIO functionality, care should be taken to ensure the signal is stable in its inactive state of the native functionality, immediately after reset until it is initialized to GPIO functionality. 11. GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Voltage tolerance on the signal is the same as VccSusHDA. GPIO13 I/O
3.3 V or
1.5 V (Note 11) HDA Suspend GPI Yes Multiplexed with HDA_DOCK_RST# (Mobile Only) (Note 4) GPIO12 I/O 3.3 V Suspend Native Yes Multiplexed with LAN_PHY_PWR_CTRL. GPIO / Native functionality controlled using soft strap. GPIO11 I/O 3.3 V Suspend Native Yes Multi plexed with SMBALERT#. (Note 10) GPIO10 I/O 3.3 V Suspend Native Yes Mul tiplexed with OC6#. (Note 10) GPIO9 I/O 3.3 V Suspend Native Yes Multiplexed with OC5#. (Note 10) GPIO8 I/O 3.3 V Suspend GPO Yes Unmultiplexed GPIO[7:6] I/O 3.3 V Core GPI Yes Multiplexed with TACH[3:2]. Mobile: Used as GPIO[7:6] only. GPIO[5:2] I/OD 5 V Core GPI Yes Multiplexed with PIRQ[H:E]# (Note 5). GPIO1 I/O 3.3 V Core GPI Yes Multiplexed with TACH1. Mobile: Used as GPIO1 only. GPIO0 I/O 3.3 V Core GPI Yes Unmultiplexed Table 2-25. General Purpose I/O Signals (Sheet 3 of 3) Name Type Tolerance Power Well Default Blink Capability Description
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2.26 Manageability Signals
The following signals can be optionally used by the PCH Management engine supported applications and appropriately configured by Management Engine firmware. When configured and used as a Manageability function, the associated host GPIO functionality is no longer available. If the Manageability function is not used in a platform, the signal can be used as a host General Purpose I/O or a native function. NOTE: SLP_LAN#/GPIO29 may also be configured by ME FW in Sx/Moff. See SLP_LAN#/GPIO29 signal description for details. Table 2-26. Manageability Signals Name Type Description GPIO30/ PROC_MISSING (Desktop Only) I Used to indicate Processor Missing to the PCH Management Engine. SATA5GP / GPIO49 / TEMP_ALERT# O Used as an alert (active low) to indicate to the external controller (such as, EC or SIO) that temperatures are out of range for the PCH or Graphics/Memory Controller or the processor core. ACPRESENT (Mobile Only)/ GPIO31 I Used in Mobile systems. Input signal from the Embedded Controller to indicate AC power source or the system battery. Active High indicates AC power. NOTE: This Signal is required unless using Intel Management Engine Ignition firmware. SUS_PWR_DN_ACK (Mobile Only)/ GPIO30 O Active High output signal asserted by the Intel ® ME to the Embedded Controller, when it does not require the PCH Suspend well to be powered. NOTE: This signal is required by Management Engine in all platforms.
2.27 Power and Ground Signals
Table 2-27. Power and Ground Signals (Sheet 1 of 2) Name Description DcpRTC Decoupling: This signal is for RTC decoupling only. This signal requires decoupling. DcpSST Decoupling: Internally generated 1.5V powered off of Suspend Well. This signal requires decoupling. Decoupling is required even if this feature is not used. DcpSus Decoupling: 1.05 V Suspend well supply that is supplied internally by Internal VRs. This signal requires decoupling. DcpSusByp Decoupling: 1.05 V Suspend well supply that is supplied internally by Internal VRs. This signal requires decoupling. V5REF Reference for 5 V tolerance on core well inputs. This power may be shut off in S3, S4, S5 or G3 states. V5REF_Sus Reference for 5 V tolerance on suspend well inputs. This power is not expected to be shut off unless the system is unplugged. VccCore 1.05 V supply for core well logic. This power may be shut off in S3, S4, S5 or G3 states. Vcc3_3 3.3 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5 or G3 states. VccME 1.05 V supply for the Intel® Management Engine. This plane must be on in S0 and other times the Intel® Management Engine is used. VccME3_3 3.3 V supply for the Intel® Management Engine I/O and SPI I/O. This is a separate power plane that may or may not be powered in S3–S5 states. This plane must be on in S0 and other times the Intel® Management Engine is used. VccDMI Power supply for DMI. 1.1 V or 1.05 V based on the processor used. See the respective processor documentation to find the appropriate voltage level. VccLAN 1.05 V supply for LAN controller logic. This is a separate power plane that may or may not be powered in S3–S5 states. NOTE: VccLAN may be grounded if Intel LAN is disabled. VccRTC 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This power is not expected to be shut off unless the RTC battery is removed or completely drained. NOTE: Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Clearing CMOS in a PCH-based platform can be done by using a jumper on RTCRST# or GPI. VccIO 1.05 V supply for core well I/O buffers. This power may be shut off in S3, S4, S5 or G3 states. VccSus3_3 3.3 V supply for suspend well I/O buffers. This power is not expected to be shut off unless the system is unplugged. VccSusHDA Suspend supply for Intel® High Definition Audio. This pin can be either 1.5 or 3.3 V. VccVRM 1.8 V supply for internal PLL and VRMs VccpNAND This pin should be pulled up to 1.8V or 3.3V.
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VccADPLLA 1.05 V supply for Display PLL A Analog Power. This power is supplied by the core well. VccADPLLB 1.05 V supply for Display PLL B Analog Power. This power is supplied by the core well. VccADAC 3.3 V supply for Display DAC Analog Power. This power is supplied by the core well. Vss Grounds. VSS_NCTF Non-Critical To Function. These pins are for package mechanical reliability. NOTE: These pins should be connected to Ground. Vcc3_3_NCTF Non-Critical To Function. These pins are for package mechanical reliability. NOTE: These pins should be connected the same as the Vcc3_3 pins. VccRTC_NCTF Non-Critical To Function. These pins are for package mechanical reliability. NOTE: These pins should be connected to DcpRTC or left as No Connect. VccSUS3_3_N CTF Non-Critical To Function. These pins are for package mechanical reliability. NOTE: These pins should be connected the same as the VccSUS3_3 pins. V_CPU_IO_NC TF Non-Critical To Function. These pins are for package mechanical reliability. NOTE: These pins should be connected the same as the V_CPU_IO pins. TP22_NCTF Non-Critical To Function. These pins are for package mechanical reliability. NOTE: These pins should be connected to Ground. VccAClk 1.05 V Analog power supply for internal clock PLL. This requires a filter and power is supplied by the core well. NOTE: This pin can be left as no connect in On-Die VR enabled mode (default). VccSATAPLL 1.05 V Analog power supply for SATA. This signal is used for the analog power for SATA. This requires an LC filter and is supplied by the core well. Must be powered even if SATA is not used. NOTE: This pin can be left as no connect in On-Die VR enabled mode (default). VccAPLLEXP 1.05 V Analog Power for DMI. This power is supplied by the core well. This requires an LC filter. NOTE: This pin can be left as no connect in On-Die VR enabled mode (default). VccFDIPLL 1.05 V analog power supply for the FDI PLL. This power is supplied with core well. This requires an LC filter. NOTE: This pin can be left as no connect in On-Die VR enabled mode (default). VccALVDS 3.3 V Analog power supply for LVDS (Mobile Only) VccTX_LVDS 1.8 V I/O power supply for LVDS. (Mobile Only) This power is supplied by core well. V_CPU_IO Powered by the same supply as the processor I/O voltage. This supply is used to drive the processor interface signals. See the respective processor documentation to find the appropriate voltage level. Table 2-27. Power and Ground Signals (Sheet 2 of 2) Name Description
2.28 Pin Straps
2.28.1 Functional Straps
The following signals are used for static configuration. They are sampled at the rising edge of PWROK to select configurations (except as noted), and then revert later to their normal usage. To invoke the associated mode, the signal should be driven at least four PCI clocks prior to the time it is sampled. The PCH has implemented Soft Straps. Soft Straps are used to configure specific functions within the PCH and processor very early in the boot process before BIOS or SW intervention. When Descriptor Mode is enabled, the PCH will read Soft Strap data out of the SPI device prior to the de-assertion of reset to both the Management Engine and the Host system. See Section 5.24.2 for information on Descriptor Mode. Table 2-28. Functional Strap Definitions (Sheet 1 of 4) Signal Usage When Sampled Comment SPKR No Reboot Rising edge of PWROK The signal has a weak internal pull-down. NOTE: The internal pull-down is disabled after PLTRST# de- asserts. If the signal is sampled high, this indicates that the system is strapped to the “No Reboot” mode (the PCH will disable the TCO Timer system reboot feature). The status of this strap is readable using the NO REBOOT bit (Chipset Config Registers: Offset 3410h:bit 5). INIT3_3V# Reserved Rising edge of PWROK This signal has a weak internal pull up. Note that the internal pull-up is disabled after PLTRST# de-asserts. NOTE: This signal should not be pulled low. GNT[3]#/ GPIO[55] Top-Block Swap Override Rising edge of PWROK The signal has a weak internal pull-up. If the signal is sampled low, this indicates that the system is strapped to the “topblock swap” mode. The status of this strap is readable using the Top Swap bit (Chipset Config Registers:Offset 3414h:bit 0). NOTES: 1. The internal pull-up is disabled after PLTRST# deasserts. 2. Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3#/GPIO55 being pulled down. INTVRMEN Integrated 1.05 V VRM Enable / Disable Always Integrated 1.05 V VRMs is enabled when high NOTE: This signal should always be pulled high
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GNT1# / GPIO51 Boot BIOS Strap bit [1] BBS[1] Rising edge of PWROK This signal has a weak internal pull-up. Note that the internal pull-up is disabled after PCIRST# de- asserts. This field determines the destination of accesses to the BIOS memory range. Also, controllable using Boot BIOS Destination bit (Chipset Config Registers:Offset 3410h:bit 11). This strap is used in conjunction with Boot BIOS Destination Selection 0 strap. NOTE: If option 00 LPC is selected, BIOS may still be placed on LPC; however, all platforms with the PCH require SPI flash connected directly to the PCH SPI bus with a valid descriptor to boot. NOTE: Booting to PCI is intended for debut/testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or using Boot BIOS Destination Bit will not affect SPI accesses initiated by Intel Management Engine or Integrated GbE LAN. GNT[0]# Boot BIOS Strap bit[0] BBS[0] Rising edge of PWROK This Signal has a weak internal pull-up. Note that the internal pull-up is disabled after PCIRST# de- asserts. This field determines the destination of accesses to the BIOS memory range. Also, controllable using Boot BIOS Destination bit (Chipset Config Registers:Offset 3410h:bit 10). This strap is used in conjunction with Boot BIOS Destination Selection 1 strap. NOTE: If option 00 LPC is selected, BIOS may still be placed on LPC; however, all platforms with the PCH require SPI flash connected directly to the PCH's SPI bus with a valid descriptor to boot. NOTE: Booting to PCI is intended for debut/testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or using Boot BIOS Destination Bit will not affect SPI accesses initiated by Management Engine or Integrated GbE LAN. Table 2-28. Functional Strap Definitions (Sheet 2 of 4) Signal Usage When Sampled Comment Bit11 Bit 10 Boot BIOS Destination
01 R e s e r v e d
10 P C I
11 S P I
00 L P C
GNT2#/ GPIO53 ESI Strap (Server Only) Rising edge of PWROK This Signal has a weak internal pull-up. Note that the internal pull-up is disabled after PCIRST# de- asserts. Tying this strap low configures DMI for ESI compatible operation. NOTE: ESI compatible mode is for server platforms only. This signal should not be pulled low for desktop and mobile. NV_ALE Reserved Rising edge of PWROK This signal has a weak internal pull down. NOTE: This signal should not be pulled high HDA_DOCK_E N#/GPIO[33] Flash Descriptor Security Override/ ME Debug Mode Rising edge of PWROK Signal has a weak internal pull-up. If strap is sampled high, the security measures defined in the Flash Descriptor will be in effect (default). If sampled low, the Flash Descriptor Security will be overridden. This strap should only be asserted low using external pull down in manufacturing/debug environments ONLY. NOTE: Asserting the GPIO33 low on the rising edge of PWROK will also halt Intel ® Management Engine after chipset bringup and disable runtime Intel® Management Engine features. This is a debug mode and must not be asserted after manufacturing/ debug. SPI_MOSI Reserved Rising edge of MEPWROK This signal has a weak internal pull-down resistor. This signal must be sampled low. NV_CLE DMI Termination Voltage Rising edge of PWROK This signal has a weak internal pull-down. HDA_SDO Reserved Rising edge of RSMRST# This signal has a weak internal pull down. NOTE: This signal should not be pulled high GPIO8 Reserved Rising edge of RSMRST# This signal has a weak internal pull up. Note that the weak internal pull-up is disabled after RSMRST# de-asserts. NOTE: This signal should not be pulled low GPIO27 Reserved Rising edge of RSMRST# This signal has a weak internal pull-up. note that the weak internal pull-up is disabled after RSMRST# de-asserts. NOTE: This signal should not be pulled low and can be left as a No Connect. HDA_SYNC On-Die PLL Voltage Regulator Voltage Select Rising edge of RSMRST# pin This signal has a weak internal pull down. On-Die PLL VR is supplied by 1.8 V when sampled low. NOTE: This signal should not be pulled high. Table 2-28. Functional Strap Definitions (Sheet 3 of 4) Signal Usage When Sampled Comment
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NOTE: See Section 3.1 for full details on pull-up/pull-down resistors. GPIO15 Reserved Rising edge of RSMRST# pin Low = Intel® Management Engine Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High = Intel® Management Engine Crypto TLS cipher suite with confidentiality This signal has a weak internal pull down. NOTE: A strong pull up may be needed for GPIO functionality NOTE: This signal is required to be pulled up to enable TLS. If this signal is pulled down or left floating Intel® RPAT and Intel® AMT with TLS will not be functional. L_DDC_DATA LVDS Rising Edge of PWROK This signal has a weak internal pull-down. Note that the weak internal pull-down is disabled after PLTRST# de-asserts. LVDS is enabled when sampled high. When sampled low LVDS is Disabled. SDVO_CTRLDA TA Digital Display Port (Port B) Rising Edge of PWROK This signal has a weak internal pull-down. Note that the weak internal pull-down is disabled after PLTRST# de-asserts. Port B is enabled when sampled high. When sampled low Port B is Disabled. DDPC_CTRLDA TA Digital Display Port (Port C) Rising Edge of PWROK This signal has a weak internal pull-down. Note that the weak internal pull-down is disabled after PLTRST# de-asserts. Port C is enabled when sampled high. When sampled low Port C is Disabled. DDPD_CTRLDA TA Digital Display Port (Port D) Rising Edge of PWROK This signal has a weak internal pull-down. Note that the weak internal pull-down is disabled after PLTRST# de-asserts. Port D is enabled when sampled high. When sampled low Port D is Disabled. Table 2-28. Functional Strap Definitions (Sheet 4 of 4) Signal Usage When Sampled Comment
2.28.2 External RTC Circuitry
The PCH implements an internal oscillator circuit that is sensitive to step voltage changes in VccRTC. Figure 2-2 shows an example schematic recommended to ensure correct operation of the PCH RTC. Notes: 1. The exact capacitor values for C1 and C2 must be based on the crystal maker recommendations. 2. Vbatt is voltage provided by the battery. 3. VccRTC, RTCX1, and RTCX2 are PCH pins. 4. VccRTC powers PCH RTC well. 5. RTCX1 is the input to the internal oscillator. 6. RTCX2 is the amplified feedback for the external crystal. § § Figure 2-2. Example External RTC Circuit
32.768 KHz
10MΩ VCCRTC RTCX2 RTCX1 Vbatt 1uF 1 KΩ 3.3V Sus C1 C2 RTCRST# 1.0 uF 20 KΩ 0.1uF SRTCRST# 20 KΩ 1.0 uF Schottky Diodes
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3 PCH Pin States
3.1 Integrated Pull-Ups and Pull-Downs
Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 1 of 2) Signal Resistor Nominal Notes CL_CLK1 Pull-up/Pull- down 32/100 13, 22 CL_DATA1 Pull-up/Pull- down 32/100 13, 22 CLKOUTFLEX[3:0]/GPIO[67:64] Pull-down 20K 1, 16 HDA_RST# Pull-down 20K 2, 16 GPIO15 Pull-down 20K 3, 21 HDA_BCLK Pull-down 20K 1, 16 HDA_DOCK_EN#/GPIO33 Pull-up 20K 3, 7 HDA_SDIN[3:0] P ull-down 20K 2 HDA_DOCK_RST# /GPIO13 Pull-down 20K 19, 20 HDA_SYNC, HDA_SDO Pull-down 20K 2, 7 GNT[3:1]#/GPIO[55,53,51], GNT0# Pull-up 20K 3, 11, 12 GPIO8 Pull-up 20K 3, 21 LAD[3:0]# / FHW[3:0]# Pull-up 20K 3 LDRQ0#, LDRQ1# / GPIO23 Pull-up 20K 3 NV_ALE, NV_CLE Pull-down 20K 13 PME# Pull-up 20K 3 INIT3_3V# Pull-up 20K 3 PWRBTN# Pull-up 20K 3 SPI_MOSI Pull-down 20K 3,7 SPI_CS0#, SPI_CS1#, SPI_MISO Pull-up 20K 3 SPKR Pull-down 20K 3,15 TACH[3:0]/GPIO[7,6,1,17] Pull-up 20K 3;only on TACH[3:0] USB[13:0] [P,N] Pull-down 20K 5 DDP[D:C]_CTRLCLK Pull-down 10K DDP[D:C]_CRTLDATA Pull down 20K 3, 15 SDVO_CTRLDATA,L_DDC_DATA Pull down 20K 3, 15 SDVO_CTRLCLK Pull down 20K 3 BATLOW#/GPIO72 Pull-up 20K 3 CLKOUT_PCI[4:0] Pull-down 20K 1, 16 GPIO27 Pull-up 20K 3, 21 PCIECLKRQ0#/GPIO73 Pull-up 20K 3, 21 JTAG_TDI, JTAG_TMS, TRST# Pull-up 20K 1, 17
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NOTES: 1. Simulation data shows that these resistor values can range from 10 kΩ to 40 kΩ. 2. Simulation data shows that these resistor values can range from 9 kΩ to 50 kΩ. 3. Simulation data shows that these resistor values can range from 15 kΩ to 40 kΩ. 4. Simulation data shows that these resistor values can range from 7.5kΩ to 16kΩ. 5. Simulation data shows that these resistor values can range from 14.25 kΩ to 24.8 kΩ. 6. Simulation data shows that these resistor values can range from 10 kΩ to 30 kΩ. 7. The pull-up or pull-down on this signal is on ly enabled at boot/reset for strapping function. 8. Simulation data shows that these resistor values can range from 10 kΩ to 20 kΩ. The internal pull-up is only enabled during PLTRST# assertion. 9. The pull-down on this signal is only enabled when in S3. 10. The pull-up or pull-dow n on this signal is only enabled during reset. 11. The pull-up on this signal is not enabled when PCIRST# is high. 12. The pull-up on this signal is not enabled when PWROK is low. 13. Simulation data shows that these resistor values can range from 15 kΩ to 31 kΩ. 14. The pull-down is disabled after pins are driven strongly to logic zero when PWROK is asserted. 15. The Pull-up or pull down is not ac tive when PLTRST# is NOT asserted. 16. The pull-down is enabled when PWROK is low. 17. External termination is also required on th ese signals for JTAG enabling. Internal pull-up is added in B-step Silicon. 18. External termination is also required on these signals for JTAG enabling. Internal pull-down is added in B-step Silicon. 19. Simulation data shows that these resistor values can range from 20 kΩ to 27 kΩ. 20. Pull-down is enabled only when PCIRST# pin is driven low. 21. Pull-up is disabled afte r RSMRST# is de-asserted. 22. The Controller Link Clock an d Data buffers use internal pull-up or pull-down resistors to drive a logical 1 or 0. JTAG_TCK Pull-down 20K 1, 18 GPIO28 Pull-up 20K 3 PCIECLKRQ6#/GPIO45 Pull-up 20K 3 Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 2 of 2) Signal Resistor Nominal Notes
3.2 Output and I/O Signals Planes and States
Table 3.2and Table 3-3 shows the power plane associated with the output and I/O signals, as well as the state at various times. Within the table, the following terms are used: “High-Z” Tri-state. The PCH not driving the signal high or low. “High” The PCH is driving the signal to a logic 1. “Low” The PCH is driving the signal to a logic 0. “Defined” Driven to a level that is defi ned by the function or external pull- up/pull-down resistor (will be high or low). “Undefined” The PCH is driving the si gnal, but the value is indeterminate. “Running” Clock is toggling or signal is transitioning because function not stopping. “Off” The power plane is off; The PCH is not driving when configured as an output or sampling when configured as an input. “Input” The PCH is sampling and signal state determined by external driver. Note: Signal levels are the same in S4 and S5, except as noted. The PCH suspend well signal states are indeterminate and undefined and may glitch prior to RSMRST# de-assertion. This does not apply to SLP_S3#, SLP_S4#, SLP_S5#, GPIO24, and GPIO29. These signals are determinate and defined prior to RSMRST# de- assertion. The PCH core well signal states are indeterminate and undefined and may glitch prior to PWROK assertion. This does not apply to THRMTRIP#. This signal is determinate and defined prior to PWROK assertion. Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet 1 of 5) Signal Name Power Plane During Reset2 Immediately after Reset2 S0/S1 S3 S4/S5 PCI Express* PETp[8:1], PETn[8:1] Core High High 5 Defined OFF OFF DMI DMI[3:0]TXP, DMI[3:0]TXN Core High High Defined Off Off PCI Bus AD[31:0] Core Low Undefined Defined Off Off C/BE[3:0]# Core Low Undefined Defined Off Off DEVSEL# Core High-Z High-Z High-Z Off Off FRAME# Core High-Z High-Z High-Z Off Off GNT0#8, GNT[3:1]#8/ GPIO[55, 53, 51] Core High High High Off Off IRDY#, TRDY# Core High-Z High-Z High-Z Off Off
102 Datasheet
PAR Core Low Low Low Off Off PCIRST# Suspend Low High High Low Low PERR# Core High-Z High-Z High-Z Off Off PLOCK# Core High-Z High-Z High-Z Off Off STOP# Core High-Z High-Z High-Z Off Off LPC/FWH Interface LAD[3:0] / FWH[3:0] Core High High High Off Off LFRAME# / FWH[4] Core High High High Off Off INIT3_3V#8 Core High High High Off Off SATA Interface SATA[5:0]TXP, SATA[5:0]TXN Core High-Z High-Z Defined Off Off SATALED# Core High-Z High-Z Defined Off Off SATAICOMPO Core High High Defined Off Off SCLOCK/GPIO22 Core High-Z (Input) High-Z (Input) Defined Off Off SLOAD/GPIO38 Core High-Z (Input) High-Z (Input) Defined Off Off SDATAOUT[1:0]/ GPIO[48,39] Core High-Z High-Z High-Z Off Off Interrupts PIRQ[A:D]#, Core High-Z High-Z High-Z Off Off PIRQ[H:E]# / GPIO[5:2] Core High-Z (Input) High-Z (Input) Defined Off Off SERIRQ Core High-Z High-Z High-Z Off Off USB Interface USB[13:0][P,N] Suspend Low Low Defined Defined Defined USBRBIAS Suspend High-Z High-Z High High High Power Management LAN_PHY_PWR_CTRL11 /GPIO12 Suspend Low Low Defined Defined Defined PLTRST# Suspend Low High High Low Low SLP_M#6 Suspend Low High High Defined Defined SLP_S3# Suspend Low High High Low Low SLP_S4# Suspend Low High High High Low SLP_S5#/GPIO63 Suspend Low High High High Low SUS_STAT#/GPIO61 Suspend Low High High Low Low SUSCLK/GPIO62 Suspend Low Running DRAMPWROK Suspend Low High-Z High-Z High-Z Low PMSYNCH Core Low Low Defined Off Off Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet 2 of 5) Signal Name Power Plane During Reset2 Immediately after Reset2 S0/S1 S3 S4/S5
STP_PCI#/GPIO34 Core High-Z (Input) High-Z (Input) Defined Off Off SLP_LAN#/GPIO299 Suspend Low Defined 9 High Defined Defined Processor Interface A20M# CPU Dependant on A20GATE Signal See Note 1 High Off Off PROCPWRGD CPU Low 3 High High Off Off SMBus Interface SMBCLK, SMBDATA Suspend High-Z High-Z Defined Defined Defined System Management Interface SML0ALERT# / GPIO60 Suspend High-Z High-Z 12 Defined Defined Defined SML0DATA Suspend High-Z High-Z Defined Defined Defined SML0CLK Suspend High-Z High -Z Defined Defined Defined GPIO58/SML1CLK Suspend High-Z Hi gh-Z Defined Defined Defined SML1ALERT#/GPIO74 Suspend High-Z High-Z Defined Defined Defined SML1DATA//GPIO75 Suspend High-Z High-Z Defined Defined Defined JTAG_TDO Suspend High-Z High-Z High-Z High-Z High-Z Miscellaneous Signals SPKR8 Core Low Low Defined Off Off Clocking Signals CLKOUT_BCLK0_P / CLKOUT_PCIE8_P, CLKOUT_BCLK0_N / CLKOUT_PCIE8_N Core Running Running Running Off Off CLKOUT_DP_P / CLKOUT_BCLK1_P, CLKOUT_DP_N / CLKOUT_BCLK1_N Core Running Running Running Off Off CLKOUT_DMI_P, CLKOUT_DMI_N Core Running Running Running Off Off CLKOUT_PEG_A_P, CLKOUT_PEG_A_N Core Running Running Running Off Off CLKOUT_PEG_B_P, CLKOUT_PEG_B_N Core Running Running Running Off Off CLKOUT_PCIE[7:0] P, CLKOUT_PCIE[7:0] N Core Running Running Running Off Off CLKOUT_PCI[4:0] Core Running Running Running Off Off CLKOUTFLEX[3:0]/ GPIO[67:64] Core Low Low Running/ Low Off Off XTAL25_OUT Core Running Running Running Off Off XCLK_RCOMP Core High-Z High-Z High-Z Off Off Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet 3 of 5) Signal Name Power Plane During Reset2 Immediately after Reset2 S0/S1 S3 S4/S5
104 Datasheet
Intel® High Definition Audio Interface HDA_RST# HDA Suspend Low Low 4 Defined Low Low HDA_SDO8 HDA Suspend Low Low Low Low Low HDA_SYNC8 HDA Suspend Low Low Low Low Low HDA_BCLK HDA Suspend Low Low Low Low Low UnMultiplexed GPIO Signals GPIO88 Suspend High High Defined Defined Defined GPIO158 Suspend Low Low Defined Defined Defined GPIO24 Suspend Low Low Defined Defined Defined GPIO278 Suspend High Low Defined Defined Defined GPIO32 Core High High Defined Off Off GPIO35 Core Low Low Defined Off Off GPIO57 Suspend High-Z (Input) High-Z (Input) Defined Defined Defined GPIO72 Suspend High-Z (Input) High-Z (Input) Defined Defined Defined Multiplexed GPIO Signals used as GPIO only GPIO0 Core High-Z (Input) High-Z(Input) Defined Off Off GPIO13 10, 14 HDA Suspend Low High-Z Defined Defined Defined GPIO28 Suspend High-Z High-Z Defined Defined Defined GPIO3010 Suspend High-Z (Input) High-Z (Input) Defined Defined Defined GPIO3110 Suspend High-Z (Input) High-Z (Input) Defined Defined Defined GPIO3310 Core High High Defined Off Off SPI Interface SPI_CS0# ME33IO High 13 High Defined Defined Defined SPI_CS1# ME33IO High 13 High Defined Defined Defined SPI_MOSI8 ME33IO Low 13 Low Defined Defined Defined SPI_CLK ME33IO Low 13 Low Running Defined Defined Intel® Quiet System Technology and Thermal Reporting PWM[3:0] Core High-Z Low Defined Off Off SST Suspend High-Z Low Defined Off Off PECI CPU Low Low Defined Off Off Analog Display / CRT DAC Signals CRT_RED, CRT_GREEN, CRT_BLUE Core High-Z High-Z High-Z Off Off DAC_IREF Core High-Z High-Z High-Z Off Off Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet 4 of 5) Signal Name Power Plane During Reset2 Immediately after Reset2 S0/S1 S3 S4/S5
NOTES: 1. PCH drives PROCPWRGD after PWROK and SYS_PW ROK signals are active, and thus will be driven low by PCH when either of these signals are inactive. During boot, or during a hard reset with power cycling, PROCPWRGD will be expected to transition from low to High-Z 2. The states of Core and proc essor signals are evaluated at the times During PLTRST# and Immediately after PLTRST#. The states of the LAN and GLAN signals are evaluated at the times During LAN_RST# and Immediately after LAN_RST#. The states of the Controller Link signals are taken at the times During CL_RST1# and Immediately after CL_RST1#. The states of the Suspend signals are evaluated at the times During RSMRST# and Immediately after RSMRST#, with an exception to GPIO signals; see Section 2.25 for more details on GPIO state after reset. The states of the HDA signals are evaluated at the times During HDA_RST# and Immediately after HDA_RST#. 3. SLP_S5# signals will be high in the S4 state. 4. Low until Intel ® High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time HDA_RST# will be High and HDA_BIT_CLK will be Running. 5. PETp/n[8:1] high until port is enabled by software. 6. The SLP_M# state will be determined by Intel ® Management Engine Firmware. 7. The state of signals in S3–S 5 will be defined by Intel® AMT Policies. 8. This signal is sampled as a fu nctional strap during reset. See Functional straps definition table for usage. 9. SLP_LAN# behavior after reset is dependen t on value of SLP_LAN# default value bit. CRT_HSYNC Core Low Low Low Off Off CRT_VSYNC Core Low Low Low Off Off CRT_DDC_CLK Core High-Z High-Z High-Z Off Off CRT_DDC_DATA Core High-Z High-Z High-Z Off Off CRT_IRTN Core High-Z High-Z High-Z Off Off Intel® Flexible Display Interface FDI_RXP[7:0], FDI_RXN[7:0] Core High-Z High-Z High-Z Off Off FDI_FSYNC[1:0] Core High-Z High-Z High-Z Off Off FDI_LSYNC[1:0] Core High-Z High-Z High-Z Off Off FDI_INT Core High-Z High-Z High-Z Off Off Digital Display Interface DDP[D:B]_[3:0]P, DDP[D:B]_[3:0]N Core High-Z High-Z Defined Off Off DDP[D:B]_AUXP, DDP[D:B]_AUXN Core High-Z High-Z Defined Off Off SDVO_CTRLCLK, SDVO_CTRLDATA Core Low High-Z Defined Off Off DDPC_CTRLCLK, DDPC_CTRLDATA Core High-Z High-Z Defined Off Off DDPD_CTRLCLK, DDPD_CTRLDATA Core High-Z High-Z Defined Off Off Table 3-2. Power Plane and States for Output and I/O Signals for Desktop Configurations (Sheet 5 of 5) Signal Name Power Plane During Reset2 Immediately after Reset2 S0/S1 S3 S4/S5
106 Datasheet
- Native functionality multiplexed with these GPIOs are not used in Desktop Configurations. During reset an Internal pull-down will drive this pin low. The pull down will be disabled after PCIRST# de-assertion. 11. Native/GPIO functionality controlled using soft straps. Default to Native functionality until soft straps are loaded. 12. State of the pins depend on the source of VccME3_3 power. 13. Pin is tri-stated prior to MEPWROK assertion during Reset. 14. GPIO13 is powered by VccSus HDA (either 3.3 V or 1.5 V). Pin tolerance is determined by VccSusHDA voltage. Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet 1 of 5) Signal Name Power Plane During Reset2 Immediately after Reset2 C-x states S0/S1 S3 S4/S5 PCI Express* PET[8:1]p, PET[8:1]n Core High High 5 Defined Defined Off Off DMI DMI[3:0]TXP, DMI[3:0]TXN Core High High Defined Defined Off Off PCI Bus AD[31:0] Core Low Undefined Defined Defined Off Off C/BE[3:0]# Core Low Undefined Defined Defined Off Off CLKRUN#18 (Mobile Only) / GPIO32 Core Low Low Defined Defined Off Off GNT0#8 GNT[3:1]#8/ GPIO[55,53,51] Core High High High High Off Off DEVSEL# Core High-Z High-Z High-Z High-Z Off Off FRAME# Core High-Z High-Z High-Z High-Z Off Off IRDY#, TRDY# Core High-Z High-Z High-Z High-Z Off Off PAR Core Low Undefined Defined Defined Off Off PCIRST# Suspend Low High High High Low Low PERR# Core High-Z High-Z High-Z High-Z Off Off PLOCK# Core High-Z High-Z High-Z High-Z Off Off STOP# Core High-Z High-Z High-Z High-Z Off Off
LAD[3:0] / FWH[3:0] Core High High High High Off Off LFRAME# / FWH[4] Core High High High High Off Off INIT3_3V#8 Core High High High High Off Off SATA Interface SATA[5:0]TXP, SATA[5:0]TXN Core High-Z High-Z Defined Defined Off Off SATALED# Core High-Z High-Z Defined Defined Off Off SATAICOMPO Core High-Z High -Z Defined Defined Off Off SCLOCK/GPIO22 Core High-Z (Input) High-Z (Input) Defined Defined Off Off SLOAD/GPIO38 Core High-Z (Input) High-Z (Input) Defined Defined Off Off SDATAOUT[1:0]/ GPIO[48,39] Core High-Z (Input) High-Z (Input) Defined Defined Off Off Interrupts PIRQ[A:D]# Core High-Z High-Z Defined Defined Off Off PIRQ[H:E]# / GPIO[5:2] Core High-Z (Input) High-Z (Input) Defined Defined Off Off SERIRQ Core High-Z High-Z Running High-Z Off Off USB Interface USB[13:0][P,N] Suspend Low Low Defined Defined Defined Defined USBRBIAS Suspend High-Z High-Z Defined Defined Defined Defined Power Management PLTRST# Suspend Low High High High Low Low SLP_M#6 Suspend Low High High High Defined Defined SLP_S3# Suspend Low High High High Low Low SLP_S4# Suspend Low High High High High Defined SLP_S5#/GPIO63 Suspend Low High High High High Low 3 SUS_STAT#/GPIO61 Suspend Low High High High Low Low SUSCLK Suspend Low Running SUS_PWR_DN_ACK/ GPIO30 Suspend High-Z (Input) High-Z (Input) Defined Defined Defined Defined DRAMPWROK Suspend Low High-Z High-Z High-Z High-Z Low LAN_PHY_PWR_CTR L10/GPIO12 Suspend Low Low Defined Defined Defined Defined PMSYNCH Core Low Low Defined/ Low Defined Off Off STP_PCI#/GPIO34 Core High-Z (Input) High-Z (Input) Defined Defined Off Off SLP_LAN#15/ GPIO29 Suspend Low Defined 15 High High Defined Defined Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet 2 of 5) Signal Name Power Plane During Reset2 Immediately after Reset2 C-x states S0/S1 S3 S4/S5
108 Datasheet
PROCPWRGD1 Core Low High High High Off Off SMBus Interface SMBCLK, SMBDATA Suspend High-Z High -Z Defined Defined Defined Defined System Management Interface SML0ALERT#/ GPIO60 Suspend High-Z High-Z Defined Defined Defined Defined SML0DATA Suspend High-Z High-Z Defined Defined Defined Defined SML0CLK Suspend High-Z High-Z De fined Defined Defined Defined GPIO58/SML1CLK Suspend High-Z High-Z Defined Defined Defined Defined SML1ALERT#/ GPIO74 Suspend High-Z High-Z Defined Defined Defined Defined SML1DATA/GPIO75 Suspend High-Z High -Z Defined Defined Defined Defined JTAG_TDO Suspend High-Z High-Z High-Z High-Z High-Z High-Z Miscellaneous Signals SPKR8 Core Low Low Defined Defined Off Off Clocking Signals CLKOUT_BCLK0_P / CLKOUT_PCIEB_P, CLKOUT_BCLK0_N / CLKOUT_PCIEB_N Core Running Running Running Running Off Off CLKOUT_DP_P / CLKOUT_BCLK1_P, CLKOUT_DP_N / CLKOUT_BCLK1_N, Core Running Running Running Running Off Off CLKOUT_DMI_P, CLKOUT_DMI_N Core Running Running Running Running Off Off XTAL25_OUT Core High-Z High-Z High-Z High-Z Off Off XCLK_RCOMP Core High-Z High-Z High-Z High-Z Off Off CLKOUT_PEG_A_P, CLKOUT_PEG_A_N Core Running Running Running Running Off Off CLKOUT_PEG_B_P, CLKOUT_PEG_B_N Core Running Running Running Running Off Off CLKOUT_PCIE[7:0] CLKOUT_PCIE[7:0] N Core Running Running Running Running Off Off CLKOUT_PCI[4:0] Core Running Running Running Running Off Off CLKOUTFLEX[3:0]/ GPIO[67:64] Core Low Low Running/ Low Running Off Off Intel® High Definition Audio Interface HDA_RST# HDA Suspend Low Low 4 High Defined Low Low Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet 3 of 5) Signal Name Power Plane During Reset2 Immediately after Reset2 C-x states S0/S1 S3 S4/S5
HDA_SDO8 HDA Suspend Low Low Low Low Low Low HDA_SYNC8 HDA Suspend Low Low Low Low Low Low HDA_BCLK HDA Suspend Low Low Low Low Low Low HDA_DOCK_EN#/ GPIO33 Core High High 12 Defined Defined Off Off HDA_DOCK_RST#/ GPIO1319 HDA Suspend Low11 High-Z11 Defined Defined Defined Defined UnMultiplexed GPIO Signals GPIO88 Suspend High High Defined Defined Defined Defined GPIO158 Suspend Low Low Defined Defined Defined Defined GPIO24 Suspend Low Low Defined Defined Defined Defined GPIO278 Suspend High Low Defined Defined Defined Defined GPIO28 Suspend High-Z High-Z Defined Defined Defined Defined GPIO35 Core Low Low Defined Defined Off Off GPIO57 Suspend High-Z (Input) High-Z (Input) Defined Defined Defined Defined Multiplexed GPIO Signals used as GPIO only GPIO0 Core High-Z (Input) High-Z (Input) Defined Defined Off Off GPIO[7,6,1,17]
9 Core High-Z High-Z Defined Defined Off Off
SPI_CS0# ME33IO High 17 High Defined Defined Defined Defined SPI_CS1# ME33IO High 17 High Defined Defined Defined Defined SPI_MOSI8 ME33IO Low 17 Low Defined Defined Defined Defined SPI_CLK ME33IO Low 17 Low Running Running Defined Defined Intel® Quiet System Technology and Thermal Reporting PECI CPU Low Low Defined Defined Off Off Controller Link CL_CLK16 Suspend High/Low 14 High/Low14 Defined Defined Defined Defined CL_DATA16 Suspend High/Low 14 High/Low14 Defined Defined Defined Defined CL_RST1#6 Suspend Low High High High High High LVDS Signals LVDSA_DATA[3:0], LVDSA_DATA#[3:0] Core High-Z High-Z Defined/ High-Z13 Defined/ High-Z13 Off Off LVDSA_CLK, LVDSA_CLK# Core High-Z High-Z Defined/ High-Z13 Defined/ High-Z13 Off Off LVDSB_DATA[3:0], LVDSB_DATA#[3:0] Core High-Z High-Z Defined/ High-Z13 Defined/ High-Z13 Off Off Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet 4 of 5) Signal Name Power Plane During Reset2 Immediately after Reset2 C-x states S0/S1 S3 S4/S5
110 Datasheet
LVDSB_CLK, LVDSB_CLK# Core High-Z High-Z Defined/ High-Z13 Defined/ High-Z13 Off Off L_DDC_CLK Core High-Z High-Z High-Z High-Z Off Off L_DDC_DATA Core Low High-Z High-Z High-Z Off Off L_VDD_EN Core High-Z High-Z High/ High-Z13 High/ High-Z13 Off Off L_BKLTEN Core High-Z High-Z High/ High-Z13 High/ High-Z13 Off Off L_BKLTCTL Core High-Z High-Z High/ High-Z13 High/ High-Z13 Off Off L_CTRL_CLK Core High-Z High-Z High-Z High-Z Off Off L_CTRL_DATA Core High-Z High-Z High-Z High-Z Off Off LVD_VBG, LVD_VREFH, LVD_VREFL Core High-Z High-Z High-Z High-Z Off Off Analog Display / CRT DAC Signals CRT_RED, CRT_GREEN, CRT_BLUE Core High-Z High-Z Defined Defined Off Off DAC_IREF Core High-Z High-Z High-Z High-Z Off Off CRT_HSYNC Core Low Low Low Low Off Off CRT_VSYNC Core Low Low Low Low Off Off CRT_DDC_CLK Core High-Z High-Z High-Z High-Z Off Off CRT_DDC_DATA Core High-Z High-Z High-Z High-Z Off Off CRT_IRTN Core High-Z High-Z High-Z High-Z Off Off Intel® Flexible Display Interface FDI_RXP[7:0], FDI_RXN[7:0] Core High-Z High-Z Defined Defined Off Off FDI_FSYNC[1:0] Core High-Z Hi gh-Z Defined Defined Off Off FDI_LSYNC[1:0] Core High-Z Hi gh-Z Defined Defined Off Off FDI_INT Core High-Z High-Z Defined Defined Off Off Digital Display Interface DDP[D:B]_[3:0]P, DDP[D:B]_[3:0]N, Core High-Z High-Z Defined Defined Off Off DDP[D:B]_AUXP, DDP[D:B]_AUXN Core High-Z High-Z Defined Defined Off Off SDVO_CTRLCLK, SDVO_CTRLDATA Core Low High-Z Defined Defined Off Off DDPC_CTRLCLK, DDPC_CTRLDATA Core High-Z High-Z Defined Defined High-Z Off DDPD_CTRLCLK, DDPD_CTRLDATA Core High-Z High-Z Defined Defined High-Z Off Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations (Sheet 5 of 5) Signal Name Power Plane During Reset2 Immediately after Reset2 C-x states S0/S1 S3 S4/S5
NOTES: 1. PCH drives PROCPWRGD after PWROK and SYS_PW ROK signals are active, and thus will be driven low by PCH when either of these signals are inactive. During boot, or during a hard reset with power cycling, PROCPWRGD will be expected to transition from low to High-Z 2. The states of Core and proc essor signals are evaluated at the times during PLTRST# and Immediately after PLTRST#. The states of the LAN and GLAN signals are evaluated at the times During LAN_RST# and Immediately after LAN_RST#. The states of the Controller Link signals are taken at the times During CL_RST1# and Immediately after CL_RST1#. The states of the Suspend signals are evaluated at the times During RSMRST# and Immediately after RSMRST#, with an exception to GPIO signals; see Section 2.25 for more details on GPIO state after reset. The states of the HDA signals are evaluated at the times During HDA_RST# and Immediately after HDA_RST#. 3. SLP_S5# signals will be high in the S4 state. 4. Low until Intel ® High Definition Audio Controller Reset bit set (D27:F0:Offset HDBAR+08h:bit 0), at which time HDA_RST# will be High and HDA_BIT_CLK will be Running. 5. PETp/n[8:1] high until port is enabled by software. 6. The SLP_M# state will be determined by Intel ® Management Engine Firmware. 7. The state of signals in S3–S 5 will be defined by Intel® AMT Policies. 8. This signal is sampled as a fu nctional strap during Reset. See Functional straps definition table for usage. 9. Native functionality multiplexed with these GPIOs is not used in Mobile Configurations. 10. Native/GPIO functional ity controlled using soft straps. Default to Native functionality until soft straps are loaded. 11. This pin will be driv en to a High when Dock Attach bit is set (Docking Control Register D27:F0 offset 4Ch). During reset an Internal pull-down will drive this pin low. The pull down will be disabled after PCIRST# de-assertion. 12. This pin will be driv en to a Low when Dock Attach bit is set (Docking Control Register D27:F0 offset 4Ch). 13. PCH tristates these signals when LVDS port is disabled. 14. Controller Link Clock and Data buffers use internal pull-up and pull-down resistors to drive a logical 1 or a 0. 15. SLP_LAN# behavior after reset is dependen t on value of SLP_LAN# default value bit. 16. State of the pins depend on the source of VccME3_3 power. 17. Pin is tri-stated prior to MEPWROK assertion during Reset. 18. CLKRUN# is driven to a logic 1 during reset for Mobile configurations (default is native function) to ensure that PCI clocks can toggle before devices come out of reset. For desktop configurations this pin defaults to GPIO mode strongly driving a logic 1. 19. HDA_DOCK_RST#/GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Pin tolerance is determined by VccSusHDA voltage.
112 Datasheet
3.3 Power Planes for Input Signals
Table 3-4 and Table 3-5 show the power plane associated with each input signal, as well as what device drives the signal at various times. Valid states include:
- H i g h
- L o w
- Static: Will be high or low, but will not change
- Driven: Will be high or low, and is allowed to change
- Running: For input clocks The PCH suspend well signal states are indeterminate and undefined and may glitch prior to RSMRST# de-assertion. This does not apply to LAN_RST#, SLP_S3#, SLP_S4#, S4_STATE# and SLP_S5#. These signals are determinate and defined prior to RSMRST# de-assertion. The PCH core well signal states are indeterminate and undefined and may glitch prior to PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals are determinate and defined prior to PWROK assertion. Table 3-4. Power Plane for Input Signals fo r Desktop Configurations (Sheet 1 of 3) Signal Name Power Well Driver During Reset S0/S1 S3 S4/S5 DMI DMI_CLKP, DMI_CLKN Core Clock Generator Running Off Off DMI[3:0]RXP, DMI[3:0]RXN Core Processor Driven Off Off PCI Express* PER[8:1]p, PERn[8:1]n Core PCI Express* Device Driven Off Off PCI Bus REQ0#, REQ1# / GPIO501 REQ2# / GPIO521 REQ3# / GPIO541 Core External Pull-up Driven Off Off PME# Suspend Internal Pull-up Driven Driven Driven SERR# Core PCI Bus Peripherals High Off Off LPC Interface LDRQ0# Core LPC Devices High Off Off LDRQ1# / GPIO231 Core LPC Devices High Off Off SATA Interface SATA[5:0]RXP, SATA[5:0]RXN Core SATA Drive Driven Off Off SATAICOMPI Core High-Z High-Z Defined Off SATA[5:4]GP/TEMP_ALERT/ GPIO[49,16]1 Core External Device or External Pull-up/Pull-down Driven Off Off SATA[3:0]GP / GPIO[37, 36, 19, 21]1 Core External Device or External Pull-up/Pull-down Driven Off Off
OC[7:0]#/ GPIO[14,10,9,43:40,59]1 Suspend External Pull-ups Driven Driven Driven USBRBIAS# Suspend External Pull-down Driven Driven Driven Power Management MEPWROK Suspend External Circuit High Driven Driven LAN_RST# Suspend External Circuit High Static Static PWRBTN# Suspend Internal Pull-up Driven Driven Driven PWROK RTC System Power Supply Driven Driven Driven RI# Suspend Serial Port Buffer Driven Driven Driven RSMRST# RTC External RC Circuit High High High SYS_RESET# Core External Circuit Driven Off Off SYS_PWROK Suspend External Circuit High Driven Driven THRMTRIP# CPU External Thermal Sensor Driven Off Off WAKE# Suspend External Pull-up Driven Driven Driven Processor Interface A20GATE Core External Micro controller Static Off Off RCIN# Core External Micro controller High Off Off System Management Interface SMBALERT# / GPIO11 Suspend External Pull-up Driven Driven Driven INTRUDER# RTC External Switch Driven High High JTAG Interface JTAG_TDI Suspend Internal Pull-up 4 High High High JTAG_TMS Suspend Internal Pull-up 4 High High High JTAG_TCK Suspend Internal Pull-down 5 Low Low Low Miscellaneous Signals INTVRMEN2 RTC External Pull-up High High High RTCRST# RTC External RC Circuit High High High SRTCRST# RTC External RC Circuit High High High Digital Display Interface DDP[B:C:D]_HPD Core External Pull-down Driven Off Off SDVO_INTP, SDVO_INTN Core SDVO controller device Driven Off Off SDVO_TVCLKINP, SDVO_TVCLKINN Core SDVO controller device Driven Off Off Table 3-4. Power Plane for Input Signals fo r Desktop Configurations (Sheet 2 of 3) Signal Name Power Well Driver During Reset S0/S1 S3 S4/S5
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NOTES: 1. These signals can be configured as outputs in GPIO mode. 2. This signal is sampled as a f unctional strap during Reset. See Functional straps definition table for usage. 3. State of the pins depend on the source of VccME3_3 power. 4. Internal pull-ups are implemented. 5. Internal pull-down is implemented. SDVO_STALLP, SDVO_STALLN Core SDVO controller device Driven Off Off Intel® Flexible Display Interface FDI_RXP[7:0], FDI_RXN[7:0] Core Processor Driven Off Off Clock Interface CLKIN_DMI_P, CLKIN_DMI_N Core C lock Generator Running Running Off CLKIN_SATA_N/CKSSCD_N, CLKIN_SATA_P/CKSSCD_P Core Clock Generator Running Running Off CLKIN_BCLK_P, CLKIN_BCLK_N Core Clock Generator Running Running Off CLKIN_DOT_96P, CLKIN_DOT_96N Core Clock Generator Running Running Off CLKIN_PCILOOPBACK Core Clock Generator Running Running Off PCIECLKRQ[7:3]#/ GPIO[46:44,26:25]1,PCIECL KRQ0#/GPIO731 Suspend External Pull-up Driven Driven Driven PCIECLKRQ[2:1]#/ GPIO[20:18]1 Core External Pull-up Driven Driven Off PEG_A_CLKRQ#/GPIO471, PEG_B_CLKRQ#/GPIO561 Suspend External Pull-up Driven Driven Driven REFCLK14IN Core Clock Generator Running Running Off XTAL25_IN Core Clock Generator High-Z High-Z High-Z Intel® High Definition Audio Interface HDA_SDIN[3:0] Suspend Internal Pull-down Low Low Low SPI Interface SPI_MISO ME33IO External Pull-up Driven Driven Driven Intel® Quiet System Technology TACH[3:0]/GPIO[7,6,1,17]1 Core External Pull-up Driven Off Off Table 3-4. Power Plane for Input Signals fo r Desktop Configurations (Sheet 3 of 3) Signal Name Power Well Driver During Reset S0/S1 S3 S4/S5
Table 3-5. Power Plane for Input Signals fo r Mobile Configurations (Sheet 1 of 3) Signal Name Power Well Driver During Reset C-x states S0/S1 S3 S4/S5 DMI DMI_CLKP, DMI_CLKN Core Clock Generator Running Running Off Off DMI[3:0]RXP, DMI[3:0]RXN Core Processor Driven Driven Off Off PCI Express* PER[6:1]p, PER[6:1]n Core PCI Express* Device Driven Driven Off Off PCI Bus REQ0#, REQ1# / GPIO501 REQ2# / GPIO521 REQ3# / GPIO541 Core External Pull-up Driven Driven Off Off PME# Suspend Internal Pull-up Driven Driven Driven Driven SERR# Core PCI Bus Peripherals Driven High Off Off LPC Interface LDRQ0# Core Internal Pull-up Driven High Off Off LDRQ1# / GPIO231 Core Internal Pull-up Driven High Off Off SATA Interface SATA[5:0]RXP, SATA[5:0]RXN Core SATA Drive Driven Driven Off Off SATAICOMPI Core High-Z High-Z Defined Off Off SATA[5:4]GP/ TEMP_ALERT/ GPIO[49,16]1 Core External Device or External Pull-up/Pull-down Driven Driven Off Off SATA[3:0]GP / GPIO[37, 36, 19, 21]1 Core External Device or External Pull-up/Pull-down Driven Driven Off Off USB Interface OC[7:0]#/ 59] Suspend External Pull-ups Driven Driven Driven Driven USBRBIAS# Suspend External Pull-down Driven Driven Driven Driven Power Management ACPRESENT (Mobile Only) /GPIO311 Suspend External Microcontroller Driven Driven Driven Driven BATLOW# (Mobile Only) /GPIO721 Suspend External Pull-up High High Driven Driven MEPWROK Suspend External Circuit Driven Driven Driven Driven LAN_RST# Suspend External Circuit High High High High PWRBTN# Suspend Internal Pull-up Driven Driven Driven Driven PWROK RTC System Power Supply Driven Driven Off Off RI# Suspend Serial Port Buffer Driven Driven Driven Driven
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RSMRST# RTC External RC Circuit High High High High SYS_RESET# Core External Circuit Driven Driven Off Off THRMTRIP# CPU Thermal Sensor Driven Driven Off Off WAKE# Suspend External Pull-up Driven Driven Driven Driven Processor Interface A20GATE Core External Microcontroller Static Static Off Off RCIN# Core External Microcontroller High High Off Off System Management Interface SMBALERT# / GPIO11 Suspend External Pull-up Driven Driven Driven Driven INTRUDER# RTC External Sw itch Driven Driven High High JTAG Interface JTAG_TDI Suspend Internal Pull-up 4 High High High High JTAG_TMS Suspend Internal Pull-up 4 High High High High JTAG_TCK Suspend Internal Pull-down 5 Low Low Low Low Miscellaneous Signals INTVRMEN2 RTC External Pull-up High High High High RTCRST# RTC External RC Circuit High High High High SRTCRST# RTC External RC Circuit High High High High Intel® High Definition Audio Interface HDA_SDIN[3:0] Suspend Intel® High Definition Audio Codec Driven Low Low Low SPI Interface SPI_MISO ME33IO Internal Pull-up Driven Driven Driven Driven Clock Interface CLKIN_DMI_P, CLKIN_DMI_N Core Clock Generator Running Running Off Off CLKIN_SATA_N/ CKSSCD_N, CLKIN_SATA_P/ CKSSCD_P Core Clock Generator Running Running Off Off CLKIN_BCLK_P, CLKIN_BCLK_N Core Clock Generator Running Running Off Off CLKIN_DOT_96P, CLKIN_DOT_96N Core Clock Generator Running Running Off Off CLKIN_PCILOOPBACK Core Clock Generator Running Running Off Off PCIECLKRQ[7:3]#/ PCIECLKRQ0#/ GPIO731 Suspend External Pull-up Driven Driven Driven Driven Table 3-5. Power Plane for Input Signals fo r Mobile Configurations (Sheet 2 of 3) Signal Name Power Well Driver During Reset C-x states S0/S1 S3 S4/S5
NOTES: 1. These signals can be configured as outputs in GPIO mode. 2. This signal is sampled as a fu nctional strap during Reset. See Functional straps definition table for usage. 3. State of the pins depend on the source of VccME3_3 power. 4. Internal pull-ups are implemented . 5. Internal pull-down is implemented only. § § PCIECLKRQ[2:1]#/ GPIO[20:18]1 Core External Pull-up Driven Driven Off Off PEG_A_CLKRQ#/ GPIO471, PEG_B_CLKRQ#/ GPIO561 Suspend External Pull-up Driven Driven Driven Driven XTAL25_IN Core Clock Generator High-Z High-Z Off Off REFCLK14IN Core Clock Generator High-Z High-Z Off Off CLKIN_PCILOOPBACK Core Clock Generator High-Z High-Z Off Off Intel® Flexible Display Interface FDI_RXP[7:0], FDI_RXN[7:0] Core Processor Driven Driven Off Off Digital Display Interface DDP[B:C:D]_HPD Core External Pull-down Driven Driven Off Off SDVO_INTP, SDVO_INTN Core SDVO controller device Driven Driven Off Off SDVO_TVCLKINP, SDVO_TVCLKINN Core SDVO controller device Driven Driven Off Off SDVO_STALLP, SDVO_STALLN Core SDVO controller device Driven Driven Off Off Table 3-5. Power Plane for Input Signals fo r Mobile Configurations (Sheet 3 of 3) Signal Name Power Well Driver During Reset C-x states S0/S1 S3 S4/S5
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Table 4-1 shows the system clock input to the PCH. Table 4-2 shows system clock domains generated by the PCH in buffered mode. Figure 4-1 shows the assumed connection of the Main Clock Generator to the PCH in buffer mode to the various system components. For complete details of the system clocking solution, see the system’s clock generator component specification, Clock Signals section and the PCH Clocks. Table 4-1. PCH System Clock Inputs Clock Domain Frequency Usage CLKIN_SATA_P / CKSSCD_P, CLKIN_SATA_N / CKSSCD_N
100 MHz 100 MHz differential reference clock from a clock chip for
use only as a 100 MHz source for SATA clock. CLKIN_DMI_P, CLKIN_DMI_N 100 MHz
100 MHz differential reference clock from a clock chip used
for DMI. NOTE: This input clock is required to be PCIe 2.0 jitter spec compliant from a clock chip, for PCIe 2.0 discrete Graphics platforms. CLKIN_PCILOOPB ACK 33 MHz
33 MHz clock feedback input to reduce skew between PCH
PCI clock and clock observed by connected PCI devices. This signal must be connected to one of the pins in the group CLKOUT_PCI[4:0] REFCLK14IN 14.31818 MHz Single-ended 14.31818 MHz reference clock driven by a clock chip. Used for ACPI timer and Multimedia Timers. Expected to be shut off during S3. CLKIN_DOT96P, CLKIN_DOT96N 96 MHz 96 MHz differential reference clock from a clock chip. Used to generate the 48-MHz USB/SIO clocks and 24 MHz HDA bit clock. CLKIN_BCLK_P, CLKIN_BCLK_N 133 MHZ 133 MHz differential reference clock from a clock chip in Buffer-Through Mode.
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Table 4-2. PCH System Clock Outputs Clock Domain Fr equency Usage CLKOUT_PCI[4:0] 33 MHz Single Ended 33.3MHz outputs to PCI connectors/ devices. One of these signals must be connected to CLKIN_PCILOOPBACK to function as a PCI clock loopback. This allows skew control for variable lengths of CLKOUT_PCI[4:0]. PCI Bus, LPC I/F. These only go to external PCI and LPC devices. CLKOUT_PCIE[7:0]P, CLKOUT_PCIE[7:0]N 100 MHz 100 MHz PCIe* Gen1.1 specification differential output to PCI Express* devices CLKOUT_PEG_A_P, CLKOUT_PEG_A_N, CLKOUT_PEG_B_P, CLKOUT_PEG_B_N,
100 MHz 100 MHz PCIe* Gen2 specification differential output to
PCI Express* Graphics devices CLKOUTFLEX0 / GPIO64, CLKOUTFLEX1 / GPIO65, CLKOUTFLEX2 / GPIO66
33 MHz or
14.31818 MHz 33 MHz or 14.31818 MHz output CLKOUTFLEX3 / GPIO67
48 MHz, 33
MHz, or 14.31818 MHz 48 MHz, 33 MHz, 14.31818 MHz output SPI_CLK 17.86 MHz/
31.25 MHz
Drive SPI devices connected to the PCH. Generated by the PCH. CLKOUT_BCLK0_P / CLKOUT_PCIE8_P, CLKOUT_BCLK0_N / CLKOUT_PCIE8_N
133 MHz Or
100 MHz
PCIe* Gen 1.1 specification differential output to PCI Express* devices CLKOUT_DP_P / CLKOUT_BCLK1_P, CLKOUT_DP_N / CLKOUT_BCLK1_N
120 MHz or
133 MHz
120 MHz Differential output for DisplayPort reference or
§ § Figure 4-1. PCH High-Level Clock Diagram
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5 Functional Description
This chapter describes the functions and interfaces of the Intel® 5 Series Chipset and Intel® 3400 Series Chipset.
5.1 DMI-to-PCI Bridge (D30:F0)
The DMI-to-PCI bridge resides in PCI Device 30, Function 0 on bus 0. This portion of the PCH implements the buffering and control logic between PCI and Direct Media Interface (DMI). The arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must decode the ranges for the DMI. All register contents are lost when core well power is removed. Direct Media Interface (DMI) is the chip-to-chip connection between the Processor and the PCH. This high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is completely software transparent permitting current and legacy software to operate normally. To provide for true isochronous transfers and configurable Quality of Service (QoS) transactions, the PCH supports two virtual channels on DMI—VC0 and VC1. These two channels provide a fixed arbitration scheme where VC1 is always the highest priority. VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be specifically enabled and configured at both ends of the DMI link (that is, the PCH and processor). Configuration registers for DMI, virtual channel support, and DMI active state power management (ASPM) are in the RCRB space in the Chipset Config Registers (Chapter 10.1.1). DMI is also capable of operating in an Enterprise Southbridge Interface (ESI) compatible mode. ESI is a chip-to-chip connection for server chipsets. In this ESI- compatible mode, the DMI signals require AC coupling. A hardware strap is used to configure DMI in ESI-compatible mode see Section 2.28 for details.
5.1.1 PCI Bus Interface
The PCH PCI interface supports PCI Local Bus Specification, Revision 2.3, at 33 MHz. The PCH integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internal PCH requests.
5.1.2 PCI Bridge As an Initiator
The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge generates the following cycle types: Table 5-1. PCI Bridge Initiator Cycle Types Command C/BE# Notes I/O Read/Write 2h/3h Non-posted Memory Read/Write 6h/7h Writes are posted Configuration Read/Write Ah/Bh Non-posted Special Cycles 1h Posted
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5.1.2.1 Memory Reads and Writes
The bridge bursts memory writes on PCI that are received as a single packet from DMI.
5.1.2.2 I/O Reads and Writes
The bridge generates single DW I/O read and write cycles. When the cycle completes on the PCI bus, the bridge generates a corresponding completion on DMI. If the cycle is retried, the cycle is kept in the down bound queue and may be passed by a postable cycle.
5.1.2.3 Configuration Reads and Writes
The bridge generates single DW configuration read and write cycles. When the cycle completes on the PCI bus, the bridge generates a corresponding completion. If the cycle is retried, the cycle is kept in the down bound queue and may be passed by a postable cycle.
5.1.2.4 Locked Cycles
The bridge propagates locks from DMI per the PCI Local Bus Specification. The PCI bridge implements bus lock, which means the arbiter will not grant to any agent except DMI while locked. If a locked read results in a target or master abort, the lock is not established (as per the PCI Local Bus Specification). Agents north of the PCH must not forward a subsequent locked read to the bridge if they see the first one finish with a failed completion.
5.1.2.5 Target / Master Aborts
When a cycle initiated by the bridge is master/target aborted, the bridge will not re- attempt the same cycle. For multiple DW cycles, the bridge increments the address and attempts the next DW of the transaction. For all non-postable cycles, a target abort response packet is returned for each DW that was master or target aborted on PCI. The bridge drops posted writes that abort.
5.1.2.6 Secondary Master Latency Timer
The bridge implements a Master Latency Timer using the SMLT register which, upon expiration, causes the de-assertion of FRAME# at the next legal clock edge when there is another active request to use the PCI bus.
5.1.2.7 Dual Address Cycle (DAC)
The bridge will issue full 64-bit dual address cycles for device memory-mapped registers above 4 GB.
5.1.2.8 Memory and I/O Decode to PCI
The PCI bridge in the PCH is a subtractive decode agent, which follows the following rules when forwarding a cycle from DMI to the PCI interface:
- The PCI bridge will positively decode any memory/IO address within its window registers, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set for memory windows and PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set for I/O windows.
- The PCI bridge will subtractively decode any 64-bit memory address not claimed by another agent, assuming PCICMD.MSE (D30:F0:Offset 04h:bit 1) is set.
- The PCI bridge will subtractively decode any 16-bit I/O address not claimed by another agent assuming PCICMD.IOSE (D30:F0:Offset 04h:bit 0) is set.
- If BCTRL.IE (D30:F0:Offset 3Eh:bit 2) is set, the PCI bridge will not positively forward from primary to secondary called out ranges in the I/O window per PCI Local Bus Specification (I/O transactions addressing the last 768 bytes in each, 1 KB block: offsets 100h to 3FFh). The PCI bridge will still take them subtractively assuming the above rules.
- If BCTRL.VGAE (D30:F0:Offset 3Eh:bit 3) is set, the PCI bridge will positively forward from primary to secondary I/O and memory ranges as called out in the PCI Bridge Specification, assuming the above rules are met.
5.1.3 Parity Error Detection and Generation
PCI parity errors can be detected and reported. The following behavioral rules apply:
- When a parity error is detected on PCI, the bridge sets the SECSTS.DPE (D30:F0:Offset 1Eh:bit 15).
- If the bridge is a master and BCTRL.PERE (D30:F0:Offset 3Eh:bit 0) is set and one of the parity errors defined below is detected on PCI, then the bridge will set SECSTS.DPD (D30:F0:Offset 1Eh:bit 8) and will also generate an internal SERR#. — During a write cycle, the PERR# signal is active, or — A data parity error is detected while performing a read cycle
- If an address or command parity error is detected on PCI and PCICMD.SEE (D30:F0:Offset 04h:bit 8), BCTRL.PERE, and BCTRL.SEE (D30:F0:Offset 3Eh:bit 1) are all set, the bridge will set PSTS.SSE (D30:F0:Offset 06h:bit 14) and generate an internal SERR#.
- If the PSTS.SSE is set because of an ad dress parity error and the PCICMD.SEE is set, the bridge will generate an internal SERR#.
- When bad parity is detected from DMI, bad parity will be driven on all data from the bridge.
- When an address parity error is detected on PCI, the PCI bridge will never claim the cycle. This is a slight deviation from the PCI bridge spec, which says that a cycle should be claimed if BCTRL.PERE is not set. However, DMI does not have a concept of address parity error, so claiming the cycle could result in the rest of the system seeing a bad transaction as a good transaction.
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5.1.4 PCIRST#
The PCIRST# pin is generated under two conditions:
- P L T R S T # a c t i v e
- BCTRL.SBR (D30:F0:Offset 3Eh:bit 6) set to 1 The PCIRST# pin is in the suspend well. PCIRST# should be tied to PCI bus agents, but not other agents in the system.
5.1.5 Peer Cycles
The PCI bridge may be the initiator of peer cycles. Peer cycles include memory, I/O, and configuration cycle types. Peer cycles are only allowed through VC0, and are enabled with the following bits:
- BPC.PDE (D30:F0:Offset 4Ch:bit 2) – Memory and I/O cycles
- BPC.CDE (D30:F0:Offset 4Ch:bit 1) – Configuration cycles When enabled for peer for one of the above cycle types, the PCI bridge will perform a peer decode to see if a peer agent can receive the cycle. When not enabled, memory cycles (posted and/or non-posted) are sent to DMI, and I/O and/or configuration cycles are not claimed. Configuration cycles have special considerations. Under the PCI Local Bus Specification, these cycles are not allowed to be forwarded upstream through a bridge. However, to enable things such as manageability, BPC.CDE can be set. When set, type 1 cycles are allowed into the part. The address format of the type 1 cycle is slightly different from a standard PCI configuration cycle to allow addressing of extended PCI space. The format is shown in Table 5-2. Note: The PCH USB controllers cannot perform peer-to-peer traffic. Table 5-2. Type 1 Address Format Bits Definition 31:27 Reserved (same as the PCI Local Bus Specification) 26:24 Extended Configuration Address – allows addressing of up to 4K. These bits are combined with bits 7:2 to get the full register. 23:16 Bus Number (same as the PCI Local Bus Specification) 15:11 Device Number (same as the PCI Local Bus Specification) 10:8 Function Number (same as the PCI Local Bus Specification) 7:2 Register (same as the PCI Local Bus Specification) 0 Must be 1 to indicate a type 1 cy cle. Type 0 cycles are not decoded.
5.1.6 PCI-to-PCI Bridge Model
From a software perspective, the PCH contains a PCI-to-PCI bridge. This bridge connects DMI to the PCI bus. By using the PCI-to-PCI bridge software model, the PCH can have its decode ranges programmed by existing plug-and-play software such that PCI ranges do not conflict with graphics aperture ranges in the Host controller.
5.1.7 IDSEL to Device Number Mapping
When addressing devices on the external PCI bus (with the PCI slots), the PCH asserts one address signal as an IDSEL. When accessing device 0, the PCH asserts AD16. When accessing Device 1, the PCH asserts AD17. This mapping continues all the way up to device 15 where the PCH asserts AD31. Note that the PCH internal functions (Intel® High Definition Audio, USB, SATA and PCI Bridge) are enumerated like they are off of a separate PCI bus (DMI) from the external PCI bus.
5.1.8 Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI Local Bus Specification, Revision 2.3 defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported by a mapping mechanism implemented within the PCH. The PCI Local Bus Specification, Revision 2.3 defines two mechanisms to access configuration space, Mechanism 1 and Mechanism 2. The PCH only supports Mechanism 1. Warning: Configuration writes to internal devices, when the devices are disabled, are illegal and may cause undefined results.
5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5,
F6, F7) There are eight root ports available in the PCH. The root ports are compliant to the PCI Express 2.0 specification running at 2.5 GT/s. The ports all reside in device 28, and take function 0 – 7. Port 1 is function 0, port 2 is function 1, port 3 is function 2, port 4 is function 3, port 5 is function 4, port 6 is function 5, port 7 is function 6, and port 8 is function 7. Note: This section assumes the default PCI Express Function Number-to-Root Port mapping is used. Function numbers for a given root port are assignable through the “Root Port Function Number and Hide for PCI Express Root Ports” registers (RCBA+0404h). PCI Express Root Ports 1-4 and Ports 5-8 can independently be configured as four x1s, two x2s, one x2 and 2 x1s, or one x4 port widths. The port configuration is set by soft straps in the Flash Descriptor. Note: PCI Express port 7 and 8 are not available for the H55, HM55, and Intel 3400 chipsets. PCIe* ports are numbered from 1–8.
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5.2.1 Interrupt Generation
The root port generates interrupts on behalf of Hot-Plug and power management events, when enabled. These interrupts can either be pin based, or can be MSIs, when enabled. When an interrupt is generated using the legacy pin, the pin is internally routed to the PCH interrupt controllers. The pin that is driven is based upon the setting of the chipset configuration registers. Specifically, the chipset configuration registers used are the D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) registers. Table 5-3 summarizes interrupt behavior for MSI and wire-modes. In the table “bits” refers to the Hot-Plug and PME interrupt bits.
5.2.2 Power Management
5.2.2.1 S3/S4/S5 Support
Software initiates the transition to S3/S4/S5 by performing an IO write to the Power Management Control register in the PCH. After the IO write completion has been returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction Layer Packet) message on its downstream link. The device attached to the link will eventually respond with a PME_TO_Ack TLP message followed by sending a PM_Enter_L23 DLLP (Data Link Layer Packet) request to enter the L2/L3 Ready state. When all of the PCH root ports links are in the L2/L3 Ready state, the PCH power management control logic will proceed with the entry into S3/S4/S5. Prior to entering S3, software is required to put each device into D3 HOT. When a device is put into D3HOT, it will initiate entry into a L1 link state by sending a PM_Enter_L1 DLLP. Thus under normal operating conditions when the root ports sends the PME_Turn_Off message the link will be in state L1. However, when the root port is instructed to send the PME_Turn_Off message, it will send it whether or not the link was in L1. Endpoints attached to PCH can make no assumptions about the state of the link prior to receiving a PME_Turn_Off message. Table 5-3. MSI versus PCI IRQ Actions Interrupt Register Wire-Mode Action MSI Action All bits 0 Wire inactive No action One or more bits set to 1 Wire active Send message One or more bits set to 1, new bit gets set to 1 Wire active Send message One or more bits set to 1, software clears some (but not all) bits Wire active Send message One or more bits set to 1, software clears all bits Wire inactive No action Software clears one or more bits, and one or more bits are set on the same clock Wire active Send message
5.2.2.2 Resuming from Suspended State
The root port contains enough circuitry in the suspend well to detect a wake event through the WAKE# signal and to wake the system. When WAKE# is detected asserted, an internal signal is sent to the power management controller of the PCH to cause the system to wake up. This internal message is not logged in any register, nor is an interrupt/GPE generated due to it.
5.2.2.3 Device Initiated PM_PME Message
When the system has returned to a working state from a previous low power state, a device requesting service will send a PM_PME message continuously, until acknowledge by the root port. The root port will take different actions depending upon whether this is the first PM_PME has been received, or whether a previous message has been received but not yet serviced by the operating system. If this is the first message received (RSTS.PS - D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 60h:bit 16 is cleared), the root port will set RSTS.PS, and log the PME Requester ID into RSTS.RID (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 60h:bits 15:0). If an interrupt is enabled using RCTL.PIE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 5Ch:bit 3), an interrupt will be generated. This interrupt can be either a pin or an MSI if MSI is enabled using SMI/SCI generation. If this is a subsequent message received (RSTS.PS is already set), the root port will set RSTS.PP (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 60h:bit 17) and log the PME Requester ID from the message in a hidden register. No other action will be taken. When the first PME event is cleared by software clearing RSTS.PS, the root port will set RSTS.PS, clear RSTS.PP, and move the requester ID from the hidden register into RSTS.RID. If RCTL.PIE is set, an interrupt will be generated. If RCTL.PIE is not set, a message will be sent to the power management controller so that a GPE can be set. If messages have been logged (RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, and interrupt will be generated. This last condition handles the case where the message was received prior to the operating system re-enabling interrupts after resuming from a low power state.
5.2.2.4 SMI/SCI Generation
Interrupts for power management events are not supported on legacy operating systems. To support power management on non-PCI Express aware operating systems, PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set. When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/F3/F4/ F5/F6/F7:Offset DCh:bit 31) to be set. Additionally, BIOS workarounds for power management can be supported by setting MPC.PMME (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset D8h:bit 0). When this bit is set, power management events will set SMSCS.PMMS (D28:F0/F1/F2/F3/F4/F5/F6/ F7:Offset DCh:bit 0), and SMI # will be generated. This bit will be set regardless of whether interrupts or SCI is enabled. The SMI# may occur concurrently with an interrupt or SCI.
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5.2.3 SERR# Generation
SERR# may be generated using two paths – through PCI mechanisms involving bits in the PCI header, or through PCI Express* mechanisms involving bits in the PCI Express capability structure.
5.2.4 Hot-Plug
Each root port implements a Hot-Plug controller which performs the following:
- Messages to turn on / off / blink LEDs
- Presence and attention button detection
- Interrupt generation The root port only allows Hot-Plug with modules (such as, ExpressCard*). Edge- connector based Hot-Plug is not supported.
5.2.4.1 Presence Detection
When a module is plugged in and power is supplied, the physical layer will detect the presence of the device, and the root port sets SLSTS.PDS (D28:F0/F1/F2/F3/F4/ F5:Offset 5Ah:bit 6) and SLSTS.PDC (D28:F0/F1/F2/F3:Offset 6h:bit 3). If SLCTL.PDE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:bit 3) and SLCTL.HPE (D28:F0/F1/F2/F3/ F4/F5/F6/F7:Offset 58h:bit 5) are both set, the root port will also generate an interrupt. When a module is removed (using the physical layer detection), the root port clears port will also generate an interrupt. Figure 5-1. Generation of SERR# to Platform PSTS.SSE SERR#PCICMD.SEE Secondary Parity Error Primary Parity Error Secondary SERR# Correctable SERR# Fatal SERR# Non-Fatal SERR# PCI PCI Express
5.2.4.2 Message Generation
When system software writes to SLCTL.AIC (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:bits 7:6) or SLCTL.PIC (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:bits 9:8), the root port will send a message down the link to change the state of LEDs on the module. Writes to these fields are non-postable cycles, and the resulting message is a postable cycle. When receiving one of these writes, the root port performs the following:
- Changes the state in the register
- Generates a completion into the upstream queue
- Formulates a message for the downstream po rt if the field is written to regardless of if the field changed
- Generates the message on the downstream port
- When the last message of a command is transmitted, sets SLSTS.CCE (D28:F0/F1/ F2/F3/F4/F5/F6/F7:Offset 58h:bit 4) to indicate the command has completed. If SLCTL.CCE and SLCTL.HPE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:bit 5) are set, the root port generates an interrupt. The command completed register (SLSTS.CC) applies only to commands issued by software to control the Attention Indicator (SLCTL.AIC), Power Indicator (SLCTL.PIC), or Power Controller (SLCTL.PCC). However, writes to other parts of the Slot Control Register would invariably end up writing to the indicators, power controller fields; Hence, any write to the Slot Control Register is considered a command and if enabled, will result in a command complete interrupt. The only exception to this rule is a write to disable the command complete interrupt which will not result in a command complete interrupt. A single write to the Slot Control register is considered to be a single command, and hence receives a single command complete, even if the write affects more than one field in the Slot Control Register.
5.2.4.3 Attention Button Detection
When an attached device is ejected, an attention button could be pressed by the user. This attention button press will result in a the PCI Express message “Attention_Button_Pressed” from the device. Upon receiving this message, the root port will set SLSTS.ABP (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 5Ah:bit 0). If SLCTL.ABE (D28:F0/F1/F2/F3/F4/F5:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/ F2/F3/F4/F5/F6/F7:Offset 58h:bit 5) are set, the Hot-Plug controller will also generate an interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is already set, a new interrupt will not be generated.
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5.2.4.4 SMI/SCI Generation
Interrupts for Hot-Plug events are not supported on legacy operating systems. To support Hot-Plug on non-PCI Express aware operating systems, Hot-Plug events can be routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3/F4/F5/F6/ F7:Offset D8h:bit 30) must be set. When set, enabled Hot-Plug events will cause SMSCS.HPCS (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset DCh:bit 30) to be set. Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset D8h:bit 1). When this bit is set, Hot-Plug events can cause SMI status bits in SMSCS to be set. Supported Hot-Plug events and their corresponding SMSCS bit are:
- Command Completed – SCSCS.HPCCM (D 28:F0/F1/F2/F3/F4/F5/F6/F7:Offset DCh:bit 3)
- Presence Detect Changed – SMSCS.HPPDM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset DCh:bit 1)
- Attention Button Pressed – SMSCS.HPABM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset DCh:bit 2)
- Link Active State Changed – SMSCS.HPLA S (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset DCh:bit 4) When any of these bits are set, SMI# will be generated. These bits are set regardless of whether interrupts or SCI are enabled for Hot-Plug events. The SMI# may occur concurrently with an interrupt or SCI.
5.3 Gigabit Ethernet Controller (B0:D25:F0)
The PCH chipset integrates a Gigabit Ethernet (GbE) controller. The integrated GbE controller is compatible with the Intel ® 82577/82578 Platform LAN Connect device. The integrated GbE controller provides two interfaces for 10/100/1000 Mb/s and manageability operation:
- Based on PCI Express*—A high-speed SerD es interface using PCI Express electrical signaling at half speed while keeping the custom logical protocol for active state operation mode.
- System Management Bus (SMBus)—A very low speed connection for low power state mode for manageability communication only. At this low power state mode the Ethernet link speed is reduced to 10 Mb/s. The 82577/82578 can be connected to any available PCI Express port in the PCH chipset. The 82577/82578 only runs at a speed of 1250 Mb/s, which is 1/2 of the gen1 2.5 Gb/s PCI Express frequency. Each of the PCI Express root ports in the PCH chipset have the ability to run at the 1250 Mb/s rate. There is no need to implement a mechanism to detect that the 82577/82578 is connected. The port configuration (if any), attached to the 82577/82578, is pre-loaded from the NVM. The selected port adjusts the transmitter to run at the 1250 Mb/s rate and does not need to be PCI Express compliant. Note: PCIe validation tools cannot be used for electrical validation of this interface; however, PCIe layout rules apply for on-board routing. The integrated GbE controller operates at full-duplex at all supported speeds or half- duplex at 10/100 Mb/s. It also adheres to the IEEE 802.3x Flow Control Specification. Note: GbE operation (1000 Mb/s) is only supported in S0 mode. In Sx modes, SMBus is the only active bus and is used to support manageability/remote wake-up functionality.
The integrated GbE controller provides a system interface using a PCI Express function. A full memory-mapped or I/O-mapped interface is provided to the software, along with DMA mechanisms for high performance data transfer. The integrated GbE controller features are:
- N e t w o r k F e a t u r e s — Compliant with the 1 Gb/s Ethern et 802.3 802.3u 802.3ab specifications — Multi-speed operation: 10/100/1000 Mb/s — Full-duplex operation at 10/100/1000Mb/s: Half-duplex at 10/100 Mb/s — Flow control support compliant with the 802.3X specification — VLAN support compliant with the 802.3q specification — MAC address filters: perfect match unica st filters; multicast hash filtering, broadcast filter and promiscuous mode — PCI Express/SMBus interface to GbE PHYs
- Host Interface Features — 64-bit address master support for system s using more than 4 GB of physical memory — Programmable host memory receive buffers (256 Bytes to 16 KB) — Intelligent interrupt generation feat ures to enhance driver performance — Descriptor ring management hard ware for transmit and receive — Software controlled reset (resets everything except the configuration space) — Message Signaled Interrupts
- Performance Features — Configurable receive and transmit data FIFO, programmable in 1 KB increments — TCP segmentation capability compatib le with NT 5.x off loading features — Fragmented UDP checksum offload for packet reassembly — IPv4 and IPv6 checksum offload support (receive, transmit, and TCP segmentation offload) — Split header support to eliminate payload copy from user space to host space — Receive Side Scaling (RSS) with two hardware receive queues — Supports 9018 bytes of jumbo packets —P a c k e t b u f f e r s i z e — LinkSec offload compliant with 802.3ae specification — TimeSync offload compliant with 802.1as specification
- Virtualization Technology Features — Warm function reset – function level reset (FLR) —V M D q 1
- Power Management Features — Magic Packet* wake-up enable with unique MAC address — ACPI register set and power down functionality supporting D0 and D3 states — Full wake up support (APM, ACPI) — MAC power down at Sx, DMoff with and without WoL
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5.3.1 GbE PCI Express* Bus Interface
The GbE controller has a PCI Express interface to the host processor and host memory. The following sections detail the bus transactions.
5.3.1.1 Transaction Layer
The upper layer of the host architecture is the transaction layer. The transaction layer connects to the device core using an implementation specific protocol. Through this core-to-transaction-layer protocol, the application-specific parts of the device interact with the subsystem and transmit and receive requests to or from the remote agent, respectively.
5.3.1.2 Data Alignment
5.3.1.2.1 4 KB Boundary PCI requests must never specify an address/length combination that causes a memory space access to cross a 4 KB boundary. It is hardware’s responsibility to break requests into 4 KB-aligned requests (if needed). This does not pose any requirement on software. However, if software allocates a buffer across a 4 KB boundary, hardware issues multiple requests for the buffer. Software should consider aligning buffers to a 4 KB boundary in cases where it improves performance. The alignment to the 4 KB boundaries is done in the core. The transaction layer does not do any alignment according to these boundaries. 5.3.1.2.2 64 Bytes PCI requests are multiples of 64 bytes and aligned to make better use of memory controller resources. Writes, however, can be on any boundary and can cross a 64-byte alignment boundary.
5.3.1.3 Configuration Request Retry Status
The integrated GbE controller might have a delay in initialization due to an NVM read. If the NVM configuration read operation is not completed and the device receives a configuration request, the device responds with a configuration request retry completion status to terminate the request, and thus effectively stalls the configuration request until such time that the sub-system has completed local initialization and is ready to communicate with the host.
5.3.2 Error Events and Error Reporting
5.3.2.1 Data Parity Error
The PCI host bus does not provide parity protection, but it does forward parity errors from bridges. The integrated GbE controller recognizes parity errors through the internal bus interface and sets the Parity Error bit in PCI configuration space. If parity errors are enabled in configuration space, a system error is indicated on the PCI host bus. The offending cycle with a parity error is dropped and not processed by the integrated GbE controller.
5.3.2.2 Completion with Unsu ccessful Completion Status
A completion with unsuccessful completion status (any status other than 000) is dropped and not processed by the integrated GbE controller. Furthermore, the request that corresponds to the unsuccessful completion is not retried. When this unsuccessful completion status is received, the System Error bit in the PCI configuration space is set. If the system errors are enabled in configuration space, a system error is indicated on the PCI host bus.
5.3.3 Ethernet Interface
The integrated GbE controller provides a complete CSMA/CD function supporting IEEE 802.3 (10 Mb/s), 802.3u (100 Mb/s) implementations. It also supports the IEEE 802.3z and 802.3ab (1000 Mb/s) implementations. The device performs all of the functions required for transmission, reception, and collision handling called out in the standards. The mode used to communicate between the PCH and the 82577/82578 PHY supports 10/100/1000 Mb/s operation, with both half- and full-duplex operation at 10/100 Mb/s, and full-duplex operation at 1000 Mb/s.
5.3.3.1 Intel ® 5 Series Chipset and Intel® 3400 Series Chipset
The integrated GbE controller and the 82577/82578 PHY communicate through the PCIe and SMBus interfaces. All integrated GbE controller configuration is performed using device control registers mapped into system memory or I/O space. The 82577/ 82578 is configured using the PCI Express or SMBus interface. The integrated GbE controller supports various modes as listed in Table 5-4. Table 5-4. LAN Mode Support Mode System State Interface Active Connections Normal 10/100/1000 Mb/s S0 PCI Express or SMBus1 NOTES: 1. GbE operation is not supported in Sx states. Manageability and Remote Wake-up Sx SMBus 82577/82578
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5.3.4 PCI Power Management
The integrated GbE controller supports the Advanced Configuration and Power Interface (ACPI) specification as well as Advanced Power Management (APM). This enables the network-related activity (using an internal host wake signal) to wake up the host. For example, from Sx (S3-S5) to S0. The integrated GbE controller contains power management registers for PCI and supports D0 and D3 states. PCIe transactions are only allowed in the D0 state, except for host accesses to the integrated GbE controller’s PCI configuration registers.
5.3.4.1 Wake Up
The integrated GbE controller supports two types of wake-up mechanisms: 1. Advanced Power Management (APM) Wake Up 2. ACPI Power Management Wake Up Both mechanisms use an internal logic signal to wake the system up. The wake-up steps are as follows: 1. Host wake event occurs (note that packet is not delivered to host). 2. The 82577/82578 receives a WoL packet/link status change. 3. The 82577/82578 wakes up the integrated GbE controller using an SMBus message. 4. The integrated GbE controller sets the PME_STATUS bit. 5. System wakes from Sx state to S0 state. 6. The host LAN function is transitioned to D0. 7. The host clears the PME_STATUS bit.
5.3.4.1.1 Advanced Power Management Wake Up
Advanced Power Management Wake Up or APM Wake Up was previously known as Wake on LAN (WoL). It is a feature that has existed in the 10/100 Mb/s NICs for several generations. The basic premise is to receive a broadcast or unicast packet with an explicit data pattern and then to assert a signal to wake up the system. In earlier generations, this was accomplished by using a special signal that ran across a cable to a defined connector on the motherboard. The NIC would assert the signal for approximately 50 ms to signal a wake up. The integrated GbE controller uses (if configured to) an in-band PM_PME message for this. At power up, the integrated GbE controller reads the APM Enable bits from the NVM PCI Init Control Word into the APM Enable (APME) bits of the Wake Up Control (WUC) register. These bits control enabling of APM wake up. When APM wake up is enabled, the integrated GbE controller checks all incoming packets for Magic Packets*. Once the integrated GbE controller receives a matching Magic Packet*, it:
- Sets the Magic Packet* Received bit in the Wake Up Status (WUS) register.
- Sets the PME_Status bit in the Power Management Control/Status Register (PMCSR). APM wake up is supported in all power states and only disabled if a subsequent NVM read results in the APM Wake Up bit being cleared or the software explicitly writes a 0b to the APM Wake Up (APM) bit of the WUC register.
Note: APM wake up settings will be restored to NVM default by the PCH when LAN connected Device (PHY) power is turned off and subsequently restored. Some example host WOL flows are: 1. When system transitions to G3 after WOL is disabled from the BIOS, APM host WOL would get enabled. 2. Anytime power to the LAN Connected Device (PHY) is cycled while in S4/S5 after WOL is disabled from the BIOS, APM host WOL would get enabled. Anytime power to the LAN Connected Device (PHY) is cycled while in S3, APM host WOL configuration is lost.
5.3.4.1.2 ACPI Power Management Wake Up
The integrated GbE controller supports ACPI Power Management based Wake ups. It can generate system wake-up events from three sources:
- Receiving a Magic Packet*.
- Receiving a Network Wake Up Packet.
- Detecting a link change of state. Activating ACPI Power Management Wakeup requires the following steps:
- The software device driver programs the Wake Up Filter Control (WUFC) register to indicate the packets it needs to wake up from and supplies the necessary data to the IPv4 Address Table (IP4AT) and the Flexible Filter Mask Table (FFMT), Flexible Filter Length Table (FFLT), and the Flexible Filter Value Table (FFVT). It can also set the Link Status Change Wake Up Enable (LNKC) bit in the Wake Up Filter Control (WUFC) register to cause wake up when the link changes state.
- The operating system (at configuration time) writes a 1b to the PME_EN bit of the Power Management Control/Status Register (PMCSR.8). Normally, after enabling wake up, the operating system writes a 11b to the lower two bits of the PMCSR to put the integrated GbE controller into low-power mode. Once wake up is enabled, the integrated GbE controller monitors incoming packets, first filtering them according to its standard address filtering method, then filtering them with all of the enabled wake-up filters. If a packet passes both the standard address filtering and at least one of the enabled wake-up filters, the integrated GbE controller:
- Sets the PME_Status bit in the PMCSR
- Sets one or more of the Received bits in the Wake Up Status (WUS) register. (More than one bit is set if a packet matches more than one filter.) If enabled, a link state change wake up causes similar results, setting the Link Status Changed (LNKC) bit in the Wake Up Status (WUS) register when the link goes up or down. After receiving a wake-up packet, the integrated GbE controller ignores any subsequent wake-up packets until the software device driver clears all of the Received bits in the Wake Up Status (WUS) register. It also ignores link change events until the software device driver clears the Link Status Changed (LNKC) bit in the Wake Up Status (WUS) register. Note: ACPI wake up settings are not preserved when the LAN Connected Device (PHY) power is turned off and subsequently restored. Some example host WOL flows are: 1. Anytime power to the LAN Connected Device (PHY) is cycled while in S3 or S4, ACPI host WOL configuration is lost.
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5.3.5 Configurable LEDs
The integrated GbE controller supports three controllable and configurable LEDs that are driven from the 82577/82578. Each of the three LED outputs can be individually configured to select the particular event, state, or activity, which is indicated on that output. In addition, each LED can be individually configured for output polarity as well as for blinking versus non-blinking (steady-state) indication. The configuration for LED outputs is specified using the LEDCTL register. Furthermore, the hardware-default configuration for all the LED outputs, can be specified using NVM fields, thereby supporting LED displays configurable to a particular OEM preference. Each of the three LEDs might be configured to use one of a variety of sources for output indication. The MODE bits control the LED source:
- LINK_100/1000 is asserted when link is established at either 100 or 1000 Mb/s.
- LINK_10/1000 is asserted when link is established at either 10 or 1000 Mb/s.
- LINK_UP is asserted when any spee d link is established and maintained.
- ACTIVITY is asserted when link is established and packets are being transmitted or received.
- LINK/ACTIVITY is asserted when link is established AND there is NO transmit or receive activity
- LINK_10 is asserted when a 10 Mb/ps link is established and maintained.
- LINK_100 is asserted when a 100 Mb/s link is established and maintained.
- LINK_1000 is asserted when a 1000 Mb/s link is established and maintained.
- FULL_DUPLEX is asserted when the link is configured for full duplex operation.
- COLLISION is asserted when a collision is observed.
- PAUSED is asserted when the device's transmitter is flow controlled.
- LED_ON is always asserted; LED_OFF is always de-asserted. The IVRT bits enable the LED source to be inverted before being output or observed by the blink-control logic. LED outputs are assumed to normally be connected to the negative side (cathode) of an external LED. The BLINK bits control whether the LED should be blinked while the LED source is asserted, and the blinking frequency (either 200 ms on and 200 ms off or 83 ms on and 83 ms off). The blink control can be especially useful for ensuring that certain events, such as ACTIVITY indication, cause LED transitions, which are sufficiently visible to a human eye. The same blinking rate is shared by all LEDs.
5.3.6 Function Level Reset Support (FLR)
The integrated GbE controller supports FLR capability. FLR capability can be used in conjunction with Intel® Virtualization Technology. FLR allows an operating system in a Virtual Machine to have complete control over a device, including its initialization, without interfering with the rest of the platform. The device provides a software interface that enables the operating system to reset the entire device as if a PCI reset was asserted.
5.3.6.1 FLR Steps
5.3.6.1.1 FLR Initialization
- FLR is initiated by software by writing a 1b to the Initiate FLR bit. 2. All subsequent requests targeting the function is not claimed and will be master abort immediate on the bus. This includes any configuration, I/O or memory cycles, however, the function must continue to accept completions targeting the function.
5.3.6.1.2 FLR Operation
Function resets all configuration, I/O and memory registers of the function except those indicated otherwise and resets all internal states of the function to the default or initial condition.
5.3.6.1.3 FLR Completion
The Initiate FLR bit is reset (cleared) when the FLR reset completes. This bit can be used to indicate to the software that the FLR reset completed. Note: From the time the Initiate FLR bit is written to 1b, software must wait at least 100 ms before accessing the function.
5.4 LPC Bridge (with System and Management
Functions) (D31:F0) The LPC bridge function of the PCH resides in PCI Device 31:Function 0. In addition to the LPC bridge function, D31:F0 contains other functional units including DMA, Interrupt controllers, Timers, Power Management, System Management, GPIO, and RTC. In this chapter, registers and functions associated with other functional units (power management, GPIO, USB, etc.) are described in their respective sections. Note: The LPC bridge cannot be configured as a subtractive decode agent.
5.4.1 LPC Interface
The PCH implements an LPC interface as described in the Low Pin Count Interface Specification, Revision 1.1. The LPC interface to the PCH is shown in Figure 5-2. Note that the PCH implements all of the signals that are shown as optional, but peripherals are not required to do so.
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5.4.1.1 LPC Cycle Types
The PCH implements all of the cycle types described in the Low Pin Count Interface Specification, Revision 1.1. Table 5-5 shows the cycle types supported by the PCH. NOTES: 1. The PCH provides a single generic memory ra nge (LGMR) for decoding memory cycles and forwarding them as LPC Memory cycles on the LPC bus. The LGMR memory decode range is 64 KB in size and can be defined as being anywhere in the 4 GB memory space. This range needs to be configured by BIOS during POST to provide the necessary memory resources. BIOS should advertise the LPC Generic Memory Range as Reserved to the OS to avoid resource conflict. For larger transfers, the PCH performs multiple 8-bit transfers. If the cycle is not claimed by any peripheral, it is subsequently aborted, and the PCH returns a value of all 1s to the processor. This is done to maintain compatibility with ISA memory cycles where pull-up resistors would keep the bus high if no device responds. 2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any address. However, the 2-byte transfer must be word-aligned (that is, with an address where A0=0). A DWord transfer must be DWord-aligned (that is, with an address where A1 and A0 are both 0). Figure 5-2. LPC Interface Diagram PCH LPC Device PCI Bus PCI CLK PCI RST# PCI SERIRQ PCI PME# LAD [3:0] LFRAME# LPCPD# (Optional)SUS_STAT# LDRQ[1:0]# (Optional) LSMI# (Optional)GPI Table 5-5. LPC Cycle Types Supported Cycle Type Comment Memory Read 1 byte only. (See Note 1 below) Memory Write 1 byte only. (See Note 1 below) I/O Read 1 byte only. The PCH breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. I/O Write 1 byte only. The PCH breaks up 16- and 32-bit processor cycles into multiple 8-bit transfers. DMA Read Can be 1, or 2 bytes DMA Write Can be 1, or 2 bytes Bus Master Read Can be 1, 2, or 4 bytes. (See Note 2 below) Bus Master Write Can be 1, 2, or 4 bytes. (See Note 2 below)
5.4.1.2 Start Field Definition
NOTE: All other encodings are RESERVED.
5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR)
The PCH always drives bit 0 of this field to 0. Peripherals running bus master cycles must also drive bit 0 to 0. Table 5-7 shows the valid bit encodings.
5.4.1.4 Size
Bits[3:2] are reserved. The PCH always drives them to 00. Peripherals running bus master cycles are also supposed to drive 00 for bits 3:2; however, the PCH ignores those bits. Bits[1:0] are encoded as listed in Table 5-8. Table 5-6. Start Field Bit Definitions Bits[3:0] Encoding Definition
0000 Start of cycle for a generic target
0010 Grant for bus master 0
0011 Grant for bus master 1
1111 Stop/Abort: End of a cycle for a
target. Table 5-7. Cycle Type Bit Definitions Bits[3:2] Bit1 Definition 00 0 I/O Read 00 1 I/O Write 01 0 Memory Read 01 1 Memory Read 10 0 DMA Read 10 1 DMA Write 11 x Reserved. If a peripheral performing a bus master cycle generates this value, the PCH aborts the cycle. Table 5-8. Transfer Size Bit Definition Bits[1:0] Size 00 8-bit transfer (1 byte) 01 16-bit transfer (2 bytes) 10 Reserved. The PCH never drives this combination. If a peripheral running a bus master cycle drives this combination, the PCH may abort the transfer. 11 32-bit transfer (4 bytes)
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5.4.1.5 SYNC
Valid values for the SYNC field are shown in Table 5-9. NOTES: 1. All other combinations are RESERVED. 2. If the LPC controller receives any SYNC retu rned from the device other than short (0101), long wait (0110), or ready (0000) when running a FWH cycle, indeterminate results may occur. A FWH device is not allowed to assert an Error SYNC.
5.4.1.6 SYNC Time-Out
There are several error cases that can occur on the LPC interface. The PCH responds as defined in section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1 to the stimuli described therein. There may be other peripheral failure conditions; however, these are not handled by the PCH.
5.4.1.7 SYNC Error Indication
The PCH responds as defined in section 4.2.1.10 of the Low Pin Count Interface Specification, Revision 1.1. Upon recognizing the SYNC field indicating an error, the PCH treats this as a SERR by reporting this into the Device 31 Error Reporting Logic.
5.4.1.8 LFRAME# Usage
The PCH follows the usage of LFRAME# as defined in the Low Pin Count Interface Specification, Revision 1.1. The PCH performs an abort for the following cases (possible failure cases):
- The PCH starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after four consecutive clocks.
- The PCH starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern.
- A peripheral drives an illegal address when performing bus master cycles.
- A peripheral drives an invalid value. Table 5-9. SYNC Bit Definition Bits[3:0] Indication 0000 Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request de-assertion and no more transfers desired for that channel. 0101 Short Wait: Part indicating wait-states. For bus master cycles, the PCH does not use this encoding. Instead, the PCH uses the Long Wait encoding (see next encoding below). 0110 Long Wait: Part indicating wait-states, and many wait-states will be added. This encoding driven by the PCH for bus master cycles, rather than the Short Wait (0101). 1001 Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no error and more DMA transfers desired to continue after this transfer. This value is valid only on DMA transfers and is not allowed for any other type of cycle. 1010 Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious error in this transfer. For DMA transfers, this not only indicates an error, but also indicates DMA request de-assertion and no more transfers desired for that channel.
5.4.1.9 I/O Cycles
For I/O cycles targeting registers specified in the PCH decode ranges, the PCH performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision 1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, the PCH breaks the cycle up into multiple 8-bit transfers to consecutive I/O addresses. Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the PCH returns a value of all 1s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up resistors would keep the bus high if no device responds.
5.4.1.10 Bus Master Cycles
The PCH supports Bus Master cycles and requests (using LDRQ#) as defined in the Low Pin Count Interface Specification, Revision 1.1. The PCH has two LDRQ# inputs, and thus supports two separate bus master devices. It uses the associated START fields for Bus Master 0 (0010b) or Bus Master 1 (0011b). Note: The PCH does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters should only perform memory read or memory write cycles.
5.4.1.11 LPC Power Management
LPCPD# Protocol Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals drive LDRQ# low or tri-state it. The PCH shuts off the LDRQ# input buffers. After driving SUS_STAT# active, the PCH drives LFRAME# low, and tri-states (or drive low) LAD[3:0]. Note: The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This specification explicitly states that this protocol only applies to entry/exit of low power states which does not include asynchronous reset events. The PCH asserts both SUS_STAT# (connects to LPCPD#) and PLTRST# (connects to LRST#) at the same time during a global reset. This is not inconsistent with the LPC LPCPD# protocol.
5.4.1.12 Configuration and PCH Implications
To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the PCH includes several decoders. During configuration, the PCH must be programmed with the same decode ranges as the peripheral. The decoders are programmed using the Device 31:Function 0 configuration space. Note: The PCH cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar characteristics (specifically those with a “Retry Read” feature which is enabled) to an LPC device if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are not part of normal system operation, but may be encountered as part of platform validation testing using custom test fixtures. Bus Master Device Mapping and START Fields Bus Masters must have a unique START field. In the case of the PCH that supports two LPC bus masters, it drives 0010 for the START field for grants to bus master 0 (requested using LDRQ0#) and 0011 for grants to bus master #1 (requested using LDRQ1#.). Thus, no registers are needed to configure the START fields for a particular bus master.
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5.5 DMA Operation (D31:F0)
The PCH supports LPC DMA using the PCH’s DMA controller. The DMA controller has registers that are fixed in the lower 64 KB of I/O space. The DMA controller is configured using registers in the PCI configuration space. These registers allow configuration of the channels for use by LPC DMA. The DMA circuitry incorporates the functionality of two 8237 DMA controllers with seven independently programmable channels (Figure 5-3). DMA controller 1 (DMA-1) corresponds to DMA channels 0–3 and DMA controller 2 (DMA-2) corresponds to channels 5–7. DMA channel 4 is used to cascade the two controllers and defaults to cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for any other purpose. In addition to accepting requests from DMA slaves, the DMA controller also responds to requests that software initiates. Software may initiate a DMA service request by setting any bit in the DMA Channel Request Register to a 1. Each DMA channel is hardwired to the compatible settings for DMA device size: channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. The PCH provides 24-bit addressing in compliance with the ISA-Compatible specification. Each channel includes a 16-bit ISA-Compatible Current Register which holds the 16 least-significant bits of the 24-bit address, an ISA-Compatible Page Register which contains the eight next most significant bits of address. The DMA controller also features refresh address generation, and auto-initialization following a DMA termination.
5.5.1 Channel Priority
For priority resolution, the DMA consists of two logical channel groups: channels 0–3 and channels 4–7. Each group may be in either fixed or rotate mode, as determined by the DMA Command Register. DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However, a software request for DMA service can be presented through each channel's DMA Request Register. A software request is subject to the same prioritization as any hardware request. See the detailed register description for Request Register programming information in Section 13.2.
5.5.1.1 Fixed Priority
The initial fixed priority structure is as follows: The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, channel 0 has the highest priority, and channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume the priority position of channel 4 in DMA-2, thus taking priority over channels 5, 6, and 7. Figure 5-3. PCH DMA Controller Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 DMA-1 DMA-2 High priority Low priority 0, 1, 2, 3 5, 6, 7
5.5.1.2 Rotating Priority
Rotation allows for “fairness” in priority resolution. The priority chain rotates so that the last channel serviced is assigned the lowest priority in the channel group (0–3, 5–7). Channels 0–3 rotate as a group of 4. They are always placed between channel 5 and channel 7 in the priority list. Channel 5–7 rotate as part of a group of 4. That is, channels (5–7) form the first three positions in the rotation, while channel group (0–3) comprises the fourth position in the arbitration.
5.5.2 Address Compatibility Mode
When the DMA is operating, the addresses do not increment or decrement through the High and Low Page Registers. Therefore, if a 24-bit address is 01FFFFh and increments, the next address is 010000h, not 020000h. Similarly, if a 24-bit address is 020000h and decrements, the next address is 02FFFFh, not 01FFFFh. However, when the DMA is operating in 16-bit mode, the addresses still do not increment or decrement through the High and Low Page Registers but the page boundary is now 128 K. Therefore, if a 24-bit address is 01FFFEh and increments, the next address is 000000h, not 0100000h. Similarly, if a 24-bit address is 020000h and decrements, the next address is 03FFFEh, not 02FFFEh. This is compatible with the 8237 and Page Register implementation used in the PC-AT. This mode is set after CPURST is valid.
5.5.3 Summary of DMA Transfer Sizes
Table 5-10 lists each of the DMA device transfer sizes. The column labeled “Current Byte/Word Count Register” indicates that the register contents represents either the number of bytes to transfer or the number of 16-bit words to transfer. The column labeled “Current Address Increment/Decrement” indicates the number added to or taken from the Current Address register after each DMA transfer cycle. The DMA Channel Mode Register determines if the Current Address Register will be incremented or decremented.
5.5.3.1 Address Shifting When Pr ogrammed for 16-Bit I/O Count
The PCH maintains compatibility with the implementation of the DMA in the PC AT that used the 8237. The DMA shifts the addresses for transfers to/from a 16-bit device count-by-words. Note: The least significant bit of the Low Page Register is dropped in 16-bit shifted mode. When programming the Current Address Register (when the DMA channel is in this mode), the Current Address must be programmed to an even address with the address value shifted right by one bit. Table 5-10. DMA Transfer Size DMA Device Date Size And Word Count Current Byte/Word Count Register Current Address Increment/ Decrement 8-Bit I/O, Count By Bytes Bytes 1 16-Bit I/O, Count By Words (Address Shifted) Words 1
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The address shifting is shown in Table 5-11. NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.
5.5.4 Autoinitialize
By programming a bit in the DMA Channel Mode Register, a channel may be set up as an autoinitialize channel. When a channel undergoes autoinitialization, the original values of the Current Page, Current Address and Current Byte/Word Count Registers are automatically restored from the Base Page, Address, and Byte/Word Count Registers of that channel following TC. The Base Registers are loaded simultaneously with the Current Registers by the microprocessor when the DMA channel is programmed and remain unchanged throughout the DMA service. The mask bit is not set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to perform another DMA service, without processor intervention, as soon as a valid DREQ is detected.
5.5.5 Softwar e Commands
There are three additional special software commands that the DMA controller can execute. The three software commands are:
- Clear Byte Pointer Flip-Flop
- M a s t e r C l e a r
- Clear Mask Register They do not depend on any specific bit pattern on the data bus. Table 5-11. Address Shifting in 16-Bit I/O DMA Transfers Output Address 8-Bit I/O Programmed Address (Ch 0–3) 16-Bit I/O Programmed Address (Ch 5–7) (Shifted) A[16:1] A[23:17] A[16:1] A[23:17] A[15:0] A[23:17]
5.6 LPC DMA
DMA on LPC is handled through the use of the LDRQ# lines from peripherals and special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0–3 are 8 bit channels. Channels 5–7 are 16-bit channels. Channel 4 is reserved as a generic bus master request.
5.6.1 Asserting DMA Requests
Peripherals that need DMA service encode their requested channel number on the LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own dedicated LDRQ# signal (they may not be shared between two separate peripherals). The PCH has two LDRQ# inputs, allowing at least two devices to support DMA or bus mastering. LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 5-4, the peripheral uses the following serial encoding sequence:
- Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high during idle conditions.
- The next three bits contain the en coded DMA channel number (MSB first).
- The next bit (ACT) indicates whether the request for the indicated DMA channel is active or inactive. The ACT bit is 1 (high) to indicate if it is active and 0 (low) if it is inactive. The case where ACT is low is rare, and is only used to indicate that a previous request for that channel is being abandoned.
- After the active/inactive indication, the LDRQ# signal must go high for at least 1 clock. After that one clock, LDRQ# signal can be brought low to the next encoding sequence. If another DMA channel also needs to request a transfer, another sequence can be sent on LDRQ#. For example, if an encoded request is sent for channel 2, and then channel 3 needs a transfer before the cycle for channel 2 is run on the interface, the peripheral can send the encoded request for channel 3. This allows multiple DMA agents behind an I/O device to request use of the LPC interface, and the I/O device does not need to self- arbitrate before sending the message. Figure 5-4. DMA Request Assertion through LDRQ# Start MSB LSB ACT Start LCLK LDRQ#
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5.6.2 Abandoning DMA Requests
DMA Requests can be de-asserted in two fashions: on error conditions by sending an LDRQ# message with the ‘ACT’ bit set to 0, or normally through a SYNC field during the DMA transfer. This section describes boundary conditions where the DMA request needs to be removed prior to a data transfer. There may be some special cases where the peripheral desires to abandon a DMA transfer. The most likely case of this occurring is due to a floppy disk controller which has overrun or underrun its FIFO, or software stopping a device prematurely. In these cases, the peripheral wishes to stop further DMA activity. It may do so by sending an LDRQ# message with the ACT bit as 0. However, since the DMA request was seen by the PCH, there is no assurance that the cycle has not been granted and will shortly run on LPC. Therefore, peripherals must take into account that a DMA cycle may still occur. The peripheral can choose not to respond to this cycle, in which case the host will abort it, or it can choose to complete the cycle normally with any random data. This method of DMA de-assertion should be prevented whenever possible, to limit boundary conditions both on the PCH and the peripheral.
5.6.3 General Flow of DMA Transfers
Arbitration for DMA channels is performed through the 8237 within the host. Once the host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA transfer is as follows: 1. The PCH starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted. 2. The PCH asserts ‘cycle type’ of DMA, direction based on DMA transfer direction. 3. The PCH asserts channel number and, if applicable, terminal count. 4. The PCH indicates the size of the transfer: 8 or 16 bits. 5. If a DMA read… — The PCH drives the first 8 bits of data and turns the bus around. — The peripheral acknowledges the data with a valid SYNC. — If a 16-bit transfer, the process is repeated for the next 8 bits. 6. If a DMA write… — The PCH turns the bus around and waits for data. — The peripheral indicates data ready th rough SYNC and transfers the first byte. — If a 16-bit transfer, the peripheral indicates data ready and transfers the next byte. 7. The peripheral turns around the bus.
5.6.4 Terminal Count
Terminal count is communicated through LAD[3] on the same clock that DMA channel is communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates the last byte of transfer, based upon the size of the transfer. For example, on an 8-bit transfer size (SIZE field is 00b), if the TC bit is set, then this is the last byte. On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, then the second byte is the last byte. The peripheral, therefore, must internalize the TC bit when the CHANNEL field is communicated, and only signal TC when the last byte of that transfer size has been transferred.
5.6.5 Verify Mode
Verify mode is supported on the LPC interface. A verify transfer to the peripheral is similar to a DMA write, where the peripheral is transferring data to main memory. The indication from the host is the same as a DMA write, so the peripheral will be driving data onto the LPC interface. However, the host will not transfer this data into main memory.
5.6.6 DMA Request De-assertion
An end of transfer is communicated to the PCH through a special SYNC field transmitted by the peripheral. An LPC device must not attempt to signal the end of a transfer by de-asserting LDREQ#. If a DMA transfer is several bytes (such as, a transfer from a demand mode device) the PCH needs to know when to de-assert the DMA request based on the data currently being transferred. The DMA agent uses a SYNC encoding on each byte of data being transferred, which indicates to the PCH whether this is the last byte of transfer or if more bytes are requested. To indicate the last byte of transfer, the peripheral uses a SYNC value of 0000b (ready with no error), or 1010b (ready with error). These encodings tell the PCH that this is the last piece of data transferred on a DMA read (PCH to peripheral), or the byte that follows is the last piece of data transferred on a DMA write (peripheral to the PCH). When the PCH sees one of these two encodings, it ends the DMA transfer after this byte and de-asserts the DMA request to the 8237. Therefore, if the PCH indicated a 16-bit transfer, the peripheral can end the transfer after one byte by indicating a SYNC value of 0000b or 1010b. The PCH does not attempt to transfer the second byte, and de- asserts the DMA request internally. If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the indicated size, then the PCH only de-asserts the DMA request to the 8237 since it does not need to end the transfer. If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of 1001b (ready plus more data). This tells the 8237 that more data bytes are requested after the current byte has been transferred, so the PCH keeps the DMA request active to the 8237. Therefore, on an 8-bit transfer size, if the peripheral indicates a SYNC value of 1001b to the PCH, the data will be transferred and the DMA request will remain active to the 8237. At a later time, the PCH will then come back with another START–CYCTYPE–CHANNEL–SIZE etc. combination to initiate another transfer to the peripheral. The peripheral must not assume that the next START indication from the PCH is another grant to the peripheral if it had indicated a SYNC value of 1001b. On a single mode DMA device, the 8237 will re-arbitrate after every transfer. Only demand mode DMA devices can be assured that they will receive the next START indication from the PCH. Note: Indicating a 0000b or 1010b encoding on the SYNC field of an odd byte of a 16-bit channel (first byte of a 16-bit transfer) is an error condition. Note: The host stops the transfer on the LPC bus as indicated, fills the upper byte with random data on DMA writes (peripheral to memory), and indicates to the 8237 that the DMA transfer occurred, incrementing the 8237’s address and decrementing its byte count.
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5.6.7 SYNC Field / LDRQ# Rules
Since DMA transfers on LPC are requested through an LDRQ# assertion message, and are ended through a SYNC field during the DMA transfer, the peripheral must obey the following rule when initiating back-to-back transfers from a DMA channel. The peripheral must not assert another message for eight LCLKs after a de-assertion is indicated through the SYNC field. This is needed to allow the 8237, that typically runs off a much slower internal clock, to see a message de-asserted before it is re-asserted so that it can arbitrate to the next agent. Under default operation, the host only performs 8-bit transfers on 8-bit channels and 16-bit transfers on 16-bit channels. The method by which this communication between host and peripheral through system BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC peripheral are motherboard devices, no “plug-n-play” registry is required. The peripheral must not assume that the host is able to perform transfer sizes that are larger than the size allowed for the DMA channel, and be willing to accept a SIZE field that is smaller than what it may currently have buffered. To that end, it is recommended that future devices that may appear on the LPC bus, that require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus mastering interface and not rely on the 8237. 5.7 8254 Timers (D31:F0) The PCH contains three counters that have fixed uses. All registers and functions associated with the 8254 timers are in the core well. The 8254 unit is clocked by a 14.31818 MHz clock. Counter 0, System Timer This counter functions as the system timer by controlling the state of IRQ0 and is typically programmed for Mode 3 operation. The counter produces a square wave with a period equal to the product of the counter period (838 ns) and the initial count value. The counter loads the initial count value 1 counter period after software writes the count value to the counter I/O address. The counter initially asserts IRQ0 and decrements the count value by two each counter period. The counter negates IRQ0 when the count value reaches 0. It then reloads the initial count value and again decrements the initial count value by two each counter period. The counter then asserts IRQ0 when the count value reaches 0, reloads the initial count value, and repeats the cycle, alternately asserting and negating IRQ0. Counter 1, Refresh Request Signal This counter provides the refresh request signal and is typically programmed for Mode 2 operation and only impacts the period of the REF_TOGGLE bit in Port 61. The initial count value is loaded one counter period after being written to the counter I/O address. The REF_TOGGLE bit will have a square wave behavior (alternate between 0 and 1) and will toggle at a rate based on the value in the counter. Programming the counter to anything other than Mode 2 will result in undefined behavior for the REF_TOGGLE bit. Counter 2, Speaker Tone This counter provides the speaker tone and is typically programmed for Mode 3 operation. The counter provides a speaker frequency equal to the counter clock frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled by a write to port 061h (see NMI Status and Control ports).
5.7.1 Timer Programming
The counter/timers are programmed in the following fashion: 1. Write a control word to select a counter. 2. Write an initial count for that counter. 3. Load the least and/or most significant bytes (as required by Control Word bits 5, 4) of the 16-bit counter. 4. Repeat with other counters. Only two conventions need to be observed when programming the counters. First, for each counter, the control word must be written before the initial count is written. Second, the initial count must follow the count format specified in the control word (least significant byte only, most significant byte only, or least significant byte and then most significant byte). A new initial count may be written to a counter at any time without affecting the counter's programmed mode. Counting is affected as described in the mode definitions. The new count must follow the programmed count format. If a counter is programmed to read/write two-byte counts, the following precaution applies: A program must not transfer control between writing the first and second byte to another routine which also writes into that same counter. Otherwise, the counter will be loaded with an incorrect count. The Control Word Register at port 43h controls the operation of all three counters. Several commands are available:
- Control Word Command. Specifies which counter to read or write, the operating mode, and the count format (binary or BCD).
- Counter Latch Command. Latches the current count so that it can be read by the system. The countdown process continues.
- Read Back Command. Reads the count value, programmed mode, the current state of the OUT pins, and the state of the Null Count Flag of the selected counter. Table 5-12 lists the six operating modes for the interval counters. Table 5-12. Counter Operating Modes Mode Function Description 0 Out signal on end of count (=0) Output is 0. When count goes to 0, output goes to 1 and stays at 1 until counter is reprogrammed. 1 Hardware retriggerable one-shot Output is 0. When count goes to 0, output goes to 1 for one clock time.
2 Rate generator (divide by n
counter) Output is 1. Output goes to 0 for one clock time, then back to 1 and counter is reloaded. 3S q u a r e w a v e o u t p u t Output is 1. Output goes to 0 when counter rolls over, and counter is reloaded. Output goes to 1 when counter rolls over, and counter is reloaded, etc. 4 Software triggered strobe Output is 1. Output goes to 0 when count expires for one clock time. 5 Hardware triggered strobe Output is 1. Output goes to 0 when count expires for one clock time.
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5.7.2 Reading from the Interval Timer
It is often desirable to read the value of a counter without disturbing the count in progress. There are three methods for reading the counters: a simple read operation, counter Latch command, and the Read-Back command. Each is explained below. With the simple read and counter latch command methods, the count must be read according to the programmed format; specifically, if the counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other. Read, write, or programming operations for other counters may be inserted between them.
5.7.2.1 Simple Read
The first method is to perform a simple read operation. The counter is selected through port 40h (counter 0), 41h (counter 1), or 42h (counter 2). Note: Performing a direct read from the counter does not return a determinate value, because the counting process is asynchronous to read operations. However, in the case of counter 2, the count can be stopped by writing to the GATE bit in port 61h.
5.7.2.2 Counter Latch Command
The Counter Latch command, written to port 43h, latches the count of a specific counter at the time the command is received. This command is used to ensure that the count read from the counter is accurate, particularly when reading a two-byte count. The count value is then read from each counter’s Count register as was programmed by the Control register. The count is held in the latch until it is read or the counter is reprogrammed. The count is then unlatched. This allows reading the contents of the counters on the fly without affecting counting in progress. Multiple Counter Latch Commands may be used to latch more than one counter. Counter Latch commands do not affect the programmed mode of the counter in any way. If a Counter is latched and then, some time later, latched again before the count is read, the second Counter Latch command is ignored. The count read is the count at the time the first Counter Latch command was issued.
5.7.2.3 Read Back Command
The Read Back command, written to port 43h, latches the count value, programmed mode, and current states of the OUT pin and Null Count flag of the selected counter or counters. The value of the counter and its status may then be read by I/O access to the counter address. The Read Back command may be used to latch multiple counter outputs at one time. This single command is functionally equivalent to several counter latch commands, one for each counter latched. Each counter's latched count is held until it is read or reprogrammed. Once read, a counter is unlatched. The other counters remain latched until they are read. If multiple count Read Back commands are issued to the same counter without reading the count, all but the first are ignored. The Read Back command may additionally be used to latch status information of selected counters. The status of a counter is accessed by a read from that counter's I/O port address. If multiple counter status latch operations are performed without reading the status, all but the first are ignored.
Both count and status of the selected counters may be latched simultaneously. This is functionally the same as issuing two consecutive, separate Read Back commands. If multiple count and/or status Read Back commands are issued to the same counters without any intervening reads, all but the first are ignored. If both count and status of a counter are latched, the first read operation from that counter returns the latched status, regardless of which was latched first. The next one or two reads, depending on whether the counter is programmed for one or two type counts, returns the latched count. Subsequent reads return unlatched count. 5.8 8259 Interrupt Controllers (PIC) (D31:F0) The PCH incorporates the functionality of two 8259 interrupt controllers that provide system interrupts for the ISA compatible interrupts. These interrupts are: system timer, keyboard controller, serial ports, parallel ports, floppy disk, mouse, and DMA channels. In addition, this interrupt controller can support the PCI based interrupts, by mapping the PCI interrupt onto the compatible ISA interrupt line. Each 8259 core supports eight interrupts, numbered 0–7. Table 5-13 shows how the cores are connected. The PCH cascades the slave controller onto the master controller through master controller interrupt input 2. This means there are only 15 possible interrupts for the PCH PIC. Table 5-13. Interrupt Controller Core Connections 8259 8259 Input Typical Interrupt Source Connected Pin / Function Master
0 Internal Internal Timer / Counter 0 output / HPET #0
1 Keyboard IRQ1 via SERIRQ
2 Internal Slave controller INTR output
3 Serial Port A IRQ3 via SERIRQ, PIRQ#
4 Serial Port B IRQ4 via SERIRQ, PIRQ#
5 Parallel Port / Generic IRQ5 via SERIRQ, PIRQ#
6 Floppy Disk IRQ6 via SERIRQ, PIRQ#
7 Parallel Port / Generic IRQ7 via SERIRQ, PIRQ#
0 Internal Real Time
Clock Internal RTC / HPET #1
1 Generic IRQ9 via SERIRQ, SCI, TCO, or PIRQ#
2 Generic IRQ10 via SERIRQ, SCI, TCO, or PIRQ#
3G e n e r i c IRQ11 via SERIRQ, SCI, TCO, or PIRQ#, or HPET 4P S / 2 M o u s e IRQ12 via SERIRQ, SCI, TCO, or PIRQ#, or HPET 5I n t e r n a l State Machine output based on processor FERR# assertion. May optionally be used for SCI or TCO interrupt if FERR# not needed. 6S A T A SATA Primary (legacy mode), or via SERIRQ or PIRQ# 7S A T A SATA Secondary (legacy mode) or via SERIRQ or PIRQ#
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Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2, IRQ8#, and IRQ13. Note: Active-low interrupt sources (such as, the PIRQ#s) are inverted inside the PCH. In the following descriptions of the 8259s, the interrupt levels are in reference to the signals at the internal interface of the 8259s, after the required inversions have occurred. Therefore, the term “high” indicates “active,” which means “low” on an originating PIRQ#.
5.8.1 Interrupt Handling
5.8.1.1 Generating Interrupts
The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each interrupt level. These bits are used to determine the interrupt vector returned, and status of any other pending interrupts. Table 5-14 defines the IRR, ISR, and IMR.
5.8.1.2 Acknowledging Interrupts
The processor generates an interrupt acknowledge cycle that is translated by the host bridge into a PCI Interrupt Acknowledge Cycle to the PCH. The PIC translates this command into two internal INTA# pulses expected by the 8259 cores. The PIC uses the first internal INTA# pulse to freeze the state of the interrupts for priority resolution. On the second INTA# pulse, the master or slave sends the interrupt vector to the processor with the acknowledged interrupt code. This code is based upon bits [7:3] of the corresponding ICW2 register, combined with three bits representing the interrupt within that controller. Table 5-14. Interrupt Status Registers Bit Description IRR Interrupt Request Register. This bit is set on a low to high transition of the interrupt line in edge mode, and by an active high level in level mode. This bit is set whether or not the interrupt is masked. However, a masked interrupt will not generate INTR. ISR Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared, when an interrupt acknowledge cycle is seen, and the vector returned is for that interrupt. IMR Interrupt Mask Register. This bit determines whether an interrupt is masked. Masked interrupts will not generate INTR. Table 5-15. Content of Interrupt Vector Byte Master, Slave Interrupt Bits [7:3] Bits [2:0] IRQ7,15 ICW2[7:3] 111 IRQ6,14 110 IRQ5,13 101 IRQ4,12 100 IRQ3,11 011 IRQ2,10 010 IRQ1,9 001 IRQ0,8 000
5.8.1.3 Hardware/Softwa re Interrupt Sequence
- One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or seen high in level mode, setting the corresponding IRR bit. 2. The PIC sends INTR active to the processor if an asserted interrupt is not masked. 3. The processor acknowledges the INTR and responds with an interrupt acknowledge cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host bridge. This command is broadcast over PCI by the PCH. 4. Upon observing its own interrupt acknowledge cycle on PCI, the PCH converts it into the two cycles that the internal 8259 pair can respond to. Each cycle appears as an interrupt acknowledge pulse on the internal INTA# pin of the cascaded interrupt controllers. 5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR bit is set and the corresponding IRR bit is reset. On the trailing edge of the first pulse, a slave identification code is broadcast by the master to the slave on a private, internal three bit wide bus. The slave controller uses these bits to determine if it must respond with an interrupt vector during the second INTA# pulse. 6. Upon receiving the second internally generated INTA# pulse, the PIC returns the interrupt vector. If no interrupt request is present because the request was too short in duration, the PIC returns vector 7 from the master controller. 7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine.
5.8.2 Initialization Command Words (ICWx)
Before operation can begin, each 8259 must be initialized. In the PCH, this is a four byte sequence. The four initialization command words are referred to by their acronyms: ICW1, ICW2, ICW3, and ICW4. The base address for each 8259 initialization command word is a fixed location in the I/O memory space: 20h for the master controller, and A0h for the slave controller.
5.8.2.1 ICW1
An I/O write to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to ICW1. Upon sensing this write, the PCH’s PIC expects three more byte writes to 21h for the master controller, or A1h for the slave controller, to complete the ICW sequence. A write to ICW1 starts the initialization sequence during which the following automatically occur: 1. Following initialization, an interrupt request (IRQ) input must make a low-to-high transition to generate an interrupt. 2. The Interrupt Mask Register is cleared. 3. IRQ7 input is assigned priority 7. 4. The slave mode address is set to 7. 5. Special mask mode is cleared and Status Read is set to IRR.
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5.8.2.2 ICW2
The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the interrupt vector that will be released during an interrupt acknowledge. A different base is selected for each interrupt controller.
5.8.2.3 ICW3
The third write in the sequence (ICW3) has a different meaning for each controller.
- For the master controller, ICW3 is used to indicate which IRQ input line is used to cascade the slave controller. Within the PCH, IRQ2 is used. Therefore, bit 2 of ICW3 on the master controller is set to a 1, and the other bits are set to 0s.
- For the slave controller, ICW3 is the slave identification code used during an interrupt acknowledge cycle. On interrupt acknowledge cycles, the master controller broadcasts a code to the slave controller if the cascaded interrupt won arbitration on the master controller. The slave controller compares this identification code to the value stored in its ICW3, and if it matches, the slave controller assumes responsibility for broadcasting the interrupt vector.
5.8.2.4 ICW4
The final write in the sequence (ICW4) must be programmed for both controllers. At the very least, bit 0 must be set to a 1 to indicate that the controllers are operating in an Intel Architecture-based system.
5.8.3 Operation Command Words (OCW)
These command words reprogram the Interrupt controller to operate in various interrupt modes.
- OCW1 masks and unmasks interrupt lines.
- OCW2 controls the rotation of interrupt priorities when in rotating priority mode, and controls the EOI function.
- OCW3 sets up ISR/IRR reads, enables/disables the special mask mode (SMM), and enables/disables polled interrupt mode.
5.8.4 Modes of Operation
5.8.4.1 Fully Nested Mode
In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being the highest. When an interrupt is acknowledged, the highest priority request is determined and its vector placed on the bus. Additionally, the ISR for the interrupt is set. This ISR bit remains set until: the processor issues an EOI command immediately before returning from the service routine; or if in AEOI mode, on the trailing edge of the second INTA#. While the ISR bit is set, all further interrupts of the same or lower priority are inhibited, while higher levels generate another interrupt. Interrupt priorities can be changed in the rotating priority mode.
5.8.4.2 Special Fully-Nested Mode
This mode is used in the case of a system where cascading is used, and the priority has to be conserved within each slave. In this case, the special fully-nested mode is programmed to the master controller. This mode is similar to the fully-nested mode with the following exceptions:
- When an interrupt request from a certain slave is in service, this slave is not locked out from the master's priority logic and further interrupt requests from higher priority interrupts within the slave are recognized by the master and initiate interrupts to the processor. In the normal-nested mode, a slave is masked out when its request is in service.
- When exiting the Interrupt Service routine, software has to check whether the interrupt serviced was the only one from that slave. This is done by sending a Non- Specific EOI command to the slave and then reading its ISR. If it is 0, a non- specific EOI can also be sent to the master.
5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)
In some applications, there are a number of interrupting devices of equal priority. Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a device receives the lowest priority after being serviced. In the worst case, a device requesting an interrupt has to wait until each of seven other devices are serviced at most once. There are two ways to accomplish automatic rotation using OCW2; the Rotation on Non-Specific EOI Command (R=1, SL=0, EOI=1) and the rotate in automatic EOI mode which is set by (R=1, SL=0, EOI=0).
5.8.4.4 Specific Rotation Mode (Specific Priority)
Software can change interrupt priorities by programming the bottom priority. For example, if IRQ5 is programmed as the bottom priority device, then IRQ6 is the highest priority device. The Set Priority Command is issued in OCW2 to accomplish this, where: R=1, SL=1, and LO–L2 is the binary priority level code of the bottom priority device. In this mode, internal status is updated by software control during OCW2. However, it is independent of the EOI command. Priority changes can be executed during an EOI command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1 and LO–L2=IRQ level to receive bottom priority.
5.8.4.5 Poll Mode
Poll mode can be used to conserve space in the interrupt vector table. Multiple interrupts that can be serviced by one interrupt service routine do not need separate vectors if the service routine uses the poll command. Poll mode can also be used to expand the number of interrupts. The polling interrupt service routine can call the appropriate service routine, instead of providing the interrupt vectors in the vector table. In this mode, the INTR output is not used and the microprocessor internal Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is achieved by software using a Poll command. The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte returned during the I/O read contains a 1 in bit 7 if there is an interrupt, and the binary code of the highest priority level in bits 2:0.
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5.8.4.6 Edge and Level Triggered Mode
In ISA systems this mode is programmed using bit 3 in ICW1, which sets level or edge for the entire controller. In the PCH, this bit is disabled and a new register for edge and level triggered mode selection, per interrupt input, is included. This is the Edge/Level control Registers ELCR1 and ELCR2. If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition on the corresponding IRQ input. The IRQ input can remain high without generating another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high level on the corresponding IRQ input and there is no need for an edge detection. The interrupt request must be removed before the EOI command is issued to prevent a second interrupt from occurring. In both the edge and level triggered modes, the IRQ inputs must remain active until after the falling edge of the first internal INTA#. If the IRQ input goes inactive before this time, a default IRQ7 vector is returned.
5.8.4.7 End of Interrupt (EOI) Operations
An EOI can occur in one of two fashions: by a command word write issued to the PIC before returning from a service routine, the EOI command; or automatically when AEOI bit in ICW4 is set to 1.
5.8.4.8 Normal End of Interrupt
In normal EOI, software writes an EOI command before leaving the interrupt service routine to mark the interrupt as completed. There are two forms of EOI commands: Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC clears the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of operation of the PIC within the PCH, as the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge. When the PIC is operated in modes that preserve the fully nested structure, software can determine which ISR bit to clear by issuing a Specific EOI. An ISR bit that is masked is not cleared by a Non-Specific EOI if the PIC is in the special mask mode. An EOI command must be issued for both the master and slave controller.
5.8.4.9 Automatic End of Interrupt Mode
In this mode, the PIC automatically performs a Non-Specific EOI operation at the trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this mode should be used only when a nested multi-level interrupt structure is not required within a single PIC. The AEOI mode can only be used in the master controller and not the slave controller.
5.8.5 Masking Interrupts
5.8.5.1 Masking on an Indi vidual Interrupt Request
Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This register is programmed through OCW1. Each bit in the IMR masks one interrupt channel. Masking IRQ2 on the master controller masks all requests for service from the slave controller.
5.8.5.2 Special Mask Mode
Some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control. For example, the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion. The special mask mode enables all interrupts not masked by a bit set in the Mask register. Normally, when an interrupt service routine acknowledges an interrupt without issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority requests. In the special mask mode, any interrupts may be selectively enabled by loading the Mask Register with the appropriate pattern. The special mask mode is set by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0.
5.8.6 Steering PCI Interrupts
The PCH can be programmed to allow PIRQA#-PIRQH# to be routed internally to interrupts 3–7, 9–12, 14 or 15. The assignment is programmable through the PIRQx Route Control registers, located at 60–63h and 68–6Bh in Device 31:Function 0. One or more PIRQx# lines can be routed to the same IRQx input. If interrupt steering is not required, the Route registers can be programmed to disable steering. The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on a PCI board to share a single line across the connector. When a PIRQx# is routed to specified IRQ line, software must change the IRQ's corresponding ELCR bit to level sensitive mode. The PCH internally inverts the PIRQx# line to send an active high level to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no longer be used by an active high device (through SERIRQ). However, active low interrupts can share their interrupt with PCI interrupts. Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external PIRQ to be asserted. The PCH receives the PIRQ input, like all of the other external sources, and routes it accordingly.
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5.9 Advanced Programmable Interrupt Controller
(APIC) (D31:F0) In addition to the standard ISA-compatible PIC described in the previous chapter, the PCH incorporates the APIC. While the standard interrupt controller is intended for use in a uni-processor system, APIC can be used in either a uni-processor or multi- processor system.
5.9.1 Interrupt Handling
The I/O APIC handles interrupts very differently than the 8259. Briefly, these differences are:
- Method of Interrupt Transmission. The I/O APIC transmits interrupts through memory writes on the normal datapath to the processor, and interrupts are handled without the need for the processor to run an interrupt acknowledge cycle.
- Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the interrupt number. For example, interrupt 10 can be given a higher priority than interrupt 3.
- More Interrupts. The I/O APIC in the PCH supports a total of 24 interrupts.
- Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O APIC devices in the system with their own interrupt vectors.
5.9.2 Interrupt Mapping
The I/O APIC within the PCH supports 24 APIC interrupts. Each interrupt has its own unique vector assigned by software. The interrupt vectors are mapped as follows, and match “Config 6” of the Multi-Processor Specification. Table 5-16. APIC Interrupt Mapping 1 (Sheet 1 of 2) IRQ # Using SERIRQ Direct from Pin Using PCI Message Internal Modules
0 No No No Cascade from 8259 #1
2 No No No 8254 Counter 0, HPET #0 (legacy mode)
8N o N o N o R T C , H P E T # 1 ( l e g a c y m o d e )
9 Yes No Yes Option for SCI, TCO
10 Yes No Yes Option for SCI, TCO
11 Yes No Yes HPET #2, Option for SCI, TCO (Note2)
12 Yes No Yes HPET #3 (Note 3)
13 No No No FERR# logic
14 Yes No Yes SATA Primary (legacy mode)
15 Yes No Yes SATA Secondary (legacy mode)
NOTES: 1. When programming the polarity of internal interrupt sources on the APIC, interrupts 0 through 15 receive active-high internal interrupt sources, while interrupts 16 through 23 receive active-low internal interrupt sources. 2. If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other devices to ensure the proper operation of HPET #2. The PCH hardware does not prevent sharing of IRQ 11. 3. If IRQ 12 is used for HPET #3, software should ensure IRQ 12 is not shared with any other devices to ensure the proper operation of HPET #3. The PCH hardware does not prevent sharing of IRQ 12. 4. PIRQ[E:H] are Multiplexed with GPIO pins. Interrupts PIRQ[E:H] will not be exposed if they are configured as GPIOs.
5.9.3 PCI / PCI Express* Message-Based Interrupts
When external devices through PCI / PCI Express wish to generate an interrupt, they will send the message defined in the PCI Express* Base Specification, Revision 1.0a for generating INTA# – INTD#. These will be translated internal assertions/de-assertions of INTA# – INTD#.
5.9.4 IOxAPIC A ddress Remapping
To support Intel® Virtualization Technology, interrupt messages are required to go through similar address remapping as any other memory request. Address remapping allows for domain isolation for interrupts, so a device assigned in one domain is not allowed to generate an interrupt to another domain. The address remapping is based on the Bus: Device: Function field associated with the requests. The internal APIC is required to initiate the interrupt message using a unique Bus: Device: function. The PCH allows BIOS to program the unique Bus: Device: Function address for the internal APIC. This address field does not change the APIC functionality and the APIC is not promoted as a stand-alone PCI device. See Device 31: Function 0 Offset 6Ch for additional information.
5.9.5 External Interrup t Controller Support
The PCH supports external APICs off of PCI Express ports, and does not support APICs on the PCI bus. The EOI special cycle is only forwarded to PCI Express ports.
16 PIRQA# PIRQA#
Yes Internal devices are routable; see
17 PIRQB# PIRQB#
18 PIRQC# PIRQC#
19 PIRQD# PIRQD#
20 N/A PIRQE#
Option for SCI, TCO, HPET #0,1,2, 3. Other internal devices are routable; see
21 N/A PIRQF# 4
22 N/A PIRQG# 4
23 N/A PIRQH# 4
Table 5-16. APIC Interrupt Mapping 1 (Sheet 2 of 2) IRQ # Using SERIRQ Direct from Pin Using PCI Message Internal Modules
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5.10 Serial Interrupt (D31:F0)
The PCH supports a serial IRQ scheme. This allows a single signal to be used to report interrupt requests. The signal used to transmit this information is shared between the host, the PCH, and all peripherals that support serial interrupts. The signal line, SERIRQ, is synchronous to PCI clock, and follows the sustained tri-state protocol that is used by all PCI signals. This means that if a device has driven SERIRQ low, it will first drive it high synchronous to PCI clock and release it the following PCI clock. The serial IRQ protocol defines this sustained tri-state signaling in the following fashion:
- S – Sample Phase. Signal driven low
- R – Recovery Phase. Signal driven high
- T – Turn-around Phase. Signal released The PCH supports a message for 21 serial interrupts. These represent the 15 ISA interrupts (IRQ0–1, 2–15), the four PCI interrupts, and the control signals SMI# and IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts (20–23). Note: When the SATA controller is configured for legacy IDE mode, IRQ14 and IRQ15 are expected to behave as ISA legacy interrupts that cannot be shared (that is, through the Serial Interrupt pin). If IRQ14 and IRQ15 are shared with Serial Interrupt pin then abnormal system behavior may occur. For example, IRQ14/15 may not be detected by the PCH's interrupt controller. When the SATA controller is not running in Native IDE mode, IRQ14 and IRQ15 are used as special interrupts. If the SATA controller is in native modes, these interrupts can be mapped to other devices accordingly.
5.10.1 Start Frame
The serial IRQ protocol has two modes of operation which affect the start frame. These two modes are: Continuous, where the PCH is solely responsible for generating the start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the start frame. The mode that must first be entered when enabling the serial IRQ protocol is continuous mode. In this mode, the PCH asserts the start frame. This start frame is 4, 6, or 8 PCI clocks wide based upon the Serial IRQ Control Register, bits 1:0 at 64h in Device 31:Function 0 configuration space. This is a polling mode. When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a peripheral drives the SERIRQ signal low. The PCH senses the line low and continues to drive it low for the remainder of the Start Frame. Since the first PCI clock of the start frame was driven by the peripheral in this mode, the PCH drives the SERIRQ line low for 1 PCI clock less than in continuous mode. This mode of operation allows for a quiet, and therefore lower power, operation.
5.10.2 Data Frames
Once the Start frame has been initiated, all of the SERIRQ peripherals must start counting frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has exactly 3 phases of 1 clock each:
- Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the corresponding interrupt signal is low. If the corresponding interrupt is high, then the SERIRQ devices tri-state the SERIRQ signal. The SERIRQ line remains high due to pull-up resistors (there is no internal pull-up resistor on this signal, an external pull-up resistor is required). A low level during the IRQ0–1 and IRQ2–15 frames indicates that an active-high ISA interrupt is not being requested, but a low level during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active-low interrupt is being requested.
- Recovery Phase. During this phase, the device drives the SERIRQ line high if in the Sample Phase it was driven low. If it was not driven in the sample phase, it is tri-stated in this phase.
- Turn-around Phase. The device tri-states the SERIRQ line.
5.10.3 Stop Frame
After all data frames, a Stop Frame is driven by the PCH. The SERIRQ signal is driven low by the PCH for 2 or 3 PCI clocks. The number of clocks is determined by the SERIRQ configuration register. The number of clocks determines the next mode.
5.10.4 Specific Interrupts Not Supported Using SERIRQ
There are three interrupts seen through the serial stream that are not supported by the PCH. These interrupts are generated internally, and are not sharable with other devices within the system. These interrupts are:
- IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.
- IRQ8#. RTC interrupt can only be generated internally.
- IRQ13. Floating point error interrupt generated off of the processor assertion of FERR#. The PCH ignores the state of these interrupts in the serial stream, and does not adjust their level based on the level seen in the serial stream. Table 5-17. Stop Frame Explanation Stop Frame Width Next Mode 2 PCI clocks Quiet Mode. Any SERIRQ device may initiate a Start Frame 3 PCI clocks Continuous Mode. Only the host (the PCH) may initiate a Start Frame
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5.10.5 Data Frame Format
Table 5-18 shows the format of the data frames. For the PCI interrupts (A–D), the output from the PCH is AND’d with the PCI input signal. This way, the interrupt can be signaled using both the PCI interrupt input signal and using the SERIRQ signal (they are shared). Table 5-18. Data Frame Format Data Frame Interrupt Clocks Past Start Frame Comment 1I R Q 0 2 Ignored. IRQ0 can only be generated using the internal 8524 2I R Q 1 5 3 SMI# 8 Causes SMI# if low. Wi ll set the SERIRQ_SMI_STS bit. 4I R Q 3 1 1 5I R Q 4 1 4 6I R Q 5 1 7 7I R Q 6 2 0 8I R Q 7 2 3 9 IRQ8 26 Ignored. IRQ8# can only be generated internally.
10 IRQ9 29
11 IRQ10 32
12 IRQ11 35
13 IRQ12 38
14 IRQ13 41 Ignored. IRQ13 can only be generated from FERR#
15 IRQ14 44 Not attached to SATA logic
16 IRQ15 47 Not attached to SATA logic
17 IOCHCK# 50 Same as ISA IOCHCK# going active.
18 PCI INTA# 53 Drive PIRQA#
19 PCI INTB# 56 Drive PIRQB#
20 PCI INTC# 59 Drive PIRQC#
21 PCI INTD# 62 Drive PIRQD#
5.11 Real Time Clock (D31:F0)
The Real Time Clock (RTC) module provides a battery backed-up date and time keeping device with two banks of static RAM with 128 bytes each, although the first bank has 114 bytes for general purpose usage. Three interrupt features are available: time of day alarm with once a second to once a month range, periodic rates of 122 µs to 500 ms, and end of update cycle notification. Seconds, minutes, hours, days, day of week, month, and year are counted. Daylight savings compensation is no longer supported. The hour is represented in twelve or twenty-four hour format, and data can be represented in BCD or binary format. The design is functionally compatible with the Motorola MS146818B. The time keeping comes from a 32.768 kHz oscillating source, which is divided to achieve an update every second. The lower 14 bytes on the lower RAM block has very specific functions. The first ten are for time and date information. The next four (0Ah to 0Dh) are registers, which configure and report RTC functions. The time and calendar data should match the data mode (BCD or binary) and hour mode (12 or 24 hour) as selected in register B. It is up to the programmer to make sure that data stored in these locations is within the reasonable values ranges and represents a possible date and time. The exception to these ranges is to store a value of C0–FFh in the Alarm bytes to indicate a don’t care situation. All Alarm conditions must match to trigger an Alarm Flag, which could trigger an Alarm Interrupt if enabled. The SET bit must be 1 while programming these locations to avoid clashes with an update cycle. Access to time and date information is done through the RAM locations. If a RAM read from the ten time and date bytes is attempted during an update cycle, the value read do not necessarily represent the true contents of those locations. Any RAM writes under the same conditions are ignored. Note: The leap year determination for adding a 29th day to February does not take into account the end-of-the-century exceptions. The logic simply assumes that all years divisible by 4 are leap years. According to the Royal Observatory Greenwich, years that are divisible by 100 are typically not leap years. In every fourth century (years divisible by 400, like 2000), the 100-year-exception is over-ridden and a leap-year occurs. Note that the year 2100 will be the first time in which the current RTC implementation would incorrectly calculate the leap-year. The PCH does not implement month/year alarms.
5.11.1 Update Cycles
An update cycle occurs once a second, if the SET bit of register B is not asserted and the divide chain is properly configured. During this procedure, the stored time and date are incremented, overflow is checked, a matching alarm condition is checked, and the time and date are rewritten to the RAM locations. The update cycle will start at least 488 µs after the UIP bit of register A is asserted, and the entire cycle does not take more than 1984 µs to complete. The time and date RAM locations (0–9) are disconnected from the external bus during this time. To avoid update and data corruption conditions, external RAM access to these locations can safely occur at two times. When a updated-ended interrupt is detected, almost 999 ms is available to read and write the valid time and date data. If the UIP bit of Register A is detected to be low, there is at least 488 µs before the update cycle begins. Warning: The overflow conditions for leap years adjustments are based on more than one date or time item. To ensure proper operation when adjusting the time, the new time and data values should be set at least two seconds before leap year occurs.
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5.11.2 Interrupts
The real-time clock interrupt is internally routed within the PCH both to the I/O APIC and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the PCH, nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is ignored. However, the High Performance Event Timers can also be mapped to IRQ8#; in this case, the RTC interrupt is blocked.
5.11.3 Lockable RAM Ranges
The RTC battery-backed RAM supports two 8-byte ranges that can be locked using the configuration space. If the locking bits are set, the corresponding range in the RAM will not be readable or writable. A write cycle to those locations will have no effect. A read cycle to those locations will not return the location’s actual value (resultant value is undefined). Once a range is locked, the range can be unlocked only by a hard reset, which will invoke the BIOS and allow it to relock the RAM range.
5.11.4 Century Rollover
The PCH detects a rollover when the Year byte (RTC I/O space, index offset 09h) transitions form 99 to 00. Upon detecting the rollover, the PCH sets the NEWCENTURY_STS bit (TCOBASE + 04h, bit 7). If the system is in an S0 state, this causes an SMI#. The SMI# handler can update registers in the RTC RAM that are associated with century value. If the system is in a sleep state (S1–S5) when the century rollover occurs, the PCH also sets the NEWCENTURY_STS bit, but no SMI# is generated. When the system resumes from the sleep state, BIOS should check the NEWCENTURY_STS bit and update the century value in the RTC RAM.
5.11.5 Clearing Battery-Backed RTC RAM
Clearing CMOS RAM in a PCH-based platform can be done by using a jumper on RTCRST# or GPI. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. Using RTCRST# to Clear CMOS A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default, the state of those configuration bits that reside in the RTC power well. When the RTCRST# is strapped to ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) will be set and those configuration bits in the RTC power well will be set to their default state. BIOS can monitor the state of this bit, and manually clear the RTC CMOS array once the system is booted. The normal position would cause RTCRST# to be pulled up through a weak pull-up resistor. Table 5-19 shows which bits are set to their default state when RTCRST# is asserted. This RTCRST# jumper technique allows the jumper to be moved and then replaced—all while the system is powered off. Then, once booted, the RTC_PWR_STS can be detected in the set state.
A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the setting of this GPI on system boot-up, and manually clear the CMOS array. Note: The GPI strap technique to clear CMOS requires multiple steps to implement. The system is booted with the jumper in new position, then powered back down. The jumper is replaced back to the normal position, then the system is rebooted again. Warning: Do not implement a jumper on VccRTC to clear CMOS. Table 5-19. Configuration Bits Reset by RTCRST# Assertion Bit Name Register Location Bit(s) Default State Alarm Interrupt Enable (AIE) Register B (General Configuration) (RTC_REGB) I/O space (RTC Index + 0Bh) 5X Alarm Flag (AF) Register C (Flag Register) (RTC_REGC) I/O space (RTC Index + 0Ch) 5X SWSMI_RATE_SEL General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 7:6 0 SLP_S4# Minimum Assertion Width General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 5:4 0 SLP_S4# Assertion Stretch Enable General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 3 0 RTC Power Status (RTC_PWR_STS) General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 2 0 Power Failure (PWR_FLR) General PM Configuration 3 Register (GEN_PMCON_3) D31:F0:A4h 1 0 AFTERG3_EN General PM Configuration 3 Register GEN_PMCON_3 D31:F0:A4h 0 0 Power Button Override Status (PRBTNOR_STS) Power Management 1 Status Register (PM1_STS) PMBase + 00h 11 0 RTC Event Enable (RTC_EN) Power Management 1 Enable Register (PM1_EN) PMBase + 02h 10 0 Sleep Type (SLP_TYP) Power Management 1 Control (PM1_CNT) PMBase + 04h 12:10 0 PME_EN General Purpose Event 0 Enables Register (GPE0_EN) PMBase + 2Ch 11 0 BATLOW_EN General Purpose Event 0 Enables Register (GPE0_EN) PMBase + 2Ch 10 0 RI_EN General Purpose Event 0 Enables Register (GPE0_EN) PMBase + 2Ch 8 0 NEWCENTURY_ST S TCO1 Status Register (TCO1_STS) TCOBase + 04h 7 0 Intruder Detect (INTRD_DET) TCO2 Status Register (TCO2_STS) TCOBase + 06h 0 0 Top Swap (TS) Backed Up Control Register (BUC) Chipset Config Registers:Offset 3414h 0X
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5.12 Processor Interface (D31:F0)
The PCH interfaces to the processor with following pin-based signals other than DMI:
- Standard Outputs to processor: A20GATE, INIT3_3V#, PROCPWRGD, PMSYNCH, PECI.
- Standard Input from processor: THRMTRIP#. Most PCH outputs to the processor use standard buffers. The PCH has separate V_CPU_IO signals that are pulled up at the system level to the processor voltage, and thus determines VOH for the outputs to the processor. The following Processor interface legacy pins were removed from the PCH:
- IGNNE#, STPCLK#, DPSLP#, are DPRSLPVR are no longer required on PCH based systems.
- A20M#, SMI#, NMI, INIT#, INTR, FERR#: Functionality has been replaced by in- band Virtual Legacy Wire (VLW) messages. See Section 5.12.3.
5.12.1 Processor Interface Signals and VLW Messages
This section describes each of the signals that interface between the PCH and the processor(s). Note that the behavior of some signals may vary during processor reset, as the signals are used for frequency strapping.
5.12.1.1 A20M# (Mask A20) / A20GATE
The A20M# VLW message is asserted when both of the following conditions are true:
- The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0.
- The A20GATE input signal is a 0. The A20GATE input signal is expected to be generated by the external microcontroller (KBC).
5.12.1.2 INIT (Initialization)
The INIT# VLW Message is asserted based on any one of several events described in Table 5-20. When any of these events occur, INIT# is asserted for 16 PCI clocks, then driven high. Note: INIT3_3V# is functionally identical to INIT# VLW but it is a physical signal at 3.3 V on desktop SKUs only.
5.12.1.3 FERR# (Numeric Coprocessor Error)
The PCH supports the coprocessor error function with the FERR# message. The function is enabled using the CEN bit. If FERR# is driven active by the processor, IRQ13 goes active (internally). When it detects a write to the COPROC_ERR register (I/O Register F0h), the PCH negates the internal IRQ13 and IGNNE# will be active. IGNNE# remains active until FERR# is driven inactive. IGNNE# is never driven active unless FERR# is active. Note: IGNNE# (Ignore Numeric Error is now internally generated by the processor. Table 5-20. INIT# Going Active Cause of INIT3_3V# Going Active Comment Shutdown special cycle from processor observed on PCH-Processor interconnect. INIT assertion based on value of Shutdown Policy Select register (SPS) PORT92 write, where INIT_NOW (bit 0) transitions from a 0 to a 1. PORTCF9 write, where SYS_RST (bit 1) was a 0 and RST_CPU (bit 2) transitions from 0 to 1. RCIN# input signal goes low. RCIN# is expected to be driven by the external microcontroller (KBC). 0 to 1 transition on RCIN# must occur before the PCH will arm INIT3_3V# to be generated again. NOTE: RCIN# signal is expected to be low during S3, S4, and S5 states. Transition on the RCIN# signal in those states (or the transition to those states) may not necessarily cause the INIT3_3V# signal to be generated to the processor. CPU BIST To enter BIST, software sets CPU_BIST_EN bit and then does a full processor reset using the CF9 register.
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5.12.1.4 NMI (Non-Maskable Interrupt)
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in Table 5-21.
5.12.1.5 Processor Power Good (PROCPWRGD)
This signal is connected to the processor’s VCCPRWGOOD_0 and VCCPRWGOOD_1 input. This signal represents a logical AND of the PCH’s PWROK and SYS_PWROK signals.
5.12.2 Dual-Processor Issues
5.12.2.1 Usage Differences
In dual-processor designs, some of the processor signals are unused or used differently than for uniprocessor designs.
- A20M#/A20GATE and FERR# are generally not used, but still supported.
- I/O APIC and SMI# are assumed to be used.
5.12.3 Virtual Legacy Wire (VLW) Messages
The PCH supports VLW messages as alternative method of conveying the status of the following legacy sideband interface signals to the processor:
- A20M#, INTR, SMI#, INIT#, NMI Note: IGNNE# VLW message is not required to be generated by the PCH as it is internally emulated by the Processor. VLW are inbound messages to the processor. They are communicated using Vendor Defined Message over the DMI link. Legacy processor signals can only be delivered using VLW in the PCH. Delivery of legacy processor signals (A20M#, INTR, SMI#, INIT# or NMI) using I/O APIC controller is not supported. Table 5-21. NMI Sources Cause of NMI Comment SERR# goes active (either internally, externally using SERR# signal, or using message from processor) Can instead be routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h, bit 11). IOCHK# goes active using SERIRQ# stream (ISA system Error) Can instead be routed to generate an SCI, through the NMI2SCI_EN bit (Device 31:Function 0, TCO Base + 08h, bit 11).
5.13 Power Management (D31:F0)
5.13.1 Features
- Support for Advanced Configuration and Power Interface, Version 3.0b (ACPI) providing power and thermal management — ACPI 24-Bit Timer SCI and SMI# Generation
- PCI PME# signal for Wake Up from Low-Power states
- System Sleep State Control — ACPI S3 state—Suspend to RAM (STR) — ACPI S4 state—Suspend-to-Disk (STD) — ACPI G2/S5 state—Soft Off (SOFF) — Power Failure Detection and Recovery
- Management Engine Power Management Support — Wake events from the Management Engine (enabled from all S-States including Catastrophic S5 conditions)
5.13.2 PCH and System Power States
Table 5-22 shows the power states defined for PCH-based platforms. The state names generally match the corresponding ACPI states. Table 5-22. General Power States for Systems Using the PCH State/ Substates Legacy Name / Description G0/S0/C0 Full On: Processor operating. Individual devices may be shut down or be placed into lower power states to save power. G0/S0/Cx Cx State: Cx states are processor power states within the S0 system state that provide for various levels of power savings. The processor initiates C-state entry and exit while interacting with the PCH. The PCH will base its behavior on the processor state. G1/S1 S1: The PCH provides the S1 messages and the S0 messages on a wake event. It is preferred for systems to use C-states than S1. G1/S3 Suspend-To-RAM (STR): The system context is maintained in system DRAM, but power is shut off to non-critical circuits. Memory is retained and refreshes continue. All external clocks stop except RTC. G1/S4 Suspend-To-Disk (STD): The context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume. G2/S5 Soft Off (SOFF): System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking. Mechanical OFF (MOFF): System context not maintained. All power is shut off except for the RTC. No “Wake” events are possible. This state occurs if the user removes the main system batteries in a mobile system, turns off a mechanical switch, or if the system power supply is at a level that is insufficient to power the “waking” logic. When system power returns, transition will depend on the state just prior to the entry to G3 and the AFTERG3_EN bit in the GEN_PMCON3 register (D31:F0, offset A4). See Table 5-28 for more details.
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Table 5-23 shows the transitions rules among the various states. Note that transitions among the various states may appear to temporarily transition through intermediate states. For example, in going from S0 to S3, it may appear to pass through the G1/S1 states. These intermediate transitions and states are not listed in the table. NOTES: 1. Some wake events can be pr eserved through power failure. 2. Transitions from the S1–S5 or G3 states to the S0 state are deferred until BATLOW# is inactive in mobile configurations. Table 5-23. State Transition Rules for the PCH Present State Transition Trigger Next State G0/S0/C0
- D M I M s g
- S L P _ E N b i t s e t
- Power Button Override
- Mechanical Off/Power Failure
- G 0 / S 0 / C x
- G 1 / S x o r G 2 / S 5 s t a t e
- G 2 / S 5
- G 3 G0/S0/Cx
- D M I M s g
- Power Button Override
- Mechanical Off/Power Failure
- G 0 / S 0 / C 0
- S 5
- G 3 G1/S1, G1/S3, or G1/S4
- Any Enabled Wake Event
- Power Button Override
- Mechanical Off/Power Failure
- G0/S0/C0 (See Note 2)
- G 2 / S 5
- G 3 G2/S5 • Any Enabled Wake Event
- Mechanical Off/Power Failure
- G0/S0/C0 (See Note 2)
- G 3 G3 • Power Returns
- Optional to go to S0/C0 (reboot) or G2/ S5 (stay off until power button pressed or other wake event). (See Notes 1 and
5.13.3 System Power Planes
The system has several independent power planes, as described in Table 5-24. Note that when a particular power plane is shut off, it should go to a 0 V level. s
5.13.4 SMI#/SCI Generation
Upon any enabled SMI event taking place while the End of SMI (EOS) bit is set, the PCH will clear the EOS bit and assert SMI to the processor, which will cause it to enter SMM space. SMI assertion is performed using a Virtual Legacy Wire (VLW) message. Prior system generations (those based upon legacy processors) used an actual SMI# pin. Once the SMI VLW has been delivered, the PCH takes no action on behalf of active SMI events until Host software sets the End of SMI (EOS) bit. At that point, if any SMI events are still active, the PCH will send another SMI VLW message. The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the 8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed to level mode for that interrupt. Table 5-24. System Power Plane Plane Controlled By Description CPU SLP_S3# signal The SLP_S3# signal can be used to cut the power to the processor completely. MAIN SLP_S3# signal When SLP_S3# goes active, power can be shut off to any circuit not required to wake the system from the S3 state. Since the S3 state requires that the memory context be preserved, power must be retained to the main memory. The processor, devices on the PCI bus, LPC I/F, and graphics will typically be shut off when the Main power plane is off, although there may be small subsections powered. MEMORY SLP_S4# signal SLP_S5# signal When SLP_S4# goes active, power can be shut off to any circuit not required to wake the system from the S4. Since the memory context does not need to be preserved in the S4 state, the power to the memory can also be shut down. When SLP_S5# goes active, power can be shut off to any circuit not required to wake the system from the S5 state. Since the memory context does not need to be preserved in the S5 state, the power to the memory can also be shut. ME SLP_M# This pin is asserted when the manageability platform goes to MOff. Depending on the platform, this pin may be used to control the Management Engine power planes, the clock chip power, LAN subsystem power, and the SPI flash power. LAN SLP_LAN# This signal is asserted in Sx/Moff when both host and Intel ® ME WOL are not supported. This signal can be use to control power to the Intel 82567 GbE PHY and depending on platform design may also control power to VccME3_3. DEVICE[n] Implementation Specific Individual subsystems may have their own power plane. For example, GPIO signals may be used to control the power to disk drives, audio amplifiers, or the display screen.
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In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or 23. The interrupt polarity changes depending on whether it is on an interrupt shareable with a PIRQ or not (see Section 13.1.3). The interrupt remains asserted until all SCI sources are removed. Table 5-25 shows which events can cause an SMI and SCI. Note that some events can be programmed to cause either an SMI or SCI. The usage of the event for SCI (instead of SMI) is typically associated with an ACPI-based system. Each SMI or SCI source has a corresponding enable and status bit. Table 5-25. Causes of SMI and SCI (Sheet 1 of 2) Cause SCI SMI Additional Enables Where Reported PME# Yes Yes PME_EN=1 PME_STS PME_B0 (Internal, Bus 0, PME- Capable Agents) Yes Yes PME_B0_EN=1 PME_B0_STS PCI Express* PME Messages Yes Yes PCI_EXP_EN=1 (Not enabled for SMI) PCI_EXP_STS PCI Express Hot Plug Message Yes Yes HOT_PLUG_EN=1 (Not enabled for SMI) HOT_PLUG_STS Power Button Press Yes Yes PWRBTN_EN=1 PWRBTN_STS Power Button Override (Note 7) Yes No None PRBTNOR_STS RTC Alarm Yes Yes RTC_EN=1 RTC_STS Ring Indicate Yes Yes RI_EN=1 RI_STS USB#1 wakes Yes Yes USB1_EN=1 USB1_STS USB#2 wakes Yes Yes USB2_EN=1 USB2_STS USB#3 wakes Yes Yes USB3_EN=1 USB3_STS USB#4 wakes Yes Yes USB4_EN=1 USB4_STS USB#5 wakes Yes Yes USB5_EN=1 USB5_STS USB#6 wakes Yes Yes USB6_EN=1 USB6_STS USB#7 wakes Yes Yes USB7_EN=1 USB7_STS ACPI Timer overflow (2.34 sec.) Yes Yes TMROF_EN=1 TMROF_STS Any GPI[15:0] Yes Yes GPI[x]_Route=10; GPI[x]_EN=1 (SCI) GPI[x]_Route=01; ALT_GPI_SMI[x]_EN=1 (SMI) GPI[x]_STS ALT_GPI_SMI[x]_STS GPIO[27] Yes Yes GP27_EN=1 GP27_STS TCO SCI Logic Yes No TCOSCI_EN=1 TCOSCI_STS TCO SCI message from CPU Yes No none CPUSCI_STS TCO SMI Logic No Yes TCO_EN=1 TCO_STS TCO SMI—Year 2000 Rollover No Yes none NEWCENTURY_STS TCO SMI—TCO TIMEROUT No Yes none TIMEOUT TCO SMI—OS writes to TCO_DAT_IN register No Yes none OS_TCO_SMI TCO SMI—Message from CPU No Yes none CPUSMI_STS TCO SMI—NMI occurred (and NMIs mapped to SMI) No Yes NMI2SMI_EN=1 NMI2SMI_STS
NOTES: 1. SCI_EN must be 1 to enable SCI, except fo r BIOS_RLS. SCI_EN must be 0 to enable SMI. 2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode). 3. GBL_SMI_EN must be 1 to enable SMI. 4. EOS must be written to 1 to re-enable SMI for the next 1. 5. The PCH must have SMI fully enabled when the PCH is also enabled to trap cycles. If SMI is not enabled in conjunction with the trap enabling, then hardware behavior is undefined. 6. Only GPI[15:0] may generate an SMI or SCI. 7. When a power button override first occurs, th e system will transition immediately to S5. The SCI will only occur after the next wake to S0 if the residual status bit (PRBTNOR_STS) is not cleared prior to setting SCI_EN. 8. GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set. Software must take great care not to set the BIOS_RLS bit (which causes GBL_STS to be set) if the SCI handler is not in place. TCO SMI—INTRUDER# signal goes active No Yes INTRD_SEL=10 INTRD_DET TCO SMI—Change of the BIOSWE (D31:F0:DCh, bit 0) bit from 0 to 1 No Yes BLE=1 BIOSWR_STS TCO SMI—Write attempted to BIOS No Yes BIOSWE=1 BIOSWR_STS BIOS_RLS written to Yes No GBL_EN=1 GBL_STS GBL_RLS written to No Yes BIOS_EN=1 BIOS_STS Write to B2h register No Yes APMC_EN = 1 APM_STS Periodic timer expires No Yes PERIODIC_EN=1 PERIODIC_STS 64 ms timer expires No Yes SW SMI_TMR_EN=1 SWSMI_TMR_STS Enhanced USB Legacy Support Event No Yes LEGACY_USB2_EN = 1 LEGACY_USB2_STS Enhanced USB Intel Specific Event No Yes INTEL_USB2_EN = 1 INTEL_USB2_STS Serial IRQ SMI reported No Yes none SERIRQ_SMI_STS Device monitors match address in its range No Yes none DEVTRAP_STS SMBus Host Controller No Yes SMB_SMI_EN Host Controller Enabled SMBus host status reg. SMBus Slave SMI message No Yes none SMBUS_SMI_STS SMBus SMBALERT# signal active No Yes none SMBUS_SMI_STS SMBus Host Notify message received No Yes HOST_NOTIFY_INTREN SMBUS_SMI_STS HOST_NOTIFY_STS (Mobile Only) BATLOW# assertion Yes Yes BATLOW_EN=1 BATLOW_STS Access microcontroller 62h/66h No Yes MCSMI_EN MCSMI_STS SLP_EN bit written to 1 No Yes SMI_ON_SLP_EN=1 SMI_ON_SLP_EN_STS SPI Command Completed No Yes None SPI_SMI_STS Software Generated GPE Yes Yes SWGPE=1 SWGPE_STS USB Per-Port Registers Write Enable bit changes to 1 No Yes USB2_EN=1, Write_Enable_SMI_Enable=1 USB2_STS, Write Enable Status GPIO Lockdown Enable bit changes from ‘1’ to ‘0’ No Yes GPIO_UNLOCK_SMI_EN=1 GPIO_UNLOCK_SMI_STS Table 5-25. Causes of SMI and SCI (Sheet 2 of 2) Cause SCI SMI Additional Enables Where Reported
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5.13.4.1 PCI Express* SCI
PCI Express ports and the processor (using DMI) have the ability to cause PME using messages. When a PME message is received, the PCH will set the PCI_EXP_STS bit. If the PCI_EXP_EN bit is also set, the PCH can cause an SCI using the GPE1_STS register.
5.13.4.2 PCI Express* Hot-Plug
PCI Express has a Hot-Plug mechanism and is capable of generating a SCI using the GPE1 register. It is also capable of generating an SMI. However, it is not capable of generating a wake event.
5.13.5 C-States
PCH-based systems implement C-states by having the processor control the states. The chipset exchanges messages with the processor as part of the C-state flow, but the chipset no longer directly controls any of the processor impacts of C-states, such as voltage levels or processor clocking. In addition to the new messages, the PCH also provides additional information to the processor using a sideband pin (PM_SYNC). All of the legacy C-state related pins (STPCLK#, STP_CPU#, DPRSLP#, DPRSLPVR#, etc.) do not exist on the PCH.
5.13.6 Dynamic PCI Clock Control (Mobile Only)
The PCI clock can be dynamically controlled independent of any other low-power state. This control is accomplished using the CLKRUN# protocol as described in the PCI Mobile Design Guide, and is transparent to software. The Dynamic PCI Clock control is handled using the following signals:
- CLKRUN#: Used by PCI and LPC peripherals to request the system PCI clock to run
- STP_PCI#: Used to stop the system PCI clock Note: The 33 MHz clock to the PCH is “free-running” and is not affected by the STP_PCI# signal. Note: STP_PCI# is only used if PCI/LPC clocks are distributed from clock synthesizer rather than PCH.
5.13.6.1 Conditions for Checking the PCI Clock
When there is a lack of PCI activity the PCH has the capability to stop the PCI clocks to conserve power. “PCI activity” is defined as any activity that would require the PCI clock to be running. Any of the following conditions will indicate that it is not okay to stop the PCI clock:
- C y c l e s o n P C I o r L P C
- Cycles of any internal device that would need to go on the PCI bus
- SERIRQ activity Behavioral Description
- When there is a lack of activity (as de fined above) for 29 PCI clocks, the PCH de- asserts (drive high) CLKRUN# for 1 clock and then tri-states the signal.
5.13.6.2 Conditions for Ma intaining the PCI Clock
PCI masters or LPC devices that wish to maintain the PCI clock running will observe the CLKRUN# signal de-asserted, and then must re-assert if (drive it low) within 3 clocks.
- When the PCH has tri-stated the CLKRUN # signal after de-asserting it, the PCH then checks to see if the signal has been re-asserted (externally).
- After observing the CLKRUN# signal asserted for 1 clock, the PCH again starts asserting the signal.
- If an internal device needs the PCI bu s, the PCH asserts the CLKRUN# signal.
5.13.6.3 Conditions for Stopping the PCI Clock
- If no device re-asserts CLKRUN# once it has been de-asserted for at least 6 clocks, the PCH stops the PCI clock by asserting the STP_PCI# signal to the clock synthesizer.
- For case when PCH distribute PCI clock, PCH stop PCI clocks without the involvement of STP_PCI#.
5.13.6.4 Conditions for Re -Starting the PCI Clock
- A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started.
- When the PCH observes the CLKRUN# signal asserted for 1 (free running) clock, the PCH de-asserts the STP_PCI# signal to the clock synthesizer within 4 (free running) clocks.
- Observing the CLKRUN# signal asserted ex ternally for 1 (free running) clock, the PCH again starts driving CLKRUN# asserted. If an internal source requests the clock to be re-started, the PCH re-asserts CLKRUN#, and simultaneously de-asserts the STP_PCI# signal. For case when PCH distribute PCI clock, PCH start PCI clocks without the involvement of STP_PCI#.
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5.13.6.5 LPC Devices and CLKRUN#
If an LPC device (of any type) needs the 33 MHz PCI clock, such as for LPC DMA or LPC serial interrupt, then it can assert CLKRUN#. Note that LPC devices running DMA or bus master cycles will not need to assert CLKRUN#, since the PCH asserts it on their behalf. The LDRQ# inputs are ignored by the PCH when the PCI clock is stopped to the LPC devices to avoid misinterpreting the request. The PCH assumes that only one more rising PCI clock edge occurs at the LPC device after the assertion of STP_PCI#. Upon de-assertion of STP_PCI#, the PCH assumes that the LPC device receives its first clock rising edge corresponding to the PCH’s second PCI clock rising edge after the de- assertion.
5.13.7 Sleep States
5.13.7.1 Sleep State Overview
The PCH directly supports different sleep states (S1–S5), which are entered by methods such as setting the SLP_EN bit or due to a Power Button press. The entry to the Sleep states is based on several assumptions:
- The G3 state cannot be entered using any software mechanism. The G3 state indicates a complete loss of power.
5.13.7.2 Initiating Sleep State
Sleep states (S1–S5) are initiated by:
- Masking interrupts, turning off all bus master enable bits, setting the desired type in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts to gracefully put the system into the corresponding Sleep state.
- Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button Override event. In this case the transition to the S5 state is less graceful, since there are no dependencies on DMI messages from the processor or on clocks other than the RTC clock.
- Assertion of the THRMTRIP# signal will cause a transition to the S5 state. This can occur when system is in S0 or S1 state.
- Shutdown by integrated mana geability functions (ASF/Intel® AMT).
- Internal watchdog timer timeout events. Table 5-26. Sleep Types Sleep Type Comment S1 System lowers the processor’s power consumption. No snooping is possible in this state. The PCH asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical circuits. Power is only retained to devices needed to wake from this sleeping state, as well as to the memory. The PCH asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to the memory subsystem. Only devices needed to wake from this state should be powered. S5 The PCH asserts SLP_S3#, SLP_S4# and SLP_S5#.
5.13.7.3 Exiting Sleep States
Sleep states (S1–S5) are exited based on Wake events. The Wake events forces the system to a full on state (S0), although some non-critical subsystems might still be shut off and have to be brought back manually. For example, the hard disk may be shut off during a sleep state and have to be enabled using a GPIO pin before it can be used. Upon exit from the PCH-controlled Sleep states, the WAK_STS bit is set. The possible causes of Wake Events (and their restrictions) are shown in Table 5-27. Note: (Mobile Only) If the BATLOW# signal is asserted, the PCH does not attempt to wake from an S1–S5 state, even if the power button is pressed. This prevents the system from waking when the battery power is insufficient to wake the system. Wake events that occur while BATLOW# is asserted are latched by the PCH, and the system wakes after BATLOW# is de-asserted. Table 5-27 Causes of Wake Events (Sheet 1 of 2) Cause How Enabled Wake from S1, Sx Wake from S1, Sx After Power Loss (Note 1) Wake from “Reset” Types (Note 2) RTC Alarm Set RTC_EN bit in PM1_EN register. Y Y Power Button Always enabled as Wake event. Y Y Y GPI[15:0] GPE0_EN register Note: GPIs that are in the core well are not capable of waking the system from sleep states when the core well is not powered. Y GPIO27 Set GP27_EN in GPE0_EN Register. Y Y Y LAN Will use PME#. Wake enable set with LAN logic. YY RI# Set RI_EN bit in GPE0_EN register. Y Y Intel ® High Definition Audio Event sets PME_B0_STS bit; PM_B0_EN must be enabled. Can not wake from S5 state if it was entered due to power failure or power button override. YY Primary PME# PME_B0_EN bit in GPE0_EN register. Y Y Secondary PME# Set PME_EN bit in GPE0_EN register. Y Y PCI_EXP_WA KE# PCI_EXP_WAKE bit. (Note 3) Y Y SATA Set PME_EN bit in GPE0_EN register. (Note 4) S1 S1 PCI_EXP PME Message Must use the PCI Express* WAKE# pin rather than messages for wake from S3, S4, or S5. S1 S1 SMBALERT# Always enabled as Wake event. Y Y Y
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NOTES: 1. This column represen ts what the PCH would honor as wake events but there may be enabling dependencies on the device side which are not enabled after a power loss. 2. Reset Types include: Power Button override, In tel ME initiated power button override, Intel ME initiated host partition reset with power down, Intel ME Watchdog Timer, SMBus unconditional power down, Processor thermal trip, PCH catastrophic temperature event. 3. When the WAKE# pin is active and the PCI Ex press device is enabled to wake the system, the PCH will wake the platform. 4. SATA can only trigger a wake event in S1, bu t if PME is asserted prior to S3/S4/S5 entry and software does not clear the PME_B0_STS, a wake event would still result. It is important to understand that the various GPIs have different levels of functionality when used as wake events. The GPIs that reside in the core power well can only generate wake events from sleep states where the core well is powered. Also, only certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits reside in ACPI I/O space. Table 5-27 summarizes the use of GPIs as wake events. The latency to exit the various Sleep states varies greatly and is heavily dependent on power supply design, so much so that the exit latencies due to the PCH are insignificant. SMBus Slave Wake Message (01h) Wake/SMI# command always enabled as a Wake event. Note: SMBus Slave Message can wake the system from S1–S5, as well as from S5 due to Power Button Override. YYY SMBus Host Notify message received HOST_NOTIFY_WKEN bit SMBus Slave Command register. Reported in the SMB_WAK_STS bit in the GPEO_STS register. YYY Intel ® ME Non-Maskable Wake Always enabled as a wake event. Y Y Y Integrated WOL Enable Override WOL Enable Override bit (in Configuration Space). Y Y Y Table 5-27 Causes of Wake Events (Sheet 2 of 2) Cause How Enabled Wake from S1, Sx Wake from S1, Sx After Power Loss (Note 1) Wake from “Reset” Types (Note 2) Table 5-27. GPI Wake Events GPI Power Well Wake From Notes GPI[7:0] Core S1 ACPI Compliant GPI[15:8] Suspend S1–S5 ACPI Compliant
5.13.7.4 PCI Express* WAKE# Signal and PME Event Message
PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5) using the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go active in the GPE_STS register. PCI Express ports and the processor (using DMI) have the ability to cause PME using messages. When a PME message is received, the PCH will set the PCI_EXP_STS bit.
5.13.7.5 Sx-G3-Sx, Ha ndling Power Failures
Depending on when the power failure occurs and how the system is designed, different transitions could occur due to a power failure. The AFTERG3_EN bit provides the ability to program whether or not the system should boot once power returns after a power loss event. If the policy is to not boot, the system remains in an S5 state (unless previously in S4). There are only three possible events that will wake the system after a power failure. 1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low (G3 state), the PWRBTN_STS bit is reset. When the PCH exits G3 after power returns (RSMRST# goes high), the PWRBTN# signal is already high (because VCC- standby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0. 2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a wake event, it is important to keep this signal powered during the power loss event. If this signal goes low (active), when power returns the RI_STS bit is set and the system interprets that as a wake event. 3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss. Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low. The PCH monitors both PCH PWROK and RSMRST# to detect for power failures. If PCH PWROK goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set. Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.
5.13.8 Event Input Signals and Their Usage
The PCH has various input signals that trigger specific events. This section describes those signals and how they should be used. Table 5-28. Transitions Due to Power Failure State at Power Failure AFTERG3_EN bit Transition When Power Returns S0, S1, S3 1 S4 1 S5 1
182 Datasheet
5.13.8.1 PWRBTN# (Power Button)
The PCH PWRBTN# signal operates as a “Fixed Power Button” as described in the Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16 ms de-bounce on the input. The state transition descriptions are included in Table 5-29. Note that the transitions start as soon as the PWRBTN# is pressed (but after the debounce logic), and does not depend on when the Power Button is released. Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width (if enabled), the Power Button is not a wake event. See Power Button Override Function section below for further detail. Power Button Override Function If PWRBTN# is observed active for at least four consecutive seconds, the state machine should unconditionally transition to the G2/S5 state, regardless of present state (S0–S4), even if the PCH PWROK is not active. In this case, the transition to the G2/S5 state should not depend on any particular response from the processor (such as, a DMI Messages), nor any similar dependency from any other subsystem. The PWRBTN# status is readable to check if the button is currently being pressed or has been released. The status is taken after the de-bounce, and is readable using the PWRBTN_LVL bit. Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The 4-second timer starts counting when the PCH is in a S0 state. If the PWRBTN# signal is asserted and held active when the system is in a suspend state (S1–S5), the assertion causes a wake event. Once the system has resumed to the S0 state, the 4-second timer starts. Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width (if enabled by D31:F0:A4h bit 3), the Power Button is not a wake event. As a result, it is conceivable that the user will press and continue to hold the Power Button waiting for the system to awake. Since a 4-second press of the Power Button is already defined as an Unconditional Power down, the power button timer will be forced to inactive while the power-cycle timer is in progress. Once the power-cycle timer has expired, the Power Button awakes the system. Once the minimum SLP_S4# power cycle expires, the Power Button must be pressed for another 4 to 5 seconds to create the Override condition to S5. Table 5-29. Transitions Due to Power Button Present State Event Transition/Action Comment S0/Cx PWRBTN# goes low SMI or SCI generated (depending on SCI_EN, PWRBTN_EN and GLB_SMI_EN) Software typically initiates a Sleep state S1–S5 PWRBTN# goes low Wake Event. Transitions to S0 state Standard wakeup G3 PWRBTN# pressed None No effect since no power Not latched nor detected S0–S4 PWRBTN# held low for at least 4 consecutive seconds Unconditional transition to S5 state No dependence on processor (DMI Messages) or any other subsystem
The Advanced Configuration and Power Interface, Version 2.0b defines an optional Sleep button. It differs from the power button in that it only is a request to go from S0 to S1–S4 (not S5). Also, in an S5 state, the Power Button can wake the system, but the Sleep Button cannot. Although the PCH does not include a specific signal designated as a Sleep Button, one of the GPIO signals can be used to create a “Control Method” Sleep Button. See the Advanced Configuration and Power Interface, Version 2.0b for implementation details.
5.13.8.2 RI# (Ring Indicator)
The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states. Table 5-30 shows when the wake event is generated or ignored in different states. If in the G0/S0/Cx states, the PCH generates an interrupt based on RI# active, and the interrupt will be set up as a Break event. Note: Filtering/Debounce on RI# will not be done in PCH. Can be in modem or external.
5.13.8.3 PME# (PCI Power Management Event)
The PME# signal comes from a PCI device to request that the system be restarted. The PME# signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs when the PME# signal goes from high to low. No event is caused when it goes from low to high. There is also an internal PME_B0 bit. This is separate from the external PME# signal and can cause the same effect.
5.13.8.4 SYS_RESET# Signal
When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the PCH attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to go idle. If the SMBus is idle when the pin is detected active, the reset occurs immediately; otherwise, the counter starts. If at any point during the count the SMBus goes idle the reset occurs. If, however, the counter expires and the SMBus is still active, a reset is forced upon the system even though activity is still occurring. Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the SYS_RESET# input remains asserted or not. It cannot occur again until SYS_RESET# has been detected inactive after the debounce logic, and the system is back to a full S0 state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then SYS_RESET# will result in a full power cycle reset.
5.13.8.5 THRMTRIP# Signal
If THRMTRIP# goes active, the processor is indicating an overheat condition, and the PCH immediately transitions to an S5 state, driving SLP_S3#, SLP_S4#, SLP_S5# low, and setting the CTS bit. The transition looks like a power button override. Table 5-30. Transitions Due to RI# Signal Present State Event RI_EN Event S0 RI# Active X Ignored S1–S5 RI# Active 0 Ignored Wake Event
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When a THRMTRIP# event occurs, the PCH will power down immediately without following the normal S0 -> S5 path. The PCH will immediately drive SLP_S3#, SLP_S4#, and SLP_S5# low after sampling THRMTRIP# active. If the processor is running extremely hot and is heating up, it is possible (although very unlikely) that components around it, such as the PCH, are no longer executing cycles properly. Therefore, if THRMTRIP# goes active, and the PCH is relying on state machine logic to perform the power down, the state machine may not be working, and the system will not power down. The PCH provides filtering for short low glitches on the THRMTRIP# signal to prevent erroneous system shut downs from noise. Glitches shorter than 25 nsec are ignored. During boot, THRMTRIP# is ignored until SLP_S3#, PWROK, and PLTRST# are all ‘1’. During entry into a powered-down state (due to S3, S4, S5 entry, power cycle reset, etc.) THRMTRIP# is ignored until either SLP_S3# = 0, or PCH PWROK = 0, or SYS_PWROK = 0. Note: A thermal trip event will:
- Clear the PWRBTN_STS bit
- Clear all the GPE0_EN register bits
- Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave receiving message and not set due to SMBAlert
5.13.9 ALT Access Mode
Before entering a low power state, several registers from powered down parts may need to be saved. In the majority of cases, this is not an issue, as registers have read and write paths. However, several of the ISA compatible registers are either read only or write only. To get data out of write-only registers, and to restore data into read-only registers, the PCH implements an ALT access mode. If the ALT access mode is entered and exited after reading the registers of the PCH timer (8254), the timer starts counting faster (13.5 ms). The following steps listed below can cause problems: 1. BIOS enters ALT access mode for reading the PCH timer related registers. 2. BIOS exits ALT access mode. 3. BIOS continues through the execution of other needed steps and passes control to the operating system. After getting control in step #3, if the operating system does not reprogram the system timer again, the timer ticks may be happening faster than expected. For example Microsoft MS-DOS* and its associated software assume that the system timer is running at 54.6 ms and as a result the time-outs in the software may be happening faster than expected. Operating systems (such as, Microsoft Windows* 98 and Windows* 2000) reprogram the system timer and therefore do not encounter this problem. For other operating systems (such as, Microsoft MS-DOS*) the BIOS should restore the timer back to 54.6 ms before passing control to the operating system. If the BIOS is entering ALT access mode before entering the suspend state it is not necessary to restore the timer contents after the exit from ALT access mode.
5.13.9.1 Write Only Registers with Read Paths in ALT Access Mode
The registers described in Table 5-31 have read paths in ALT access mode. The access number field in the table indicates which register will be returned per access to that port. Table 5-31. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2) Restore Data Restore Data I/O Addr # of Rds Access Data I/O Addr # of Rds Access Data 00h 2
1 DMA Chan 0 base address
1 Timer Counter 0 status, bits
[5:0]
2 DMA Chan 0 base address
high byte 2 Timer Counter 0 base count low byte 01h 2
1 DMA Chan 0 base count low
byte 3 Timer Counter 0 base count high byte
2 DMA Chan 0 base count high
byte 4 Timer Counter 1 base count low byte 02h 2
1 DMA Chan 1 base address
low byte 5 Timer Counter 1 base count high byte
2 DMA Chan 1 base address
high byte 6 Timer Counter 2 base count low byte 03h 2
1 DMA Chan 1 base count low
byte 7 Timer Counter 2 base count high byte
2 DMA Chan 1 base count high
byte 41h 1 Timer Counter 1 status, bits [5:0] 04h 2
1 DMA Chan 2 base address
low byte 42h 1 Timer Counter 2 status, bits [5:0]
2 DMA Chan 2 base address
high byte 70h 1 Bit 7 = NMI Enable, Bits [6:0] = RTC Address 05h 2
1 DMA Chan 2 base count low
1 DMA Chan 5 base address
2 DMA Chan 2 base count high
byte 2 DMA Chan 5 base address high byte 06h 2
1 DMA Chan 3 base address
1 DMA Chan 5 base count low
2 DMA Chan 3 base address
high byte 2 DMA Chan 5 base count high byte 07h 2
1 DMA Chan 3 base count low
1 DMA Chan 6 base address
2 DMA Chan 3 base count high
byte 2 DMA Chan 6 base address high byte
186 Datasheet
NOTES: 1. The OCW1 register must be read before entering ALT access mode. 2. Bits 5, 3, 1, and 0 return 0. 08h 6
1 DMA Chan 0–3 Command 2
1 DMA Chan 6 base count low
2 DMA Chan 0–3 Request 2 DMA Chan 6 base count
3 DMA Chan 0 Mode:
Bits(1:0) = 00 CCh 2
1 DMA Chan 7 base address
4 DMA Chan 1 Mode:
Bits(1:0) = 01 2 DMA Chan 7 base address high byte
5 DMA Chan 2 Mode:
Bits(1:0) = 10 CEh 2
1 DMA Chan 7 base count low
6 DMA Chan 3 Mode: Bits(1:0)
= 11. 2 DMA Chan 7 base count high byte 20h 12
1 PIC ICW2 of Master controller
1 DMA Chan 4–7 Command 2
2 PIC ICW3 of Master controller 2 DMA Chan 4–7 Request
3 PIC ICW4 of Master controller 3 DMA Chan 4 Mode:
Bits(1:0) = 00
4 PIC OCW1 of Master
controller1 4 DMA Chan 5 Mode: Bits(1:0) = 01
5 PIC OCW2 of Master
controller 5 DMA Chan 6 Mode: Bits(1:0) = 10
6 PIC OCW3 of Master
controller 6 DMA Chan 7 Mode: Bits(1:0) = 11.
7 PIC ICW2 of Slave controller
8 PIC ICW3 of Slave controller
9 PIC ICW4 of Slave controller
10 PIC OCW1 of Slave
11 PIC OCW2 of Slave controller
12 PIC OCW3 of Slave controller
Table 5-31. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2) Restore Data Restore Data I/O Addr # of Rds Access Data I/O Addr # of Rds Access Data
5.13.9.2 PIC Reserved Bits
Many bits within the PIC are reserved, and must have certain values written for the PIC to operate properly. Therefore, there is no need to return these values in ALT access mode. When reading PIC registers from 20h and A0h, the reserved bits shall return the values listed in Table 5-32.
5.13.9.3 Read Only Registers with Write Paths in ALT Access Mode
The registers described in Table 5-33 have write paths to them in ALT access mode. Software restores these values after returning from a powered down state. These registers must be handled special by software. When in normal mode, writing to the base address/count register also writes to the current address/count register. Therefore, the base address/count must be written first, then the part is put into ALT access mode and the current address/count register is written.
5.13.10 System Power Supplies, Planes, and Signals
The SLP_S3# output signal can be used to cut power to the system core supply, since it only goes active for the Suspend-to-RAM state (typically mapped to ACPI S3). Power must be maintained to the PCH suspend well, and to any other circuits that need to generate Wake signals from the Suspend-to-RAM state. During S3 (Suspend-to-RAM) all signals attached to powered down plans will be tri-stated or driven low, unless they are pulled using a pull-up resistor. Cutting power to the core may be done using the power supply, or by external FETs on the motherboard. The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done using the power supply, or by external FETs on the motherboard. Table 5-32. PIC Reserved Bits Return Values PIC Reserved Bits Value Returned ICW2(2:0) 000 ICW4(7:5) 000 ICW4(3:2) 00 ICW4(0) 0 OCW2(4:3) 00 OCW3(7) 0 OCW3(5) Reflects bit 6 OCW3(4:3) 01 Table 5-33. Register Write Accesses in ALT Access Mode I/O Address Register Write Value 08h DMA Status Register for channels 0–3. D0h DMA Status Register for channels 4–7.
188 Datasheet
The SLP_S4# output signal is used to remove power to additional subsystems that are powered during SLP_S3#. SLP_S5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done using the power supply, or by external FETs on the motherboard. SLP_M# output signal can be used to cut power to the Management Engine, Clock chip and SPI flash on a platform that supports Intel ® AMT. SLP_LAN# output signal can be used to cut power to the external Intel 82567 GbE PHY device. Depending on platform design SLP_LAN# may also be used to control power to VccME3_3 if it is desired to always power the LAN and ME subsystems up and down together.
5.13.10.2 SLP_S4# and Su spend-To-RAM Sequencing
The system memory suspend voltage regulator is controlled by the Glue logic. The SLP_S4# signal should be used to remove power to system memory rather than the SLP_S5# signal. The SLP_S4# logic in the PCH provides a mechanism to fully cycle the power to the DRAM and/or detect if the power is not cycled for a minimum time. Note: To use the minimum DRAM power-down feature that is enabled by the SLP_S4# Assertion Stretch Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled by the SLP_S4# signal.
5.13.10.3 PWROK Signal
When asserted, PWROK is an indication to the PCH that its core well power rails are powered and stable. PWROK can be driven asynchronously. When PCH PWROK is low, the PCH asynchronously asserts PLTRST#. PWROK must not glitch, even if RSMRST# is low. It is required that the power associated with PCI/PCIe have been valid for 99 ms prior to PWROK assertion to comply with the 100 ms PCI 2.3 / PCIe 2.0 specification on PLTRST# de-assertion. Note: SYS_RESET# is recommended for implementing the system reset button. This saves external logic that is needed if the PWROK input is used. Additionally, it allows for better handling of the SMBus and processor resets and avoids improperly reporting power failures.
5.13.10.4 BATLOW# (Batte ry Low) (Mobile Only)
The BATLOW# input can inhibit waking from S3, S4, and S5 states if there is not sufficient power. It also causes an SMI if the system is already in an S0 state.
5.13.10.5 SLP_LAN# Pin Behavior
Table 5-34 summarizes SLP_LAN# pin behavior.
5.13.10.6 RTCRST# and SRTCRST#
RTCRST# is used to reset PCH registers in the RTC Well to their default value. If a jumper is used on this pin, it should only be pulled low when system is in the G3 state and then replaced to the default jumper position. Upon booting, BIOS should recognize that RTCRST# was asserted and clear internal PCH registers accordingly. It is imperative that this signal not be pulled low in the S0 to S5 states. SRTCRST# is used to reset portions of the Intel Manageability Engine and should not be connected to a jumper or button on the platform. The only time this signal gets asserted (driven low in combination with RTCRST#) should be when the coin cell battery is removed or not installed and the platform is in the G3 state. Pulling this signal low independently (without RTCRST# also being driven low) may cause the platform to enter an indeterminate state. Similar to RTCRST#, it is imperative that SRTCRST# not be pulled low in the S0 to S5 states. See Figure 2-2 which demonstrates the proper circuit connection of these pins.
5.13.11 Clock Generators
The clock generator is expected to provide the frequencies shown in Table 4-1. Table 5-34. SLP_LAN# Pin Behavior Pin Functionality (Determined by soft strap) SLP_LAN Default Value Bit GPIO29 Input / Output (Determined by GP_IO_SEL bit) Pin Value In S0 or M3 Value in S3-S5/ Moff SLP_LAN# 0 (Default) In (Default) 1 0 Out 1 Depends on GPIO29 output data value In (Default) 1 1 Out 1 Depends on GPIO29 output data value GPIO29 0 (Default) In Z (tri-state) 0
1 In Z (tri-state) 1
190 Datasheet
5.13.12 Legacy Power Manageme nt Theory of Operation
Instead of relying on ACPI software, legacy power management uses BIOS and various hardware mechanisms. The scheme relies on the concept of detecting when individual subsystems are idle, detecting when the whole system is idle, and detecting when accesses are attempted to idle subsystems. However, the operating system is assumed to be at least APM enabled. Without APM calls, there is no quick way to know when the system is idle between keystrokes. The PCH does not support burst modes.
5.13.12.1 APM Power Mana gement (Desktop Only)
The PCH has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and Enable register, generates an SMI once per minute. The SMI handler can check for system activity by reading the DEVTRAP_STS register. If none of the system bits are set, the SMI handler can increment a software counter. When the counter reaches a sufficient number of consecutive minutes with no activity, the SMI handler can then put the system into a lower power state. If there is activity, various bits in the DEVTRAP_STS register will be set. Software clears the bits by writing a 1 to the bit position. The DEVTRAP_STS register allows for monitoring various internal devices, or Super I/O devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions on LPC or PCI. Other PCI activity can be monitored by checking the PCI interrupts.
5.13.12.2 Mobile APM Power Management (Mobile Only)
In mobile systems, there are additional requirements associated with device power management. To handle this, the PCH has specific SMI traps available. The following algorithm is used: 1. The periodic SMI timer checks if a device is idle for the require time. If so, it puts the device into a low-power state and sets the associated SMI trap. 2. When software (not the SMI handler) attempts to access the device, a trap occurs (the cycle doesn’t really go to the device and an SMI is generated). 3. The SMI handler turns on the device and turns off the trap. 4. The SMI handler exits with an I/O restart. This allows the original software to continue.
5.13.13 Reset Behavior
When a reset is triggered, the PCH will send a warning message to the processor to allow the processor to attempt to complete any outstanding memory cycles and put memory into a safe state before the platform is reset. When the processor is ready, it will send an acknowledge message to the PCH. Once the message is received the PCH asserts PLTRST#. The PCH does not require an acknowledge message from the processor to trigger PLTRST#. A global reset will occur after 4 seconds if an acknowledge from the processor is not received. When the PCH causes a reset by asserting PLTRST# its output signals will go to their reset states as defined in Chapter 3.
A reset in which the host platform is reset and PLTRST# is asserted is called a Host Reset or Host Partition Reset. Depending on the trigger a host reset may also result in power cycling see Table 5-37 for details. If a host reset is triggered and the PCH times out before receiving an acknowledge message from the processor a Global Reset with power cycle will occur. A reset in which the host and Intel ME partitions of the platform are reset is called a Global Reset. During a Global Reset, all PCH functionality is reset except RTC Power Well backed information and Suspend well status, configuration, and functional logic for controlling and reporting the reset. Intel ME and Host power back up after the power cycle period. Straight to S5 is another reset type where all power wells that are controlled by the SLP_S3#, SLP_S4#, and SLP_A# pins, as well as SLP_S5# and SLP_LAN# (if pins are not configured as GPIOs), are turned off. All PCH functionality is reset except RTC Power Well backed information and Suspend well status, configuration, and functional logic for controlling and reporting the reset. The host stays there until a valid wake event occurs. Table 5-35 shows the various reset triggers. Table 5-35. Causes of Host and Global Resets (Sheet 1 of 2) Trigger Host Reset without Power Cycle1 Host Reset with Power Cycle2 Global Reset with Power Cycle3 Straight to S5 (Host Stays there) Write of 0Eh to CF9h Register when Global Reset Bit=0b No Yes No (Note 4) Write of 06h to CF9h Register when Global Reset Bit=0b Yes No No (Note 4) Write of 06h or 0Eh to CF9h Register when Global Reset Bit=1b No No Yes SYS_RESET# Asserted and CF9h Bit 3 = 0 Yes No No (Note 4) SYS_RESET# Asserted and CF9h Bit 3 = 1 No Yes No (Note 4) SMBus Slave Message received for Reset with Power Cycle No Yes No (Note 4) SMBus Slave Message received for Reset without Power Cycle Yes No No (Note 4) TCO Watchdog Timer reaches zero two times Yes No No (Note 4) Power Failure: PWROK signal goes inactive in S0/S1 or RSMRST# asserts No No Yes SYS_PWROK Failure: SYS_PWROK signal goes inactive in S0/S1 No No Yes Processor Thermal Trip (THRMTRIP#) causes transition to S5 and reset asserts No No No Yes Power Button 4 second override causes transition to S5 and reset asserts No No No Yes Special shutdown cycle from processor causes CF9h-like PLTRST# and CF9h Global Reset Bit = 1 No No Yes Special shutdown cycle from processor causes CF9h-like PLTRST# and CF9h Global Reset Bit = 0 and Bit 3 = 1 No Yes No (Note 4) Special shutdown cycle from processor causes CF9h-like PLTRST# and CF9h Global Reset Bit = 0 and Bit 3 = 0 Yes No No (Note 4) Intel ® Management Engine Triggered Host Reset without power cycle Yes No No (Note 4) Intel Management Engine Triggered Host Reset with power cycle No Yes No (Note 4) Intel Management Engine Watchdog Timer Timeout No No No Yes Intel Management Engine Triggered Global Reset No No Yes
192 Datasheet
NOTES: 1. The PCH drops this type of reset request if received while the system is in S3/S4/S5. 2. PCH does not drop this type of reset reques t if received while system is in a software- entered S3/S4/S5 state. However, the PCH will perform the reset without executing the RESET_WARN protocol in these states. 3. The PCH does not send warning message to processor, reset occurs without delay. 4. Trigger will result in Global Reset with power cycle if the acknowledge message is not received by the PCH. 5. The PCH waits for enabled wa ke event to complete reset.
5.14 System Management (D31:F0)
The PCH provides various functions to make a system easier to manage and to lower the Total Cost of Ownership (TCO) of the system. Features and functions can be augmented using external A/D converters and GPIO, as well as an external microcontroller. The following features and functions are supported by the PCH:
- Processor present detection — Detects if processor fails to fetch the first instruction after reset
- Various Error detection (such as ECC Errors) indicated by host controller — Can generate SMI#, SCI, SERR, NMI, or TCO interrupt
- Intruder Detect input — Can generate TCO interrupt or SMI# when the system cover is removed — INTRUDER# allowed to go active in any power state, including G3
- Detection of bad BIOS Flash (FWH or Flash on SPI) programming — Detects if data on first read is FFh (indicates that BIOS flash is not programmed)
- Ability to hide a PCI device — Allows software to hide a PCI device in terms of configuration space through the use of a device hide register (See Section 10.1.65) Note: Voltage ID from the processor can be read using GPI signals. Intel Management Engine Triggered Host Reset with power down (host stays there) No Yes (Note 5) No (Note 4) PLTRST# Entry Time-out No No Yes S3/4/5 Entry Timeout No No No Yes PROCPWRGD Stuck Low No No Yes Power Management Watchdog Timer No No No Yes Intel Management Engine Hardware Uncorrectable Error No No No Yes Table 5-35. Causes of Host and Global Resets (Sheet 2 of 2) Trigger Host Reset without Power Cycle1 Host Reset with Power Cycle2 Global Reset with Power Cycle3 Straight to S5 (Host Stays there)
5.14.1 Theory of Operation
The System Management functions are designed to allow the system to diagnose failing subsystems. The intent of this logic is that some of the system management functionality can be provided without the aid of an external microcontroller.
5.14.1.1 Detecting a System Lockup
When the processor is reset, it is expected to fetch its first instruction. If the processor fails to fetch the first instruction after reset, the TCO timer times out twice and the PCH asserts PLTRST#.
5.14.1.2 Handling an Intruder
The PCH has an input signal, INTRUDER#, that can be attached to a switch that is activated by the system’s case being open. This input has a two RTC clock debounce. If INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the TCO2_STS register. The INTRD_SEL bits in the TCO_CNT register can enable the PCH to cause an SMI# or interrupt. The BIOS or interrupt handler can then cause a transition to the S5 state by writing to the SLP_EN bit. The software can also directly read the status of the INTRUDER# signal (high or low) by clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI if the intruder function is not required. If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes inactive. Note that this is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit. Note: The INTRD_DET bit resides in the PCH’s RTC well, and is set and cleared synchronously with the RTC clock. Thus, when software attempts to clear INTRD_DET (by writing a 1 to the bit location) there may be as much as two RTC clocks (about 65 µs) delay before the bit is actually cleared. Also, the INTRUDER# signal should be asserted for a minimum of 1 ms to ensure that the INTRD_DET bit will be set. Note: If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET bit, the bit remains set and the SMI is generated again immediately. The SMI handler can clear the INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal goes inactive and then active again, there will not be further SMIs, since the INTRD_SEL bits would select that no SMI# be generated.
5.14.1.3 Detecting Improper Flash Programming
The PCH can detect the case where the BIOS flash is not programmed. This results in the first instruction fetched to have a value of FFh. If this occurs, the PCH sets the BAD_BIOS bit. The BIOS flash may reside in FWH or flash on the SPI bus.
5.14.1.4 Heartbeat and Event Reporting using SMLink/SMBus
Heartbeat and event reporting using SMLink/SMBus is no longer supported. The AMT logic in PCH can be programmed to generate an interrupt to the Management Engine when an event occurs. The Management Engine will poll the TCO registers to gather appropriate bits to send the event message to the Gigabit Ethernet controller, if Management Engine is programmed to do so.
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5.14.2 TCO Modes
5.14.2.1 TCO Legacy/Compatible Mode
In TCO Legacy/Compatible mode, only the host SMBus is used. TCO Slave can be connected to the host SMBus internally by setting the soft trap TCO Slave Select in the flash descriptor. If a device has a single SMBus interface and needs access to the TCO slave and be visible to the host SMBus controller, TCO slave needs to be configured to be connected to the SMBus pins by the soft strap. In this mode, the Management Engine SMBus controllers are not used and should be disabled by soft strap. In TCO Legacy/Compatible mode the PCH can function directly with an external LAN controller or equivalent external LAN controller to report messages to a network management console without the aid of the system processor. This is crucial in cases where the processor is malfunctioning or cannot function due to being in a low-power state. Table 5-36 includes a list of events that will report messages to the network management console. Figure 5-5. TCO Legacy/Compati ble Mode SMBus Configuration Host SMBus TCO Slave SPD (Slave) uCtrl Legacy Sensors (Master or Slave with ALERT) TCO Legacy/Compatible Mode SMBus X Intel ME SMBus Controller 3 X X PCI/PCIe* Device 3rd Party NIC PCH Intel ME SMBus Controller 1 Intel ME SMBus Controller 2
NOTE: The GPIO11/SMBALERT# pin will trigger an event message (when enabled by the GPIO11_ALERT_DISABLE bit) regardless of whether it is configured as a GPI or not.
5.14.2.2 Advanced TCO Mode
The PCH supports the Advanced TCO mode in which SMLink0 and SMLink1 are used in addition to the host SMBus. See Figure 5-6 for more details. In this mode, the Intel ME SMBus controllers must be enabled by soft strap in the flash descriptor. The SMLink0 is dedicated to integrated LAN use and when an Intel PHY 82579 is connected to SMLink0, a soft strap must be set to indicate that the PHY is connected to SMLink0. The interface will be running at the frequency of 300 KHz - 400 KHz depending on different factors such as board routing or bus loading when the Fast Mode is enabled via a soft strap (See SPI Flash Programming Guide Application Note for more detail). When an Intel PHY 82577 or 82578 is connected to SMLink0, a soft strap must be set to indicate that the PHY is connected to SMLink0. In the case where a BMC is connected to SMLink1, the BMC communicates with Management Engine through Intel ME SMBus connected to SMLink1. The host and TCO slave communicated with BMC through SMBus. Table 5-36. Event Transiti ons that Cause Messages Event Assertion? de-assertion? Comments INTRUDER# pin yes no Must be in “S1 or hung S0” state THRM# pin yes yes Must be in “S1 or hung S0” state. Note that the THRM# pin is isolated when the core power is off, thus preventing this event in S3–S5. Watchdog Timer Expired yes no (NA) “S1 or hung S0” state entered GPIO[11]/ SMBALERT# pin yes yes Must be in “S1 or hung S0” state BATLOW# yes yes Must be in “S1 or hung S0” state CPU_PWR_FLR yes no “S1 or hung S0” state entered
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Figure 5-6. Advanced TCO Mode Host SMBus TCO Slave SPD (Slave) Legacy Sensors (Master or Slave with ALERT) Advanced TCO Mode SMBus SMLink0 Intel ME SMBus Controller 3 EC or BMC Intel 82577 or 82578 SMLink1 PCH Intel ME SMBus Controller 2 Intel ME SMBus Controller 1 PCI/PCIe* Device
5.15 General Purpose I/O (D31:F0)
The PCH contains up to 72 General Purpose Input/Output (GPIO) signals. Each GPIO can be configured as an input or output signal. The number of inputs and outputs varies depending on the configuration. Below is a brief summary of new GPIO features.
- Capability to mask Suspend well GPIOs from CF9h events configured using GP_RST_SEL registers)
- Added capability to program GPIO prior to switching to output
5.15.1 Power Wells
Some GPIOs exist in the suspend power plane. Care must be taken to make sure GPIO signals are not driven high into powered-down planes. Some PCH GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button Override event results in the PCH driving a pin to a logic 1 to another device that is powered down.
5.15.2 SMI# SCI and NMI Routing
The routing bits for GPIO[15:0] allow an input to be routed to SMI#, SCI, NMI or neither. Note that a bit can be routed to either an SMI# or an SCI, but not both.
5.15.3 Triggering
GPIO[15:0] have “sticky” bits on the input. See the GPE0_STS register and the ALT_GPI_SMI_STS register. As long as the signal goes active for at least 2 clock cycles, the PCH keeps the sticky status bit active. The active level can be selected in the GP_INV register. This does not apply to GPI_NMI_STS residing in GPIO IO space. If the system is in an S0 or an S1 state, the GPI inputs are sampled at 33 MHz, so the signal only needs to be active for about 60 ns to be latched. In the S3–S5 states, the GPI inputs are sampled at 32.768 kHz, and thus must be active for at least 61 microseconds to be latched. Note: GPIs that are in the core well are not capable of waking the system from sleep states where the core well is not powered. If the input signal is still active when the latch is cleared, it will again be set. Another edge trigger is not required. This makes these signals “level” triggered inputs.
5.15.4 GPIO Registers Lockdown
The following GPIO registers are locked down when the GPIO Lockdown Enable (GLE) bit is set. The GLE bit resides in D31:F0:GPIO Control (GC) register.
- Offset 00h: GPIO_USE_SEL[31:0]
- Offset 04h: GP_IO_SEL[31:0]
- Offset 0Ch: GP_LVL[31:0]
- Offset 28h: GPI_NMI_EN[15:0]
- Offset 2Ch: GPI_INV[31:0]
- Offset 30h: GPIO_USE_SEL2[63:32]
- Offset 34h: GPI_IO_SEL2[63:32]
- Offset 38h: GP_LVL2[63:32]
- Offset 40h: GPIO_USE_SEL3[95:64]
- Offset 44h: GPI_IO_SEL3[95:64]
- Offset 48h: GP_LVL3[95:64]
- Offset 60h: GP_RST_SEL[31:0]
- Offset 64h: GP_RST_SEL2[63:32]
- Offset 68h: GP_RST_SEL3[95:64]
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Once these registers are locked down, they become Read-Only registers and any software writes to these registers will have no effect. To unlock the registers, the GPIO Lockdown Enable (GLE) bit is required to be cleared to ‘0’. When the GLE bit changes from a ‘1’ to a ‘0’ a System Management Interrupt (SMI#) is generated if enabled. Once the GPIO_UNLOCK_SMI bit is set, it can not be changed until a PLTRST# occurs. This ensures that only BIOS can change the GPIO configuration. If the GLE bit is cleared by unauthorized software, BIOS will set the GLE bit again when the SMI# is triggered and these registers will continue to be locked down.
5.15.5 Serial POST Codes Over GPIO
The PCH adds the extended capability allowing system software to serialize POST or other messages on GPIO. This capability negates the requirement for dedicated diagnostic LEDs on the platform. Additionally, based on the newer BTX form factors, the PCI bus as a target for POST codes is increasingly difficult to support as the total number of PCI devices supported are decreasing.
5.15.5.1 Theory of operation
For the PCH generation POST code serialization logic will be shared with GPIO. These GPIOs will likely be shared with LED control offered by the Super I/O (SIO) component. Figure 5-7 shows a likely configuration. The anticipated usage model is that either the PCH or the SIO can drive a pin low to turn off an LED. In the case of the power LED, the SIO would normally leave its corresponding pin in a high-Z state to allow the LED to turn on. In this state, the PCH can blink the LED by driving its corresponding pin low and subsequently tri-stating the buffer. The I/O buffer should not drive a ‘1’ when configured for this functionality and should be capable of sinking 24 mA of current. An external optical sensing device can detect the on/off state of the LED. By externally post-processing the information from the optical device, the serial bit stream can be recovered. The hardware will supply a ‘sync’ byte before the actual data transmission to allow external detection of the transmit frequency. The frequency of transmission should be limited to 1 transition every 1 μs to ensure the detector can reliably sample Figure 5-7. Serial Post over GPIO Reference Circuit SIO V_3P3_STBY LED R Note: The pull-up value is based on the brightness required. PCH
the on/off state of the LED. To allow flexibility in pull-up resistor values for power optimization, the frequency of the transmission is programmable using the DRS field in the GP_GB_CMDSTS register. The serial bit stream is Manchester encoded. This choice of transmission ensures that a transition will be seen on every clock. The 1 or 0 data is based on the transmission happening during the high or low phase of the clock. As the clock will be encoded within the data stream, hardware must ensure that the Z-0 and 0-Z transitions are glitch-free. Driving the pin directly from a flop or through glitch-free logic are possible methods to meet the glitch-free requirement. A simplified hardware/software register interface provides control and status information to track the activity of this block. Software enabling the serial blink capability should implement an algorithm referenced below to send the serialized message on the enabled GPIO. 1. Read the Go/Busy status bit in the GP_GB_CMDSTS register and verify it is cleared. This will ensure that the GPIO is idled and a previously requested message is still not in progress. 2. Write the data to serialize into the GP_GB_DATA register. 3. Write the DLS and DRS values into the GP_GB_CMDSTS register and set the Go bit. This may be accomplished using a single write. The reference diagram shows the LEDs being powered from the suspend supply. By providing a generic capability that can be used both in the main and the suspend power planes maximum flexibility can be achieved. A key point to make is that the PCH will not unintentionally drive the LED control pin low unless a serialization is in progress. System board connections utilizing this serialization capability are required to use the same power plane controlling the LED as the PCH GPIO pin. Otherwise, the PCH GPIO may float low during the message and prevent the LED from being controlled from the SIO. The hardware will only be serializing messages when the core power well is powered and the processor is operational. Care should be taken to prevent the PCH from driving an active ‘1’ on a pin sharing the serial LED capability. Since the SIO could be driving the line to 0, having the PCH drive a 1 would create a high current path. A recommendation to avoid this condition involves choosing a GPIO defaulting to an input. The GP_SER_BLINK register should be set first before changing the direction of the pin to an output. This sequence ensures the open-drain capability of the buffer is properly configured before enabling the pin as an output.
5.15.5.2 Serial Message Format
To serialize the data onto the GPIO, an initial state of high-Z is assumed. The SIO is required to have its LED control pin in a high-Z state as well to allow the PCH to blink the LED (see the reference diagram). The three components of the serial message include the sync, data, and idle fields. The sync field is 7 bits of ‘1’ data followed by 1 bit of ‘0’ data. Starting from the high-Z state (LED on) provides external hardware a known initial condition and a known pattern. In case one or more of the leading 1 sync bits are lost, the 1s followed by 0 provide a clear indication of ‘end of sync’. This pattern will be used to ‘lock’ external sampling logic to the encoded clock. The data field is shifted out with the highest byte first (MSB). Within each byte, the most significant bit is shifted first (MSb).
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The idle field is enforced by the hardware and is at least 2 bit times long. The hardware will not clear the Busy and Go bits until this idle time is met. Supporting the idle time in hardware prevents time-based counting in BIOS as the hardware is immediately ready for the next serial code when the Go bit is cleared. Note that the idle state is represented as a high-Z condition on the pin. If the last transmitted bit is a 1, returning to the idle state will result in a final 0-1 transition on the output Manchester data. Two full bit times of idle correspond to a count of 4 time intervals (the width of the time interval is controlled by the DRS field). The following waveform shows a 1-byte serial write with a data byte of 5Ah. The internal clock and bit position are for reference purposes only. The Manchester D is the resultant data generated and serialized onto the GPIO. Since the buffer is operating in open-drain mode the transitions are from high-Z to 0 and back.
5.16 SATA Host Controller (D31:F2, F5)
The SATA function in the PCH has three modes of operation to support different operating system conditions. In the case of Native IDE enabled operating systems, the PCH uses two controllers to enable all six ports of the bus. The first controller (Device 31: Function 2) supports ports 0 – 3 and the second controller (Device 31: Function 5) supports ports 4 and 5. When using a legacy operating system, only one controller (Device 31: Function 2) is available that supports ports 0 – 3. In AHCI or RAID mode, only one controller (Device 31: Function 2) is used enabling all six ports and the second controller (Device 31: Function 5) shall be disabled. The MAP register, Section 15.1.28, provides the ability to share PCI functions. When sharing is enabled, all decode of I/O is done through the SATA registers. Device 31, Function 1 (IDE controller) is hidden by software writing to the Function Disable Register (D31, F0, offset F2h, bit 1), and its configuration registers are not used. The PCH SATA controllers feature six sets of interface signals (ports) that can be independently enabled or disabled (they cannot be tri-stated or driven low). Each interface is supported by an independent DMA controller. Note: SATA port 2 and 3 are not available for the HM55 and Intel 3400 chipsets. The PCH SATA controllers interact with an attached mass storage device through a register interface that is equivalent to that presented by a traditional IDE host adapter. The host software follows existing standards and conventions when accessing the register interface and follows standard command protocol conventions. Note: SATA interface transfer rates are independent of UDMA mode settings. SATA interface transfer rates will operate at the bus’s maximum speed, regardless of the UDMA mode reported by the SATA device or the system BIOS. Internal Clock Manchester D 8-bit sync field (1111_1110) Bit 7 0 123456 5A data byte 2 clk idle
5.16.1 SATA Feature Support
(AHCI/RAID Disabled) PCH (AHCI/RAID Enabled) Native Command Queuing (NCQ) N/A Supported Auto Activate for DMA N/A Supported Hot Plug Support N/A Supported Asynchronous Signal Recovery N/A Supported
3 Gb/s Transfer Rate Supported Supported
ATAPI Asynchronous Notification N/A Supported Host & Link Initiated Power Management N/A Supported Staggered Spin-Up Supported Supported Command Completion Coalescing N/A N/A External SATA N/A Supported Feature Description Native Command Queuing (NCQ) Allows the device to reorder commands for more efficient data transfers Auto Activate for DMA Collapses a DMA Setup then DMA Activate sequence into a DMA Setup only Hot Plug Support Allows for device detection without power being applied and ability to connect and disconnect devices without prior notification to the system Asynchronous Signal Recovery Provides a recovery from a loss of signal or establishing communication after hot plug
3 Gb/s Transfer Rate Capable of data transfers up to 3Gb/s
A mechanism for a device to send a notification to the host that the device requires attention Host & Link Initiated Power Management Capability for the host controller or device to request Partial and Slumber interface power states Staggered Spin-Up Enables the host the ability to spin up hard drives sequentially to prevent power load problems on boot Command Completion Coalescing Reduces interrupt and completion overhead by allowing a specified number of commands to complete and then generating an interrupt to process the commands External SATA Technology that allows for an outside the box connection of up to 2 meters (when using the cable defined in SATA-IO)
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5.16.2 Theory of Operation
5.16.2.1 Standard ATA Emulation
The PCH contains a set of registers that shadow the contents of the legacy IDE registers. The behavior of the Command and Control Block registers, PIO, and DMA data transfers, resets, and interrupts are all emulated. Note: The PCH will assert INTR when the master device completes the EDD command regardless of the command completion status of the slave device. If the master completes EDD first, an INTR is generated and BSY will remain '1' until the slave completes the command. If the slave completes EDD first, BSY will be '0' when the master completes the EDD command and asserts INTR. Software must wait for busy to clear (0) before completing an EDD command, as required by the ATA5 through ATA7 (T13) industry standards. 5.16.2.2 48-Bit LBA Operation The SATA host controller supports 48-bit LBA through the host-to-device register FIS when accesses are performed using writes to the task file. The SATA host controller will ensure that the correct data is put into the correct byte of the host-to-device FIS. There are special considerations when reading from the task file to support 48-bit LBA operation. Software may need to read all 16-bits. Since the registers are only 8-bits wide and act as a FIFO, a bit must be set in the device/control register, which is at offset 3F6h for primary and 376h for secondary (or their native counterparts). If software clears bit 7 of the control register before performing a read, the last item written will be returned from the FIFO. If software sets bit 7 of the control register before performing a read, the first item written will be returned from the FIFO.
5.16.3 SATA Swap Bay Support
The PCH provides for basic SATA swap bay support using the PSC register configuration bits and power management flows. A device can be powered down by software and the port can then be disabled, allowing removal and insertion of a new device. Note: This SATA swap bay operation requires board hardware (implementation specific), BIOS, and operating system support.
5.16.4 Hot Plug Operation
The PCH supports Hot Plug Surprise removal and Insertion Notification in the PARTIAL, SLUMBER and Listen Mode states when used with Low Power Device Presence Detection. Software can take advantage of power savings in the low power states while enabling hot plug operation. See chapter 7 of the AHCI specification for details.
5.16.4.1 Low Power Device Presence Detection
Low Power Device Presence Detection enables SATA Link Power Management to co- exist with hot plug (insertion and removal) without interlock switch or cold presence detect. The detection mechanism allows Hot Plug events to be detectable by hardware across all link power states (Active, PARTIAL, SLUMBER) as well as AHCI Listen Mode. If the Low Power Device Presence Detection circuit is disabled the PCH reverts to Hot Plug Surprise Removal Notification (without an interlock switch) mode that is mutually exclusive of the PARTIAL and SLUMBER power management states.
5.16.5 Function Level Reset Support (FLR)
The SATA Host Controller supports the Function Level Reset (FLR) capability. The FLR capability can be used in conjunction with Intel® Virtualization Technology. FLR allows an operating system in a Virtual Machine to have complete control over a device, including its initialization, without interfering with the rest of the platform. The device provides a software interface that enables the Operating System to reset the whole device as if a PCI reset was asserted.
5.16.5.1 FLR Steps
5.16.5.1.1 FLR Initialization
- A FLR is initiated by software writing a ‘1’ to the Initiate FLR bit. 2. All subsequent requests targeting the Function will not be claimed and will be Master Abort Immediate on the bus. This includes any configuration, I/O or Memory cycles, however, the Function shall continue to accept completions targeting the Function.
5.16.5.1.2 FLR Operation
The Function will Reset all configuration, I/O and memory registers of the Function except those indicated otherwise and reset all internal states of the Function to the default or initial condition.
5.16.5.1.3 FLR Completion
The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be used to indicate to the software that the FLR reset is completed. Note: From the time Initiate FLR bit is written to 1 software must wait at least 100 ms before accessing the function.
5.16.6 Intel ® Rapid Storage Technology Configuration
The Intel® Rapid Storage Technology offers several diverse options for RAID (redundant array of independent disks) to meet the needs of the end user. AHCI support provides higher performance and alleviates disk bottlenecks by taking advantage of the independent DMA engines that each SATA port offers in the PCH.
- RAID Level 0 performance scaling up to 4 drives, enabling higher throughput for data intensive applications such as video editing.
- Data security is offered through RAID Level 1, which performs mirroring.
- RAID Level 10 provides high levels of storage performance with data protection, combining the fault-tolerance of RAID Level 1 with the performance of RAID Level 0. By striping RAID Level 1 segments, high I/O rates can be achieved on systems that require both performance and fault-tolerance. RAID Level 10 requires 4 hard drives, and provides the capacity of two drives.
- RAID Level 5 provides highly efficient storage while maintaining fault-tolerance on 3 or more drives. By striping parity, and rotating it across all disks, fault tolerance of any single drive is achieved while only consuming 1 drive worth of capacity. That is, a 3 drive RAID 5 has the capacity of 2 drives, or a 4 drive RAID 5 has the capacity of 3 drives. RAID 5 has high read transaction rates, with a medium write rate. RAID 5 is well suited for applications that require high amounts of storage while maintaining fault tolerance.
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By using the PCH’s built-in Intel® Rapid Storage Technology, there is no loss of PCI resources (request/grant pair) or add-in card slot. Intel® Rapid Storage Technology functionality requires the following items: 1. The PCH SKU enabled for Intel® Rapid Storage Technology (see Section 1.3) 2. Intel® Rapid Storage Manager RAID Option ROM must be on the platform 3. Intel® Rapid Storage Manager drivers, most recent revision. 4. At least two SATA hard disk drives (minimum depends on RAID configuration). Intel® Rapid Storage Technology is not available in the following configurations: 1. The SATA controller is in compatible mode.
5.16.6.1 Intel ® Rapid Storage Manager RAID Option ROM
The Intel® Rapid Storage Manager RAID Option ROM is a standard PnP Option ROM that is easily integrated into any System BIOS. When in place, it provides the following three primary functions:
- Provides a text mode user interface that allows the user to manage the RAID configuration on the system in a pre-operating system environment. Its feature set is kept simple to keep size to a minimum, but allows the user to create & delete RAID volumes and select recovery options when problems occur.
- Provides boot support when using a RAID vo lume as a boot disk. It does this by providing Int13 services when a RAID volume needs to be accessed by DOS applications (such as NTLDR) and by exporting the RAID volumes to the System BIOS for selection in the boot order.
- At each boot up, provides the user with a status of the RAID volumes and the option to enter the user interface by pressing CTRL-I.
5.16.7 Power Management Operation
Power management of the PCH SATA controller and ports will cover operations of the host controller and the SATA wire.
5.16.7.1 Power State Mappings
The D0 PCI power management state for device is supported by the PCH SATA controller. SATA devices may also have multiple power states. From parallel ATA, three device states are supported through ACPI. They are:
- D0 – Device is working and instantly available.
- D1 – Device enters when it receives a STANDBY IMMEDIATE command. Exit latency from this state is in seconds.
- D3 – From the SATA device’s perspective, no different than a D1 state, in that it is entered using the STANDBY IMMEDIATE command. However, an ACPI method is also called which will reset the device and then cut its power. Each of these device states are subsets of the host controller’s D0 state.
Finally, SATA defines three PHY layer power states, which have no equivalent mappings to parallel ATA. They are:
- PHY READY – PHY logic and PLL are both on and active.
- Partial – PHY logic is powered, but in a reduced state. Exit latency is no longer than 10 ns.
- Slumber – PHY logic is powered, but in a reduced state. Exit latency can be up to 10 ms. Since these states have much lower exit latency than the ACPI D1 and D3 states, the SATA controller defines these states as sub-states of the device D0 state.
5.16.7.2 Power State Transitions
5.16.7.2.1 Partial and Slumber State Entry/Exit
The partial and slumber states save interface power when the interface is idle. It would be most analogous to PCI CLKRUN# (in power savings, not in mechanism), where the interface can have power saved while no commands are pending. The SATA controller defines PHY layer power management (as performed using primitives) as a driver operation from the host side, and a device proprietary mechanism on the device side. The SATA controller accepts device transition types, but does not issue any transitions as a host. All received requests from a SATA device will be ACKed. When an operation is performed to the SATA controller such that it needs to use the SATA cable, the controller must check whether the link is in the Partial or Slumber states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the SATA device must perform the same action.
5.16.7.2.2 Device D1, D3 States
These states are entered after some period of time when software has determined that no commands will be sent to this device for some time. The mechanism for putting a device in these states does not involve any work on the host controller, other then sending commands over the interface to the device. The command most likely to be used in ATA/ATAPI is the “STANDBY IMMEDIATE” command.
5.16.7.2.3 Host Controller D3 HOT State
After the interface and device have been put into a low power state, the SATA host controller may be put into a low power state. This is performed using the PCI power management registers in configuration space. There are two very important aspects to note when using PCI power management. 1. When the power state is D3, only accesses to configuration space are allowed. Any attempt to access the memory or I/O spaces will result in master abort. 2. When the power state is D3, no interrupts may be generated, even if they are enabled. If an interrupt status bit is pending when the controller transitions to D0, an interrupt may be generated. When the controller is put into D3, it is assumed that software has properly shut down the device and disabled the ports. Therefore, there is no need to sustain any values on the port wires. The interface will be treated as if no device is present on the cable, and power will be minimized. When returning from a D3 state, an internal reset will not be performed.
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5.16.7.2.4 Non-AHCI Mode PME# Generation
When in non-AHCI mode (legacy mode) of operation, the SATA controller does not generate PME#. This includes attach events (since the port must be disabled), or interlock switch events (using the SATAGP pins).
5.16.7.3 SMI Trapping (APM)
Device 31:Function2:Offset C0h (see Section 14.1.42) contain control for generating SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0–1F7h, 3F6h, 170–177h, and 376h) and native IDE ranges defined by PCMDBA, PCTLBA, SCMDBA an SCTLBA. If the SATA controller is in legacy mode and is using these addresses, accesses to one of these ranges with the appropriate bit set causes the cycle to not be forwarded to the SATA controller, and for an SMI# to be generated. If an access to the Bus-Master IDE registers occurs while trapping is enabled for the device being accessed, then the register is updated, an SMI# is generated, and the device activity status bits (Section 14.1.43) are updated indicating that a trap occurred.
5.16.8 SATA Device Presence
In legacy mode, the SATA controller does not generate interrupts based on hot plug/ unplug events. However, the SATA PHY does know when a device is connected (if not in a partial or slumber state), and it s beneficial to communicate this information to host software as this will greatly reduce boot times and resume times. The flow used to indicate SATA device presence is shown in Figure 5-8. The ‘PxE’ bit refers to PCS.P[3:0]E bits, depending on the port being checked and the ‘PxP’ bits refer to the PCS.P[3:0]P bits, depending on the port being checked. If the PCS/PxP bit is set a device is present, if the bit is cleared a device is not present. If a port is disabled, software can check to see if a new device is connected by periodically re-enabling the port and observing if a device is present, if a device is not present it can disable the port and check again later. If a port remains enabled, software can periodically poll PCS.PxP to see if a new device is connected. Figure 5-8. Flow for Port Enable / Device Present Bits
5.16.9 SATA LED
The SATALED# output is driven whenever the BSY bit is set in any SATA port. The SATALED# is an active-low open-drain output. When SATALED# is low, the LED should be active. When SATALED# is high, the LED should be inactive.
5.16.10 AHCI Operation
The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a programming interface for SATA host controllers developed through a joint industry effort. AHCI defines transactions between the SATA controller and software and enables advanced performance and usability with SATA. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices—each device is treated as a master—and hardware assisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires appropriate software support (such as, an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware. The PCH supports all of the mandatory features of the Serial ATA Advanced Host Controller Interface Specification, Revision 1.2 and many optional features, such as hardware assisted native command queuing, aggressive power management, LED indicator support, and Hot-Plug through the use of interlock switch support (additional platform hardware and software may be required depending upon the implementation). Note: For reliable device removal notification while in AHCI operation without the use of interlock switches (surprise removal), interface power management should be disabled for the associated port. See Section 7.3.1 of the AHCI Specification for more information.
5.16.11 SGPIO Signals
The SGPIO signals, in accordance to the SFF-8485 specification, support per-port LED signaling. These signals are not related to SATALED#, which allows for simplified indication of SATA command activity. The SGPIO group interfaces with an external controller chip that fetches and serializes the data for driving across the SGPIO bus. The output signals then control the LEDs. This feature is only valid in AHCI/RAID mode. Note: Intel does not validate all possible usage cases of this feature. Customers should validate their specific design implementation on their own platforms.
5.16.11.1 Mechanism
The enclosure management for SATA Controller 1 (Device 31: Function 2) involves sending messages that control LEDs in the enclosure. The messages for this function are stored after the normal registers in the AHCI BAR, at Offset 580h bytes for the PCH from the beginning of the AHCI BAR as specified by the EM_LOC global register (Section 14.4.1.8). Software creates messages for transmission in the enclosure management message buffer. The data in the message buffer should not be changed if CTL.TM bit is set by software to transmit an update message. Software should only update the message buffer when CTL.TM bit is cleared by hardware otherwise the message transmitted will be indeterminate. Software then writes a register to cause hardware to transmit the message or take appropriate action based on the message content. The software should only create message types supported by the controller, which is LED messages for the PCH. If the software creates other non LED message types (such as, SAF-TE, SES-2), the SGPIO interface may hang and the result is indeterminate.
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During reset all SGPIO pins will be in tri-state. The interface will continue to be in tri- state after reset until the first transmission occurs when software programs the message buffer and sets the transmit bit CTL.TM. The SATA Host controller will initiate the transmission by driving SCLOCK and at the same time drive the SLOAD to ‘0’ prior to the actual bit stream transmission. The Host will drive SLOAD low for at least 5 SCLOCK then only start the bit stream by driving the SLOAD to high. SLOAD will be driven high for 1 SCLOCK follow by vendor specific pattern that is default to “0000” if software has yet to program the value. A total of 21-bit stream from 7 ports (Port0, Port1, Port2, Port3, Port4 Port5 and Port6) of 3-bit per port LED message will be transmitted on SDATAOUT0 pin after the SLOAD is driven high for 1 SCLOCK. Only 3 ports (Port4, Port5 and Port6) of 9 bit total LED message follow by 12 bits of tri-state value will be transmitted out on SDATAOUT1 pin. All the default LED message values will be high prior to software setting them, except the Activity LED message that is configured to be hardware driven that will be generated based on the activity from the respective port. All the LED message values will be driven to ‘1’ for the port that is unimplemented as indicated in the Port Implemented register regardless of the software programmed value through the message buffer. There are 2 different ways of resetting the PCH’s SGPIO interface, asynchronous reset and synchronous reset. Asynchronous reset is caused by platform reset to cause the SGPIO interface to be tri-state asynchronously. Synchronous reset is caused by setting the CTL.RESET bit, clearing the GHC.AE bit or HBA reset, where Host Controller will complete the existing full bit stream transmission then only tri-state all the SGPIO pins. After the reset, both synchronous and asynchronous, the SGPIO pins will stay tri- stated. Note: The PCH Host Controller does not ensure that it will cause the target SGPIO device or controller to be reset. Software is responsible to keep the PCH SGPIO interface in tri- state for 2 second to cause a reset on the target of the SGPIO interface.
5.16.11.2 Message Format
Messages shall be constructed with a one DWord header that describes the message to be sent followed by the actual message contents. The first DWord shall be constructed as follows: Bit Description 31:28 Reserved 27:24 Message Type (MTYPE): Specifies the type of the message. The message types are: 0h = LED 1h = SAF-TE 2h = SES-2 3h = SGPIO (register based interface) All other values reserved 23:16 Data Size (DSIZE): Specifies the data size in bytes. If the message (enclosure services command) has a data buffer that is associated with it that is transferred, the size of that data buffer is specified in this field. If there is no separate data buffer, this field shall have a value of ‘0’. The data directly follows the message in the message buffer. For the PCH, this value should always be ‘0’. 15:8 Message Size (MSIZE): Specifies the size of the message in bytes. The message size does not include the one DWord header. A value of ‘0’ is invalid. For the PCH, the message size is always 4 bytes. 7:0 Reserved
The SAF-TE, SES-2, and SGPIO message formats are defined in the corresponding the responsibility of software to ensure the content of the message format is correct. If the message type is not programmed as 'LED' for this controller, the controller shall not take any action to update its LEDs. Note that for LED message type, the message size is always consisted of 4 bytes.
5.16.11.3 LED Message Type
The LED message type specifies the status of up to three LEDs. Typically, the usage for these LEDs is activity, fault, and locate. Not all implementations necessarily contain all LEDs (for example, some implementations may not have a locate LED). The message identifies the HBA port number and the Port Multiplier port number that the slot status applies to. If a Port Multiplier is not in use with a particular device, the Port Multiplier port number shall be ‘0’. The format of the LED message type is defined in Table 5-37. The LEDs shall retain their values until there is a following update for that particular slot. Table 5-37. Multi-acti vity LED message type Byte Description 3-2 Value (VAL): This field describes the state of each LED for a particular location. There are three LEDs that may be supported by the HBA. Each LED has 3 bits of control. LED values are: 000b – LED shall be off 001b – LED shall be solid on as perceived by human eye All other values reserved The LED bit locations are: Bits 2:0 – Activity LED (may be driven by hardware) Bits 5:3 – Vendor Specific LED (such as, locate) Bits 8:6 - Vendor Specific LED (such as, fault) Bits 15:9 – Reserved Vendor specific message is: Bit 3:0 – Vendor Specific Pattern Bit 15:4 – Reserved NOTE: If Activity LED Hardware Driven (ATTR.ALHD) bit is set, host will output the hardware LED value sampled internally and will ignore software written activity value on bit [2:0]. Since the PCH Enclosure Management does not support port multiplier based LED message, the LED message will be generated independently based on respective port’s operation activity. Vendor specific LED values Locate (Bits 5:3) and Fault (Bits 8:6) always are driven by software. Port Multiplier Information: Specifies slot specific information related to Port Multiplier. Bits 3:0 specify the Port Multiplier port number for the slot that requires the status update. If a Port Multiplier is not attached to the device in the affected slot, the Port Multiplier port number shall be '0'. Bits 7:4 are reserved. The PCH does not support LED messages for devices behind a Port Multiplier. This byte should be 0. HBA Information: Specifies slot specific information related to the HBA. Bits 4:0 – HBA port number for the slot that requires the status update. Bit 5 – If set to '1', value is a vendor specific message that applies to the entire enclosure. If cleared to '0', value applies to the port specified in bits 4:0. Bits 7:6 – Reserved
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5.16.11.4 SGPIO Waveform
Figure 5-9. Serial Data transm itted over the SGPIO Interface
5.16.12 External SATA
The PCH supports external SATA. External SATA uses the SATA interface outside of the system box. The usage model for this feature must comply with the Serial ATA II Cables and Connectors Volume 2 Gold specification at www.sata-io.org. Intel validates two configurations: 1. The cable-up solution involves an internal SATA cable that connects to the SATA motherboard connector and spans to a back panel PCI bracket with an eSATA connector. A separate eSATA cable is required to connect an eSATA device. 2. The back-panel solution involves running a trace to the I/O back panel and connecting a device using an external SATA connector on the board.
5.17 High Precision Event Timers
This function provides a set of timers that can be used by the operating system. The timers are defined such that in the future, the operating system may be able to assign specific timers to used directly by specific applications. Each timer can be configured to cause a separate interrupt. The PCH provides eight timers. The timers are implemented as a single counter, each with its own comparator and value register. This counter increases monotonically. Each individual timer can generate an interrupt when the value in its value register matches the value in the main counter. The registers associated with these timers are mapped to a memory space (much like the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS reports to the operating system the location of the register space. The hardware can support an assignable decode space; however, the BIOS sets this space prior to handing it over to the operating system. It is not expected that the operating system will move the location of these timers once it is set by the BIOS.
5.17.1 Timer Accuracy
- The timers are accurate over any 1 ms period to within 0.05% of the time specified in the timer resolution fields. 2. Within any 100 microsecond period, the timer reports a time that is up to two ticks too early or too late. Each tick is less than or equal to 100 ns, so this represents an error of less than 0.2%. 3. The timer is monotonic. It does not return the same value on two consecutive reads (unless the counter has rolled over and reached the same value). The main counter is clocked by the 14.31818 MHz clock, synchronized into the 66.666 MHz domain. This results in a non-uniform duty cycle on the synchronized clock, but does have the correct average period. The accuracy of the main counter is as accurate as the 14.31818 MHz clock.
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5.17.2 Interrupt Mapping
Mapping Option #1 (Legacy Replacement Option) In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is set. This forces the mapping found in Table 5-38. NOTE: The Legacy Option does not preclude delivery of IRQ0/IRQ8 using direct FSB interrupt messages. Mapping Option #2 (Standard Option) In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is 0. Each timer has its own routing control. The interrupts can be routed to various interrupts in the 8259 or I/O APIC. A capabilities field indicates which interrupts are valid options for routing. If a timer is set for edge-triggered mode, the timers should not be share with any PCI interrupts. For the PCH, the only supported interrupt values are as follows: Timer 0 and 1: IRQ20, 21, 22 & 23 (I/O APIC only). Timer 2: IRQ11 (8259 or I/O APIC) and IRQ20, 21, 22 & 23 (I/O APIC only). Timer 3: IRQ12 (8259 or I/O APIC) and IRQ 20, 21, 22 & 23 (I/O APIC only). Interrupts from Timer 4, 5, 6, 7 can only be delivered using direct FSB interrupt messages. 5.17.3 Periodic vs. No n-Periodic Modes Non-Periodic Mode Timer 0 is configurable to 32 (default) or 64-bit mode, whereas Timers 1, 2 and 3 only support 32-bit mode (See Section 20.1.5). All of the timers support non-periodic mode. Table 5-38. Legacy Replacement Routing Timer 8259 Mapping APIC Mapping Comment
0 IRQ0 IRQ2 In this case, the 8254 timer will
1 IRQ8 IRQ8 In this case, the RTC will not cause
any interrupts. 2 & 3 Per IRQ Routing Field. Per IRQ Routing Field 4, 5, 6, 7 not available not available
PC HPET Specification for a description of this mode. The following usage model is expected: 1. Software clears the ENABLE_CNF bit to prevent any interrupts. 2. Software Clears the main counter by writing a value of 00h to it. 3. Software sets the TIMER0_VAL_SET_CNF bit. 4. Software writes the new value in the TIMER0_COMPARATOR_VAL register. 5. Software sets the ENABLE_CNF bit to enable interrupts. The Timer 0 Comparator Value register cannot be programmed reliably by a single 64-bit write in a 32-bit environment except if only the periodic rate is being changed during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then the following software solution will always work regardless of the environment: 1. Set TIMER0_VAL_SET_CNF bit. 2. Set the lower 32 bits of the Timer0 Comparator Value register. 3. Set TIMER0_VAL_SET_CNF bit. 4. Set the upper 32 bits of the Timer0 Comparator Value register.
5.17.4 Enabling the Timers
The BIOS or operating system PnP code should route the interrupts. This includes the Legacy Rout bit, Interrupt Rout bit (for each timer), interrupt type (to select the edge or level type for each timer) The Device Driver code should do the following for an available timer: 1. Set the Overall Enable bit (Offset 10h, bit 0). 2. Set the timer type field (selects one-shot or periodic). 3. Set the interrupt enable. 4. Set the comparator value.
5.17.5 Interrupt Levels
Interrupts directed to the internal 8259s are active high. See Section 5.9 for information regarding the polarity programming of the I/O APIC for detecting internal interrupts. If the interrupts are mapped to the 8259 or I/O APIC and set for level-triggered mode, they can be shared with PCI interrupts. They may be shared although it’s unlikely for the operating system to attempt to do this. If more than one timer is configured to share the same IRQ (using the TIMERn_INT_ROUT_CNF fields), then the software must configure the timers to level- triggered mode. Edge-triggered interrupts cannot be shared.
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5.17.6 Handling Interrupts
If each timer has a unique interrupt and the timer has been configured for edge- triggered mode, then there are no specific steps required. No read is required to process the interrupt. If a timer has been configured to level-triggered mode, then its interrupt must be cleared by the software. This is done by reading the interrupt status register and writing a 1 back to the bit position for the interrupt to be cleared. Independent of the mode, software can read the value in the main counter to see how time has passed between when the interrupt was generated and when it was first serviced. If Timer 0 is set up to generate a periodic interrupt, the software can check to see how much time remains until the next interrupt by checking the timer value register.
5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors
A 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit instructions. However, a 32-bit processor may not be able to directly read 64-bit timer. A race condition comes up if a 32-bit processor reads the 64-bit register using two separate 32-bit reads. The danger is that just after reading one half, the other half rolls over and changes the first half. If a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before reading both the upper and lower 32-bits of the timer. If a 32-bit processor does not want to halt the timer, it can use the 64-bit timer as a 32-bit timer by setting the TIMERn_32MODE_CNF bit. This causes the timer to behave as a 32-bit timer. The upper 32-bits are always 0. Alternatively, software may do a multiple read of the counter while it is running. Software can read the high 32 bits, then the low 32 bits, the high 32 bits again. If the high 32 bits have not changed between the two reads, then a rollover has not happened and the low 32 bits are valid. If the high 32 bits have changed between reads, then the multiple reads are repeated until a valid read is performed. Note: On a 64-bit platform, if software attempts a 64 bit read of the 64-bit counter, software must be aware that some platforms may split the 64 bit read into two 32 bit reads. The read maybe inaccurate if the low 32 bits roll over between the high and low reads.
5.18 USB EHCI Host Contro llers (D29:F0 and D26:F0)
The PCH contains two Enhanced Host Controller Interface (EHCI) host controllers which support up to fourteen USB 2.0 high-speed root ports. USB 2.0 allows data transfers up to 480 Mb/s. USB 2.0 based Debug Port is also implemented in the PCH.
5.18.1 EHC Initialization
The following descriptions step through the expected PCH Enhanced Host Controller (EHC) initialization sequence in chronological order, beginning with a complete power cycle in which the suspend well and core well have been off.
5.18.1.1 BIOS Initialization
BIOS performs a number of platform customization steps after the core well has powered up. Contact your Intel Field Representative for additional PCH BIOS information.
5.18.1.2 Driver Initialization
See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0.
5.18.1.3 EHC Resets
In addition to the standard PCH hardware resets, portions of the EHC are reset by the HCRESET bit and the transition from the D3HOT device power management state to the D0 state. The effects of each of these resets are: If the detailed register descriptions give exceptions to these rules, those exceptions override these rules. This summary is provided to help explain the reasons for the reset policies.
5.18.2 Data Structur es in Main Memory
See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 for details. Reset Does Reset Does not Reset Comments HCRESET bit set. Memory space registers except Structural Parameters (which is written by BIOS). Configuration registers. The HCRESET must only affect registers that the EHCI driver controls. PCI Configuration space and BIOS-programmed parameters can not be reset. Software writes the Device Power State from D3 HOT (11b) to D0 (00b). Core well registers (except BIOS- programmed registers). Suspend well registers; BIOS- programmed core well registers. The D3-to-D0 transition must not cause wake information (suspend well) to be lost. It also must not clear BIOS- programmed registers because BIOS may not be invoked following the D3-to-D0 transition.
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5.18.3 USB 2.0 Enhanced Host Controller DMA The PCH USB 2.0 EHC implements three sources of USB packets. They are, in order of priority on USB during each microframe: 1. The USB 2.0 Debug Port (see Section USB 2.0 Based Debug Port), 2. The Periodic DMA engine, and 3. The Asynchronous DMA engine. The PCH always performs any currently-pending debug port transaction at the beginning of a microframe, followed by any pending periodic traffic for the current microframe. If there is time left in the microframe, then the EHC performs any pending asynchronous traffic until the end of the microframe (EOF1). Note that the debug port traffic is only presented on Port #1 and Port #9, while the other ports are idle during this time.
5.18.4 Data Encoding and Bit Stuffing
See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.
5.18.5 Packet Formats
See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0. The PCH EHCI allows entrance to USB test modes, as defined in the USB 2.0 specification, including Test J, Test Packet, etc. However note that the PCH Test Packet test mode interpacket gap timing may not meet the USB 2.0 specification. 5.18.6 USB 2.0 Interrupts and Error Conditions Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that cause them. All error conditions that the EHC detects can be reported through the EHCI Interrupt status bits. Only PCH-specific interrupt and error-reporting behavior is documented in this section. The EHCI Interrupts Section must be read first, followed by this section of the datasheet to fully comprehend the EHC interrupt and error-reporting functionality.
- Based on the EHC Buffer sizes and buffe r management policies, the Data Buffer Error can never occur on the PCH.
- Master Abort and Target Abort responses from hub interface on EHC-initiated read packets will be treated as Fatal Host Errors. The EHC halts when these conditions are encountered.
- The PCH may assert the interrupts which are based on the interrupt threshold as soon as the status for the last complete transaction in the interrupt interval has been posted in the internal write buffers. The requirement in the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the status is written to memory) is met internally, even though the write may not be seen on DMI before the interrupt is asserted.
- Since the PCH supports the 1024-element Frame List size, the Frame List Rollover interrupt occurs every 1024 milliseconds.
- The PCH delivers interrupts using PIRQH#.
- The PCH does not modify the CERR count on an Interrupt IN when the “Do Complete-Split” execution criteria are not met.
- For complete-split transactions in the Periodic list, the “Missed Microframe” bit does not get set on a control-structure-fetch that fails the late-start test. If subsequent accesses to that control structure do not fail the late-start test, then the “Missed Microframe” bit will get set and written back.
5.18.6.1 Aborts on USB 2. 0-Initiated Memory Reads If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The following actions are taken when this occurs:
- The Host System Error status bit is set.
- The DMA engines are halted after completi ng up to one more transaction on the USB interface.
- If enabled (by the Host System Error Enable), then an interrupt is generated.
- If the status is Master Abort, then the Received Master Abort bit in configuration space is set.
- If the status is Target Abort, then the Received Target Abort bit in configuration space is set.
- If enabled (by the SERR Enable bit in the function’s configuration space), then the Signaled System Error bit in configuration bit is set. 5.18.7 USB 2.0 Power Management
5.18.7.1 Pause Feature
This feature allows platforms to dynamically enter low-power states during brief periods when the system is idle (that is, between keystrokes). This is useful for enabling power management features in the PCH. The policies for entering these states typically are based on the recent history of system bus activity to incrementally enter deeper power management states. Normally, when the EHC is enabled, it regularly accesses main memory while traversing the DMA schedules looking for work to do; this activity is viewed by the power management software as a non-idle system, thus preventing the power managed states to be entered. Suspending all of the enabled ports can prevent the memory accesses from occurring, but there is an inherent latency overhead with entering and exiting the suspended state on the USB ports that makes this unacceptable for the purpose of dynamic power management. As a result, the EHCI software drivers are allowed to pause the EHC DMA engines when it knows that the traffic patterns of the attached devices can afford the delay. The pause only prevents the EHC from generating memory accesses; the SOF packets continue to be generated on the USB ports (unlike the suspended state).
5.18.7.2 Suspend Feature
The Enhanced Host Controller Interface (EHCI) For Universal Serial Bus Specification, Section 4.3 describes the details of Port Suspend and Resume.
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5.18.7.3 ACPI Device States
The USB 2.0 function only supports the D0 and D3 PCI Power Management states. Notes regarding the PCH implementation of the Device States: 1. The EHC hardware does not inherently consume any more power when it is in the D0 state than it does in the D3 state. However, software is required to suspend or disable all ports prior to entering the D3 state such that the maximum power consumption is reduced. 2. In the D0 state, all implemented EHC features are enabled. 3. In the D3 state, accesses to the EHC memory-mapped I/O range will master abort. Note that, since the Debug Port uses the same memory range, the Debug Port is only operational when the EHC is in the D0 state. 4. In the D3 state, the EHC interrupt must never assert for any reason. The internal PME# signal is used to signal wake events, etc. 5. When the Device Power State field is written to D0 from D3, an internal reset is generated. See section EHC Resets for general rules on the effects of this reset. 6. Attempts to write any other value into the Device Power State field other than 00b (D0 state) and 11b (D3 state) will complete normally without changing the current value in this field.
5.18.7.4 ACPI System States
The EHC behavior as it relates to other power management states in the system is summarized in the following list:
- The System is always in the S0 state when the EHC is in the D0 state. However, when the EHC is in the D3 state, the system may be in any power management state (including S0).
- When in D0, the Pause feature (See Section 5.18.7.1) enables dynamic processor low-power states to be entered.
- The PLL in the EHC is disabled when entering the S3/S4/S5 states (core power turns off).
- All core well logic is reset in the S3/S4/S5 states. 5.18.8 USB 2.0 Legacy Keyboard Operation The PCH must support the possibility of a keyboard downstream from either a full- speed/low-speed or a high-speed port. The description of the legacy keyboard support is unchanged from USB 1.1. The EHC provides the basic ability to generate SMIs on an interrupt event, along with more sophisticated control of the generation of SMIs.
5.18.9 USB 2.0 Based Debug Port The PCH supports the elimination of the legacy COM ports by providing the ability for new debugger software to interact with devices on a USB 2.0 port. High-level restrictions and features are:
- Operational before USB 2.0 drivers are loaded.
- Functions even when the port is disabled.
- Allows normal system USB 2.0 traffic in a system that may only have one USB port.
- Debug Port device (DPD) must be high-speed capable and connect directly to Port 1 and Port 9 on PCH-based systems (such as, the DPD cannot be connected to Port 1/Port 9 through a hub. When a DPD is detected the PCH EHCI will bypass the integrated Rate Matching Hub and connect directly to the port and the DPD.).
- Debug Port FIFO always makes forward progress (a bad status on USB is simply presented back to software).
- The Debug Port FIFO is only given one USB access per microframe. The Debug port facilitates operating system and device driver debug. It allows the software to communicate with an external console using a USB 2.0 connection. Because the interface to this link does not go through the normal USB 2.0 stack, it allows communication with the external console during cases where the operating system is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is being debugged. Specific features of this implementation of a debug port are:
- Only works with an external USB 2.0 debug device (console).
- Implemented for a specific port on the host controller.
- Operational anytime the port is not susp ended AND the host controller is in D0 power state.
- Capability is interrupted when port is driving USB RESET.
5.18.9.1 Theory of Operation
There are two operational modes for the USB debug port: 1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard host controller driver. In Mode 1, the Debug Port controller is required to generate a “keepalive” packets less than 2 ms apart to keep the attached debug device from suspending. The keepalive packet should be a standalone 32-bit SYNC field. 2. Mode 2 is when the host controller is running (that is, host controller’s Run/Stop# bit is 1). In Mode 2, the normal transmission of SOF packets will keep the debug device from suspending. Behavioral Rules 1. In both modes 1 and 2, the Debug Port controller must check for software requested debug transactions at least every 125 microseconds. 2. If the debug port is enabled by the debug driver, and the standard host controller driver resets the USB port, USB debug transactions are held off for the duration of the reset and until after the first SOF is sent. 3. If the standard host controller driver suspends the USB port, then USB debug transactions are held off for the duration of the suspend/resume sequence and until after the first SOF is sent. 4. The ENABLED_CNT bit in the debug register space is independent of the similar port control bit in the associated Port Status and Control register.
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Table 5-39 shows the debug port behavior related to the state of bits in the debug registers as well as bits in the associated Port Status and Control register. Table 5-39. Debug Port Behavior OWNER_CNT ENABLED_CT Port Enable Run / Stop Suspend Debug Port Behavior 0X X X X Debug port is not being used. Normal operation. 10 X X X Debug port is not being used. Normal operation. 11 0 0 X Debug port in Mode 1. SYNC keepalives sent plus debug traffic 11 0 1 X Debug port in Mode 2. SOF (and only SOF) is sent as keepalive. Debug traffic is also sent. Note that no other normal traffic is sent out this port, because the port is not enabled. 11 1 0 0 Invalid. Host controller driver should never put controller into this state (enabled, not running and not suspended). 11 1 0 1 Port is suspended. No debug traffic sent. 11 1 1 0 Debug port in Mode 2. Debug traffic is interspersed with normal traffic. 11 1 1 1 Port is suspended. No debug traffic sent.
5.18.9.1.1 OUT Transactions
An Out transaction sends data to the debug device. It can occur only when the following are true:
- The debug port is enabled
- The debug software sets the GO_CNT bit
- The WRITE_READ#_CNT bit is set The sequence of the transaction is: 1. Software sets the appropriate values in the following bits: —U S B _ A D D R E S S _ C N F —U S B _ E N D P O I N T _ C N F — DATA_BUFFER[63:0] — TOKEN_PID_CNT[7:0] — SEND_PID_CNT[15:8] —D A T A _ L E N _ C N T — WRITE_READ#_CNT: (note: this will always be 1 for OUT transactions) — GO_CNT: (note: this will always be 1 to initiate the transaction) 2. The debug port controller sends a token packet consisting of: —S Y N C — TOKEN_PID_CNT field — USB_ADDRESS_CNT field —U S B _ E N D P O I N T _ C N T f i e l d — 5-bit CRC field 3. After sending the token packet, the debug port controller sends a data packet consisting of: —S Y N C — SEND_PID_CNT field — The number of data bytes indicated in DATA_LEN_CNT from the DATA_BUFFER — 16-bit CRC NOTE: A DATA_LEN_CNT value of 0 is valid in which case no data bytes would be included in the packet. 4. After sending the data packet, the controller waits for a handshake response from the debug device: — If a handshake is received, the debug port controller: a. Places the received PID in the RECEIVED_PID_STS field b. Resets the ERROR_GOOD#_STS bit c. Sets the DONE_STS bit — If no handshake PID is received, the debug port controller: a. Sets the EXCEPTION_STS field to 001b b. Sets the ERROR_GOOD#_STS bit c. Sets the DONE_STS bit
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5.18.9.1.2 IN Transactions
An IN transaction receives data from the debug device. It can occur only when the following are true:
- The debug port is enabled
- The debug software sets the GO_CNT bit
- The WRITE_READ#_CNT bit is reset The sequence of the transaction is: 1. Software sets the appropriate values in the following bits: — USB_ADDRESS_CNF —U S B _ E N D P O I N T _ C N F — TOKEN_PID_CNT[7:0] —D A T A _ L E N _ C N T — WRITE_READ#_CNT: (note: this will always be 0 for IN transactions) — GO_CNT: (note: this will always be 1 to initiate the transaction) 2. The debug port controller sends a token packet consisting of: —S Y N C — TOKEN_PID_CNT field — USB_ADDRESS_CNT field — USB_ENDPOINT_CNT field — 5-bit CRC field. 3. After sending the token packet, the debug port controller waits for a response from the debug device. If a response is received: — The received PID is placed into the RECEIVED_PID_STS field — Any subsequent bytes are placed into the DATA_BUFFER — The DATA_LEN_CNT field is updated to show the number of bytes that were received after the PID. 4. If a valid packet was received from the device that was one byte in length (indicating it was a handshake packet), then the debug port controller: — Resets the ERROR_GOOD#_STS bit — Sets the DONE_STS bit 5. If a valid packet was received from the device that was more than one byte in length (indicating it was a data packet), then the debug port controller: — Transmits an ACK handshake packet — Resets the ERROR_GOOD#_STS bit — Sets the DONE_STS bit 6. If no valid packet is received, then the debug port controller: — Sets the EXCEPTION_STS field to 001b — Sets the ERROR_GOOD#_STS bit — Sets the DONE_STS bit.
5.18.9.1.3 Debug Software
There are two mutually exclusive conditions that debug software must address as part of its startup processing:
- The EHCI has been initialized by system software
- The EHCI has not been initialized by system software Debug software can determine the current ‘initialized’ state of the EHCI by examining the Configure Flag in the EHCI USB 2.0 Command Register. If this flag is set, then system software has initialized the EHCI. Otherwise, the EHCI should not be considered initialized. Debug software will initialize the debug port registers depending on the state of the EHCI. However, before this can be accomplished, debug software must determine which root USB port is designated as the debug port. Determining the Debug Port Debug software can easily determine which USB root port has been designated as the debug port by examining bits 20:23 of the EHCI Host Controller Structural Parameters register. This 4-bit field represents the numeric value assigned to the debug port (that is, 0001=port 1). Debug Software Startup with Non-Initialized EHCI Debug software can attempt to use the debug port if after setting the OWNER_CNT bit, the Current Connect Status bit in the appropriate (See Determining the Debug Port Presence) PORTSC register is set. If the Current Connect Status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. If a device is connected to the port, then debug software must reset/enable the port. Debug software does this by setting and then clearing the Port Reset bit the PORTSC register. To ensure a successful reset, debug software should wait at least 50 ms before clearing the Port Reset bit. Due to possible delays, this bit may not change to 0 immediately; reset is complete when this bit reads as 0. Software must not continue until this bit reads 0. If a high-speed device is attached, the EHCI will automatically set the Port Enabled/ Disabled bit in the PORTSC register and the debug software can proceed. Debug software should set the ENABLED_CNT bit in the Debug Port Control/Status register, and then reset (clear) the Port Enabled/Disabled bit in the PORTSC register (so that the system host controller driver does not see an enabled port when it is first loaded). Debug Software Startup with Initialized EHCI Debug software can attempt to use the debug port if the Current Connect Status bit in the appropriate (See Determining the Debug Port) PORTSC register is set. If the Current Connect Status bit is not set, then debug software may choose to terminate or it may choose to wait until a device is connected. If a device is connected, then debug software must set the OWNER_CNT bit and then the ENABLED_CNT bit in the Debug Port Control/Status register. Determining Debug Peripheral Presence After enabling the debug port functionality, debug software can determine if a debug peripheral is attached by attempting to send data to the debug peripheral. If all attempts result in an error (Exception bits in the Debug Port Control/Status register indicates a Transaction Error), then the attached device is not a debug peripheral. If the debug port peripheral is not present, then debug software may choose to terminate or it may choose to wait until a debug peripheral is connected.
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5.18.10 EHCI Caching
EHCI Caching is a power management feature in the USB (EHCI) host controllers which enables the controller to execute the schedules entirely in cache and eliminates the need for the DMA engine to access memory when the schedule is idle. EHCI caching allows the processor to maintain longer C-state residency times and provides substantial system power savings.
5.18.11 USB Pre-Fetch Based Pause
The Pre-Fetch Based Pause is a power management feature in USB (EHCI) host controllers to ensure maximum C3/C4 processor power state time with C2 popup. This feature applies to the period schedule, and works by allowing the DMA engine to identify periods of idleness and preventing the DMA engine from accessing memory when the periodic schedule is idle. Typically in the presence of periodic devices with multiple millisecond poll periods, the periodic schedule will be idle for several frames between polls. The USB Pre-Fetch Based Pause feature is disabled by setting bit 4 of EHCI Configuration Register Section 16.2.1.
5.18.12 Function Level Reset Support (FLR)
The USB EHCI Controllers support the Function Level Reset (FLR) capability. The FLR capability can be used in conjunction with Intel® Virtualization Technology. FLR allows an Operating System in a Virtual Machine to have complete control over a device, including its initialization, without interfering with the rest of the platform. The device provides a software interface that enables the Operating System to reset the whole device as if a PCI reset was asserted.
5.18.12.1 FLR Steps
5.18.12.1.1 FLR Initialization
- A FLR is initiated by software writing a ‘1’ to the Initiate FLR bit. 2. All subsequent requests targeting the Function will not be claimed and will be Master Abort Immediate on the bus. This includes any configuration, I/O or Memory cycles, however, the Function shall continue to accept completions targeting the Function.
5.18.12.1.2 FLR Operation
The Function will Reset all configuration, I/O and memory registers of the Function except those indicated otherwise and reset all internal states of the Function to the default or initial condition.
5.18.12.1.3 FLR Completion
The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be used to indicate to the software that the FLR reset is completed. Note: From the time Initiate FLR bit is written to 1, software must wait at least 100 ms before accessing the function.
5.18.13 USB Overcurrent Protection
The PCH has implemented programmable USB Overcurrent signals. The PCH provides a total of 8 overcurrent pins to be shared across the 14 ports. Four overcurrent signals have been allocated to the ports in each USB Device:
- OC[3:0]# for Device 29 (Ports 0-7)
- OC[7:4]# for Device 26 (Ports 8-13) Each pin is mapped to one or more ports by setting bits in the USBOCM1 and USBOCM2 ensure that each port is mapped to only one over current pin. Operation with more than one overcurrent pin mapped to a port is undefined. It is expected that multiple ports are mapped to a single overcurrent pin, however they should be connected at the port and not at the PCH pin. Shorting these pins together may lead to reduced test capabilities. By default, two ports are routed to each of the OC[6:0]# pins. OC7# is not used by default. NOTES: 1. All USB ports routed out of the package must have Overcurrent protection. It is system BIOS responsibility to ensure all used ports have OC protection. 2. USB Ports that are unused on the system (not routed out from the package) should not have OC pins assigned to them.
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5.19 Integrated USB 2.0 Rate Matching Hub
5.19.1 Overview
The PCH has integrated two USB 2.0 Rate Matching Hubs (RMH). One hub is connected to each of the EHCI controllers as shown in the figure below. The Hubs convert low and full-speed traffic into high-speed traffic. When the RMHs are enabled, they will appear to software like an external hub is connected to Port 0 of each EHCI controller. In addition, port 1 of each of the RMHs is muxed with Port 1 of the EHCI controllers and is able to bypass the RMH for use as the Debug Port. The hub operates like any USB 2.0 Discrete Hub and will consume one tier of hubs hubs can be supported on any of the PCH USB Ports. The RMH will report the following Vendor ID = 8087h and Product ID = 0020h.
5.19.2 Architecture
A hub consists of three components: the Hub Repeater, the Hub Controller, and the Transaction Translator. 1. The Hub Repeater is responsible for connectivity setup and tear-down. It also supports exception handling, such as bus fault detection and recovery and connect/ disconnect detect. 2. The Hub Controller provides the mechanism for host-to-hub communication. Hub- specific status and control commands permit the host to configure a hub and to monitor and control its individual downstream facing ports. 3. The Transaction Translator (TT) responds to high-speed split transactions and translates them to full-/low-speed transactions with full-/low-speed devices attached on downstream facing ports. There is 1 TT per RMH in the PCH. See chapter 11 of the USB 2.0 Specification for more details on the architecture of the hubs. Figure 5-10. EHCI with USB 2.0 with Rate Matching Hub
5.20 SMBus Controller (D31:F3)
The PCH provides an System Management Bus (SMBus) 2.0 host controller as well as an SMBus Slave Interface. The host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves). The PCH is also capable of operating in a mode in which it can communicate with I 2C compatible devices. The PCH can perform SMBus messages with either packet error checking (PEC) enabled or disabled. The actual PEC calculation and checking is performed in hardware by the PCH. The Slave Interface allows an external master to read from or write to the PCH. Write cycles can be used to cause certain events or pass messages, and the read cycles can be used to determine the state of various status bits. The PCH’s internal host controller cannot access the PCH’s internal Slave Interface. The PCH SMBus logic exists in Device 31:Function 3 configuration space, and consists of a transmit data path, and host controller. The transmit data path provides the data flow logic needed to implement the seven different SMBus command protocols and is controlled by the host controller. The PCH’s SMBus controller logic is clocked by RTC clock. The SMBus Address Resolution Protocol (ARP) is supported by using the existing host controller commands through software, except for the new Host Notify command (which is actually a received message). The programming model of the host controller is combined into two portions: a PCI configuration portion, and a system I/O mapped portion. All static configuration, such as the I/O base address, is done using the PCI configuration space. Real-time programming of the Host interface is done in system I/O space. The PCH SMBus host controller checks for parity errors as a target. If an error is detected, the detected parity error bit in the PCI Status Register (Device 31:Function 3:Offset 06h:bit 15) is set. If bit 6 and bit 8 of the PCI Command Register (Device 31:Function 3:Offset 04h) are set, an SERR# is generated and the signaled SERR# bit in the PCI Status Register (bit 14) is set.
5.20.1 Host Controller
The SMBus host controller is used to send commands to other SMBus slave devices. Software sets up the host controller with an address, command, and, for writes, data and optional PEC; and then tells the controller to start. When the controller has finished transmitting data on writes, or receiving data on reads, it generates an SMI# or interrupt, if enabled. The host controller supports 8 command protocols of the SMBus interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, Block Write–Block Read Process Call, and Host Notify. The SMBus host controller requires that the various data and command fields be setup for the type of command to be sent. When software sets the START bit, the SMBus Host controller performs the requested transaction, and interrupts the processor (or generates an SMI#) when the transaction is completed. Once a START command has been issued, the values of the “active registers” (Host Control, Host Command, Transmit Slave Address, Data 0, Data 1) should not be changed or read until the interrupt status message (INTR) has been set (indicating the completion of the command). Any register values needed for computation purposes should be saved prior to issuing of a new command, as the SMBus host controller updates all registers while completing the new command.
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The PCH supports the System Management Bus (SMBus) Specification, Version 2.0. Slave functionality, including the Host Notify protocol, is available on the SMBus pins. The SMLink and SMBus signals can be tied together externally depending on TCO mode used. See Section 5.14.2 for more details. Using the SMB host controller to send commands to the PCH SMB slave port is not supported.
5.20.1.1 Command Protocols
In all of the following commands, the Host Status Register (offset 00h) is used to determine the progress of the command. While the command is in operation, the HOST_BUSY bit is set. If the command completes successfully, the INTR bit will be set in the Host Status Register. If the device does not respond with an acknowledge, and the transaction times out, the DEV_ERR bit is set. If software sets the KILL bit in the Host Control Register while the command is running, the transaction will stop and the FAILED bit will be set. Quick Command When programmed for a Quick Command, the Transmit Slave Address Register is sent. The PEC byte is never appended to the Quick Protocol. Software should force the PEC_EN bit to 0 when performing the Quick Command. Software must force the I2C_EN bit to 0 when running this command. See section 5.5.1 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Send Byte / Receive Byte For the Send Byte command, the Transmit Slave Address and Device Command Registers are sent. For the Receive Byte command, the Transmit Slave Address Register is sent. The data received is stored in the DATA0 register. Software must force the I2C_EN bit to 0 when running this command. The Receive Byte is similar to a Send Byte, the only difference is the direction of data Specification, Version 2.0 for the format of the protocol. Write Byte/Word The first byte of a Write Byte/Word access is the command code. The next 1 or 2 bytes are the data to be written. When programmed for a Write Byte/Word command, the Transmit Slave Address, Device Command, and Data0 Registers are sent. In addition, the Data1 Register is sent on a Write Word command. Software must force the I2C_EN bit to 0 when running this command. See section 5.5.4 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Read Byte/Word Reading data is slightly more complicated than writing data. First the PCH must write a command to the slave device. Then it must follow that command with a repeated start condition to denote a read from that device's address. The slave then returns 1 or 2 bytes of data. Software must force the I2C_EN bit to 0 when running this command. When programmed for the read byte/word command, the Transmit Slave Address and Device Command Registers are sent. Data is received into the DATA0 on the read byte, and the DAT0 and DATA1 registers on the read word. See section 5.5.5 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.
The process call is so named because a command sends data and waits for the slave to return a value dependent on that data. The protocol is simply a Write Word followed by a Read Word, but without a second command or stop condition. When programmed for the Process Call command, the PCH transmits the Transmit Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the device is stored in the DATA0 and DATA1 registers. The Process Call command with I2C_EN set and the PEC_EN bit set produces undefined results. Software must force either I2C_EN or PEC_EN to 0 when running this command. See section 5.5.6 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Note: For process call command, the value written into bit 0 of the Transmit Slave Address Register (SMB I/O register, offset 04h) needs to be 0. Note: If the I2C_EN bit is set, the protocol sequence changes slightly: the Command Code (bits 18:11 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 19 in the sequence). Block Read/Write The PCH contains a 32-byte buffer for read and write data which can be enabled by setting bit 1 of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a single byte of buffering. This 32-byte buffer is filled with write data before transmission, and filled with read data on reception. In the PCH, the interrupt is generated only after a transmission or reception of 32 bytes, or when the entire byte count has been transmitted/received. Note: When operating in I2C mode (I2C_EN bit is set), the PCH will never use the 32-byte buffer for any block commands. The byte count field is transmitted but ignored by the PCH as software will end the transfer after all bytes it cares about have been sent or received. For a Block Write, software must either force the I2C_EN bit or both the PEC_EN and AAC bits to 0 when running this command. The block write begins with a slave address and a write condition. After the command code the PCH issues a byte count describing how many more bytes will follow in the message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h), followed by 20 bytes of data. The byte count may not be 0. A Block Read or Write is allowed to transfer a maximum of 32 data bytes. When programmed for a block write command, the Transmit Slave Address, Device Command, and Data0 (count) registers are sent. Data is then sent from the Block Data Byte register; the total data sent being the value stored in the Data0 Register. On block read commands, the first byte received is stored in the Data0 register, and the remaining bytes are stored in the Block Data Byte register. See section 5.5.7 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol. Note: For Block Write, if the I2C_EN bit is set, the format of the command changes slightly. The PCH will still send the number of bytes (on writes) or receive the number of bytes (on reads) indicated in the DATA0 register. However, it will not send the contents of the DATA0 register as part of the message. Also, the Block Write protocol sequence changes slightly: the Byte Count (bits 27:20 in the bit sequence) are not sent - as a result, the slave will not acknowledge (bit 28 in the sequence).
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This command allows the PCH to perform block reads to certain I2C devices, such as serial E2PROMs. The SMBus Block Read supports the 7-bit addressing mode only. However, this does not allow access to devices using the I2C “Combined Format” that has data bytes after the address. Typically these data bytes correspond to an offset (address) within the serial memory chips. Note: This command is supported independent of the setting of the I2C_EN bit. The I2C Read command with the PEC_EN bit set produces undefined results. Software must force both the PEC_EN and AAC bit to 0 when running this command. For I2C Read command, the value written into bit 0 of the Transmit Slave Address Register (SMB I/O register, offset 04h) needs to be 0. The format that is used for the command is shown in Table 5-40. The PCH will continue reading data from the peripheral until the NAK is received. Table 5-40. I 2C Block Read Bit Description 1S t a r t 8:2 Slave Address—7 bits 9W r i t e
10 Acknowledge from slave
18:11 Send DATA1 register
19 Acknowledge from slave
20 Repeated Start
27:21 Slave Address—7 bits
28 Read
29 Acknowledge from slave
37:30 Data byte 1 from slave—8 bits
38 Acknowledge
46:39 Data byte 2 from slave—8 bits
47 Acknowledge
– Data bytes from slave / Acknowledge – Data byte N from slave—8 bits – NOT Acknowledge –S t o p
Block Write–Block Read Process Call The block write-block read process call is a two-part message. The call begins with a slave address and a write condition. After the command code the host issues a write byte count (M) that describes how many more bytes will be written in the first part of the message. If a master has 6 bytes to send, the byte count field will have the value 6 (0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be 0. The second part of the message is a block of read data beginning with a repeated start condition followed by the slave address and a Read bit. The next byte is the read byte count (N), which may differ from the write byte count (M). The read byte count (N) cannot be 0. The combined data payload must not exceed 32 bytes. The byte length restrictions of this process call are summarized as follows:
- M ≥ 1 byte
- N ≥ 1 byte
- M + N ≤ 32 bytes The read byte count does not include the PEC byte. The PEC is computed on the total message beginning with the first slave address and using the normal PEC computational rules. It is highly recommended that a PEC byte be used with the Block Write-Block Read Process Call. Software must do a read to the command register (offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register. Note that there is no STOP condition before the repeated START condition, and that a NACK signifies the end of the read transfer. Note: E32B bit in the Auxiliary Control register must be set when using this protocol. See section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.
5.20.2 Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the SMBDATA line low to signal a start condition. The PCH continuously monitors the SMBDATA line. When the PCH is attempting to drive the bus to a 1 by letting go of the SMBDATA line, and it samples SMBDATA low, then some other master is driving the bus and the PCH will stop transferring data. If the PCH sees that it has lost arbitration, the condition is called a collision. The PCH will set the BUS_ERR bit in the Host Status Register, and if enabled, generate an interrupt or SMI#. The processor is responsible for restarting the transaction. When the PCH is a SMBus master, it drives the clock. When the PCH is sending address or command as an SMBus master, or data bytes as a master on writes, it drives data relative to the clock it is also driving. It will not start toggling the clock until the start or stop condition meets proper setup and hold time. The PCH will also ensure minimum time between SMBus transactions as a master. Note: The PCH supports the same arbitration protocol for both the SMBus and the System Management (SMLink) interfaces.
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5.20.3 Bus Timing
5.20.3.1 Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the PCH as an SMBus master would like. They have the capability of stretching the low time of the clock. When the PCH attempts to release the clock (allowing the clock to go high), the clock will remain low for an extended period of time. The PCH monitors the SMBus clock line after it releases the bus to determine whether to enable the counter for the high time of the clock. While the bus is still low, the high time counter must not be enabled. Similarly, the low period of the clock can be stretched by an SMBus master if it is not ready to send or receive data.
5.20.3.2 Bus Time Out (The PCH as SMBus Master)
If there is an error in the transaction, such that an SMBus device does not signal an acknowledge, or holds the clock lower than the allowed time-out time, the transaction will time out. The PCH will discard the cycle and set the DEV_ERR bit. The time out minimum is 25 ms (800 RTC clocks). The time-out counter inside the PCH will start after the last bit of data is transferred by the PCH and it is waiting for a response. The 25 ms timeout counter will not count under the following conditions: 1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, bit 7) is set 2. The SECOND_TO_STS bit (TCO I/O Offset 06h, bit 1) is not set (this indicates that the system has not locked up).
5.20.4 Interrupts / SMI#
The PCH SMBus controller uses PIRQB# as its interrupt pin. However, the system can alternatively be set up to generate SMI# instead of an interrupt, by setting the SMBUS_SMI_EN bit (Device 31:Function 0:Offset 40h:bit 1). Table 5-42 and Table 5-43 specify how the various enable bits in the SMBus function control the generation of the interrupt, Host and Slave SMI, and Wake internal signals. The rows in the tables are additive, which means that if more than one row is true for a particular scenario then the Results for all of the activated rows will occur. Table 5-41. Enable for SMBALERT# Event INTREN (Host Control I/O Register, Offset 02h, Bit 0) SMB_SMI_EN (Host Configuration Register, D31:F3:Offset 40h, Bit 1) SMBALERT_DIS (Slave Command I/O Register, Offset 11h, Bit 2) Result SMBALERT# asserted low (always reported in Host Status Register, Bit 5) XX X W a k e g e n e r a t e d X1 0 Slave SMI# generated (SMBUS_SMI_STS) 10 0 Interrupt generated
5.20.5 SMBALERT#
SMBALERT# is multiplexed with GPIO[11]. When enable and the signal is asserted, the PCH can generate an interrupt, an SMI#, or a wake event from S1–S5.
5.20.6 SMBus CRC Generation and Checking
If the AAC bit is set in the Auxiliary Control register, the PCH automatically calculates and drives CRC at the end of the transmitted packet for write cycles, and will check the CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The PEC bit must not be set in the Host Control register if this bit is set, or unspecified behavior will result. If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the Auxiliary Status register at offset 0Ch will be set. Table 5-42. Enables for SMBus Slave Write and SMBus Host Events Event INTREN (Host Control I/O Register, Offset 02h, Bit 0) SMB_SMI_EN (Host Configuration Register, D31:F3:Offset 40h, Bit1) Event Slave Write to Wake/ SMI# Command XX Wake generated when asleep. Slave SMI# generated when awake (SMBUS_SMI_STS). Slave Write to SMLINK_SLAVE_SMI Command XX Slave SMI# generated when in the S0 state (SMBUS_SMI_STS) Any combination of Host Status Register [4:1] asserted 0X N o n e 1 0 Interrupt generated
11 H o s t S M I # g e n e r a t e d
Table 5-43. Enables for the Host Notify Command HOST_NOTIFY_INTREN (Slave Control I/O Register, Offset 11h, bit SMB_SMI_EN (Host Config Register, D31:F3:Off40h, Bit 1) HOST_NOTIFY_WKEN (Slave Control I/O Register, Offset 11h, bit Result 0X0 N o n e XX1 W a k e g e n e r a t e d 1 0 X Interrupt generated 11X Slave SMI# generated (SMBUS_SMI_STS)
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5.20.7 SMBus Slave Interface
The PCH SMBus Slave interface is accessed using the SMBus. The SMBus slave logic will not generate or handle receiving the PEC byte and will only act as a Legacy Alerting Protocol device. The slave interface allows the PCH to decode cycles, and allows an external microcontroller to perform specific actions. Key features and capabilities include:
- Supports decode of three types of messages: Byte Write, Byte Read, and Host Notify.
- Receive Slave Address register: This is the address that the PCH decodes. A default value is provided so that the slave interface can be used without the processor having to program this register.
- Receive Slave Data register in the SMBus I/O space that includes the data written by the external microcontroller.
- Registers that the external microcontroller can read to get the state of the PCH.
- Status bits to indicate that the SMBus sl ave logic caused an interrupt or SMI# due to the reception of a message that matched the slave address. — Bit 0 of the Slave Status Register for the Host Notify command — Bit 16 of the SMI Status Register ( Section 13.8.3.9) for all others Note: The external microcontroller should not attempt to access the PCH SMBus slave logic until either: — 800 milliseconds after both: RTCRST# is high and RSMRST# is high, OR — The PLTRST# de-asserts If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more in the middle of a cycle, the PCH slave logic's behavior is undefined. This is interpreted as an unexpected idle and should be avoided when performing management activities to the slave logic. Note: When an external microcontroller accesses the SMBus Slave Interface over the SMBus a translation in the address is needed to accommodate the least significant bit used for read/write control. For example, if the PCH slave address (RCV_SLVA) is left at 44h (default), the external micro controller would use an address of 88h/89h (write/read).
5.20.7.1 Format of Slave Write Cycle
The external master performs Byte Write commands to the PCH SMBus Slave I/F. The “Command” field (bits 11:18) indicate which register is being accessed. The Data field (bits 20:27) indicate the value that should be written to that register. Table 5-44 has the values associated with the registers. Table 5-44. Slave Write Registers (Sheet 1 of 2) Register Function 0 Command Register. See Table 5-45 below for legal values written to this register. 1–3 Reserved
4 Data Message Byte 0
5 Data Message Byte 1
NOTE: The external microcontroller is responsible to make sure that it does not update the contents of the data byte registers until they have been read by the system processor. The PCH overwrites the old value with any new value received. A race condition is possible where the new value is being written to the register just at the time it is being read. The PCH will not attempt to cover this race condition (that is, unpredictable results in this case). 6–7 Reserved
8 Reserved
9–FFh Reserved Table 5-44. Slave Write Registers (Sheet 2 of 2) Register Function Table 5-45. Command Types Command Type Description
0 Reserved
WAKE/SMI#. This command wakes the system if it is not already awake. If system is already awake, an SMI# is generated. NOTE: The SMB_WAK_STS bit will be set by this command, even if the system is already awake. The SMI handler should then clear this bit. 2 Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and has the same effect as the Powerbutton Override occurring. HARD RESET WITHOUT CYCLING: This command causes a hard reset of the system (does not include cycling of the power supply). This is equivalent to a write to the CF9h register with bits 2:1 set to 1, but bit 3 set to 0. HARD RESET SYSTEM. This command causes a hard reset of the system (including cycling of the power supply). This is equivalent to a write to the CF9h register with bits 3:1 set to 1. Disable the TCO Messages. This command will disable the PCH from sending Heartbeat and Event messages (as described in Section 5.14). Once this command has been executed, Heartbeat and Event message reporting can only be re- enabled by assertion and de-assertion of the RSMRST# signal. 6 WD RELOAD: Reload watchdog timer.
7 Reserved
SMLINK_SLV_SMI. When the PCH detects this command type while in the S0 state, it sets the SMLINK_SLV_SMI_STS bit (see Section 13.9.5). This command should only be used if the system is in an S0 state. If the message is received during S1–S5 states, the PCH acknowledges it, but the SMLINK_SLV_SMI_STS bit does not get set. NOTE: It is possible that the system transitions out of the S0 state at the same time that the SMLINK_SLV_SMI command is received. In this case, the SMLINK_SLV_SMI_STS bit may get set but not serviced before the system goes to sleep. Once the system returns to S0, the SMI associated with this bit would then be generated. Software must be able to handle this scenario. 9–FFh Reserved
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5.20.7.2 Format of Read Command
The external master performs Byte Read commands to the PCH SMBus Slave interface. The “Command” field (bits 18:11) indicate which register is being accessed. The Data field (bits 30:37) contain the value that should be read from that register. Table 5-46. Slave Read Cycle Format Bit Description Driven by Comment
1 Start External Microcontroller
2-8 Slave Address - 7 bits External Microcontroller Must match value in Receive Slave Address register
9 Write External Microcontroller Always 0
10 ACK PCH
11-18 Command code – 8 bits External Microcontroller Indicates which register is being accessed. See Table 5-47 below for list of implemented registers.
19 ACK PCH
20 Repeated Start External Microcontroller
21-27 Slave Address - 7 bits External Microcontroller Must match value in Receive Slave Address register
28 Read External Microcontroller Always 1
29 ACK PCH
Value depends on register being accessed. Table 5-47 below for list of implemented registers.
38 NOT ACK External Microcontroller
39 Stop External Microcontroller
Table 5-47. Data Values for Slave Read Registers (Sheet 1 of 2) Register Bits Description 07 : 0 Reserved for capabilities indication. Should always return 00h. Future chips may return another value to indicate different capabilities. 12 : 0 System Power State 000 = S0 001 = S1 010 = Reserved 011 = S3 100 = S4 101 = S5 110 = Reserved 111 = Reserved 7:3 Reserved 23 : 0 R e s e r v e d 7:4 Reserved 35 : 0 Watchdog Timer current value Note that Watchdog Timer has 10 bits, but this field is only 6 bits. If the current value is greater than 3Fh, the PCH will always report 3Fh in this field. 7:6 Reserved 40 1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the system cover has probably been opened. 1 1 = BTI Temperature Event occurred. This bit will be set if the PCH’s THRM# input signal is active. Else this beat will read “0.”
2 DOA Processor Status. This bit will be 1 to indicate that the processor is dead 3 1 = SECOND_TO_STS bit set. This bit will be set after the second time- out (SECOND_TO_STS bit) of the Watchdog Timer occurs. 6:4 Reserved. Will always be 0, but software should ignore. Reflects the value of the GPIO[11]/SMBALERT# pin (and is dependent upon the value of the GPI_INV[11] bit. If the GPI_INV[11] bit is 1, then the value in this bit equals the level of the GPI[11]/SMBALERT# pin (high = 1, low = 0). If the GPI_INV[11] bit is 0, then the value of this bit will equal the inverse of the level of the GPIO[11]/SMBALERT# pin (high = 0, low = 1). 5 0 FWH bad bit. This bit will be 1 to indicate that the FWH read returned FFh, which indicates that it is probably blank.
1 Reserved
2 CPU Power Failure Status: ‘1’ if the CPUPWR_FLR bit in the
GEN_PMCON_2 register is set. INIT3_3V# due to receiving Shutdown message: This event is visible from the reception of the shutdown message until a platform reset is done if the Shutdown Policy Select bit (SPS) is configured to drive INIT3_3V#. When the SPS bit is configured to generate PLTRST# based on shutdown, this register bit will always return 0. Events on signal will not create a event message
4 Reserved
POWER_OK_BAD: Indicates the failure core power well ramp during boot/resume. This bit will be active if the SLP_S3# pin is de-asserted and PWROK pin is not asserted. Thermal Trip: This bit will shadow the state of processor Thermal Trip status bit (CTS) (16.2.1.2, GEN_PMCON_2, bit 3). Events on signal will not create a event message Reserved: Default value is “X” NOTE: Software should not expect a consistent value when this bit is read through SMBUS/SMLink 67 : 0 Contents of the Message 1 register. See Section 13.9.8 for the description of this register. 77 : 0 Contents of the Message 2 register. See Section 13.9.8 for the description of this register. 87 : 0 Contents of the TCO_WDCNT register. See Section 13.9.9 for the description of this register. 97 : 0 S e c o n d s o f t h e R T C A 7:0 Minutes of the RTC B7 : 0 H o u r s o f t h e R T C C 7:0 “Day of Week” of the RTC D 7:0 “Day of Month” of the RTC E 7:0 Month of the RTC F 7:0 Year of the RTC 10h–FFh 7:0 Reserved Table 5-47. Data Values for Slave Read Registers (Sheet 2 of 2) Register Bits Description
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5.20.7.2.1 Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a Start bit – Address– Write bit sequence. When the PCH detects that the address matches the value in the Receive Slave Address register, it will assume that the protocol is always followed and ignore the Write bit (bit 9) and signal an Acknowledge during bit 10. In other words, if a Start –Address–Read occurs (which is illegal for SMBus Read or Write protocol), and the address matches the PCH’s Slave Address, the PCH will still grab the cycle. Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address–Read sequence beginning at bit 20. Once again, if the Address matches the PCH’s Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and proceed with the Slave Read cycle. Note: An external microcontroller must not attempt to access the PCH’s SMBus Slave logic until at least 1 second after both RTCRST# and RSMRST# are de-asserted (high).
5.20.7.3 Slave Read of RTC Time Bytes
The PCH SMBus slave interface allows external SMBus master to read the internal RTC’s time byte registers. The RTC time bytes are internally latched by the PCH’s hardware whenever RTC time is not changing and SMBus is idle. This ensures that the time byte delivered to the slave read is always valid and it does not change when the read is still in progress on the bus. The RTC time will change whenever hardware update is in progress, or there is a software write to the RTC time bytes. The PCH SMBus slave interface only supports Byte Read operation. The external SMBus master will read the RTC time bytes one after another. It is software’s responsibility to check and manage the possible time rollover when subsequent time bytes are read. For example, assuming the RTC time is 11 hours: 59 minutes: 59 seconds. When the external SMBus master reads the hour as 11, then proceeds to read the minute, it is possible that the rollover happens between the reads and the minute is read as 0. This results in 11 hours: 0 minute instead of the correct time of 12 hours: 0 minutes. Unless it is certain that rollover will not occur, software is required to detect the possible time rollover by reading multiple times such that the read time bytes can be adjusted accordingly if needed.
5.20.7.4 Format of Host Notify Command
The PCH tracks and responds to the standard Host Notify command as specified in the System Management Bus (SMBus) Specification, Version 2.0. The host address for this command is fixed to 0001000b. If the PCH already has data for a previously-received host notify command which has not been serviced yet by the host software (as indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address byte of the protocol. This allows the host to communicate non-acceptance to the master and retain the host notify address and data values for the previous cycle until host software completely services the interrupt. Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any necessary reads of the address and data registers. Table 5-48 shows the Host Notify format.
Table 5-48. Host Notify Format Bit Description Driven By Comment
1 Start External Master
8:2 SMB Host Address—7 bits External Master Always 0001_000
9 Write External Master Always 0
10 ACK (or NACK) PCH PCH NACKs if HOST_NOTIFY_STS is 1
17:11 Device Address – 7 bits External Master Indicates the address of the master; loaded into the Notify Device Address Register
18 Unused—Always 0 External Master 7-bit-only address; this bit is inserted
27:20 Data Byte Low—8 bits External Master Loaded into the Notify Data Low Byte Register
28 ACK PCH
36:29 Data Byte High—8 bits External Master Loaded into the Notify Data High Byte Register
37 ACK PCH
38 Stop External Master
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5.21 Thermal Management
5.21.1 Thermal Sensor
The PCH incorporates one on-die Digital thermal sensor (DTS) for thermal management. The thermal sensor is used for Intel Quiet System Technology (Intel QST). The QST firmware can internally access the temperature measured by the sensors and use the data as a factor to determine how to control the fans. This thermal sensor is located near the DMI interface. The on-die thermal sensor is placed as close as possible to the hottest on-die location to reduce thermal gradients and to reduce the error on the sensor trip thresholds. The thermal Sensor trip points may be programmed to generate various interrupts including SCI, SMI, PCI and other General Purpose events.
5.21.1.1 Internal Ther mal Sensor Operation
The internal thermal sensor reports four trip points: Aux2, Aux, Hot and Catastrophic trip points in the order of increasing temperature. Aux, Aux2 Temperature Trip Points These trip points may be set dynamically if desired and provides an interrupt to ACPI (or other software) when it is crossed in either direction. These auxiliary temperature trip points do not automatically cause any hardware throttling but may be used by software to trigger interrupts. This trip point is set below the Hot temperature trip point and responses are separately programmable from the hot temperature settings, to provide incrementally more aggressive actions. Aux and Aux2 trip points are fully Software programmable during system run-time. Aux2 trip point is set below the Aux temperature trip point. Hot Temperature Trip Point This trip point may be set dynamically if desired and provides an interrupt to ACPI (or other software) when it is crossed in either direction. Software could optionally set this as an Interrupt when the temperature exceeds this level setting. Hot trip does not provide any default hardware based thermal throttling, and is available only as a customer configurable interrupt when T j,max has been reached. Catastrophic Trip Point This trip point is set at the temperature at which the PCH must be shut down immediately without any software support. The catastrophic trip point must correspond to a temperature ensured to be functional for the interrupt generation and Hardware response. Hardware response using THERMTRIP# would be an unconditional transition to S5. The catastrophic transition to the S5 state does not enforce a minimum time in the S5 state. It is assumed that the S5 residence and the reboot sequence cools down the system. If the catastrophic condition remains when the catastrophic power down enable bit is set by BIOS, then the system will re-enter S5. Thermometer Mode The thermometer is implemented using a counter that starts at 0 and increments during each sample point until the comparator indicates the temperature is above the current value. The value of the counter is loaded into a read-only register (Thermal Sensor Thermometer Read) when the comparator first trips.
5.21.1.1.1 Recommended Programm ing for Available Trip Points
There may be a ±2 °C offset due to thermal gradient between the hot-spot and the location of the thermal sensor. Trip points should be programmed to account for this temperature offset between the hot-spot Tj,max and the thermal sensor. Aux Trip Points should be programmed for software and firmware control using interrupts. Hot Trip Point should be set to throttle at 108 °C (Tj,max) due to DTS trim accuracy adjustments. Hot trip points should also be programmed for a software response. Catastrophic Trip Point should be set to halt operation to avoid maximum Tj of about 120 °C. Note: Crossing a trip point in either direction may generate several types of interrupts. Each trip point has a register that can be programmed to select the type of interrupt to be generated. Crossing a trip point is implemented as edge detection on each trip point to generate the interrupts.
5.21.1.1.2 Thermal Sensor Accuracy (T accuracy)
Taccuracy for the PCH is ±5 °C in the temperature range 90 °C to 120 °C. Taccuracy is ±10 °C for temperatures from 45 °C – 90 °C. The PCH may not operate above +108 °C. This value is based on product characterization and is not ensured by manufacturing test. Software has the ability to program the Tcat, Thot, and Taux trip points, but these trip points should be selected with consideration for the thermal sensor accuracy and the quality of the platform thermal solution. Overly conservative (unnecessarily low) temperature settings may unnecessarily degrade performance due to frequent throttling, while overly aggressive (dangerously high) temperature settings may fail to protect the part against permanent thermal damage.
5.21.2 Thermal Reporting Over System Management Link 1
Interface (SMLink1) SMLink1 interface in the PCH is the SMBus link to an optional external controller. A SMBus protocol is defined on the PCH to allow compatible devices such as Embedded Controller (EC) or SIO to obtain system thermal data from sensors integrated into components on the system using the SMLink1 interface. The sensors that can be monitored using the SMLink1 include those in the processor, the PCH, and DIMMs with sensors implemented. This solution allows an external device or controller to use the system thermal data for system thermal management. Note: To enable Thermal Reporting, the Thermal Data Reporting enable and processor/PCH/ DIMM temperature read enables have to be set in the Thermal Reporting Control (TRC) Register (See Section 22.2 for details on the register) There are 2 uses for the PCH's thermal reporting capability: 1. To provide system thermal data to an external controller. The controller can manage the fans and other cooling elements based on this data. In addition, the PCH can be programmed by setting appropriate bits in the Alert Enable (AE) Register (See Section 22.2 for details on this register) to alert the controller when a device has gone outside of its temperature limits. The alert causes the assertion of the PCH TEMP_ALERT# (SATA5GP/GPIO49/TEMP_ALERT#) signal. See Section 5.21.2.6 for more details. 2. To provide an interface between the external controller and host software. This software interface has no direct affect on the PCH's thermal collection. It is strictly a software interface to pass information or data.
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The PCH responds to thermal requests only when the system is in S0 or S1. Once the PCH has been programmed, it will start responding to a request while the system is in S0 or S1. To implement this thermal reporting capability, the platform is required to have appropriate Intel® ME firmware, BIOS support, and compatible devices that support the SMBus protocol.
5.21.2.1 Supported Addresses
The PCH supports 2 addresses: I2C Address for writes and Block Read Address for reads. These addresses need to be distinct. The two addresses may be fixed by the external controller, or programmable within the controller. The addresses used by the PCH are completely programmable.
5.21.2.1.1 I 2C Address
This address is used for writes to the PCH.
- The address is set by soft straps which are values stored in SPI flash and are defined by the OEM. The address can be set to any value the platform requires.
- This address supports all the writes listed in Table 5-49.
- SMBus reads by the external controller to this address are not allowed and result in indeterminate behavior.
5.21.2.1.2 Block Read Address
This address is used for reads from the PCH.
- The address is set by soft straps or BIOS. It can be set to any value the platform requires.
- This address only supports SMBus Bloc k Read command and not Byte or Word Read.
- The Block Read command is supported as defined in the SMBus 2.0 specification, with the command being 40h, and the byte count being provided by the PCH following the block read format in the SMBus specification.
- Writes are not allowed to this address, and result in indeterminate behavior.
- Packet Error Code (PEC) may be enabled or not, which is set up by BIOS.
5.21.2.2 I 2C Write Commands to the Intel® ME
Table 5-49 lists the write commands supported by the Intel® ME. All bits in the write commands must be written to the PCH or the operation will be aborted. For example, for 6-bytes write commands, all 48 bits must be written or the operation will be aborted. The command format follows the Block Write format of the SMBus specification. NOTE: The Status Register (STS register) is only writable by an external controller and readable by host SW. Whenever the controller writes to this register, an interrupt, if enabled by BIOS/OS, is sent to the host. The controller must always write a full 48 bits to update this register. Writes of anything other than 6 bytes result in indeterminate behavior. For bit
5.21.2.3 Block Read Command
The external controller may read thermal information from the PCH using the SMBus Block Read Command. Byte-read and Word-read SMBus commands are not supported. Note that the reads use a different address than the writes. The command format follows the Block Read format of the SMBus spec. The PCH and external controller are set up by BIOS with the length of the read that is supported by the platform. The device must always do reads of the lengths set up by BIOS. The PCH supports any one of the following lengths: 1, 2, 4, 5, 9, 10, 14 or 20 bytes. The data always comes in the order described in Table 5-50, where 0 is the first byte received in time on the SMBus. Table 5-49. I 2C Write Commands to the ME Transaction Slave Addr Data Byte0 (Commd) Data Byte 1 (Byte Count) Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Write STS Register (See Note below) I2C 41h 6h STS [47:40] STS [39:32] STS [31:24] STS [23:16] STS [15:8] STS [7:0] Write Processor Core Temp Limits I 2C 42h 4h Lower Limit [15:8] Lower Limit [7:0] Upper Limit [15:8] Upper Limit [7:0] Write Memory Controller/ Graphics Temp Limits I 2C 43h 2h Lower Limit [7:0] Upper Limit [7:0] Write PCH Temp Limits I2C 44h 2h Lower Limit [7:0] Upper Limit [7:0] Write DIMM Temp Limits I2C 45h 2h Lower Limit [7:0] Upper Limit [7:0] Write Processor Core Power Clamp I 2C 50h 2h Power Clamp [15:8] Power Clamp [7:0]
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Table 5-50. Block Read Command – Byte Definition (Sheet 1 of 2) Byte Definition Byte 0 Maximum temperature, in absolute degrees Celsius (C), of the processor core and graphics. Note that the PCH is not included in this field. It is a single byte for the highest temperature between the 2 components. This is not relative to some max or limit, but is the maximum in absolute degrees. If both the processor core and memory controller/graphics have errors on the temperature collection, this field will be FFh. If either the processor core or memory controller/graphics reports a good temper- ature, that good temperature is reported in this field. Read value represents bits [7:0] of PTV (Processor Temperature Value) Register described in Section 22.2. NOTE: Requires TRC (Thermal Reporting Control) Register bit [12] to be enabled. See Section 22.2. Byte 1 The PCH temp in degrees C. FFh indicates error condition. Read value represents bits [7:0] of ITV (Internal Temperature Values) Register described in Section 22.2. NOTE: Requires TRC (Thermal Reporting Control) Register bit [5] to be enabled. See Section 22.2. Byte 3:2 The processor core temp in degrees C. See Table 5-55 for the bit definitions. Byte 3 has bits [15:8] and Byte 2 has bits[7:0]. See Table 5-54 for Read data format and definitions. SMBUS Byte Read value [15:0] represents bits [13:0, 14,15] of CTV1 (Core Temperature Value1) Register described in Section 22.2. NOTE: Requires TRC (Thermal Reporting Control) Register bit [7] to be enabled. See Section 22.2. Byte 4 The memory controller/graphics temp in degrees C. FFh indicates error condition Read value represents bits[15:8] of ITV (Internal Temperature Values) Register described in Section 22.2. NOTE: Requires TRC (Thermal Reporting Control) Register bit [4] to be enabled. See Section 22.2. Byte 5 Thermal Sensor (TS) on DIMM 0 If DIMM not populated, or if there is no TS on DIMM, value will be 0h Read value represents bits[7:0] of DTV (DIMM Temperature Values) Register described in Section 22.2. NOTE: Requires TRC (Thermal Reporting Control) Register bit [0] to be enabled. See Section 22.2. Byte 6 Thermal Sensor (TS) on DIMM 1 If DIMM not populated, or if there is no TS on DIMM, value will be 0h Read value represents bits[15:8] of DTV (DIMM Temperature Values) Register described in Section 22.2. NOTE: Requires TRC (Thermal Reporting Control) Register bit [1] to be enabled. See Section 22.2. Byte 7 Thermal Sensor (TS) on DIMM 2 If DIMM not populated, or if there is no TS on DIMM, value will be 0h. Read value represents bits[23:16] of DTV (DIMM Temperature Values) Register described in Section 22.2. NOTE: Requires TRC (Thermal Reporting Control) Register bit [2] to be enabled. See Section 22.2.
A controller that only wants the single highest temperature from the processor core and memory controller/graphics could read one byte. A 2-byte read would provide both the PCH and processor temperature. A device that wants each components temperature would do a 5-byte read and ignore the first byte. A device that also wants DIMM information would read 9 bytes. If an external controller wanted to read the Host status, it must read 20 bytes and ignore the first 14. A device can also read the energy data provided by the processor core by reading 14 bytes.
5.21.2.4 Read Data Format
For each of the data fields an ERROR Code is listed below. This code indicates that the PCH failed in its access to the device. This would be for the case where the read returned no data, or some illegal value. In general that would mean the device is broken. The EC can treat the device that failed the read as broken or with some fail- safe mechanism. Byte 8 Thermal Sensor (TS) on DIMM 3 If DIMM not populated, or if there is no TS on DIMM, value will be 0h. Read value represents bits[31:24] of DTV (DIMM Temperature Values) Register described in Section 22.2. NOTE: Requires TRC (Thermal Reporting Control) Register bit [3] to be enabled. Byte 9 Sequence number. Can be used to check if the PCH's FW or HW is hung. See Section 5.21.2.9 for usage. This byte is updated every time the collected data is updated Read value represents bits[23:16] of ITV (Internal Temperature Values) Register described in Section 22.2. Byte 10 Bits [7:0] of the latest read of the processor core’s energy register NOTE: Requires TRC (Thermal Reporting Control TBARB+1Ah) Register bit [6] to be enabled. Byte 11 Bits [15:8] of the latest read of the processor core's energy register NOTE: Requires TRC (Thermal Reporting Control) Register bit [6] to be enabled. Byte 12 Bits [23:16] of the latest read of the processor core's energy register NOTE: Requires TRC (Thermal Reporting Control) Register bit [6] to be enabled. Byte 13 Bits [31:24] of the latest read of the processor core's energy register NOTE: Requires TRC (Thermal Reporting Control) Register bit [6] to be enabled. Byte 19:14 Host Status - This reflects what the host is presently executing. Byte 14 has bits [7:0], and byte 19 has bits [47:40] of HTS Register. For bit definition, see Section 22.2.22. Table 5-50. Block Read Command – Byte Definition (Sheet 2 of 2) Byte Definition
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5.21.2.4.1 Processor Core Temperature
The processor core temperature reading on SMLink1 is 16 bits as described in Table 5-51. The granularity is 1/64th degree. The Top byte of the SMLink1 reported processor temperature (byte 3 in Table 5-53) represents the integer component of the data, while top 6 bits of byte 2 represents the fraction portion of the reported temperature. Bit[1] is unused and Bit[0] is used as an error flag. This interpretation of the SMLink1 reported temperature differs from the temperature stored in Core Temperature Value 1 (CTV1) register. See the CTV1 register in Section 22.2.17 for the interpretation of the fields. If the processor core polling has been disabled, then the value returned is 0000h. If there is an error when the PCH reads the data from the processor core, then bit 0 is set to 1. The data provided on the SMBus read and the Write Processor Core Temp Limits command use the format above for their data.
5.21.2.4.2 PCH, Memory Controlle r/Graphics, and DIMM Temperature
The temperature readings for Bytes 0–1 and 4–8, which are the PCH, DIMM, and memory controller/graphics temperatures, are 8-bit unsigned values from 0–255. The minimum granularity supported by the internal thermal sensor is 1 °C. Thus, there are no fractional values for the PCH, memory controller/graphics, or DIMM temperatures. Note the sensors used within the components do not support values below 0 degrees, so this field is treated as 8 bits (0–255) absolute and not 2's complement (-128 to 127). Devices that are not present or that are disabled will be set to 0h. Devices that have a failed reading (that is, the read from the device did not return any legal value) will be set to FFh. A failed reading means that the attempt to read that device returned a failure. The failure could have been from a bus failure or that the device itself had an internal failure. For instance, a system may only have one DIMM and it would report only that one value, and the values for the other DIMMs would all be 00h.
5.21.2.5 Thermal Data Update Rate
The temperature values are updated every 200 ms in the PCH, so reading more often than that simply returns the same data multiple times. Also, the data may be up to 200 ms old if the external controller reads the data right before the next update window. Table 5-51. Processor Core Read Data Definition Bit Description 15:8 Integer component (0 to 255) of the processor core temperature. Note the processor core temperature can never be below 0 degrees, so this field is treated as 8 bits (0-255) absolute and not 2's complement (-128 to 127). 7:2 Fraction Value (in 1/64th). 1R e s e r v e d Illegal value or error in reading the processor core. 0 = Reads successful 1 = failure on getting the data from the processor core.
5.21.2.6 Temperature Comparator and Alert
The PCH has the ability to alert the external controller when temperatures are out of range. This is done using the PCH TEMP_ALERT# signal. The alert is a simple comparator. If any device's temperature is outside the limit range for that device, then the signal is asserted (electrical low). Note that this alert does not use the SML1ALERT#. The PCH supports 4 ranges: 1. Processor core range - upper and lower limit (8 bits each, 6 bits for fraction, in degrees C). 2. Memory Controller/Graphics range - upper and lower limit (8 bits each, in degrees C) for memory controller/graphics temperature. 3. PCH range - upper and lower limit (8 bits each, in degrees C) for the PCH temperature. 4. DIMM range - upper and lower limit (8 bits each, in degrees C), applies to all DIMMs (up to 4 supported) that are enabled. Disabled (unpopulated) DIMMs do not participate in the thermal compares. The comparator checks if the device is within the specified range, including the limits. For example, a device that is at 100 degrees when the upper limit is 100 will not trigger the alert. Likewise, a device that is at 70 degrees when the lower limit is 70 will not trigger the alert. The compares are done only on devices that have been enabled by BIOS for checking. Since BIOS knows how many DIMMs and processors are in the system, it enables the checking only for those devices that are physically present. The compares are done in firmware, so all the compares are executed in one software loop and at the end, if there is any out of bound temperature, the PCH’s TEMP_ALERT# signal is asserted. When the external controller sees the TEMP_ALERT# signal low, it knows some device is out of range. It can read the temperatures and then change the limits for the devices. Note that it may take up to 250 ms before the actual writes cause the signal to change state. For instance if the processor core is at 105 degrees and the limit is 100, the alert is triggered. If the controller changes the limits to 110, the TEMP_ALERT# signal may remain low until the next thermal sampling window (every 200 ms) occurs and only then go high, assuming the processor core was still within its limits. At boot, the controller can monitor the TEMP_ALERT# signal state. When BIOS has finished all the initialization and enabled the temperature comparators, the TEMP_ALERT# signal will be asserted since the default state of the limit registers is 0h; hence, when the PCH first reads temperatures, they will be out of range. This is the positive indication that the external controller may now read thermal information and get valid data. If the TEMP_ALERT# signal is enabled and not asserted within 30 seconds after PLTRST#, the external controller should assume there is a fatal error and handle accordingly. In general the TEMP_ALERT# signal will assert within a 1–4 seconds, depending on the actual BIOS implementation and flow. Note: The TEMP_ALERT# assertion is only valid when PLTRST# is de-asserted. The controller should mask the state of this signal when PLTRST# is asserted. Since the controller may be powered even when the PCH and the rest of the platform are not, the signal may glitch as power is being asserted; thus, the controller should wait until PLTRST# has de-asserted before monitoring the signal.
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5.21.2.6.1 Special Conditions
The external controller should have a graceful means of handling the following: 1. TEMP_ALERT# asserts, and the controller reads PCH, but all temperature values are within limits. In this case, the controller should assume that by the time the controller could read the data, it had changed and moved back within the limits. 2. External controller writes new values to temperature limits, but TEMP_ALERT# is still asserted after several hundred msecs. When read, the values are back within limits. In this case, the controller should treat this as case where the temperature changed and caused TEMP_ALERT# assertion, and then changed again to be back within limits. 3. There is the case where the external controller writes an update to the limit register, while the PCH is collecting the thermal information and updating the thermal registers. The limit change will only take affect when the write completes and the Intel® ME can process this change. If the Intel® ME is already in the process of collecting data and doing the compares, then it will continue to use the old limits during this round of compares, and then use the new limits in the next compare window. 4. Each SMBus write to change the limits is an atomic operation, but is distinct in itself. Therefore the external controller could write PCH limit, and then write memory controller/graphics limit. In the middle of those 2 writes, the thermal collecting procedure could be called by the Intel® ME, so that the comparisons for the limits are done with the new PCH limits but the old memory controller/graphics limits. Note: The limit writes are done when the SMBus write is complete; therefore, the limits are updated atomically with respect to the thermal updates and compares. There is never a case where the compares and the thermal update are interrupted in the middle by the write of new limits. The thermal updates and compares are done as one non- interruptible routine, and then the limit writes would change the limit value outside of that routine.
5.21.2.7 BIOS Set Up
For the PCH to properly report temperature and enable alerts, the BIOS must configure the PCH at boot or from suspend/resume state by writing the following information to the PCH MMIO space. This information is NOT configurable using the external controller.
- Enables for each of the 4 possible thermal alerts (Processor core, Memory Controller/Graphics, PCH and DIMM). Note that each DIMM is enabled individually.
- Enables for reading DIMM, Processor Co re, Memory Controller/Graphics, and PCH temperatures. Note that each can be enabled individually.
- SMBus address to use for each DIMM. Setting up the temperature calculation equations.
5.21.2.8 SMBus Rules
The PCH may NACK an incoming SMBus transaction. In certain cases the PCH will NACK the address, and in other cases it will NACK the command depending on internal conditions (such as, errors, busy conditions). Given that most of the cases are due to internal conditions, the external controller must alias a NACK of the command and a NACK of the address to the same behavior. The controller must not try to make any determination of the reason for the NACK, based on the type of NACK (command vs. address). The PCH will NACK when it is enabled but busy. The external controller is required to retry up to 3 times when they are NACK'ed to determine if the FW is busy with a data update. When the data values are being updated by the Intel ® ME, it will force this NACK to occur so that the data is atomically updated to the external controller. In reality if there is a NACK because of the PCH being busy, in almost all cases the next read will succeed since the update internally takes very little time. The only long delay where there can be a NACK is if the internal Intel ® ME engine is reset. This is due to some extreme error condition and is therefore rare. In this case the NACK may occur for up to 30 seconds. After that, the external controller must assume that the PCH will never return good data. Even in the best of cases, when this internal reset occurs, it will always be a second or 2 to re-enable responding.
5.21.2.8.1 During Block Read
On the Block Read, the PCH will respect the NACK and Stop indications from the external controller, but will consider this an error case. It will recover from this case and correctly handle the next SMBus request. The PCH will honor STOP during the block read command and cease providing data. On the next Block Read, the data will start with byte 0 again. However, this is not a recommended usage except for 'emergency cases'. In general the external controller should read the entire length of data that was originally programmed.
5.21.2.8.2 Power On
On the Block Read, the PCH will respect the NACK and Stop indications from the external controller, but will consider this an error case. It will recover from this case and correctly handle the next SMBus request. The PCH will honor STOP during the block read command and cease providing data. On the next Block Read, the data will start with byte 0 again. However, this is not a recommended usage except for 'emergency cases'. In general the external controller should read the entire length of data that was originally programmed.
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5.21.2.9 Case for Considerations
Below are some corner cases and some possible actions that the external controller could take. Note that a 1-byte sequence number is available to the data read by the external controller. Each time the PCH updates the thermal information it will increment the sequence number. The external controller can use this value as an indication that the thermal FW is actually operating. Note that the sequence number will roll over to 00h when it reaches FFh. 1. Power on: The PCH will not respond to any SMBus activity (on SMLink1 interface) until it has loaded the thermal Firmware (FW), which in general would take 1–4 seconds. During this period, the PCH will NACK any SMBus transaction from the external controller. The load should take 1-4 seconds, but the external controller should design for 30 seconds based on long delays for S4 resume which takes longer than normal power up. This would be an extreme case, but for larger memory footprints and non-optimized recovery times, 30 seconds is a safe number to use for the timeout. Recover/Failsafe: if the PCH has not responded within 30 seconds, the external controller can assume that the system has had a major error and the external controller should ramp the fans to some reasonably high value. The only recover from this is an internal reset on the PCH, which is not visible to the external controller. Therefore the external controller might choose to poll every 10-60 seconds (some fairly long period) hereafter to see if the PCH's thermal reporting has come alive. 2. The PCH Thermal FW hangs and requires an internal reset which is not visible to the external controller. The PCH will NACK any SMBus transaction from the external controller. The PCH may not be able to respond for up to 30 seconds while the FW is being reset and reconfigured. The external controller could choose to poll every 1-10 seconds to see if the thermal FW has been successfully reset and is now providing data. General recovery for this case is about 1 second, but 30 seconds should be used by the external controller at the timeout. Recovery/Failsafe: same as in case #1. 3. Fatal PCH error, causes a global reset of all components. When there is a fatal PCH error, a global reset may occur, and then case #1 applies. The external controller can observe, if desired, PLTRST# assertion as an indication of this event. 4. The PCH thermal FW fails or is hung, but no reset occurs. The sequence number will not be updated, so the external controller knows to go to failsafe after some number of reads (8 or so) return the same sequence number. The external controller could choose to poll every 1-10 seconds to see if the thermal FW has been successfully reset and working again. In the absence of other errors, the updates for the sequence number should never be longer than 400 ms, so the number of reads needed to indicate that there is a hang should be at around 2 seconds. But when there is an error, the sequence number may not get updated for seconds. In the case that the
external controller sees a NACK from the PCH, then it should restart its sequence counter, or otherwise be aware that the NACK condition needs to be factored into the sequence number usage. The use of sequence numbers is not required, but is provided as a means to ensure correct PCH FW operation. 5. When the PCH updates the Block Read data structure, the external controller gets a NACK during this period. To ensure atomicity of the SMBus data read with respect to the data itself, when the data buffer is being updated, the PCH will NACK the Block Read transaction. The update is only a few micro-seconds, so very short in terms of SMBus polling time; therefore, the next read should be successful. The external controller should attempt 3 reads to handle this condition before moving on. If the Block read has started (that is, the address is ACK'ed) then the entire read will complete successfully, and the PCH will update the data only after the SMBus read has completed. 6. System is going from S0 to S3/4/5. Note that the thermal monitoring FW is fully operational if the system is in S0/S1, so the following only applies to S3/4/5. When the PCH detects the OS request to go to S3/4/5, it will take the SMLink1 controller offline as part of the system preparation. The external controller will see a period where its transactions are getting NACK'ed, and then see SLP_S3# assert. This period is relatively short (a couple of seconds depending on how long all the devices take to place themselves into the D3 state), and would be far less than the 30 second limit mentioned above. 7. TEMP_ALERT#—Since there can be an in ternal reset, the TEMP_ALERT# may get asserted after the reset. The external controller must accept this assertion and handle it.
5.21.2.9.1 Example Algorithm for Handling Transaction
One algorithm for the transaction handling could be summarized as follows. This is just an example to illustrate the above rules. There could be other algorithms that can achieve the same results. 1. Perform SMBus transaction. 2. If ACK, then continue. 3. If NACK: a. Try again for 2 more times, in case the PCH is busy updating data. b. If 3 successive transactions receive NACK, then: - Ramp fans, assuming some general long reset or failure - Try every 1-10 seconds to see if SMBus transactions are now working - If they start then return to step 1 - If they continue to fail, then stay in this step and poll, but keep the fans ramped up or implement some other failure recovery mechanism
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5.22 Intel ® High Definition Audio Overview (D27:F0)
The PCH High Definition Audio (HDA) controller communicates with the external codec(s) over the Intel® High Definition Audio serial link. The controller consists of a set of DMA engines that are used to move samples of digitally encoded data between system memory and an external codec(s). The PCH implements four output DMA engines and 4 input DMA engines. The output DMA engines move digital data from system memory to a D-A converter in a codec. The PCH implements a single Serial Data Output signal (HDA_SDOUT) that is connected to all external codecs. The input DMA engines move digital data from the A-D converter in the codec to system memory. The PCH implements four Serial Digital Input signals (HDA_SDI[3:0]) supporting up to four codecs. Audio software renders outbound and processes inbound data to/from buffers in system memory. The location of individual buffers is described by a Buffer Descriptor List (BDL) that is fetched and processed by the controller. The data in the buffers is arranged in a predefined format. The output DMA engines fetch the digital data from memory and reformat it based on the programmed sample rate, bit/sample and number of channels. The data from the output DMA engines is then combined and serially sent to the external codecs over the Intel ® High Definition Audio link. The input DMA engines receive data from the codecs over the Intel® High Definition Audio link and format the data based on the programmable attributes for that stream. The data is then written to memory in the predefined format for software to process. Each DMA engine moves one stream of data. A single codec can accept or generate multiple streams of data, one for each A-D or D-A converter in the codec. Multiple codecs can accept the same output stream processed by a single DMA engine. Codec commands and responses are also transported to and from the codecs using DMA engines. The PCH HD audio controller supports the Function Level Reset (FLR).
5.22.1 Intel ® High Definition Audio Docking (Mobile Only)
5.22.1.1 Dock Sequence
Note that this sequence is followed when the system is running and a docking event occurs. 1. Since the PCH supports docking, the Docking Supported (DCKSTS. DS) bit defaults to a 1. POST BIOS and ACPI BIOS software uses this bit to determine if the HD Audio controller supports docking. BIOS may write a 0 to this RWO bit during POST to effectively turn off the docking feature. 2. After reset in the undocked quiescent state, the Dock Attach (DCKCTL.DA) bit and the Dock Mate (DCKSTS.DM) bit are both de-asserted. The HDA_DOCK_EN# signal is de-asserted and HDA_DOCK_RST# is asserted. Bit Clock, SYNC and SDO signals may or may no be running at the point in time that the docking event occurs. 3. The physical docking event is signaled to ACPI BIOS software using ACPI control methods. This is normally done through a GPIO signal on the PCH and is outside the scope of this section of the spec. 4. ACPI BIOS software first checks that the docking is supported using DCKSTS.DS=1 and that the DCKSTS.DM=0 and then initiates the docking sequence by writing a 1 to the DCKCTL.DA bit. 5. The HD Audio controller then asserts the HDA_DOCK_EN# signal so that the Bit Clock signal begins toggling to the dock codec. HDA_DOCK_EN# shall be asserted synchronously to Bit Clock and timed such that Bit Clock is low, SYNC is low, and SDO is low. Pull-down resistors on these signals in the docking station discharge
the signals low so that when the state of the signal on both sides of the switch is the same when the switch is turned on. This reduces the potential for charge coupling glitches on these signals. Note that in the PCH the first 8 bits of the Command field are “reserved” and always driven to 0's. This creates a predictable point in time to always assert HDA_DOCK_EN#. Note that the HD Audio link reset exit specification that requires that SYNC and SDO be driven low during Bit Clock startup is not ensured. Note also that the SDO and Bit Clock signals may not be low while HDA_DOCK_RST# is asserted which also violates the spec. 6. After the controller asserts HDA_DOCK_EN# it waits for a minimum of 2400 Bit Clocks (100us) and then de-asserts HDA_DOCK_RST#. This is done in such a way to meet the HD Audio link reset exit specification. HDA_DOCK_RST# de-assertion should be synchronous to Bit Clock and timed such that there are least 4 full Bit ClockS from the de-assertion of HDA_DOCK_RST# to the first frame SYNC assertion. 7. The Connect/Turnaround/Address Frame hardware initialization sequence will now occur on the dock codecs' SDI signals. A dock codec is detected when SDI is high on the last Bit Clock cycle of the Frame Sync of a Connect Frame. The appropriate bit(s) in the State Change Status (STATESTS) register will be set. The Turnaround and Address Frame initialization sequence then occurs on the dock codecs' SDI(s). 8. After this hardware initialization sequence is complete (approximately 32 frames), the controller hardware sets the DCKSTS.DM bit to 1 indicating that the dock is now mated. ACPI BIOS polls the DCKSTS.DM bit and when it detects it is set to 1, conveys this to the OS through a plug-N-play IRP. This eventually invokes the HD Audio Bus Driver, which then begins it's codec discovery, enumeration, and configuration process. 9. Alternatively to step #8, the HD Audio Bus Driver may choose to enable an interrupt by setting the WAKEEN bits for SDINs that didn't originally have codecs attached to them. When a corresponding STATESTS bit gets set an interrupt will be generated. In this case the HD Audio Bus Driver is called directly by this interrupt instead of being notified by the plug-N-play IRP. 10. HD Audio Bus Driver software “discovers” the dock codecs by comparing the bits now set in the STATESTS register with the bits that were set prior to the docking event.
5.22.1.2 Exiting D3/CRST# when Docked
- In D3/CRST#, CRST# is asserted by the HD Audio Bus Driver. CRST# asserted resets the dock state machines, but does not reset the DCKCTL.DA bit. Because the dock state machines are reset, the dock is electrically isolated (HDA_DOCK_EN# de-asserted) and DOCK_RST# is asserted. 2. The Bus Driver clears the STATESTS bits, then de-asserts CRST#, waits approximately 7ms, then checks the STATESTS bits to see which codecs are present. 3. When CRST# is de-asserted, the dock state machine detects that DCKCTL.DA is still set and the controller hardware sequences through steps to electrically connect the dock by asserting HDA_DOCK_EN# and then eventually de-asserts DOCK_RST#. This completes within the 7ms mentioned in step 2). 4. The Bus Driver enumerates the codecs present as indicated using the STATESTS bits. 5. Note that this process did not require BIOS or ACPI BIOS to set the DCKCTL.DA bit.
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5.22.1.3 Cold Boot/Resume from S3 When Docked
- When booting and resuming from S3, PLTRST# switches from asserted to de- asserted. This clears the DCKCTL.DA bit and the dock state machines. Because the dock state machines are reset, the dock is electrically isolated (HDA_DOCK_EN# de-asserted) and DOCK_RST# is asserted. 2. POST BIOS detects that the dock is attached and sets the DCKCTL.DA bit to 1. Note that at this point CRST# is still asserted so the dock state machine will remain in it's reset state. 3. The Bus Driver clears the STATESTS bits, then de-asserts CRST#, waits approximately 7ms, then checks the STATESTS bits to see which codecs are present. 4. When CRST# is de-asserted, the dock state machine detects that DCKCTL.DA is still set and the controller hardware sequences through steps to electrically connect the dock by asserting HDA_DOCK_EN# and then eventually de-asserts DOCK_RST#. This completes within the 7ms mentioned in step 3). 5. The Bus Driver enumerates the codecs present as indicated using the STATESTS bits.
5.22.1.4 Undock Sequence
There are two possible undocking scenarios. The first is the one that is initiated by the user that invokes software and gracefully shuts down the dock codecs before they are undocked. The second is referred to as the “surprise undock” where the user undocks while the dock codec is running. Both of these situations appear the same to the controller as it is not cognizant of the “surprise removal”. But both sequences will be discussed here.
5.22.1.5 Normal Undock
- In the docked quiescent state, the Dock Attach (DCKCTL.DA) bit and the Dock Mate (DCKSTS.DM) bit are both asserted. The HDA_DOCK_EN# signal is asserted and HDA_DOCK_RST# is de-asserted. 2. The user initiates an undock event through the GUI interface or by pushing a button. This mechanism is outside the scope of this section of the document. Either way ACPI BIOS software will be invoked to manage the undock process. 3. ACPI BIOS will call the HD Audio Bus Driver software to halt the stream to the dock codec(s) prior to electrical undocking. If the HD Audio Bus Driver is not capable of halting the stream to the docked codec, ACPI BIOS will initiate the hardware undocking sequence as described in the next step while the dock stream is still running. From this standpoint, the result is similar to the “surprise undock” scenario where an audio glitch may occur to the docked codec(s) during the undock process. 4. The ACPI BIOS initiates the hardware undocking sequence by writing a 0 to the DCKCTL.DA bit. 5. The HD Audio controller asserts HDA_DOCK_RST#. HDA_DOCK_RST# assertion shall be synchronous to Bit Clock. There are no other timing requirements for HDA_DOCK_RST# assertion. Note that the HD Audio link reset specification requirement that the last Frame sync be skipped will not be met. 6. A minimum of 4 Bit Clocks after HDA_DOCK_RST# the controller will de-assert HDA_DOCK_EN# to isolate the dock codec signals from the PCH HD Audio link signals. HDA_DOCK_EN# is de-asserted synchronously to Bit Clock and timed such that Bit Clock, SYNC, and SDO are low. 7. After this hardware undocking sequence is complete the controller hardware clears the DCKSTS.DM bit to 0 indicating that the dock is now un-mated. ACPI BIOS software polls DCKSTS.DM and when it sees DM set, conveys to the end user that physical undocking can proceed. The controller is now ready for a subsequent docking event.
5.22.1.6 Surprise Undock
- In the surprise undock case the user undocks before software has had the opportunity to gracefully halt the stream to the dock codec and initiate the hardware undock sequence. 2. A signal on the docking connector is connected to the switch that isolates the dock codec signals from the PCH HD Audio link signals (DOCK_DET# in the conceptual diagram). When the undock event begins to occur the switch will be put into isolate mode. 3. The undock event is communicated to the ACPI BIOS using ACPI control methods that are outside the scope of this section of the document. 4. ACPI BIOS software writes a 0 to the DCKCTL.DA bit. ACPI BIOS then calls the HD Audio Bus Driver using plug-N-play IRP. The Bus Driver then posthumously cleans up the dock codec stream. 5. The HD Audio controller hardware is oblivious to the fact that a surprise undock occurred. The flow from this point on is identical to the normal undocking sequence described in section 0 starting at step 3). It finishes with the hardware clearing the DCKSTS.DM bit set to 0 indicating that the dock is now un-mated. The controller is now ready for a subsequent docking event.
5.22.1.7 Interaction Between Dock /Undock and Power Management
When exiting from S3, PLTRST# will be asserted. The POST BIOS is responsible for initiating the docking sequence if the dock is already attached when PLTRST# is de- asserted. POST BIOS writes a 1 to the DCKCTL.DA bit prior to the HD Audio driver de- asserting CRTS# and detecting and enumerating the codecs attached to the HDA_DOCK_RST# signal. The HD Audio controller does not directly monitor a hardware signal indicating that a dock is attached. Therefore a method outside the scope of this document must be used to cause the POST BIOS to initiate the docking sequence. When exiting from D3, CRST# will be asserted. When CRST# bit is “0” (asserted), the DCKCTL.DA bit is not cleared. The dock state machine will be reset such that HDA_DOCK_EN# will be de-asserted, HDA_DOCK_RST# will be asserted and the DCKSTS.DM bit will be cleared to reflect this state. When the CRST# bit is de-asserted, the dock state machine will detect that DCKCTL.DA is set to “1” and will begin sequencing through the dock process. Note that this does not require any software intervention.
5.22.1.8 Relationship between HDA_DOCK_RST# and HDA_RST#
HDA_RST# will be asserted when a PLTRST# occurs or when the CRST# bit is 0. As long as HDA_RST# is asserted, the DOCK_RST# signal will also be asserted. When PLTRST# is asserted, the DCKCTL.DA and DCKSTS.DM bits will be get cleared to their default state (0's), and the dock state machine will be reset such that HDA_DOCK_EN# will be de-asserted, and HDA_DOCK_RST# will be asserted. After any PLTRST#, POST BIOS software is responsible for detecting that a dock is attached and then writing a “1” to the DCKCTL.DA bit prior to the HD Audio Bus Driver de-asserting CRST#. When CRST# bit is “0” (asserted), the DCKCTL.DA bit is not cleared. The dock state machine will be reset such that HDA_DOCK_EN# will be de-asserted, HDA_DOCK_RST# will be asserted and the DCKSTS.DM bit will be cleared to reflect this state. When the CRST# bit is de-asserted, the dock state machine will detect that DCKCTL.DA is set to “1” and will begin sequencing through the dock process. Note that this does not require any software intervention
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5.23 Intel ® Active Management Technology 6.0 (Intel® AMT) Intel® Active Management Technology is a set of advanced manageability features developed to meet the evolving demands placed on IT to manage a network infrastructure. Intel® AMT reduces the Total Cost of Ownership (TCO) for IT management through features such as asset tracking, remote manageability, and robust policy-based security, resulting in fewer desk-side visits and reduced incident support durations. Intel ® AMT extends the manageability capability for IT through Out Of Band (OOB), allowing asset information, remote diagnostics, recovery, and contain capabilities to be available on client systems even when they are in a low power, or “off” state, or in situations when the operating system is hung. Figure 5-11. PCH Intel® Management Engine High-Level Block Diagram
5.23.1 Intel ® AMT6.x and ASF 2.0 Features
- E-Asset Tag and OOB hardware and software Inventory Logs
- OOB Alerts that may trigger one or more aspects of Intel ® AM's management and security features over IPv4, IPv6, and KVM. Available only over wired LAN.
- IDE Redirect and Serial over LAN for Remote Control
- Remote diagnostics, remote BIOS recovery and update
- OS Lock-Up Alert and operating system Repair
- Wake capability from lower system power state, including Wake on LAN* (WOL), Wake on Manageability Packet (WOME), Wake on VOIP (WOV), and Wake on Event (WOX)
- DASH 1.0/1.1 profile compatibility and Microsoft* NAP* posturing
- Client Initiated Remote Access (CIRA)—Allows a client on the internet to, at its request, make itself discoverable on an AMT infrastructure behind a firewall for remote manageability. Available both over wired and wireless LAN.
- I n t e l® Anti-Theft Technology OOB key recovery
5.23.2 Intel ® AMT Requirements
Intel® AMT is a platform-level solution that uses multiple system components including:
- I n t e l® AMT-Ready PCH SKU
- I n t e l® Gigabit Ethernet PHY (Intel® 82577/82578 Gigabit Platform LAN Connect device) with Intel® AMT for remote access
- SPI flash memory that meets requirements set in Section 5.24.4 (64 Mb minimum for Intel® AMT 6.0) to store asset information, management software code, and logs
- BIOS to provide asset detection and POST diagnostics (BIOS and Intel ® AMT can optionally share same flash memory device)
- An ISV software package - such as LANDesk*, Altiris*, or Microsoft* SMS* - to take advantage of Intel® AMT’s platform manageability capabilities
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5.24 Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a lower-cost alternative for system flash versus the Firmware Hub on the LPC bus. The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In (MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select (SPI_CS[1:0]#). The PCH supports up to two SPI flash devices using two separate Chip Select pins. Each SPI flash device can be up to 16 MBytes. The PCH SPI interface supports 20 MHz, 33MHz, and 50 MHz SPI devices. A SPI Flash device on with Chip Select 0 with a valid descriptor MUST be attached directly to the PCH. Communication on the SPI bus is done with a Master – Slave protocol. The Slave is connected to the PCH and is implemented as a tri-state bus. Note: If Boot BIOS Strap =’00’ LPC is selected as the location for BIOS. BIOS may still be placed on LPC, but all platforms with the PCH requires SPI flash connected directly to the PCH's SPI bus with a valid descriptor connected to Chip select 0 to boot. Note: When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected by the PCH, LPC based BIOS flash is disabled.
5.24.1 SPI Supported Feature Overview
SPI Flash on the PCH has two operational modes, descriptor and non-descriptor.
5.24.1.1 Non-Descriptor Mode
Non-Descriptor Mode is not supported as a valid flash descriptor is required for all PCH Platforms.
5.24.1.2 Descriptor Mode
Descriptor Mode is required for all SKUs of the PCH. It enables many new features of the chipset:
- Integrated Gigabit Ethernet and Host processor for Gigabit Ethernet Software
- I n t e l® Active Management Technology
- I n t e l® Quiet System Technology
- I n t e l® Management Engine Firmware
- PCI Express* root port configuration
- Supports up to two SPI components using two separate chip select pins
- Hardware enforced security restricting master accesses to different regions
- Chipset Soft Strap regions provides the ability to use Flash NVM as an alternative to hardware pull-up/pull-down resistors for the PCH and Processor
- Supports the SPI Fast Read instruction and frequencies of up to 33 MHz
- Uses standardized Flash Instruction Set
5.24.1.2.1 SPI Flash Regions
In Descriptor Mode the Flash is divided into five separate regions: Only three masters can access the four regions: Host processor running BIOS code, Integrated Gigabit Ethernet and Host processor running Gigabit Ethernet Software, and Management Engine. The only required region is Region 0, the Flash Descriptor. Region 0 must be located in the first sector of device 0 (offset 0). Flash Region Sizes SPI flash space requirements differ by platform and configuration. The Flash Descriptor requires one 4 KB or larger block. GbE requires two 4 KB or larger blocks. The amount of flash space consumed is dependent on the erase granularity of the flash part and the platform requirements for the ME and BIOS regions. The Intel ME region contains firmware to support Intel Active Management Technology and other Intel ME capabilities. Region Content
0 Flash Descriptor
2 Management Engine
3 Gigabit Ethernet
Table 5-52. Region Size versus Er ase Granularity of Flash Components Region Size with 4 KB Blocks Size with 8 KB Blocks Size with 64 KB Blocks Descriptor 4 KB 8 KB 64 KB GbE 8 KB 16 KB 128 KB BIOS Varies by Platform Varies by Platform Varies by Platform ME Varies by Platform Varies by Platform Varies by Platform
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5.24.1.3 Device Partitioning
The PCH SPI Flash controller supports two sets of attributes in SPI flash space. This allows for supporting an asymmetric flash component that has two separate sets of attributes in the upper and lower part of the memory array. An example of this is a flash part that has different erase granularities in two different parts of the memory array. This allows for the usage of two separate flash vendors if using two different flash parts.
5.24.2 Flash Descriptor
The maximum size of the Flash Descriptor is 4 KB. If the block/sector size of the SPI flash device is greater than 4 KB, the flash descriptor will only use the first 4 KB of the first block. The flash descriptor requires its own block at the bottom of memory (00h). The information stored in the Flash Descriptor can only be written during the manufacturing process as its read/write permissions must be set to Read only when the computer leaves the manufacturing floor. The Flash Descriptor is made up of eleven sections (see Figure 5-13). Figure 5-12. Flash Partition Boundary Lower Flash Partition Upper Flash Partition Flash Partition Boundary
- The Flash signature selects Descriptor Mode as well as verifies if the flash is programmed and functioning. The data at the bottom of the flash (offset 0) must be 0FF0A55Ah to be in Descriptor mode. 2. The Descriptor map has pointers to the other five descriptor sections as well as the size of each. Figure 5-13. Flash Descriptor Sections Descriptor MAP Component Signature Region Master PCH Soft Straps 4KB Management Engine VSCC Table Descriptor Upper MAP OEM Section Reserved
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- The component section has information about the SPI flash in the system including: the number of components, density of each, illegal instructions (such as chip erase), and frequencies for read, fast read and write/erase instructions. 4. The Region section points to the three other regions as well as the size of each region. 5. The master region contains the security settings for the flash, granting read/write permissions for each region and identifying each master by a requestor ID. See Section 5.24.2.1 for more information. 6 & 7. The Processor and PCH chipset soft strap sections contain Processor and PCH configurable parameters. 8. The Reserved region between the top of the Processor strap section and the bottom of the OEM Section is reserved for future chipset usages. 9. The Descriptor Upper MAP determines the length and base address of the Management Engine VSCC Table. 10. The Management Engine VSCC Table holds the JEDEC ID and the VSCC information of the entire SPI Flash supported by the NVM image. 11. OEM Section is 256 Bytes reserved at the top of the Flash Descriptor for use by OEM.
5.24.2.1 Descriptor Master Region
The master region defines read and write access setting for each region of the SPI device. The master region recognizes three masters: BIOS, Gigabit Ethernet, and Management Engine. Each master is only allowed to do direct reads of its primary regions. Table 5-53. Region Access Control Table Master Read/Write Access Region Processor and BIOS ME GbE Controller Descriptor N/A N/A N/A BIOS CPU and BIOS can always read from and write to BIOS Region Read / Write Read / Write Management Engine Read / Write ME can always read from and write to ME Region Read / Write Gigabit Ethernet Read / Write Read / Write GbE software can always read from and write to GbE region Platform Data Region N/A N/A N/A
5.24.3 Flash Access
There are two types of flash accesses: Direct Access:
- Masters are allowed to do direct read only of their primary region — Gigabit Ethernet region can only be directly accessed by the Gigabit Ethernet controller. Gigabit Ethernet software must use Program Registers to access the Gigabit Ethernet region.
- Master's Host or Management Engine virtual read address is converted into the SPI Flash Linear Address (FLA) using the Flash Descriptor Region Base/Limit registers Program Register Access:
- Program Register Accesses are not allowed to cross a 4 KB boundary and can not issue a command that might extend across two components
- Software programs the FLA corresponding to the region desired — Software must read the devices Primary Region Base/Limit address to create a FLA.
5.24.3.1 Direct Access Security
- Requester ID of the device must match that of the primary Requester ID in the Master Section
- Calculated Flash Linear Address must fall between primary region base/limit
- Direct Write not allowed
- Direct Read Cache contents are reset to 0's on a read from a different master — Supports the same cache flush mechanism in ICH7 which includes Program Register Writes
5.24.3.2 Register Access Security
- Only primary region masters can access the registers Note: Processor running Gigabit Ethernet software can access Gigabit Ethernet registers
- Masters are only allowed to read or wr ite those regions they have read/write permission
- Using the Flash Region Access Permissions, one master can give another master read/write permissions to their area
- Using the five Protected Range registers, each master can add separate read/write protection above that granted in the Flash Descriptor for their own accesses — Example: BIOS may want to protect different regions of BIOS from being erased — Ranges can extend across region boundaries
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5.24.4 Serial Flash Device Compatibility Requirements
A variety of serial flash devices exist in the market. For a serial flash device to be compatible with the PCH SPI bus, it must meet the minimum requirements detailed in the following sections. Note: All PCH platforms have require Intel® Management engine Firmware.
5.24.4.1 PCH SPI Based BIOS Requirements
A serial flash device must meet the following minimum requirements when used explicitly for system BIOS storage.
- Erase size capability of at least one of the following: 64 Kbytes, 8 Kbytes, 4 Kbytes, or 256 bytes.
- Device must support multiple writes to a page without requiring a preceding erase cycle (see Section 5.24.5).
- Serial flash device must ignore the upper address bits such that an address of FFFFFFh aliases to the top of the flash memory.
- SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising edge of the clock).
- If the device receives a command that is not supported or incomplete (less than 8 bits), the device must complete the cycle gracefully without any impact on the flash content.
- An erase command (page, sector, block, chip, etc.) must set all bits inside the designated area (page, sector, block, chip, etc.) to 1 (Fh).
- Status Register bit 0 must be set to 1 when a write, erase or write to status register is in progress and cleared to 0 when a write or erase is NOT in progress.
- Devices requiring the Write Enable co mmand mst automatically clear the Write Enable Latch at the end of Data Program instructions.
- Byte write must be supported. The flexibili ty to perform a write between 1 byte to 64 bytes is recommended.
- Hardware Sequencing requirements are optional in BIOS only platforms.
- SPI flash parts that do not meet Hardware sequencing command set requirements may work in BIOS only platforms using software sequencing.
5.24.4.2 Integrated LAN Firm ware SPI Flash Requirements
A serial flash device that will be used for system BIOS and Integrated LAN or Integrated LAN only must meet all the SPI Based BIOS Requirements plus:
- Hardware sequencing.
- 4, 8, or 64 KB erase capability must be supported.
5.24.4.2.1 SPI Flash Unlocking Re quirements for Integrated LAN
BIOS must ensure there is no SPI flash based read/write/erase protection on the GbE region. GbE firmware and drivers for the integrated LAN need to be able to read, write and erase the GbE region at all times.
5.24.4.3 Intel ® Management Engine Firmware SPI Flash Requirements
Intel® Management Engine Firmware must meet the SPI flash based BIOS Requirements plus:
- Hardware Sequencing.
- Flash part must be uniform 4 KB erasable block throughout the entire device or have 64 KB blocks with the first block (lowest address) divided into 4 KB or 8 KB blocks.
- Write protection scheme must meet SPI flash unlocking requirements for Management Engine.
5.24.4.3.1 SPI Flash Unlocking Requ irements for Management Engine
Flash devices must be globally unlocked (read, write and erase access on the ME region) from power on by writing 00h to the flash’s status register to disable write protection. If the status register must be unprotected, it must use the enable write status register command 50h or write enable 06h. Opcode 01h (write to status register) must then be used to write a single byte of 00h into the status register. This must unlock the entire part. If the SPI flash’s status register has non-volatile bits that must be written to, bits [5:2] of the flash’s status register must be all 0h to indicate that the flash is unlocked. If bits [5:2] return a non zero values, the Intel ® ME firmware will send a write of 00h to the status register. This must keep the flash part unlocked. If there is no need to execute a write enable on the status register, then opcodes 06h and 50h must be ignored. After global unlock, BIOS has the ability to lock down small sections of the flash as long as they do not involve the ME or GbE region.
5.24.4.4 Hardware Sequencing Requirements
Table 5-54 contains a list of commands and the associated opcodes that a SPI-based serial flash device must support to be compatible with hardware sequencing. Table 5-54. Hardware Sequencing Commands and Opcode Requirements (Sheet 1 of 2) Commands Opcode Notes Write to Status Register 01h Writes a byte to SPI flash’s status register. Enable Write to Status Register command must be run prior to this command. Program Data 02h Single byte or 64 byte write as determined by flash part capabilities and software. Read Data 03h Write Disable 04h Read Status 05h Outputs contents of SPI flash’s status register Write Enable 06h Fast Read 0Bh Enable Write to Status Register 50h or 60h Enables a bit in the status register to allow an update to the status register
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5.24.4.4.1 JEDEC ID
Since each serial flash device may have unique capabilities and commands, the JEDEC ID is the necessary mechanism for identifying the device so the uniqueness of the device can be comprehended by the controller (master). The JEDEC ID uses the opcode 9Fh and a specified implementation and usage model. This JEDEC Standard Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV.
5.24.5 Multiple Page Write Usage Model
The system BIOS and Intel® Management Engine firmware usage models require that the serial flash device support multiple writes to a page (minimum of 512 writes) without requiring a preceding erase command. BIOS commonly uses capabilities such as counters that are used for error logging and system boot progress logging. These counters are typically implemented by using byte-writes to ‘increment’ the bits within a page that have been designated as the counter. The Intel® ME firmware usage model requires the capability for multiple data updates within any given page. These data updates occur using byte-writes without executing a preceding erase to the given page. Both the BIOS and Intel® ME firmware multiple page write usage models apply to sequential and non-sequential data writes. Note: This usage model requirement is based on any given bit only being written once from a ‘1’ to a ‘0’without requiring the preceding erase. An erase would be required to change bits back to the 1 state.
5.24.5.1 Soft Flash Protection
There are two types of flash protection that are not defined in the flash descriptor supported by PCH: 1. BIOS Range Write Protection 2. SMI#-Based Global Write Protection Both mechanisms are logically OR’d together such that if any of the mechanisms indicate that the access should be blocked, then it is blocked. Table 5-55 provides a summary of the mechanisms. A blocked command will appear to software to finish, except that the Blocked Access status bit is set in this case. Erase Program mable 256B, 4 Kbyte, 8 Kbyte or 64 Kbyte Full Chip Erase C7h Table 5-54. Hardware Sequencing Commands and Opcode Requirements (Sheet 2 of 2) Commands Opcode Notes Table 5-55. Flash Protec tion Mechanism Summary Mechanism Accesses Blocked Range Specific? Reset-Override or SMI#- Override? Equivalent Function on FWH BIOS Range Write Protection Writes Yes Reset Override FWH Sector Protection Write Protect Writes No SMI# Override Same as Write Protect in Intel® ICHs for FWH
5.24.5.2 BIOS Range Write Protection
The PCH provides a method for blocking writes to specific ranges in the SPI flash when the Protected BIOS Ranges are enabled. This is achieved by checking the Opcode type information (which can be locked down by the initial Boot BIOS) and the address of the requested command against the base and limit fields of a Write Protected BIOS range. Note: Once BIOS has locked down the Protected BIOS Range registers, this mechanism remains in place until the next system reset.
5.24.5.3 SMI# Based Global Write Protection
The PCH provides a method for blocking writes to the SPI flash when the Write Protected bit is cleared (that is, protected). This is achieved by checking the Opcode type information (which can be locked down by the initial Boot BIOS) of the requested command. The Write Protect and Lock Enable bits interact in the same manner for SPI BIOS as they do for the FWH BIOS.
5.24.6 Flash Device Configurations
The PCH-based platform must have a SPI flash connected directly to the PCH with a valid descriptor and Intel ® Management Engine Firmware. BIOS may be stored in other locations such as Firmware Hub and SPI flash hooked up directly to an embedded controller for Mobile platforms. Note this will not avoid the direct SPI flash connected to PCH requirement.
5.24.7 SPI Flash Device Recommended Pinout
The table below contains the recommended serial flash device pin-out for an 8-pin device. Use of the recommended pin-out on an 8-pin device reduces complexities involved with designing the serial flash device onto a motherboard and allows for support of a common footprint usage model (see Section 5.24.8.1). Although an 8-pin device is preferred over a 16-pin device due to footprint compatibility, the following table contains the recommended serial flash device pin-out for a 16-pin SOIC. Table 5-56. Recommended Pinout for 8-Pin Serial Flash Device Pin # Signal 1C h i p s S e l e c t
2 Data Output
3 Write Protect
4 Ground
5 Data Input
8 Supply Voltage
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5.24.8 Serial Flash Device Package
5.24.8.1 Common Footprint Usage Model
To minimize platform motherboard redesign and to enable platform Bill of Material (BOM) selectability, many PC System OEM’s design their motherboard with a single common footprint. This common footprint allows population of a soldered down device or a socket that accepts a leadless device. This enables the board manufacturer to support, using selection of the appropriate BOM, either of these solutions on the same system without requiring any board redesign. The common footprint usage model is desirable during system debug and by flash content developers since the leadless device can be easily removed and reprogrammed without damage to device leads. When the board and flash content is mature for high- volume production, both the socketed leadless solution and the soldered down leaded solution are available through BOM selection.
5.24.8.2 Serial Flash Device Package Recommendations
It is highly recommended that the common footprint usage model be supported. An example of how this can be accomplished is as follows:
- The recommended pinout for 8-pin serial flash devices is used (see Section 5.24.7).
- The 8-pin device is supported in either an 8-contact VDFPN (6x5 mm MLP) package or an 8-contact WSON (5x6 mm) package. These packages can fit into a socket that is land pattern compatible with the wide body SO8 package.
- The 8-pin device is supported in the SO8 (150 mil) and in the wide-body SO8 (200 mil) packages. The 16-pin device is supported in the SO16 (300 mil) package. Table 5-57. Recommended Pinout for 16-Pin Serial Flash Device Pin # Signal Pin # Signal
1 Hold / Reset 9 Write Protect
2 Supply Voltage 10 Ground
3 No Connect 11 No Connect
4 No Connect 12 No Connect
5 No Connect 13 No Connect
6 No Connect 14 No Connect
7 Chip Select 15 Serial Data In
8 Serial Data Out 16 Serial Clock
5.25 Intel ® Quiet System Technology (Intel® QST)
(Desktop Only) The PCH implements 4 PWM and 4 TACH signals for Intel® Quiet System Technology (QST). Note: Intel® Quiet System Technology functionality requires a correctly configured system, including an appropriate processor, PCH with Intel® ME, Intel® ME Firmware, and system BIOS support.
5.25.1 PWM Outputs
This signal is driven as open-drain. An external pull-up resistor is integrated into the fan to provide the rising edge of the PWM output signal. The PWM output is driven low during reset, which represents 0% duty cycle to the fans. After reset de-assertion, the PWM output will continue to be driven low until one of the following occurs:
- The internal PWM control register is programmed to a non-zero value by the Intel® QST firmware.
- The watchdog timer expires (enabled and set at 4 seconds by default).
- The polarity of the signal is inverted by the Intel ® QST firmware. Note that if a PWM output will be programmed to inverted polarity for a particular fan, then the low voltage driven during reset represents 100% duty cycle to the fan.
5.25.2 TACH Inputs
This signal is driven as an open-collector or open-drain output from the fan. An external pull-up is expected to be implemented on the motherboard to provide the rising edge of the TACH input. This signal has analog hysteresis and digital filtering due to the potentially slow rise and fall times. This signal has a weak internal pull-up resistor to keep the input buffer from floating if the TACH input is not connected to a fan.
5.26 Feature Capability Mechanism
A set of registers is included in the PCH LPC Interface (Device 31, Function 0, offset E0h–EBh) that allows the system software or BIOS to easily determine the features supported by the PCH. These registers can be accessed through LPC PCI configuration space, thus allowing for convenient single point access mechanism for chipset feature detection. This set of registers consists of:
- Capability ID (FDCAP)
- Capability Length (FDLEN)
- Capability Version and Vendor-Specific Capability ID (FDVER)
- Feature Vector (FVECT)
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5.27 PCH Display Interfaces and Intel ® Flexible Display
Display is divided between processor and PCH. The processor houses memory interface, display planes, and pipes while PCH has transcoder and display interface or ports. Intel® FDI connects the processor and PCH display engine. The number of planes, pipes, and transcoders decide the number of simultaneous and concurrent display devices that can be driven on a platform. The PCH integrates one Analog, LVDS (mobile only) and three Digital Ports B, C, and D. Each Digital Port can transmit data according to one or more protocols. Digital Port B, C and D can be configured to drive natively HDMI, DisplayPort or DVI. Digital Port B also supports Serial Digital Video Out (SDVO) that converts one protocol to another. Digital Port D can be configured to drive natively Embedded DisplayPort (eDP). Each display port has control signals that may be used to control, configure and/or determine the capabilities of an external device. The PCH’s Analog Port uses an integrated 340.4 MHz RAMDAC that can directly drive a standard progressive scan analog monitor up to a resolution of 2048x1536 pixels with 32-bit color at 75 Hz. The PCH SDVO port (configured through Digital Port B) is capable of driving a 200 MP (Megapixels/second) rate. Each Digital Port is capable of driving resolutions up to 2560x1600 at 60 Hz through DisplayPort and 1920x1200 at 60 Hz using HDMI or DVI (with reduced blanking).
5.27.1 Analog Display Inte rface Characteristics
The Analog Port provides a RGB signal output along with a HSYNC and VSYNC signal. There is an associated Display Data Channel (DDC) signal pair that is implemented using GPIO pins dedicated to the Analog Port. The intended target device is for a moni- tor with a VGA connector. Display devices such as LCD panels with analog inputs may work satisfactory but no functionality added to the signals to enhance that capability. Figure 5-14. Analog Port Characteristics
5.27.1.1 Integrated RAMDAC
The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that transforms the digital data from the graphics and video subsystems to analog data for the VGA monitor. The PCH’s integrated 340.4 MHz RAMDAC supports resolutions up to 2048x 1536 @ 75 Hz. Three 8-bit DACs provide the R, G, and B signals to the monitor.
5.27.1.1.1 Sync Signals
HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector. Since these levels cannot be generated internal to the device, external level shifting buffers are required. These signals can be polarity adjusted and individually disabled in one of the two possible states. The sync signals should power up disabled in the high state. No composite sync or special flat panel sync support are included.
5.27.1.1.2 VESA/VGA Mode
VESA/VGA mode provides compatibility for pre-existing software that set the display mode using the VGA CRTC registers. Timings are generated based on the VGA register values and the timing generator registers are not used.
5.27.1.2 DDC (Display Data Channel)
DDC is a standard defined by VESA. Its purpose is to allow communication between the host system and display. Both configuration and control information can be exchanged allowing plug- and-play systems to be realized. Support for DDC 1 and 2 is implemented. The PCH uses the DDC_CLK and DDC_DATA signals to communicate with the analog monitor. The PCH will generate these signals at 2.5 V. External pull-up resistors and level shifting circuitry should be implemented on the board.
5.27.2 Digital Display Interfaces
The PCH can drive a number of digital interfaces natively. The Digital Ports B, C, and/or D can be configured to drive HDMI, DVI, DisplayPort, and Embedded DisplayPort (port D only). The PCH provides a dedicated port for Digital Port LVDS (mobile only).
5.27.2.1 LVDS (Mobile only)
LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an electrical standard only defining driver output characteristics and receiver input characteristics. Each channel supports transmit clock frequency ranges from 25 MHz to 112 MHz, which provides a throughput of up to 784 Mbps on each data output and up to 112 MP/s on the input. When using both channels, each carry a portion of the data; thus, doubling the throughput to a maximum theoretical pixel rate of 224 MP/s. There are two LVDS transmitter channels (Channel A and Channel B) in the LVDS interface. Channel A and Channel B consist of 4-data pairs and a clock pair each. The LVDS data pair is used to transfer pixel data as well as the LCD timing control signals. Figure 5-15 shows a pair of LVDS signals and swing voltage.
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Logic values of 1s and 0s are represented by the differential voltage between the pair of signals. As shown in the Figure 5-16 a serial pattern of 1100011 represents one cycle of the clock.
5.27.2.2 LVDS Pair States
The LVDS pairs can be put into one of five states:
- A c t i v e
- P o w e r e d d o w n H i - Z
- Powered down 0 V
- C o m m o n m o d e
- S e n d z e r o s When in the active state, several data formats are supported. When in powered down state, the circuit enters a low power state and drives out 0V or the buffer is in the Hi-Z state on both the output pins for the entire channel. The common mode Hi-Z state is both pins of the pair set to the common mode voltage. When in the send zeros state, the circuit is powered up but sends only zero for the pixel color data regardless what the actual data is with the clock lines and timing signals sending the normal clock and timing data. The LVDS Port can be enabled/disabled using software. A disabled port enters a low power state. Once the port is enabled, individual driver pairs may be disabled based on the operating mode. Disabled drivers can be powered down for reduced power consumption or optionally fixed to forced 0s output. Individual pairs or sets of LVDS pairs can be selectively powered down when not being used. The panel power sequencing can be set to override the selected power state of the drivers during power sequencing. Figure 5-15. LVDS Signals and Swing Voltage Figure 5-16. LVDS Clock and Data Relationship
5.27.2.3 Single Channel ve rsus Dual Channel Mode
In the single channel mode, only Channel-A is used. Channel-B cannot be used for single channel mode. In the dual channel mode, both Channel-A and Channel-B pins are used concurrently to drive one LVDS display. In Single Channel mode, Channel A can take 18 bits of RGB pixel data, plus 3 bits of timing control (HSYNC/VSYNC/DE) and output them on three differential data pair outputs; or 24 bits of RGB (plus 4 bits of timing control) output on four differential data pair outputs. A dual channel interface converts 36 or 48 bits of color information plus the 3 or 4 bits of timing control respectively and outputs it on six or eight sets of differential data outputs respectively. Dual Channel mode uses twice the number of LVDS pairs and transfers the pixel data at twice the rate of the single channel. In general, one channel will be used for even pixels and the other for odd pixel data. The first pixel of the line is determined by the display enable going active and that pixel will be sent out Channel-A. All horizontal timings for active, sync, and blank will be limited to be on two pixel boundaries in the two channel modes. Note: Platforms using the PCH for integrated graphics support 24-bpp display panels of Type 1 only (compatible with VESA LVDS color mapping).
5.27.2.4 Panel Power Sequencing
This section provides details for the power sequence timing relationship of the panel power, the backlight enable and the LVDS data timing delivery. to meet the panel power timing specification requirements two signals, LFP_VDD_EN and LFP_BKLT_EN, are provided to control the timing sequencing function of the panel and the backlight power supplies. A defined power sequence is recommended when enabling the panel or disabling the panel. The set of timing parameters can vary from panel to panel vendor, provided that they stay within a predefined range of values. The panel VDD power, the backlight on/ off state and the LVDS clock and data lines are all managed by an internal power sequencer. NOTE: Support for programming parameters TX and T1 through T5 using software is provided. Figure 5-17. Panel Power Sequencing Power On Sequence from off state and Power Off Sequence after full On Panel VDD Enable Panel BackLight Enable Clock/Data Lines T1+T2 T5 T3 Valid Panel On Off Off TXT4
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5.27.2.5 LVDS DDC
The display pipe selected by the LVDS display port is programmed with the panel timing parameters that are determined by installed panel specifications or read from an onboard EDID ROM. The programmed timing values are then ‘locked’ into the registers to prevent unwanted corruption of the values. From that point on, the display modes are changed by selecting a different source size for that pipe, programming the VGA registers, or selecting a source size and enabling the VGA. The LVDS DDC helps to read the panel timing parameters or panel EDID.
5.27.2.6 High Definition Multimedia Interface
The High-Definition Multimedia Interface (HDMI) is provided for transmitting uncompressed digital audio and video signals from DVD players, set-top boxes and other audiovisual sources to television sets, projectors and other video displays. It can carry high quality multi-channel audio data and all standard and high-definition consumer electronics video formats. HDMI display interface connecting the PCH and display devices utilizes transition minimized differential signaling (TMDS) to carry audiovisual information through the same HDMI cable. HDMI includes three separate communications channels: TMDS, DDC, and the optional CEC (consumer electronics control) (not supported by the PCH). As shown in Figure 5-18, the HDMI cable carries four differential pairs that make up the TMDS data and clock channels. These channels are used to carry video, audio, and auxiliary data. In addition, HDMI carries a VESA Display. The DDC channel is used by an HDMI Source to determine the capabilities and characteristics of the Sink. Audio, video and auxiliary (control/status) data is transmitted across the three TMDS data channels. The video pixel clock is transmitted on the TMDS clock channel and is used by the receiver for data recovery on the three data channels. The digital display data signals driven natively through the PCH are AC coupled and needs level shifting to convert the AC coupled signals to the HDMI compliant digital signals. PCH HDMI interface is designed as per High-Definition Multimedia Interface Specification 1.4a. The PCH supports High-Definition Multimedia Interface Compliance Test Specification 1.4a. Figure 5-18. HDMI Overview
5.27.2.7 Digital Video Interface (DVI)
The PCH Digital Ports can be configured to drive DVI-D. DVI uses TMDS for transmitting data from the transmitter to the receiver which is similar to the HDMI protocol but the audio and CEC. Refer to the HDMI section for more information on the signals and data transmission. To drive DVI-I through the back panel the VGA DDC signals is connected along with the digital data and clock signals from one of the Digital Ports. When a sys- tem has support for a DVI-I port, then either VGA or the DVI-D through a single DVI-I connector can be driven but not both simultaneously. The digital display data signals driven natively through the PCH are AC coupled and needs level shifting to convert the AC coupled signals to the HDMI compliant digital signals.
5.27.2.8 Display Port*
DisplayPort is a digital communication interface that utilizes differential signaling to achieve a high bandwidth bus interface designed to support connections between PCs and monitors, projectors, and TV displays. DisplayPort is also suitable for display connections between consumer electronics devices such as high definition optical disc players, set top boxes, and TV displays. A DisplayPort consists of a Main Link, Auxiliary channel, and a Hot Plug Detect signal. The Main Link is a uni-directional, high-bandwidth, and low latency channel used for transport of isochronous data streams such as uncompressed video and audio. The Auxiliary Channel (AUX CH) is a half-duplex bidirectional channel used for link management and device control. The Hot Plug Detect (HPD) signal serves as an interrupt request for the sink device. PCH is designed as per VESA DisplayPort Standard Version 1.1a. The PCH supports VESA DisplayPort* PHY Compliance Test Specification 1.1 and VESA DisplayPort* Link Layer Compliance Test Specification 1.1. Note: DisplayPort includes support for Dual-Mode operation.
5.27.2.9 Embedded DisplayPort
Embedded DisplayPort (eDP*) is an embedded version of the DisplayPort standard oriented towards applications such as notebook and All-In-One PC’s. eDP is supported only on Digital Port D. Like DisplayPort, Embedded DisplayPort also consists of a Main Link, Auxiliary channel, and a optional Hot Plug Detect signal. Figure 5-19. DP Overview
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The eDP support on desktop PCH is possible because of the addition of the panel power sequencing pins: L_VDD, L_BKLT_EN and L_BLKT_CTRL. The eDP on the PCH can be configured for 2 or 4 lanes. PCH supports Embedded DisplayPort* (eDP*) Standard Version 1.1.
5.27.2.10 DisplayPort Aux Channel
A bi-directional AC coupled AUX channel interface replaces the I2C for EDID read, link management and device control. I2C-to-Aux bridges are required to connect legacy display devices.
5.27.2.11 DisplayPort Hot-Plug Detect (HPD)
The PCH supports HPD for Hot-Plug sink events on the HDMI and DisplayPort interface.
5.27.2.12 Integrated Audio over HDMI and DisplayPort
DisplayPort and HDMI interfaces on PCH support audio. Table 5-58 shows the supported audio technologies on the PCH. PCH adds support for Silent stream. Silent stream is a integrated audio feature that enables short audio streams such as system events to be heard over the HDMI and DisplayPort monitors. PCH supports silent streams over the HDMI and DisplayPort interfaces at 48 kHz, 96 kHz, and 192 kHz sampling rates.
5.27.2.13 Serial Digital Video Out (SDVO)
Serial Digital Video Out (SDVO) sends display data in serialized format which then can be converted into appropriate display protocol using a SDVO device. Serial Digital Video Out (SDVO) supports SDVO-LVDS only on the PCH. Though the SDVO electrical interface is based on the PCI Express interface, the protocol and timings are completely unique. The PCH utilizes an external SDVO device to translate from SDVO protocol and timings to the desired display format and timings. SDVO is supported only on Digital Port B of the PCH. Table 5-58. PCH supported Audio fo rmats over HDMI and DisplayPort* Audio Formats HDMI DisplayPort AC-3 - Dolby* Digital Yes No Dolby* Digital Plus Yes No DTS-HD* Yes No LPCM, 192 KHz/24 bit, 8 Channel Yes Yes (two channel - up to 96 KHz 24 bit) Dolby True HD, DTS-HD Master Audio (Losses Blu-Ray Audio Format) Yes No
5.27.2.14 Control Bus
Communication to SDVO registers and if utilized, ADD2 PROMs and monitor DDCs, are accomplished by using the SDVOCTRLDATA and SDVOCTRLCLK signals through the SDVO device. These signals run up to 400 kHz and connect directly to the SDVO device. The SDVO device is then responsible for routing the DDC and PROM data streams to the appropriate location. Consult SDVO device data sheets for level shifting requirements of these signals. Figure 5-20. SDVO Conceptual Block Diagram SDVO B 3rd Party SDVO External Device GREEN B RED B BLUE B TV Clock in Control Data Control Clock Stall Interrupt PCH LVDS Panel
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5.27.3 Mapping of Digital Display Interface Signals
Table 5-59. PCH Digital Display Port Pin Mapping Port
Description
Signals HDMI Signals SDVO Signals PCH Display Port Pin details Port B DPB_LANE3 TMDSB_CLK SDVOB_CLK DDPB_[3]P DPB_LANE3# TMDSB_CLKB SDVOB_CLK# DDPB_[3]N DPB_LANE2 TMDSB_DATA0 SDVOB_BLUE DDPB_[2]P DPB_LANE2# TMDSB_DATA0B SDVOB_BLUE# DDPB_[2]N DPB_LANE1 TMDSB_DATA1 SDVOB_GREEN DDPB_[1]P DPB_LANE1# TMDSB_DATA1B SDVOB_GREEN# DDPB_[1]N DPB_LANE0 TMDSB_DATA2 SDVOB_RED DDPB_[0]P DPB_LANE0# TMDSB_DATA2B SDVOB_RED* DDPB_[0]N DPB_HPD TMDSB_HPD DDPB_HPD DPB_AUX DDPB_AUXP DPB_AUXB DDPB_AUXN Port C DPC_LANE3 TMDSC_CLK DDPC_[3]P DPC_LANE3# TMDSC_CLKB DDPC_[3]N DPC_LANE2 TMDSC_DATA0 DDPC_[2]P DPC_LANE2# TMDSC_DATA0B DDPC_[2]N DPC_LANE1 TMDSC_DATA1 DDPC_[1]P DPC_LANE1# TMDSC_DATA1B DDPC_[1]N DPC_LANE0 TMDSC_DATA2 DDPC_[0]P DPC_LANE0# TMDSC_DATA2B DDPC_[0]N DPC_HPD TMDSC_HPD DDPC_HPD DPC_AUX DDPC_AUXP DPC_AUXC DDPC_AUXN port D DPD_LANE3 TMDSD_CLK DDPD_[3]P DPD_LANE3# TMDSD_CLKB DDPD_[3]N DPD_LANE2 TMDSD_DATA0 DDPD_[2]P DPD_LANE2# TMDSD_DATA0B DDPD_[2]N DPD_LANE1 TMDSD_DATA1 DDPD_[1]P DPD_LANE1# TMDSD_DATA1B DDPD_[1]N DPD_LANE0 TMDSD_DATA2 DDPD_[0]P DPD_LANE0# TMDSD_DATA2B DDPD_[0]N DPD_HPD TMDSD_HPD DDPD_HPD DPD_AUX DDPD_AUXP DPD_AUXD DDPD_AUXN
5.27.4 Multiple Display Configurations
The following multiple display configuration modes are supported (with appropriate driver software):
- Single Display is a mode with one display port activated to display the output to one display device.
- I n t e l® Dual Display Clone is a mode with two display ports activated to drive the display content of same color depth setting but potentially different refresh rate and resolution settings to all the active display devices connected.
- Extended Desktop is a mode with two display ports activated used to drive the content with potentially different color depth, refresh rate, and resolution settings on each of the active display devices connected. Table 5-61 describes the valid interoperability between display technologies.
5.27.5 High-bandwidth Digita l Content Protection (HDCP)
HDCP is the technology for protecting high definition content against unauthorized copy or unreceptive between a source (computer, digital set top boxes, etc.) and the sink (panels, monitor and TVs). The PCH supports HDCP 1.4 for content protection over wired displays (HDMI, DVI and DisplayPort). The HDCP 1.4 keys are integrated into the PCH and customers are not required to physically configure or handle the keys. Table 5-60. Display Co-Existence Table Display Not Attached DAC Integrated LVDS Integrated DisplayPort* HDMI*/ DVI eDP* VGA Not Attached XS S S S S DAC VGA S XS 1, C, E A A S 1, C, E Integrated LVDS SS 1, C, E XS 1, C, E S 1, C, E X Integrated DisplayPort SA S 1, C, E A A S 1, C, E HDMI/DVI SA S 1, C, E A S 1, C, E S 1, C, E SDVO LVDS SS 1, C, E S 1, C, E S 1, C, E S 1, C, E A eDP SS 1, C, E XS 1, C, E S 1, C, E X
- A = Single Pipe Single Display, Intel® Dual Display Clone (Only 24-bpp), or Extended Desktop Mode
- C = Clone Mode
- E = Extended Desktop Mode
- S = Single Pipe Single Display 1 = Single Pipe Single Display With One Display Device Disabled
- X = Unsupported/Not Applicable
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5.27.6 Intel ® Flexible Display Interconnect
Intel® FDI connects the display engine in the processor with the display interfaces on the PCH. The display data from the frame buffer is processed in the display engine of the processor and sent to the PCH over the Intel FDI where it is transcoded as per the display protocol and driven to the display monitor. Intel FDI has two channels A and B. Each channel has 4 lanes and total combined is 8 lanes to transfer the data from the processor to the PCH. Depending on the data bandwidth the interface is dynamically configured as x1, x2 or x4 lanes. Intel FDI supports lane reversal and lane polarity reversal.
5.28 Intel ® Virtualization Technology
Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software. This allows for multiple, independent operating systems to be running simultaneously on a single system. Intel ® VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets. The first revision of this technology (Intel® VT-x) added hardware support in the processor to improve the virtualization performance and robustness. The second revision of this specification (Intel® VT-d) adds chipset hardware implementation to improve I/O performance and robustness. The Intel® VT-d spec and other VT documents can be referenced here: http:// www.intel.com/technology/platform-technology/virtualization/index.htm
5.28.1 Intel ® VT-d Objectives
The key Intel® VT-d objectives are domain based isolation and hardware based virtualization. A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated. Virtualization allows for the creation of one or more partitions on a single system. This could be multiple partitions in the same OS or there can be multiple operating system instances running on the same system offering benefits such as system consolidation, legacy migration, activity partitioning or security.
5.28.2 Intel ® VT-d Features Supported
- The following devices and functions support FLR in the PCH: — High Definition Audio (Device 27: Function 0) — SATA Host Controller 1 (Device 31: Function 2) — SATA Host Controller 2 (Device 31: Function 5) — USB2 (EHCI) Host Controller 1 (Device 29: Function 0) — USB2 (EHCI) Host Controller 2 (Device 26: Function 0) — GbE Lan Host Controller (Device 25: Function 0)
- Interrupt virtualization support for IOxAPIC
- Virtualization support for HPETs
Chipset and Intel® 3400 Series Chipset Intel® VT-d allows system software (VMM/OS) to assign I/O devices to multiple domains. The system software, then, requires ways to reset I/O devices or their func- tions within, as it assigns/re-assigns I/O devices from one domain to another. The reset capability is required to ensure the devices have undergone proper re-initialization and are not keeping the stale state. A standard ability to reset I/O devices is also useful for the VMM in case where a guest domain with assigned devices has become unrespon- sive or has crashed. PCI Express defines a form of device hot reset which can be initiated through the Bridge Control register of the root/switch port to which the device is attached. How- ever, the hot reset cannot be applied selectively to specific device functions. Also, no similar standard functionality exists for resetting root-complex integrated devices. Current reset limitations can be addressed through a function level reset (FLR) mecha- nism that allows software to independently reset specific device functions.
5.28.4 Virtualization Support for PCH’s IOxAPIC
The VT-d architecture extension requires Interrupt Messages to go through the similar Address Remapping as any other memory requests. This is to allow domain isolation for interrupts such that a device assigned in one domain is not allowed to generate interrupts to another domain. The Address Remapping for VT-d is based on the Bus:Device:Function field associated with the requests. Hence, it is required for the internal IOxAPIC to initiate the Interrupt Messages using a unique Bus:Device:Function. The PCH supports BIOS programmable unique Bus:Device:Function for the internal IOxAPIC. The Bus:Device:Function field does not change the IOxAPIC functionality in anyway, nor promoting IOxAPIC as a stand-alone PCI device. The field is only used by the IOxAPIC in the following:
- As the Requestor ID when initiating Interrupt Messages to the processor
- As the Completer ID when responding to the reads targeting the IOxAPIC’s Memory-Mapped I/O registers
5.28.5 Virtualization Support fo r High Precision Event Timer
(HPET) The VT-d architecture extension requires Interrupt Messages to go through the similar Address Remapping as any other memory requests. This is to allow domain isolation for interrupts such that a device assigned in one domain is not allowed to generate interrupts to another domain. The Address Remapping for VT-d is based on the Bus:Device:Function field associated with the requests. Hence, it is required for the HPET to initiate the direct FSB Interrupt Messages using unique Bus:Device:Function. The PCH supports BIOS programmable unique Bus:Device:Function for each of the HPET timers. The Bus:Device:Function field does not change the HPET functionality in anyway, nor promoting it as a stand-alone PCI device. The field is only used by the HPET timer in the following:
- As the Requestor ID when initiating direct interrupt messages to the Processor
- As the Completer ID when responding to the reads targeting its Memory-Mapped registers The registers for the programmable Bus:Device:Function for HPET timer 7:0 reside under the Device 31:Function 0 LPC Bridge’s configuration space.
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5.29 Intel ® 5 Series Chipset and Intel® 3400 Series
PCH-based platforms require several single-ended and differential clocks to synchronize signal operation and data propagation system-wide between interfaces, and across clock domains. Depending on implementation, the clocks will either be provided by a third-party clock chip, in buffered mode, or by the PCH itself. In buffered mode, the clock chip provides the following clocks to the PCH:
- 133-MHz differential, SSC capable
- 100-MHz differential, SSC capable
- 100-MHz differential isolated for SATA, SSC capable
- 96 MHz differential
- 14.318 MHz single-ended
- Some clock chips may have an additional 25-Mhz single-ended output. This output is typically provided for LAN clocking and will not be routed through the PCH. The output signals from the PCH are:
- 1x 133-MHz differential source for proce ssor and memory, reusable as a 100-MHz PCI Express * Gen. 1.1 clock source.
- 1x 100-MHz differential source for DMI (PCI Express* 2.0 jitter tolerant)
- 2x 100-MHz differential sources for PCI Express* 2.0
- 8x 100-MHz differential sources for PCI Express* 1.1
- 5x 33.3 MHz single-ended source for PCI (1x of these is reserved as loopback clock)
- 1x 120-MHz differential source for onboard DisplayPort, reusable as a processor clock source
- 2x flexible single-ended outputs that can range from 14.31818 OR 48 MHz usable for USB, legacy platform functions, etc.
5.29.1 Platform Cloc king Requirements
Providing a platform-level clocking solution uses multiple system components including:
- I n t e l® 5 Series Chipset or Intel® 3400 Series Chipset
- 3rd party clock chip
- Intel CK505 clock specification
- 25 MHz Crystal source § §
6 Ballout Definition
This chapter contains the PCH ballout information.
6.1 PCH Desktop Ballout
This section contains the PCH Desktop ballout. Figure 6-1 and Figure 6-2 show the ballout from a top of the package quadrant view. Table 6-1 is the BGA ball list, sorted alphabetically by signal name.
284 Datasheet
Figure 6-1. PCH Ballout (top view—left side) (Desktop) BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA
1 Vss_NCTF TP22_NCT
F Vcc3_3_NC TF --- AD14 --- Vss --- V5REF --- --- CLKOUTFL EX1 / GPIO65 --- VccME --- VccADAC --- --- CRT_RED --- VccAClk 1
2 Vss_NCTF Vss_NCTF --- Vcc3_3 --- AD23 --- AD13 --- AD16 AD22 --- VccME --- CRT_DDC_
CLK --- DAC_IREF Vss --- CRT_BLUE --- 2
3 Vcc3_3_NC
TF Vcc3_3 Vss C/BE0# AD12 --- AD9 --- AD15 GNT3# / GPIO55 CLKOUTFL EX3 / GPIO67 Vss --- VccME --- Vss Vss CRT_VSYN C CRT_GRE EN --- XCLK_RCO MP 4- - - REQ2# / GPIO52 PIRQH# / GPIO5 --- --- PERR# PIRQB# REQ0# --- AD18 AD24 --- VccME VccME CRT_DDC_ DATA --- Vss CRT_HSYN C --- CRT_IRTN Vss 4
5 PIRQD# --- REQ1# /
GPIO50 Vss Vss AD21 --- C/BE2# Vss --- --- Vss VccME --- VccME Vss --- --- Vss Vss --- 5 6 --- C/BE1# --- SERR# AD2 DEVSEL# --- PAR AD29 --- TRDY# GNT1# / GPIO51 --- VccME --- CLKOUT_P CI0 --- Vss --- CLKOUTFL EX2 / GPIO66 --- 6
7 Vss --- AD10 AD7 --- --- --- IRDY# AD27 --- FRAME# AD28 --- PIRQF# /
N --- CLKOUT_P CI1 --- DDPD_CT RLCLK --- 7 8 --- AD19 --- AD5 PIRQE# / GPIO2 PIRQA# AD11 --- STOP# --- Vss Vss --- REQ3# / GPIO54 --- VccME --- Vss --- Vss --- 8
9 GNT2# /
GPIO53 --- AD8 --- Vss AD0 AD6 AD4 --- --- AD26 Vss --- Vss --- CLKOUT_P CI2 --- CLKOUT_P CI3 --- DDPD_CT RLDATA --- 9 10 --- AD3 C/BE3# AD25 --- --- --- --- --- Vss AD20 Vss --- PCIRST# --- VccME --- CLKOUTFL EX0 / GPIO64 --- DDPC_CT RLCLK --- 10 11 --- TACH3 / GPIO7 TACH0 / GPIO17 TACH2 / GPIO6 --- PIRQC# Vss AD1 AD31 AD17 CLKIN_PCI LOOPBAC K GNT0# --- PME# --- Vss --- Vss --- DDPC_CT RLDATA --- 11
12 PWM0 --- PWM2 --- Vss FWH0 /
PWM1 PIRQG# / GPIO4 Vss Vss LDRQ0# PLOCK# --- AD30 --- Vss --- CLKOUT_P CI4 --- SDVO_CT RLDATA --- 12 13 --- PWM3 --- HDA_SDIN HDA_SDIN 2 --- --- --- --- --- --- --- --- VccME --- VccME --- VccME --- SDVO_CT RLCLK --- 13
14 Vss --- HDA_BCLK HDA_RST# --- Vss FWH4 /
LFRAME# LDRQ1# / GPIO23 Vss Vss TACH1 / 15 --- USBRBIAS # --- USBRBIAS HDA_SYN C --- --- --- --- --- --- --- --- Vss --- Reserved VccME VccME --- VccME VccME 15
16 USBP13P --- V5REF_Su
s --- Vss GPIO33 GPIO13 HDA_SDO HDA_SDIN FWH3 / LAD3 FWH2 / LAD2 FWH1 / LAD1 Vcc3_3 Vcc3_3 --- VccME VccME VccME --- VccME VccME 16 18 --- USBP8P Vss USBP10P --- Vss Vss HDA_SDIN
1 Vss Vss USBP12P USBP12N VccSusHD
A Vcc3_3 --- Vss VccCore VccCore --- Vss VccME 18
19 USBP8N --- USBP7P --- Vss --- --- --- --- --- --- --- --- Vss --- VccCore VccCore Vss --- Vss Vss 19
20 --- USBP5N --- USBP7N Vss USBP11P USBP11N Vss USBP9P USBP9N USBP6P USBP6N Vss VccIO --- VccCore VccCore VccCore --- Vss Vss 20 22 --- USBP2P --- USBP4P Vss Vss USBP3N USBP3P Vss CLKIN_DO T_96N CLKIN_DO T_96P Vss VccIO VccIO --- VccCore VccCore Vss --- Vss Vss 22 23 USBP1N --- USBP2N --- Vss --- --- --- --- --- --- --- --- VccIO --- VccCore VccCore VccCore --- Vss VccCore 23 24 --- USBP1P Vss Vss --- TP9 TP10 Vss INTRUDER # PWROK RSMRST# RTCRST# Vss Vss --- VccCore VccCore Vss --- VccCore VccCore 24 26 VccSus3_3 --- VccSus3_3 --- VccSus3_3 VccSus3_3 VccSus 3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 Vss Vss --- Vss VccCore VccCore --- VccCore VccIO 26 27 --- VccSus3_3 --- VccSus3_3 VccSus3_3 --- --- --- --- --- --- --- --- Vss --- DcpSusByp Vcc3_3 Vcc3_3 --- Vss VccIO 27
28 Vss --- Vss Vss --- VccIO Vss SRTCRST# Vss Vss OC5# /
OC2# / 29 --- VccRTC --- VccSus3_3 Vss --- --- --- --- --- --- --- --- Vss --- Vss --- Vss --- Vss --- 29
30 RTCX2 --- RTCX1 --- Vss OC1# /
GPIO40 Vss OC3# / GPIO42 Vss OC7# / GPIO14 OC6# / GPIO10 GPIO8 --- TP21 --- DcpSus --- Vss --- Vss --- 30 31 --- LAN_RST# INTVRMEN SML1CLK / GPIO58 --- OC0# / GPIO59 SML1DATA / GPIO75 OC4# / GPIO43 SST SMBDATA SMBALERT # / GPIO11 SUS_STAT # / GPIO61 --- SUSCLK / GPIO62 --- Vss --- Vss --- SATA2TXN --- 31 32 --- SML1ALER T# / GPIO74 / CLK_CFG_ SEL2 DRAMPWR OK SMBCLK --- --- --- --- --- Vss GPIO57 Vss --- Vss --- Vss --- SATA5TXP --- SATA2TXP --- 32 SML0ALER T# / GPIO60 / CLK_CFG_ SEL3 --- SML0CLK --- Vss RI# WAKE# PCIECLKR Q3# / GPIO25 --- --- MEPWROK JTAG_TCK --- DcpSST --- Vss --- SATA5TXN --- Vss --- 33 34 --- GPIO72 --- PLTRST# LAN_PHY_ PWR_CTR L / GPIO12 SML0DATA GPIO24 --- JTAG_TDO --- JTAG_TMS Vss --- Vss --- SATA5RXP --- Vss --- Vss --- 34
35 SLP_LAN#
/ GPIO29 --- PEG_B_CL KRQ# / GPIO56 SLP_S3# --- --- --- SLP_S4# PCIECLKR Q0# / GPIO73 --- TRST# TP18 --- TP23 --- SATA5RXN --- SATA2RXP --- SATA1TXP --- 35 36 --- GPIO15 --- PCIECLKR Q6# / GPIO45 SLP_S5# / GPIO63 SLP_M# --- PCIECLKR Q7# / GPIO46 TP19 --- JTAG_TDI PWRBTN# --- Vss --- Vss --- SATA2RXN --- SATA1TXN --- 36
37 Vss ---
Q4# / GPIO26 --- Vss GPIO30 / PROC_MIS SING --- GPIO27 Vss --- --- Vss SATA0GP / GPIO21 --- A20GATE Vss --- --- Vss SATA3TXN --- 37 38 --- DcpRTC PCIECLKR Q5# / GPIO44 --- Vss SYS_PWR OK SATA3GP / GPIO37 PCIECLKR Q2# / GPIO20 --- SLOAD / GPIO38 SYS_RESE T# --- SPKR SATA1GP / GPIO19 SDATAOU T1 / GPIO48 --- SATA4TXP SATA4TXN --- SATA3TXP Vss 38
39 VccRTC_N
CTF --- VccSus3_3 PEG_A_CL KRQ# / GPIO47 TP20 --- INIT3_3V# --- SATALED# PCIECLKR Q1# / GPIO18 SDATAOUT 0 / GPIO39 SATA2GP / GPIO36 --- SATA4GP / GPIO16 / CLK_CFG_ SEL1 --- Vss Vss Vss SATA3RXP --- Vss 39
40 VccSus3_3
_NCTF VccSus3_3 _NCTF VccSus3_3 GPIO28 --- STP_PCI# / GPIO34 --- GPIO31 --- RCIN# SERIRQ --- GPIO32 --- SATA5GP / GPIO49 / TEMP_ALE RT# --- SATA4RXP Vss --- Vss --- 40
41 TP22_NCT
F Vss_NCTF Vss_NCTF --- Vss --- GPIO35 --- SCLOCK / GPIO22 --- --- GPIO0 --- Vss --- SATA4RXN --- --- SATA3RXN --- Vss 41 BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA
Figure 6-2. PCH Ballout (top view—right side) (Desktop) YWVUTRPNMLKJHGFEDCBA 1 --- CLKOUT_P CIE0P --- --- VccADPLLB --- Vss --- DDPB_AUX P --- --- DDPB_HPD --- Vss --- Vss_NCTF --- Vss_NCTF --- --- 1
2 XTAL25_O
UT --- CLKOUT_P CIE0N Vss --- VccADPLLA --- SDVO_STA LLP --- DDPB_AUX N Vss --- DDPD_HPD --- DDPC_1P --- DDPC_3N VccVRM Vss_NCTF --- 2 3 --- Vss Vss Vss Vss --- SDVO_STA LLN --- SDVO_INT P Vss Vss DDPC_HPD --- DDPC_1N --- DDPC_0P DDPC_3P VccVRM --- TP22_NCTF 3
4 XTAL25_IN --- CLKOUT_P
CLKOUT_P CIE6N --- Vss Vss SDVO_INT N --- DDPD_AUX N DDPD_AUX P --- DDPB_3N DDPB_3P DDPC_0N Vss --- DDPC_2N DDPC_2P --- 4
5 Vss Vss --- --- Vss Vss --- Vss Vss --- --- Vss Vss --- Vss Vss --- DDPD_0P --- Vss_NCTF 5
6 CLKOUT_P
EG_A_N --- Vss --- CLKOUT_P CIE7P --- CLKOUT_P CIE4P --- CLKOUT_P CIE2N SDVO_TVC LKINP --- Vss DDPB_2P --- DDPB_2N Vss DDPD_1P --- DDPD_0N --- 6
7 CLKOUT_P
EG_A_P --- CLKOUT_P EG_B_N --- CLKOUT_P CIE7N --- CLKOUT_P CIE4N --- CLKOUT_P CIE2P SDVO_TVC LKINN --- Vss Vss --- --- --- DDPD_1N PERn8 --- Vss 7
8 CLKOUT_P
CIE5N --- CLKOUT_P EG_B_P --- Vss --- Vss --- Vss Vss --- DDPB_0N --- DDPD_2N DDPD_2P Vss PERn6 --- PERp8 --- 8
9 CLKOUT_P
CIE5P --- Vss --- CLKOUT_P CIE1P --- TP13 --- CLKOUT_P CIE3N DDPC_AUX P --- --- Vss DDPD_3N DDPD_3P Vss --- PERp6 --- Vcc3_3 9
10 Vss --- Reserved --- CLKOUT_P
CIE1N --- TP12 --- CLKOUT_P CIE3P DDPC_AUX N DDPB_0P --- --- --- --- --- PETp7 Vss Vss --- 10 11 Reserved --- Reserved --- Vss --- Vss --- Vss Vss DDPB_1P DDPB_1N PETp6 PETn6 Vss --- PETn7 Vss PERp7 --- 11
12 Reserved --- Vss --- TP7 --- TP4 --- Vss Vss PETn8 PETp8 PETn5 PETp5 Vss Vss --- PERn5 --- PERn7 12
14 --- --- --- --- --- --- --- Vss Vss PETp4 PETn4 Vss PETn3 PETp3 Vss --- PERn4 PERp3 --- Vss 14
15 VccME --- VccIO VccIO VccIO --- VccIO --- --- --- --- --- --- --- --- Vss PERn1 --- PERn3 --- 15
16 VccME --- Vss Vss Vss --- VccIO VccIO VccIO Vss Vss Vss PETn2 PETp2 Vss Vss --- PERp1 --- PERp2 16
18 VccME --- Vss Vss Vss --- VccIO VccIO VccIO TP1 TP2 Vss DMI3RXP DMI3RXN Vss --- PETn1 Vss DMI0RXP --- 18
19 VccME --- Vss VccIO VccIO --- VccIO --- --- --- --- --- --- --- --- Vss --- DMI1RXP --- DMI0RXN 19
20 VccLAN --- TP11 VccCore VccCore --- Vss VccIO VccIO Vss Vss TP3 CLKIN_DMI
CLKIN_DMI _P Vss DMI2RXN DMI2RXP --- DMI1RXN --- 20 MP DMI_ZCOM P --- VccAPLLEX P 22 VccLAN --- Vss VccCore VccCore --- Vss VccIO VccIO Vss Vss DMI0TXN DMI0TXP DMI1TXN DMI1TXP Vss Vss --- Vss --- 22
23 VccCore --- VccCore VccCore VccCore --- Vss --- --- --- --- --- --- --- --- Vss --- Vss --- VccDMI 23
24 VccCore --- VccCore Vss VccCore --- VccIO VccIO VccIO DMI3TXN DMI3TXP Vss DMI2TXN DMI2TXP Vss --- VccIO VccIO VccIO --- 24 26 VccIO --- VccCore VccCore VccCore --- VccCore VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccCore --- VccCore --- VccCore 26 27 Vss --- Vss Vss VccCore --- VccCore --- --- --- --- --- --- --- --- VccCore VccCore --- VccCore --- 27 28 --- --- --- --- --- --- --- VccCore VccCore VccCore VccCore VccCo re VccCore VccCore VccCore --- VccCore VccCore --- VccCore 28 29 VccIO --- VccIO --- VccIO --- VccCore --- --- --- --- --- --- --- --- VccCore VccCore --- VccCore --- 29 30 Vss --- SPI_MISO --- VccIO --- VccPNAND --- Reserved Vss FDI_RXN0 FDI_RXP0 FDI_RXN1 FDI_RXP1 Vss Vss --- FDI_RXN5 --- Vss 30
31 CLKIN_BCL
K_P --- SPI_CLK --- Reserved --- Vss --- Reserved Vss FDI_RXN4 FDI_RXP4 Vss FDI_RXP3 FDI_RXN3 --- FDI_RXN2 Vss FDI_RXP5 --- 31
32 CLKIN_BCL
K_N --- SPI_CS0# --- SPI_CS1# --- Reserved --- Reserved Vss Vss --- --- --- --- --- FDI_RXP2 Vss FDI_RXP6 --- 32 33 Vss --- Vss --- Reserved --- Reserved --- Vss Reserved --- --- Reserved Reserved Reserved Vss --- FDI_RXN7 --- FDI_RXN6 33 CLKIN_SAT A_N / CKSSCD_N --- TP8 --- SPI_MOSI --- Vss --- Reserved Vss --- NV_ALE --- Vss Vss FDI_FSYNC
0 Vss --- FDI_RXP7 --- 34
CLKIN_SAT A_P / CKSSCD_P --- Vss --- Vss --- Reserved --- Reserved NV_CLE --- Reserved Reserved --- --- --- FDI_LSYNC FDI_LSYNC 0 --- Vss 35 36 VccIO --- VccIO --- VccIO --- Reserved --- Reserv ed Reserved --- Reserved Reserved --- Reserved FDI_FSYNC
1 PECI --- FDI_INT --- 36
37 SATA1RXP Vss --- --- VccIO VccIO --- Vss Vss --- --- Vss
CLKOUT_D P_N / CLKOUT_B CLK1_N --- Reserved Vss Vss PMSYNCH --- VccFDIPLL 37
38 SATA1RXN --- SATA0TXP SATA0TXN --- VccIO VccIO VccME3_3 ---
CLKOUT_B CLK0_N / CLKOUT_P CIE8N CLKOUT_B CLK0_P / CLKOUT_P CIE8P --- CLKOUT_D P_P / CLKOUT_B CLK1_P Vss Reserved --- --- THRMTRIP PROCPWR GD --- 38 39 --- Vss Vss Vss SATAICOM PI --- VccIO --- VccPNAND VccVRM Vss Vss --- Vss --- Reserved Vss Vss V_CPU_IO V_CPU_IO_ NCTF
40 Vss --- SATA0RXP Vcc3_3 --- VccIO --- VccME3_3 --- VccVRM Vss --- CLKOUT_D
MI_N --- Reserved --- Reserved --- Vss_NCTF Vss_NCTF 40 41 --- SATA0RXN --- --- SATAICOM PO --- VccSATAPL L --- VccPNAND --- --- CLKOUT_D MI_P --- Vss --- Reserved --- Vss_NCTF Vss_NCTF TP22_NCTF 41 YWVUTRPNML K J HGF EDCBA
286 Datasheet
Table 6-1. PCH Ballout by Si gnal name (Desktop Only) PCH Desktop Ball Name Ball # A20GATE AG37 AD0 AT9 AD1 AP11 AD2 AU6 AD3 AY10 AD4 AP9 AD5 AV8 AD6 AR9 AD7 AV7 AD8 AW9 AD9 AR3 AD10 AW7 AD11 AR8 AD12 AU3 AD13 AP2 AD14 AU1 AD15 AN3 AD16 AM2 AD17 AM11 AD18 AM4 AD19 AY8 AD20 AL10 AD21 AT5 AD22 AL2 AD23 AT2 AD24 AL4 AD25 AV10 AD26 AL9 AD27 AN7 AD28 AK7 AD29 AN6 AD30 AH12 AD31 AN11 C/BE0# AV3 C/BE1# AY6 C/BE2# AP5 C/BE3# AW10 CLKIN_BCLK_N Y32 CLKIN_BCLK_P Y31 CLKIN_DMI_N H20 CLKIN_DMI_P G20 CLKIN_DOT_96N AM22 CLKIN_DOT_96P AL22 CLKIN_PCILOOPBA CK AL11 CLKIN_SATA_N / CKSSCD_N Y34 CLKIN_SATA_P / CKSSCD_P Y35 CLKOUT_BCLK0_N / CLKOUT_PCIE8N L38 CLKOUT_BCLK0_P / CLKOUT_PCIE8P K38 CLKOUT_DMI_N H40 CLKOUT_DMI_P J41 CLKOUT_DP_N / CLKOUT_BCLK1_N H37 CLKOUT_DP_P / CLKOUT_BCLK1_P H38 CLKOUT_PCI0 AF6 CLKOUT_PCI1 AD7 CLKOUT_PCI2 AF9 CLKOUT_PCI3 AD9 CLKOUT_PCI4 AD12 CLKOUT_PCIE0N V2 CLKOUT_PCIE0P W1 CLKOUT_PCIE1N T10 CLKOUT_PCIE1P T9 CLKOUT_PCIE2N M6 CLKOUT_PCIE2P M7 CLKOUT_PCIE3N M9 CLKOUT_PCIE3P M10 CLKOUT_PCIE4N P7 CLKOUT_PCIE4P P6 CLKOUT_PCIE5N Y8 CLKOUT_PCIE5P Y9 CLKOUT_PCIE6N U4 CLKOUT_PCIE6P V4 CLKOUT_PCIE7N T7 CLKOUT_PCIE7P T6 CLKOUT_PEG_A_N Y6 CLKOUT_PEG_A_P Y7 CLKOUT_PEG_B_N V7 CLKOUT_PEG_B_P V8 CLKOUTFLEX0 / GPIO64 AD10 CLKOUTFLEX1 / GPIO65 AK1 PCH Desktop Ball Name Ball # CLKOUTFLEX2 / GPIO66 AB6 CLKOUTFLEX3 / GPIO67 AL3 CRT_BLUE AB2 CRT_DDC_CLK AG2 CRT_DDC_DATA AG4 CRT_GREEN AC3 CRT_HSYNC AD4 CRT_IRTN AB4 CRT_RED AC1 CRT_VSYNC AD3 DAC_IREF AE2 DcpRTC AY38 DcpSST AH33 DcpSus AF30 DcpSusByp AF27 DDPB_0N J8 DDPB_0P K10 DDPB_1N J11 DDPB_1P K11 DDPB_2N F6 DDPB_2P H6 DDPB_3N H4 DDPB_3P G4 DDPB_AUXN L2 DDPB_AUXP M1 DDPB_HPD J1 DDPC_0N F4 DDPC_0P E3 DDPC_1N G3 DDPC_1P F2 DDPC_2N C4 DDPC_2P B4 DDPC_3N D2 DDPC_3P D3 DDPC_AUXN L10 DDPC_AUXP L9 DDPC_CTRLCLK AB10 DDPC_CTRLDATA AB11 DDPC_HPD J3 DDPD_0N B6 DDPD_0P C5 DDPD_1N D7 PCH Desktop Ball Name Ball #
DDPD_1P D6 DDPD_2N G8 DDPD_2P F8 DDPD_3N G9 DDPD_3P F9 DDPD_AUXN L4 DDPD_AUXP K4 DDPD_CTRLCLK AB7 DDPD_CTRLDATA AB9 DDPD_HPD H2 DEVSEL# AT6 DMI_IRCOMP D21 DMI_ZCOMP C21 DMI0RXN A19 DMI0RXP B18 DMI0TXN J22 DMI0TXP H22 DMI1RXN B20 DMI1RXP C19 DMI1TXN G22 DMI1TXP F22 DMI2RXN E20 DMI2RXP D20 DMI2TXN H24 DMI2TXP G24 DMI3RXN G18 DMI3RXP H18 DMI3TXN L24 DMI3TXP K24 DRAMPWROK AW32 FDI_FSYNC0 E34 FDI_FSYNC1 E36 FDI_INT B36 FDI_LSYNC0 C35 FDI_LSYNC1 D35 FDI_RXN0 K30 FDI_RXN1 H30 FDI_RXN2 D31 FDI_RXN3 F31 FDI_RXN4 K31 FDI_RXN5 C30 FDI_RXN6 A33 FDI_RXN7 C33 FDI_RXP0 J30 PCH Desktop Ball Name Ball # FDI_RXP1 G30 FDI_RXP2 D32 FDI_RXP3 G31 FDI_RXP4 J31 FDI_RXP5 B31 FDI_RXP6 B32 FDI_RXP7 B34 FRAME# AL7 FWH0 / LAD0 AT12 FWH1 / LAD1 AK16 FWH2 / LAD2 AL16 FWH3 / LAD3 AM16 FWH4 / LFRAME# AR14 GNT0# AK11 GNT1# / GPIO51 AK6 GNT2# / GPIO53 BA9 GNT3# / GPIO55 AM3 GPIO0 AK41 GPIO8 AK30 GPIO13 AR16 GPIO15 AY36 GPIO24 AR34 GPIO27 AP37 GPIO28 AV40 GPIO31 AP40 GPIO32 AJ40 GPIO33 AT16 GPIO35 AR41 GPIO57 AL32 GPIO72 AY34 HDA_BCLK AW14 HDA_RST# AV14 HDA_SDIN0 AV13 HDA_SDIN1 AP18 HDA_SDIN2 AU13 HDA_SDIN3 AN16 HDA_SDO AP16 HDA_SYNC AU15 INIT3_3V# AR39 INTRUDER# AN24 INTVRMEN AW31 IRDY# AP7 JTAG_TCK AK33 JTAG_TDI AL36 PCH Desktop Ball Name Ball # JTAG_TDO AN34 JTAG_TMS AL34 LAN_PHY_PWR_CT RL / GPIO12 AU34 LAN_RST# AY31 LDRQ0# AL12 LDRQ1# / GPIO23 AP14 MEPWROK AL33 NV_ALE J34 NV_CLE L35 OC0# / GPIO59 AT31 OC1# / GPIO40 AT30 OC2# / GPIO41 AK28 OC3# / GPIO42 AP30 OC4# / GPIO43 AP31 OC5# / GPIO9 AL28 OC6# / GPIO10 AL30 OC7# / GPIO14 AM30 PAR AP6 PCIECLKRQ0# / GPIO73 AN35 PCIECLKRQ1# / GPIO18 AM39 PCIECLKRQ2# / GPIO20 AP38 PCIECLKRQ3# / GPIO25 AP33 PCIECLKRQ4# / GPIO26 AW37 PCIECLKRQ5# / GPIO44 AW38 PCIECLKRQ6# / GPIO45 AV36 PCIECLKRQ7# / GPIO46 AP36 PCIRST# AH10 PECI D36 PEG_A_CLKRQ# / GPIO47 AV39 PEG_B_CLKRQ# / GPIO56 AW35 PERn1 D15 PERn2 B17 PERn3 B15 PERn4 D14 PERn5 C12 PCH Desktop Ball Name Ball #
288 Datasheet
PERR# AT4 PETn1 D18 PETn2 H16 PETn3 H14 PETn4 K14 PETn5 H12 PETn6 G11 PETn7 D11 PETn8 K12 PETp1 D17 PETp2 G16 PETp3 G14 PETp4 L14 PETp5 G12 PETp6 H11 PETp7 D10 PETp8 J12 PIRQA# AT8 PIRQB# AR4 PIRQC# AT11 PIRQD# BA5 PIRQE# / GPIO2 AU8 PIRQF# / GPIO3 AH7 PIRQG# / GPIO4 AP12 PIRQH# / GPIO5 AW4 PLOCK# AK12 PLTRST# AV34 PME# AH11 PMSYNCH C37 PROC_MISSING/ GPIO30 AT37 PROCPWRGD B38 PWM0 BA12 PCH Desktop Ball Name Ball # PWM1 AR12 PWM2 AW12 PWM3 AY13 PWRBTN# AK36 PWROK AM24 RCIN# AM40 REFCLK14IN AF7 REQ0# AP4 REQ1# / GPIO50 AW5 REQ2# / GPIO52 AY4 REQ3# / GPIO54 AH8 Reserved AF15 Reserved V11 Reserved Y12 Reserved V10 Reserved Y11 Reserved H36 Reserved H35 Reserved P32 Reserved E41 Reserved T33 Reserved P35 Reserved H33 Reserved F37 Reserved E39 Reserved G33 Reserved D40 Reserved F33 Reserved T31 Reserved P33 Reserved M35 Reserved L33 Reserved M36 Reserved M34 Reserved M30 Reserved F36 Reserved P36 Reserved F40 Reserved M32 Reserved L36 Reserved M31 Reserved F38 Reserved J36 Reserved J35 PCH Desktop Ball Name Ball # RI# AT33 RSMRST# AL24 RTCRST# AK24 RTCX1 AW30 RTCX2 BA30 SATA0GP / GPIO21 AJ37 SATA0RXN W41 SATA0RXP V40 SATA0TXN U38 SATA0TXP V38 SATA1GP / GPIO19 AH38 SATA1RXN Y38 SATA1RXP Y37 SATA1TXN AB36 SATA1TXP AB35 SATA2GP / GPIO36 AK39 SATA2RXN AD36 SATA2RXP AD35 SATA2TXN AB31 SATA2TXP AB32 SATA3GP / GPIO37 AR38 SATA3RXN AC41 SATA3RXP AC39 SATA3TXN AB37 SATA3TXP AB38 SATA4GP / GPIO16 / CLK_CFG_SEL1 AH39 SATA4RXN AF41 SATA4RXP AE40 SATA4TXN AD38 SATA4TXP AE38 SATA5GP / GPIO49 / TEMP_ALERT# AG40 SATA5RXN AF35 SATA5RXP AF34 SATA5TXN AD33 SATA5TXP AD32 SATAICOMPI T39 SATAICOMPO T41 SATALED# AN39 SCLOCK / GPIO22 AN41 SDATAOUT0 / GPIO39 AL39 SDATAOUT1 / GPIO48 AG38 PCH Desktop Ball Name Ball #
SDVO_CTRLCLK AB13 SDVO_CTRLDATA AB12 SDVO_INTN N4 SDVO_INTP M3 SDVO_STALLN P3 SDVO_STALLP N2 SDVO_TVCLKINN L7 SDVO_TVCLKINP L6 SERIRQ AL40 SERR# AV6 SLOAD / GPIO38 AM38 SLP_LAN# / GPIO29 BA35 SLP_M# AT36 SLP_S3# AV35 SLP_S4# AP35 SLP_S5# / GPIO63 AU36 SMBALERT# / GPIO11 AL31 SMBCLK AV32 SMBDATA AM31 SML0ALERT# / GPIO60 / CLK_CFG_SEL3 BA33 SML0CLK AW33 SML0DATA AT34 SML1ALERT# / GPIO74 / CLK_CFG_SEL2 AY32 SML1CLK / GPIO58 AV31 SML1DATA / GPIO75 AR31 SPI_CLK V31 SPI_CS0# V32 SPI_CS1# T32 SPI_MISO V30 SPI_MOSI T34 SPKR AJ38 SRTCRST# AP28 SST AN31 STOP# AN8 STP_PCI# / GPIO34 AT40 SUS_STAT# / GPIO61 AK31 SUSCLK / GPIO62 AH31 PCH Desktop Ball Name Ball # SYS_PWROK AT38 SYS_RESET# AL38 TACH0 / GPIO17 AW11 TACH1 / GPIO1 AL14 TACH2 / GPIO6 AV11 TACH3 / GPIO7 AY11 THRMTRIP# C38 TP1 L18 TP2 K18 TP3 J20 TP4 P12 TP5 P13 TP6 T13 TP7 T12 TP8 V34 TP9 AT24 TP10 AR24 TP11 V20 TP12 P10 TP13 P9 TP18 AK35 TP19 AN36 TP20 AU39 TP21 AH30 TP22_NCTF AY1 TP22_NCTF A3 TP22_NCTF BA41 TP22_NCTF A41 TP23 AH35 TRDY# AL6 TRST# AL35 USBP0N AW25 USBP0P AY25 USBP1N BA23 USBP1P AY24 USBP2N AW23 USBP2P AY22 USBP3N AR22 USBP3P AP22 USBP4N AV21 USBP4P AV22 USBP5N AY20 USBP5P AW21 USBP6N AK20 PCH Desktop Ball Name Ball # USBP6P AL20 USBP7N AV20 USBP7P AW19 USBP8N BA19 USBP8P AY18 USBP9N AM20 USBP9P AN20 USBP10N AV17 USBP10P AV18 USBP11N AR20 USBP11P AT20 USBP12N AK18 USBP12P AL18 USBP13N AY17 USBP13P BA16 USBRBIAS AV15 USBRBIAS# AY15 V_CPU_IO B39 V_CPU_IO_NCTF A39 V5REF AN1 V5REF_Sus AW16 Vcc3_3 AV2 Vcc3_3 AY3 Vcc3_3 AK14 Vcc3_3 AJ14 Vcc3_3 AJ16 Vcc3_3 AE27 Vcc3_3 AD27 Vcc3_3 U40 Vcc3_3 A9 Vcc3_3 AH16 Vcc3_3 AH18 Vcc3_3_NCTF AW1 Vcc3_3_NCTF BA3 VccAClk AA1 VccADAC AF1 VccADPLLA R2 VccADPLLB T1 VccAPLLEXP A21 VccCore AE18 VccCore AD18 VccCore AF19 VccCore AE19 VccCore AF20 PCH Desktop Ball Name Ball #
290 Datasheet
Ball Name Ball # VccCore G28 VccCore F28 VccCore D28 VccCore C28 VccCore A28 VccCore P29 VccCore E29 VccCore D29 VccCore B29 VccDMI A23 VccFDIPLL A37 VccIO AH20 VccIO AJ22 VccIO AH22 VccIO AH23 VccIO U15 VccIO T15 VccIO AA27 VccIO Y29 VccIO V29 VccIO T29 VccIO T30 VccIO Y36 VccIO V36 VccIO T36 VccIO T37 VccIO R37 VccIO R38 VccIO P38 VccIO P39 VccIO R40 VccIO P24 VccIO U19 VccIO AA26 VccIO V15 VccIO Y26 VccIO AT28 VccIO N22 VccIO N24 VccIO N26 VccIO P15 VccIO P16 VccIO N16 VccIO M16 PCH Desktop Ball Name Ball # VccIO N18 VccIO M18 VccIO N20 VccIO M20 VccIO M22 VccIO M24 VccIO D24 VccIO C24 VccIO B24 VccIO D25 VccIO C25 VccIO B25 VccIO M26 VccIO L26 VccIO K26 VccIO J26 VccIO H26 VccIO G26 VccIO F26 VccIO P18 VccIO T19 VccIO P19 VccLAN Y20 VccLAN Y22 VccME AH1 VccME AJ2 VccME AH3 VccME AJ4 VccME AH4 VccME AJ5 VccME AG5 VccME AH6 VccME AF8 VccME AF10 VccME AH13 VccME AF13 VccME AD13 VccME AE15 VccME AD15 VccME AB16 VccME AD16 VccME AF16 VccME AE16 VccME AB15 PCH Desktop Ball Name Ball #
VccME3_3 N38 VccME3_3 N40 VccPNAND P30 VccPNAND M39 VccPNAND M41 VccRTC AY29 VccRTC_NCTF BA39 VccSATAPLL P41 VccSus3_3 AV25 VccSus3_3 BA26 VccSus3_3 AW26 VccSus3_3 AU26 VccSus3_3 AT26 VccSus3_3 AR26 VccSus3_3 AP26 VccSus3_3 AN26 VccSus3_3 AM26 VccSus3_3 AL26 VccSus3_3 AK26 VccSus3_3 AY27 VccSus3_3 AV27 VccSus3_3 AU27 VccSus3_3 AW39 VccSus3_3 AW40 VccSus3_3 AV29 VccSus3_3_NCTF BA40 VccSus3_3_NCTF AY40 VccSusHDA AJ18 VccVRM C2 VccVRM L39 VccVRM L40 VccVRM C3 Vss AV28 Vss U39 Vss B10 Vss AF3 Vss AH29 PCH Desktop Ball Name Ball # Vss AR1 Vss P1 Vss G1 Vss AD2 Vss U2 Vss K2 Vss AW3 Vss AK3 Vss AE3 Vss W3 Vss V3 Vss U3 Vss T3 Vss L3 Vss K3 Vss AE4 Vss AA4 Vss R4 Vss P4 Vss E4 Vss AV5 Vss AU5 Vss AN5 Vss AK5 Vss AF5 Vss AC5 Vss AB5 Vss Y5 Vss W5 Vss T5 Vss R5 Vss N5 Vss M5 Vss J5 Vss H5 Vss F5 Vss E5 Vss AD6 Vss V6 Vss J6 Vss E6 Vss BA7 Vss J7 Vss H7 PCH Desktop Ball Name Ball # Vss A7 Vss AL8 Vss AK8 Vss AD8 Vss AB8 Vss T8 Vss P8 Vss M8 Vss L8 Vss E8 Vss AU9 Vss AK9 Vss AH9 Vss V9 Vss H9 Vss E9 Vss AM10 Vss AK10 Vss Y10 Vss C10 Vss AR11 Vss AF11 Vss AD11 Vss T11 Vss P11 Vss M11 Vss L11 Vss F11 Vss C11 Vss AU12 Vss AN12 Vss AM12 Vss AF12 Vss V12 Vss M12 Vss L12 Vss F12 Vss E12 Vss Y13 Vss V13 Vss E13 Vss BA14 Vss AT14 Vss AN14 PCH Desktop Ball Name Ball #
292 Datasheet
Ball Name Ball # Vss P20 Vss L20 Vss K20 Vss F20 Vss BA21 Vss AU22 Vss AT22 Vss AN22 Vss AK22 Vss AD22 Vss AB22 Vss AA22 Vss V22 Vss L22 Vss K22 Vss E22 Vss D22 Vss AU23 Vss AB23 Vss E23 Vss AW24 Vss AV24 Vss AP24 Vss AJ24 Vss AH24 Vss AD24 Vss U24 Vss J24 Vss F24 Vss AJ26 Vss AH26 Vss AF26 Vss AH27 Vss AB27 Vss Y27 Vss V27 Vss U27 Vss BA28 Vss AW28 Vss AR28 Vss AN28 Vss AM28 Vss AJ28 Vss AU29 PCH Desktop Ball Name Ball # Vss AF29 Vss AD29 Vss AB29 Vss AU30 Vss AR30 Vss AN30 Vss AD30 Vss AB30 Vss Y30 Vss L30 Vss F30 Vss E30 Vss A30 Vss AF31 Vss AD31 Vss P31 Vss L31 Vss H31 Vss C31 Vss AM32 Vss AK32 Vss AH32 Vss AF32 Vss L32 Vss K32 Vss C32 Vss AU33 Vss AF33 Vss AB33 Vss Y33 Vss V33 Vss M33 Vss E33 Vss AK34 Vss AH34 Vss AD34 Vss AB34 Vss P34 Vss L34 Vss G34 Vss F34 Vss D34 Vss V35 Vss T35 PCH Desktop Ball Name Ball #
Vss_NCTF BA1 Vss_NCTF E1 Vss_NCTF C1 PCH Desktop Ball Name Ball # Vss_NCTF BA2 Vss_NCTF AY2 Vss_NCTF B2 Vss_NCTF A5 Vss_NCTF B40 Vss_NCTF A40 Vss_NCTF AY41 Vss_NCTF AW41 Vss_NCTF C41 Vss_NCTF B41 WAKE# AR33 XCLK_RCOMP AA3 XTAL25_IN Y4 XTAL25_OUT Y2 PCH Desktop Ball Name Ball #
294 Datasheet
6.2 PCH Ballout Mobile Ballout
This section contains the PCH ballout. Figure 6-3 and Figure 6-4 show the ballout from a top of the package quadrant view. Table 6-2 is the BGA ball list, sorted alphabetically by signal name.
Figure 6-3. PCH ballout (top View—Leff side) (Mobile Only) 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 BJ Vss_NC TF Vss_NC TF Vss_NC TF Vss_NC TF SDVO_ STALLN SDVO_T VCLKIN N DDPB_ AUXP DDPB_1 N DDPD_0 N DDPD_1 N PETp8 PERp8 PETp5 PERp1 VccIO BJ BH Vss_NC TF Vss_NC TF Vss SDVO_IN TP Vss DDPC_1 P Vss DDPD_ 2P Vss PERp5 Vss PETp1 VccIO BH BG Vss SDVO_ STALLP SDVO_T VCLKIN P DDPB_ AUXN DDPB_1 P DDPD_0 P DDPD_1 P PETn8 PERn8 PETn5 PERn1 VccIO BG BF Vss_NC TF Vss Vss SDVO_IN TN DDPC_1 N DDPD_ 2N PERn5 PETn1 BF BE Vss_NC TF Vss Vss Vss DDPC_ AUXN Vss DDPC_0 N Vss DDPD_3 N Vss PETp4 Vss VccIO BE BD VccADP LLB VccADP LLB Vss Vss DDPD_ AUXP DDPC_ AUXP DDPB_0 N DDPC_0 P DDPC_2 N DDPD_3 P PETp6 PETn4 PETp2 VccIO BD BC Vss DDPD_ AUXN Vss DDPB_0 P Vss DDPC_2 P Vss PETn6 Vss PETn2 VccIO BC BB VccADP LLA VccADP LLA Vss LVDSA_ DATA0 LVDSA_ DATA#0 Vss Vss DDPB_2 N Vss DDPC_3 N Vss PERp4 Vss VccIO BB BA LVDSA_ DATA#1 LVDSA_ DATA1 Vss DDPB_2 P DDPB_3 P DDPC_3 P PERn6 PERn4 PERp2 VccIO BA AY LVDSB_ DATA#0 LVDSB_ DATA0 LVDSA_ DATA2 LVDSA_ DATA#2 Vss TP5 TP4 Vss AY AW Vss Vss DDPB_3 N Vss PERp6 Vss PERn2 VccIO AW AV LVDSA_ CLK# LVDSA_ CLK Vss LVDSA_ DATA3 LVDSA_ DATA#3 Vss TP7 TP6 Vss DDPC_ HPD Vss PETp7 Vss PETp3 Vss VccIO AV AU LVDSB_ DATA#2 LVDSB_ DATA2 DDPB_ HPD PETn7 PERp7 PETn3 PERn3 VccIO AU AT LVDSB_ DATA#3 LVDSB_ DATA3 LVDSB_ DATA#1 LVDSB_ DATA1 Vss VccTX_ LVDS VccTX_L VDS LVD_VR EFH LVD_VR EFL Vss DDPD_ HPD Vss PERn7 Vss PERp3 VccIO AT AR Vss AR AP VccAClk VccAClk Vss LVDSB_ CLK# LVDSB_ CLK Vss VccTX_L VDS VccTX_L VDS Vss LVD_VB G LVD_IB G AP AN Vss Vss Vcc3_3 Vss Vss VccIO VccIO VccIO AN AM CLKOU T_PCIE CLKOU T_PCIE Vss CLKOU T_PCIE CLKOU T_PCIE Vss CLKOUT _PCIE1P CLKOUT _PCIE1N Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss AM AL Vss AL AK CLKOU T_PEG_ B_N CLKOU T_PEG_ B_P Vss CLKOU T_PCIE CLKOU T_PCIE Vss Vss Vss TP13 TP12 Vss Vss Vss Vss Vss Vss Vss Vss AK AJ CLKOU T_PCIE CLKOU T_PCIE VccIO Vss Vss VccCore VccCore Vss AJ AH XTAL25 _OUT XTAL25 _IN Vss Vss Vss CLKOU T_PCIE CLKOUT _PCIE6N Vss CLKOU T_PCIE CLKOU T_PCIE VssA_L VDS VccALV DS VccIO VccIO Vss VccCore VccCore VccCor e AH AG Vss AG AF VssA_D AC VssA_D AC Vss CLKOU T_PCIE CLKOU T_PCIE Vss Vss VccME VccME VccME Vss XCLK_R COMP Vss VccIO VccIO VccCore VccCore VccCor e AF AE VccADA C VccADA C AE AD CRT_RE D Vss Vss DAC_IR EF Vss Vss CLKOUT _PEG_A_ P CLKOUT _PEG_A_ N Vss VccME VccME VccME Vcc3_3 Vss Vss Vss Vss VccCor e AD AC Vss AC AB CRT_G REEN CRT_IR TN DDPC_ CTRLDA TA L_DDC_ CLK Vss L_CTRL _CLK NC_1 Vss NC_3 NC_4 Vss NC_2 Vcc3_3 Vcc3_3 Vss Vss Vss VccCor e AB AA CRT_BL UE Vss VccME VccME Vss Vss Vss Vss AA Y CRT_HS YNC CRT_VS YNC DDPC_ CTRLCL K L_BKLT CTL Vss Vss L_DDC_ DATA Vss VccME VccME VccME Vss VccME VccME Vss Vss Vss Vss Y W Vss W V CRT_D DC_DAT A CRT_D DC_CLK Vss L_CTRL _DATA Vss Vss Vss Vss VccME VccME VccME Vss Vss Vss Vss Vss Vss VccSus 3_3 V U DDPD_ CTRLDA TA DDPD_ CTRLCL K Vcc3_3 Vss Vss Vss Vss VccSus 3_3 U T SDVO_ CTRLDA TA SDVO_ CTRLCL K Vss L_BKLT EN L_VDD_ EN Vss CLKOUT FLEX0 / GPIO64 Vss CLKOU TFLEX2 GPIO66 Vss NC_5 T R Vss R P CLKOU T_PCI1 CLKOU T_PCI3 Vss CLKOU T_PCI4 Vss CLKOU T_PCI2 Vss CLKOUT FLEX1 / GPIO65 Vss REFCLK 14IN Vss Vcc3_3 Vss Vss Vss VccSus 3_3 P N CLKOU T_PCI0 CLKOU TFLEX3 GPIO67 Vss Vcc3_3 AD1 TP15 TP17 VccSus 3_3 N M REQ3# / GPIO54 AD22 Vss AD12 AD30 Vss AD13 AD16 Vss AD15 Vss Vcc3_3 Vss TP14 TP16 VccSus 3_3 M L Vss Vss Vcc3_3 Vss AD25 Vss VccSusHD A VccSus 3_3 L K PIRQF# / GPIO3 AD24 V5REF AD18 Vss AD21 GNT1# / GPIO51 Vss K J AD23 C/BE0# CLKIN_ PCILOO PBACK AD27 Vcc3_3 AD17 AD5 GPIO7 HDA_DOC K_RST# / GPIO13 VccSus 3_3 J H GNT3# / GPIO55 PIRQB# Vss AD9 C/BE2# PAR Vss AD0 Vss AD31 Vss HDA_DOC K_EN# / GPIO33 Vss VccSus 3_3 H G Vss AD28 Vss C/BE1# Vss PIRQA# Vss C/BE3# Vss HDA_SDI VccSus 3_3 G F AD14 REQ0# Vss GNT0# DEVSEL # AD29 AD26 AD19 GPIO17 GNT2# / GPIO53 LDRQ1# GPIO23 HDA_SDI HDA_SDI VccSus 3_3 F E Vss_NC TF PERR# Vss Vss SERR# Vss AD10 Vss AD8 Vss HDA_SDI N2 Vss VccSus 3_3 E D Vss_NC TF Vss PLOCK# AD7 STOP# GPIO6 FWH0 / LAD0 HDA_S YNC D C Vss TRDY# FRAME # AD2 AD20 AD11 GPIO1 AD4 FWH4 / LFRAM FWH2 / LAD2 HDA_RST VccSus 3_3 C B Vss_NC TF Vss_NC TF Vss REQ2# / GPIO52 Vss PIRQE# / GPIO2 Vss PIRQC # Vss FWH1 / LAD1 Vss HDA_S DO VccSu s3_3 B A Vss_NC TF Vss_NC TF Vss_NC TF Vss_NC TF PIRQH# / GPIO5 REQ1# / GPIO50 PIRQD # IRDY# AD6 AD3 PIRQG# / GPIO4 LDRQ0# FWH3 / LAD3 HDA_BCL K VccSus 3_3 A 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
296 Datasheet
Figure 6-4. PCH ballout (top View—right side) (Mobile Only) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BJ VccIO VccAPL LEXP DMI1RX N DMI3RX N VccFDIPL L FDI_RXN
3 FDI_INT FDI_LSY
H Reserved Reserved Vss_NCT F Vss_NCTF Vss_NCT F Vss_NCTF BJ BH DMI_ZC OMP Vss DMI1TXP Vss FDI_RXN
1 Vss FDI_FSYN
C1 Vss Vss Vss Vss_NCT F Vss_NCTF BH BG VccIO Vss DMI1RX P DMI3RX P Vss FDI_RXP FDI_LSY NC1 Vss PECI Reserved Reserved Vss BG BF DMI_IR COMP DMI1TXN FDI_RXP FDI_FSYN C0 Vss Reserved Vss Vss_NCTF BF BE VccIO Vss DMI0TX N Vss DMI3TXN Vss FDI_RXN
5 Vss PROCPW
RGD Vss Vss Reserved Vss_NCTF BE BD VccIO DMI0R XP DMI0TX P DMI2TX N DMI3TXP FDI_RXN FDI_RXP FDI_RXP THRMTRI P# Reserved Reserved Vss NV_ALE Reserved BD BC VccIO DMI0R XN Vss DMI2TX P Vss FDI_RXP
2 Vss FDI_RXN
7 Vss Reserved Vss BC
BB VccIO Vss TP3 Vss FDI_RXP
0 Vss FDI_RXP
6 Vss Vss Reserved Reserved Vss Reserved Reserved BB
BA VccIO CLKIN_ DMI_P TP1 DMI2RX P FDI_RXN FDI_RXN FDI_RXN
6 Vss Reserved SPI_CLK BA
AY Vss Reserved Reserved Vss NV_CLE Reserved SPI_CS1# SPI_MOSI AY AW VccIO CLKIN_ DMI_N TP2 DMI2RX N Vss FDI_RXP
4 Vss Vss AW
AV VccIO Vss Vss Vss Vss Vss Vss Vss Reserved Reserved Vss Reserved Reserved Vss SPI_CS0# SPI_MISO AV AU VccIO VccVR M Vss Vss V_CPU_I O VccDMI Vss Reserved AU AT VccIO VccVR M VccVRM VccVRM V_CPU_I O VccDMI Vss Vss Vss Reserved Vss Vss Reserved Vss CLKOUT_D P_P / CLKOUT_B CLK1_P CLKOUT_D P_N / CLKOUT_B CLK1_N AT AR Vss AR AP Reserved Vss Vss VccME3_ VccME3_
3 Vss Reserved Reserved Vss CLKIN_BCL
K_N CLKIN_BC LK_P AP AN VccIO VccIO VccIO VccIO VccIO Vss CLKOUT_ DMI_N CLKOUT _DMI_P AN AM Vss Vss VccIO Vss Vss Vss VccPNAN D VccPNAN D VccPNAN D VccPNAN D Vss VccME3_
3 VccME3_3 Vss Vss Vss
CLKOUT_B CLK0_N / CLKOUT_P CIE8N CLKOUT_B CLK0_P / CLKOUT_P CIE8P AM AL Vss AL AK Vss VccIO Vss Vss VccPNA ND VccPNA ND VccPNAN D VccPNAN D VccPNAN D Vss SATA0TX N SATA0TX P Vss SATA0RXN SATA0RX P Vss VccSATAPL L VccSATAPL L AK AJ Vss TP11 Vss Vss Vss Vss Vss Vss AJ AH VccCor e Vss VccIO VccIO VccIO VccIO Vss Vss CLKIN_SA TA_N / CKSSCD_ N CLKIN_S ATA_P / CKSSCD Vss SATA1TX N SATA1TXP Vss SATA1RX N SATA1RX P SATA3RXN SATA3RXP AH AG Vss AG AF VccCor e VccLAN VccLAN VccIO VccIO VccIO SATAICO MPO SATAICO MPI TP8 Vss SATA2RX N SATA2RX P Vss SATA2TXN SATA2TX P Vss SATA3TXN SATA3TXP AF AE Vss Vss AE AD VccCor e Vss Vss VccIO VccIO VccIO Vss Vss Vcc3_3 Vss Vss SATA4RX N SATA4RXP Vss SATA4TX N SATA4TX P SATA5RXN SATA5RXP AD AC Vss AC AB VccCor e VccCor e Vss VccIO VccIO VccIO Vss Vss SATA3GP / GPIO37 GPIO27 Vss SERIRQ Vss SATA2GP / GPIO36 SDATAOU T1 / GPIO48 Vss SATA5TXN SATA5TXP AB AA Vss Vss TP19 Vss Vss Vss SATA5GP / GPIO49 / TEMP_AL ERT# SATA4GP / GPIO16 AA Y VccIO VccIO Vss DcpSus DcpSus Byp Vss Vcc3_3 Vss Vss Vss Vss SATA0GP / GPIO21 Vss SCLOCK / GPIO22 Vss Vss BMBUSY# / GPIO0 CLKRUN# / GPIO32 Y W Vss W V VccIO VccIO VccIO Vss Vss Vss Vcc3_3 Vcc3_3 GPIO28 DcpSST Vss DcpRTC Vss Vss GPIO35 Vss SLOAD / GPIO38 SATA1GP / GPIO19 V U VccSus 3_3 VccSus 3_3 VccSus3 VccSus3 VccSus 3_3 VccSus3 PCIECLKR Q1# / GPIO18 A20GATE U T OC7# / GPIO14 CL_CLK1 Vss CL_DATA CL_RST1 # Vss GPIO15 SYS_RES ET# Vss SATALED# RCIN# T R Vss R P VccSus 3_3 Vss Vss USBP2 P VccSus3_
3 Vss
PEG_B_C LKRQ# / GPIO56 SLP_S3# Vss PCIECLK RQ0# / GPIO73 SUS_STAT # / GPIO61 ACPRESE NT / GPIO31 INIT3_3V# PWRBTN SDATAOUT 0 / GPIO39 SPKR P N VccSus 3_3 Vss USBP6P USBP2 N TP10 OC0# / GPIO59 PCIECLKR Q2# / GPIO20 TP23 N M VccSus 3_3 USBP1 2P USBP6N Vss TP9 Vss SML1ALE RT# / GPIO74 Vss STP_PCI # / GPIO34 PCIECLK RQ4# / GPIO26 Vss PME# SYS_PWR OK Vss JTAG_TCK SUS_PWR _DN_ACK / GPIO30 M L VccSus 3_3 USBP1 2N Vss USBP3 P Vss OC3# / GPIO42 Vss Vss L K Vss LAN_PH Y_PWR_ CTRL / GPIO12 SLP_M# Vss PCIRST# MEPWR OK JTAG_TMS JTAG_TDI K J VccSus 3_3 Vss USBP8P USBP3 N USBP0P OC1# / GPIO40 SML0ALE RT# / GPIO60 WAKE# TRST# JTAG_TD O J H VccSus 3_3 USBP1 1P USBP8N Vss USBP0N Vss SMBCLK TP18 GPIO24 SLP_S4# PCIECLK RQ5# / GPIO44 Vss PCIECLKR Q6# / GPIO45 PEG_A_CL KRQ# / GPIO47 H G VccSus 3_3 USBP1 1N Vss USBP4 P Vss OC5# / GPIO9 Vss SML1DA TA / GPIO75 Vss SML0DAT A Vss G F VccSus 3_3 V5REF _Sus USBP9P USBP4 N CLKIN_D OT_96N OC2# / GPIO41 RI# OC6# / GPIO10 GPIO8 GPIO57 SLP_LAN #/GPIO29 Vss SUSCLK / GPIO62 PCIECLKR Q7# / GPIO46 F E VccSus 3_3 Vss USBP9N Vss CLKIN_D OT_96P Vss OC4# / GPIO43 Vss SML1CL K / GPIO58 Vss Vss SLP_S5# / GPIO63 Vss_NCTF E D USBRBI AS USBP7P SRTCRS T# RTCX2 DRAMP WROK PLTRST# Vss_NCT F Vss_NCTF D C VccSus 3_3 USBP1 USBP10 P USBP5 P USBP1P RSMRST RTCRST # Vss TP24 SMBDATA SML0CLK C B USBRBI AS# Vss USBP7N Vss PWROK Vss RTCX1 Vss SMBALE RT# / GPIO11 Vss Vss_NCTF Vss_NCT F B A VccSus 3_3 USBP1 USBP10 N USBP5 N USBP1N INTRUDE INTVRME N VccRTC LAN_RST PCIECLKR Q3# / GPIO25 BATLOW# / GPIO72 Vss_NCT F Vss_NCTF A 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Table 6-2. PCH Ballout by Signal name (Mobile Only) PCH Mobile Ball Name Ball # A20GATE U2 ACPRESENT / GPIO31 P7 AD0 H40 AD1 N34 AD2 C44 AD3 A38 AD4 C36 AD5 J34 AD6 A40 AD7 D45 AD8 E36 AD9 H48 AD10 E40 AD11 C40 AD12 M48 AD13 M45 AD14 F53 AD15 M40 AD16 M43 AD17 J36 AD18 K48 AD19 F40 AD20 C42 AD21 K46 AD22 M51 AD23 J52 AD24 K51 AD25 L34 AD26 F42 AD27 J40 AD28 G46 AD29 F44 AD30 M47 AD31 H36 BATLOW# / GPIO72 A6 C/BE0# J50 C/BE1# G42 C/BE2# H47 C/BE3# G34 CL_CLK1 T13 CL_DATA1 T11 CL_RST1# T9 CLKIN_BCLK_N AP3 CLKIN_BCLK_P AP1 CLKIN_DMI_N AW24 CLKIN_DMI_P BA24 CLKIN_DOT_96N F18 CLKIN_DOT_96P E18 CLKIN_PCILOOPBA CK J42 CLKIN_SATA_N / CKSSCD_N AH13 CLKIN_SATA_P / CKSSCD_P AH12 CLKOUT_BCLK0_N / CLKOUT_PCIE8N AM3 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLKOUT_DMI_N AN4 CLKOUT_DMI_P AN2 CLKOUT_DP_N / CLKOUT_BCLK1_N AT1 CLKOUT_DP_P / CLKOUT_BCLK1_P AT3 CLKOUT_PCI0 N52 CLKOUT_PCI1 P53 CLKOUT_PCI2 P46 CLKOUT_PCI3 P51 CLKOUT_PCI4 P48 CLKOUT_PCIE0N AK48 CLKOUT_PCIE0P AK47 CLKOUT_PCIE1N AM43 CLKOUT_PCIE1P AM45 CLKOUT_PCIE2N AM47 CLKOUT_PCIE2P AM48 CLKOUT_PCIE3N AH42 CLKOUT_PCIE3P AH41 CLKOUT_PCIE4N AM51 CLKOUT_PCIE4P AM53 CLKOUT_PCIE5N AJ50 CLKOUT_PCIE5P AJ52 CLKOUT_PCIE6N AH45 CLKOUT_PCIE6P AH46 CLKOUT_PCIE7N AF48 CLKOUT_PCIE7P AF47 CLKOUT_PEG_A_N AD43 CLKOUT_PEG_A_P AD45 PCH Mobile Ball Name Ball # CLKOUT_PEG_B_N AK53 CLKOUT_PEG_B_P AK51 CLKOUTFLEX0 / GPIO64 T45 CLKOUTFLEX1 / GPIO65 P43 CLKOUTFLEX2 / GPIO66 T42 CLKOUTFLEX3 / GPIO67 N50 CLKRUN# / GPIO32 Y1 CRT_BLUE AA52 CRT_DDC_CLK V51 CRT_DDC_DATA V53 CRT_GREEN AB53 CRT_HSYNC Y53 CRT_IRTN AB51 CRT_RED AD53 CRT_VSYNC Y51 DAC_IREF AD48 DcpRTC V9 DcpSST V12 DcpSus Y22 DcpSusByp Y20 DDPB_0N BD42 DDPB_0P BC42 DDPB_1N BJ42 DDPB_1P BG42 DDPB_2N BB40 DDPB_2P BA40 DDPB_3N AW38 DDPB_3P BA38 DDPB_AUXN BG44 DDPB_AUXP BJ44 DDPB_HPD AU38 DDPC_0N BE40 DDPC_0P BD40 DDPC_1N BF41 DDPC_1P BH41 DDPC_2N BD38 DDPC_2P BC38 DDPC_3N BB36 DDPC_3P BA36 DDPC_AUXN BE44 PCH Mobile Ball Name Ball #
298 Datasheet
DDPC_AUXP BD44 DDPC_CTRLCLK Y49 DDPC_CTRLDATA AB49 DDPC_HPD AV40 DDPD_0N BJ40 DDPD_0P BG40 DDPD_1N BJ38 DDPD_1P BG38 DDPD_2N BF37 DDPD_2P BH37 DDPD_3N BE36 DDPD_3P BD36 DDPD_AUXN BC46 DDPD_AUXP BD46 DDPD_CTRLCLK U50 DDPD_CTRLDATA U52 DDPD_HPD AT38 DEVSEL# F46 DMI_IRCOMP BF25 DMI_ZCOMP BH25 DMI0RXN BC24 DMI0RXP BD24 DMI0TXN BE22 DMI0TXP BD22 DMI1RXN BJ22 DMI1RXP BG22 DMI1TXN BF21 DMI1TXP BH21 DMI2RXN AW20 DMI2RXP BA20 DMI2TXN BD20 DMI2TXP BC20 DMI3RXN BJ20 DMI3RXP BG20 DMI3TXN BE18 DMI3TXP BD18 DRAMPWROK D9 FDI_FSYNC0 BF13 FDI_FSYNC1 BH13 FDI_INT BJ14 FDI_LSYNC0 BJ12 FDI_LSYNC1 BG14 FDI_RXN0 BA18 FDI_RXN1 BH17 PCH Mobile Ball Name Ball # FDI_RXN2 BD16 FDI_RXN3 BJ16 FDI_RXN4 BA16 FDI_RXN5 BE14 FDI_RXN6 BA14 FDI_RXN7 BC12 FDI_RXP0 BB18 FDI_RXP1 BF17 FDI_RXP2 BC16 FDI_RXP3 BG16 FDI_RXP4 AW16 FDI_RXP5 BD14 FDI_RXP6 BB14 FDI_RXP7 BD12 FRAME# C46 FWH0 / LAD0 D33 FWH1 / LAD1 B33 FWH2 / LAD2 C32 FWH3 / LAD3 A32 FWH4 / LFRAME# C34 GNT0# F48 GNT1# / GPIO51 K45 GNT2# / GPIO53 F36 GNT3# / GPIO55 H53 GPIO0 Y3 GPIO1 C38 GPIO6 D37 GPIO7 J32 GPIO8 F10 GPIO15 T7 GPIO17 F38 GPIO24 H10 GPIO27 AB12 GPIO28 V13 GPIO35 V6 GPIO57 F8 HDA_BCLK A30 HDA_DOCK_EN# / GPIO33 H32 HDA_DOCK_RST# / GPIO13 J30 HDA_RST# C30 HDA_SDIN0 G30 HDA_SDIN1 F30 HDA_SDIN2 E32 PCH Mobile Ball Name Ball # HDA_SDIN3 F32 HDA_SDO B29 HDA_SYNC D29 INIT3_3V# P6 INTRUDER# A16 INTVRMEN A14 IRDY# A42 JTAG_TCK M3 JTAG_TDI K1 JTAG_TDO J2 JTAG_TMS K3 L_BKLTCTL Y48 L_BKLTEN T48 L_CTRL_CLK AB46 L_CTRL_DATA V48 L_DDC_CLK AB48 L_DDC_DATA Y45 L_VDD_EN T47 LAN_PHY_PWR_CT RL / GPIO12 K9 LAN_RST# A10 LDRQ0# A34 LDRQ1# / GPIO23 F34 LVD_IBG AP39 LVD_VBG AP41 LVD_VREFH AT43 LVD_VREFL AT42 LVDSA_CLK# AV53 LVDSA_CLK AV51 LVDSA_DATA#0 BB47 LVDSA_DATA#1 BA52 LVDSA_DATA#2 AY48 LVDSA_DATA#3 AV47 LVDSA_DATA0 BB48 LVDSA_DATA1 BA50 LVDSA_DATA2 AY49 LVDSA_DATA3 AV48 LVDSB_CLK# AP48 LVDSB_CLK AP47 LVDSB_DATA#0 AY53 LVDSB_DATA#1 AT49 LVDSB_DATA#2 AU52 LVDSB_DATA#3 AT53 LVDSB_DATA0 AY51 PCH Mobile Ball Name Ball #
LVDSB_DATA1 AT48 LVDSB_DATA2 AU50 LVDSB_DATA3 AT51 MEPWROK K5 NC_1 AB45 NC_2 AB38 NC_3 AB42 NC_4 AB41 NC_5 T39 NV_ALE BD3 NV_CLE AY6 OC0# / GPIO59 N16 OC1# / GPIO40 J16 OC2# / GPIO41 F16 OC3# / GPIO42 L16 OC4# / GPIO43 E14 OC5# / GPIO9 G16 OC6# / GPIO10 F12 OC7# / GPIO14 T15 PAR H44 PCIECLKRQ0# / GPIO73 P9 PCIECLKRQ1# / GPIO18 U4 PCIECLKRQ2# / GPIO20 N4 PCIECLKRQ3# / GPIO25 A8 PCIECLKRQ4# / GPIO26 M9 PCIECLKRQ5# / GPIO44 H6 PCIECLKRQ6# / GPIO45 H3 PCIECLKRQ7# / GPIO46 F1 PCIRST# K6 PECI BG10 PEG_A_CLKRQ# / GPIO47 H1 PEG_B_CLKRQ# / GPIO56 P13 PERn1 BG30 PERn2 AW30 PERn3 AU30 PERn4 BA32 PCH Mobile Ball Name Ball # PERn5 BF33 PERn6 BA34 PERn7 AT34 PERn8 BG34 PERp1 BJ30 PERp2 BA30 PERp3 AT30 PERp4 BB32 PERp5 BH33 PERp6 AW34 PERp7 AU34 PERp8 BJ34 PERR# E50 PETn1 BF29 PETn2 BC30 PETn3 AU32 PETn4 BD32 PETn5 BG32 PETn6 BC34 PETn7 AU36 PETn8 BG36 PETp1 BH29 PETp2 BD30 PETp3 AV32 PETp4 BE32 PETp5 BJ32 PETp6 BD34 PETp7 AV36 PETp8 BJ36 PIRQA# G38 PIRQB# H51 PIRQC# B37 PIRQD# A44 PIRQE# / GPIO2 B41 PIRQF# / GPIO3 K53 PIRQG# / GPIO4 A36 PIRQH# / GPIO5 A48 PLOCK# D49 PLTRST# D5 PME# M7 PMSYNCH BJ10 PROCPWRGD BE10 PWRBTN# P5 PWROK B17 PCH Mobile Ball Name Ball # RCIN# T1 REFCLK14IN P41 REQ0# F51 REQ1# / GPIO50 A46 REQ2# / GPIO52 B45 REQ3# / GPIO54 M53 Reserved AY9 Reserved BD1 Reserved AP15 Reserved BD8 Reserved AV9 Reserved BG8 Reserved AP7 Reserved AP6 Reserved BD6 Reserved BB7 Reserved BC8 Reserved BJ8 Reserved BJ6 Reserved BG6 Reserved AT6 Reserved AT9 Reserved BB1 Reserved AV6 Reserved BB3 Reserved BA4 Reserved BE4 Reserved BB6 Reserved AV7 Reserved AU2 Reserved AY8 Reserved AY5 Reserved AV11 Reserved BF5 RI# F14 RSMRST# C16 RTCRST# C14 RTCX1 B13 RTCX2 D13 SATA0GP / GPIO21 Y9 SATA0RXN AK7 SATA0RXP AK6 SATA0TXN AK11 SATA0TXP AK9 PCH Mobile Ball Name Ball #
300 Datasheet
TEMP_ALERT# AA4 SATA5RXN AD3 SATA5RXP AD1 SATA5TXN AB3 SATA5TXP AB1 SATAICOMPI AF15 SATAICOMPO AF16 SATALED# T3 SCLOCK / GPIO22 Y7 SDATAOUT0 / GPIO39 P3 SDATAOUT1 / GPIO48 AB6 SDVO_CTRLCLK T51 SDVO_CTRLDATA T53 SDVO_INTN BF45 SDVO_INTP BH45 SDVO_STALLN BJ48 SDVO_STALLP BG48 SDVO_TVCLKINN BJ46 SDVO_TVCLKINP BG46 SERIRQ AB9 SERR# E44 SLOAD / GPIO38 V3 PCH Mobile Ball Name Ball # SLP_LAN# / GPIO29 F6 SLP_M# K8 SLP_S3# P12 SLP_S4# H7 SLP_S5# / GPIO63 E4 SMBALERT# / GPIO11 B9 SMBCLK H14 SMBDATA C8 SML0ALERT# / GPIO60 J14 SML0CLK C6 SML0DATA G8 SML1ALERT# / GPIO74 M14 SML1CLK / GPIO58 E10 SML1DATA / GPIO75 G12 SPI_CLK BA2 SPI_CS0# AV3 SPI_CS1# AY3 SPI_MISO AV1 SPI_MOSI AY1 SPKR P1 SRTCRST# D17 STOP# D41 STP_PCI# / GPIO34 M11 SUS_PWR_DN_ACK / GPIO30 M1 SUS_STAT# / GPIO61 P8 SUSCLK / GPIO62 F3 SYS_PWROK M6 SYS_RESET# T6 THRMTRIP# BD10 TP1 BA22 TP2 AW22 TP3 BB22 TP4 AY45 TP5 AY46 TP6 AV43 TP7 AV45 TP8 AF13 TP9 M18 TP10 N18 PCH Mobile Ball Name Ball # TP11 AJ24 TP12 AK41 TP13 AK42 TP14 M32 TP15 N32 TP16 M30 TP17 N30 TP18 H12 TP19 AA23 TP23 N2 TP24 C10 TRDY# C48 TRST# J4 USBP0N H18 USBP0P J18 USBP1N A18 USBP1P C18 USBP2N N20 USBP2P P20 USBP3N J20 USBP3P L20 USBP4N F20 USBP4P G20 USBP5N A20 USBP5P C20 USBP6N M22 USBP6P N22 USBP7N B21 USBP7P D21 USBP8N H22 USBP8P J22 USBP9N E22 USBP9P F22 USBP10N A22 USBP10P C22 USBP11N G24 USBP11P H24 USBP12N L24 USBP12P M24 USBP13N A24 USBP13P C24 USBRBIAS D25 USBRBIAS# B25 V_CPU_IO AT18 PCH Mobile Ball Name Ball #
301 Datasheet
V_CPU_IO AU18 V5REF K49 V5REF_Sus F24 Vcc3_3 AB34 Vcc3_3 AB35 Vcc3_3 AD35 Vcc3_3 AN35 Vcc3_3 AD13 Vcc3_3 V15 Vcc3_3 V16 Vcc3_3 Y16 Vcc3_3 J38 Vcc3_3 L38 Vcc3_3 M36 Vcc3_3 N36 Vcc3_3 P36 Vcc3_3 U35 VccAClk AP51 VccAClk AP53 VccADAC AE50 VccADAC AE52 VccADPLLA BB51 VccADPLLA BB53 VccADPLLB BD51 VccADPLLB BD53 VccALVDS AH38 VccAPLLEXP BJ24 VccCore AB24 VccCore AB26 VccCore AB28 VccCore AD26 VccCore AD28 VccCore AF26 VccCore AF28 VccCore AF30 VccCore AF31 VccCore AH26 VccCore AH28 VccCore AH30 VccCore AH31 VccCore AJ30 VccCore AJ31 VccDMI AT16 VccDMI AU16 PCH Mobile Ball Name Ball # VccFDIPLL BJ18 VccIO AN30 VccIO AN31 VccIO AN23 VccIO AN24 VccIO AN26 VccIO AN28 VccIO AT26 VccIO AT28 VccIO AU26 VccIO AU28 VccIO AV26 VccIO AV28 VccIO AW26 VccIO AW28 VccIO BA26 VccIO BA28 VccIO BB26 VccIO BB28 VccIO BC26 VccIO BC28 VccIO BD26 VccIO BD28 VccIO BE26 VccIO BE28 VccIO BG26 VccIO BG28 VccIO BH27 VccIO BJ26 VccIO BJ28 VccIO AN20 VccIO AN22 VccIO V23 VccIO AH23 VccIO AH35 VccIO AJ35 VccIO AH22 VccIO AK24 VccIO AM23 VccIO AB19 VccIO AB20 VccIO AB22 VccIO AD19 VccIO AD20 PCH Mobile Ball Name Ball # VccIO AD22 VccIO AF19 VccIO AF20 VccIO AF22 VccIO AH20 VccIO AH19 VccIO AF32 VccIO AF34 VccIO AH34 VccIO V24 VccIO V26 VccIO Y24 VccIO Y26 VccLAN AF23 VccLAN AF24 VccME AD38 VccME AD39 VccME AD41 VccME AF41 VccME AF42 VccME AF43 VccME AA34 VccME Y34 VccME Y35 VccME AA35 VccME V39 VccME V41 VccME V42 VccME Y39 VccME Y41 VccME Y42 VccME3_3 AM8 VccME3_3 AM9 VccME3_3 AP11 VccME3_3 AP9 VccPNAND AK13 VccPNAND AK15 VccPNAND AK16 VccPNAND AK19 VccPNAND AK20 VccPNAND AM12 VccPNAND AM13 VccPNAND AM15 VccPNAND AM16 PCH Mobile Ball Name Ball #
VccSus3_3 U23 VccSus3_3 P18 VccSus3_3 U19 VccSus3_3 U20 VccSus3_3 U22 VccSus3_3 A26 VccSus3_3 A28 VccSus3_3 B27 VccSus3_3 C26 VccSus3_3 C28 VccSus3_3 E26 VccSus3_3 E28 VccSus3_3 F26 VccSus3_3 F28 VccSus3_3 G26 VccSus3_3 G28 VccSus3_3 H26 VccSus3_3 H28 VccSus3_3 J26 VccSus3_3 J28 VccSus3_3 L26 VccSus3_3 L28 VccSus3_3 M26 VccSus3_3 M28 VccSus3_3 N26 VccSus3_3 N28 VccSus3_3 P26 VccSus3_3 P28 VccSus3_3 U24 VccSus3_3 U26 VccSus3_3 U28 VccSus3_3 V28 VccSusHDA L30 VccTX_LVDS AP43 VccTX_LVDS AP45 VccTX_LVDS AT45 VccTX_LVDS AT46 VccVRM AT24 VccVRM AT22 VccVRM AT20 VccVRM AU24 PCH Mobile Ball Name Ball # Vss AU22 Vss AV18 Vss AA19 Vss AA20 Vss AA22 Vss AA24 Vss AA26 Vss AA28 Vss AA30 Vss AA31 Vss AA32 Vss AA50 Vss AB11 Vss AB15 Vss AB23 Vss AB30 Vss AB31 Vss AB32 Vss AB39 Vss AB43 Vss AB47 Vss AB5 Vss AB8 Vss AC2 Vss AC52 Vss AD11 Vss AD15 Vss AD16 Vss AD23 Vss AD24 Vss AD30 Vss AD31 Vss AD32 Vss AD34 Vss AD42 Vss AD46 Vss AD47 Vss AD49 Vss AD51 Vss AD7 Vss AE2 Vss AE4 Vss AF12 Vss AF35 PCH Mobile Ball Name Ball # Vss AF39 Vss AF45 Vss AF46 Vss AF49 Vss AF5 Vss AF8 Vss AG2 Vss AG52 Vss AH11 Vss AH15 Vss AH16 Vss AH24 Vss AH32 Vss AH43 Vss AH47 Vss AH48 Vss AH49 Vss AH7 Vss AJ19 Vss AJ2 Vss AJ20 Vss AJ22 Vss AJ23 Vss AJ26 Vss AJ28 Vss AJ32 Vss AJ34 Vss AJ4 Vss AK12 Vss AK22 Vss AK23 Vss AK26 Vss AK28 Vss AK30 Vss AK31 Vss AK32 Vss AK34 Vss AK35 Vss AK38 Vss AK39 Vss AK43 Vss AK45 Vss AK46 Vss AK49 PCH Mobile Ball Name Ball #
303 Datasheet
Ball Name Ball # Vss AT47 Vss AT5 Vss AT7 Vss AT8 Vss AU20 Vss AU4 Vss AV12 Vss AV14 Vss AV16 Vss AV20 Vss AV22 Vss AV24 Vss AV30 Vss AV34 Vss AV38 Vss AV42 Vss AV46 Vss AV49 Vss AV5 Vss AV8 Vss AW14 Vss AW18 Vss AW2 Vss AW32 Vss AW36 Vss AW40 Vss AW52 Vss AY11 Vss AY43 Vss AY47 Vss AY7 Vss B11 Vss B15 Vss B19 Vss B23 Vss B31 Vss B35 Vss B39 Vss B43 Vss B47 Vss B7 Vss BA12 Vss BA42 Vss BB10 PCH Mobile Ball Name Ball # Vss BB12 Vss BB16 Vss BB20 Vss BB24 Vss BB30 Vss BB34 Vss BB38 Vss BB42 Vss BB44 Vss BB49 Vss BB5 Vss BC10 Vss BC14 Vss BC18 Vss BC2 Vss BC22 Vss BC32 Vss BC36 Vss BC40 Vss BC44 Vss BC52 Vss BD48 Vss BD49 Vss BD5 Vss BE12 Vss BE16 Vss BE20 Vss BE24 Vss BE30 Vss BE34 Vss BE38 Vss BE42 Vss BE46 Vss BE48 Vss BE50 Vss BE6 Vss BE8 Vss BF3 Vss BF49 Vss BF51 Vss BF9 Vss BG12 Vss BG18 Vss BG24 PCH Mobile Ball Name Ball #
Ball Name Ball # Vss H38 Vss H42 Vss H49 Vss H5 Vss J24 Vss K11 Vss K43 Vss K47 Vss K7 Vss L14 Vss L18 Vss L2 Vss L22 Vss L32 Vss L36 Vss L40 Vss L52 Vss M12 Vss M16 Vss M20 Vss M34 Vss M38 Vss M42 Vss M46 Vss M49 Vss M5 Vss M8 Vss N24 Vss N38 Vss P11 Vss P16 Vss P22 Vss P30 Vss P32 Vss P34 Vss P38 Vss P42 Vss P45 Vss P47 Vss P49 Vss R2 Vss R52 Vss T12 Vss T41 PCH Mobile Ball Name Ball # Vss T43 Vss T46 Vss T49 Vss T5 Vss T8 Vss U30 Vss U31 Vss U32 Vss U34 Vss V11 Vss V19 Vss V20 Vss V22 Vss V30 Vss V31 Vss V32 Vss V34 Vss V35 Vss V38 Vss V43 Vss V45 Vss V46 Vss V47 Vss V49 Vss V5 Vss V7 Vss V8 Vss W2 Vss W52 Vss Y11 Vss Y12 Vss Y13 Vss Y15 Vss Y19 Vss Y23 Vss Y28 Vss Y30 Vss Y31 Vss Y32 Vss Y38 Vss Y43 Vss Y46 Vss Y47 Vss Y5 PCH Mobile Ball Name Ball #
305 Datasheet
Vss_NCTF A4 Vss_NCTF A49 Vss_NCTF A5 Vss_NCTF A50 Vss_NCTF A52 Vss_NCTF A53 Vss_NCTF B2 Vss_NCTF B4 Vss_NCTF B52 Vss_NCTF B53 Vss_NCTF BE1 Vss_NCTF BE53 Vss_NCTF BF1 Vss_NCTF BF53 Vss_NCTF BH1 Vss_NCTF BH2 Vss_NCTF BH52 Vss_NCTF BH53 Vss_NCTF BJ1 Vss_NCTF BJ2 Vss_NCTF BJ4 Vss_NCTF BJ49 Vss_NCTF BJ5 Vss_NCTF BJ50 Vss_NCTF BJ52 Vss_NCTF BJ53 Vss_NCTF D1 Vss_NCTF D2 Vss_NCTF D53 Vss_NCTF E1 Vss_NCTF E53 VssA_DAC AF51 VssA_DAC AF53 VssA_LVDS AH39 WAKE# J12 XCLK_RCOMP AF38 XTAL25_IN AH51 XTAL25_OUT AH53 PCH Mobile Ball Name Ball #
6.3 PCH Ballout Small Form Factor Ballout
This section contains the PCH Mobile Small Form Factor (SFF) ballout. Figure 6-5 and Figure 6-6 show the ballout from a top of the package quadrant view. Table 6-3 is the BGA ball list, sorted alphabetically by signal name.
307 Datasheet
Figure 6-5. PCH ballout (top vi ew—left side) (Mobile SFF Only) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 BE Vss_NCT F Vss_NCT F Vss_NCT F DDPB_0 P DDPB_2 P DDPB_3 P DDPC_1 P DDPD_1 N DDPD_0 P DDPD_2 P PETn8 PERn7 PETn5 PERn2 BE BD Vss_NCT F Vss_NCT F Vss Vss DDPB_1 P Vss DDPC_0 P Vss DDPB_H PD Vss PERn8 Vss PERn4 Vss BD BC Vss_NCT F Vss DDPB_0 N DDPB_2 N DDPB_3 N DDPC_1 N DDPD_1 P DDPD_0 N DDPD_2 N PETp8 PERp7 PETp5 PERp2 BC BB Vss Vss Vss DDPB_1 N Vss DDPC_0 N Vss DDPC_H PD VSS PERp8 VSS PERp4 VSS BB BA TP4 TP5 Vss DDPD_A UXP DDPC_A UXN DDPB_A UXN SDVO_I NTN DDPC_2 P DDPC_3 N DDPD_3P PETn6 PERp5 PERp3 BA AY TP6 TP7 Vss DDPD_A UXN Vss Vss Vss Vss Vss Vss Vss Vss Vss AY AW CLKOUT _PCIE1P CLKOUT _PCIE1N Vss Vss DDPC_A UXP DDPB_A UXP SDVO_I NTP DDPC_2 N DDPC_3 P DDPD_3N PETp6 PERn5 PERn3 AW AV Vss Vss LVDSA_ DATA1 LVDSA_ DATA#1 Vss Vss Vss Vss Vss Vss Vss Vss Vss AV AU CLKOUT _PCIE3P CLKOUT _PCIE3N Vss Vss Vss Vss SDVO_T VCLKIN N DDPD_H PD SDVO_S TALLN PERn6 PETp7 PETn4 PETn3 AU AT CLKOUT _PCIE2P CLKOUT _PCIE2N LVDSA_ DATA#3 LVDSA_ DATA3 Vss Vss Vss Vss Vss Vss Vss Vss Vss AT AR CLKOUT _PCIE4P CLKOUT _PCIE4N Vss Vss LVDSA_ DATA0 LVDSA_ DATA#0 SDVO_T VCLKINP Vss SDVO_S TALLP PERp6 PETn7 PETp4 PETp3 AR AP Vss Vss LVDSA_ CLK LVDSA_ CLK# Vss Vss Vss Vss Vss Vss Vss Vss Vss AP AN CLKOUT _PCIE6P CLKOUT _PCIE6N Vss Vss LVDSA_ DATA#2 LVDSA_ DATA2 AN AM CLKOUT _PCIE0P CLKOUT _PCIE0N LVDSB_ DATA#2 LVDSB_ DATA2 Vss Vss Vcc3_3 VSS VccADPL LA VccADPLL B Vss Vss Vss VccAPLL EXP AM AL CLKOUT _PCIE5P CLKOUT _PCIE5N Vss Vss LVDSB_ DATA0 LVDSB_ DATA#0 AL AK Vss Vss LVDSB_ DATA1 LVDSB_ DATA#1 Vss Vss Vss Vss Vss Vss Vss Vss VccIO VccIO AK AJ CLKOUT _PCIE7P CLKOUT _PCIE7N Vss Vss LVDSB_ DATA#3 LVDSB_ DATA3 AJ AH CLKOUT _PEG_B CLKOUT _PEG_B LVDSB_ CLK# LVDSB_ CLK Vss Vss VCCTX_ LVDS VCCTX_ LVDS Vss Vss VccCore VccCore VccCore VccCore AH AG CLKOUT _PEG_A CLKOUT _PEG_A Vss Vss LVD_VR EFH LVD_VR EFL AG AF V s sV s sV s sV s sV s sV s s VCCTX_ LVDS VCCTX_ LVDS VccIO VccIO Vss Vss VccCore VccCore AF AE VccA_CL K XCLK_R COMP TP16 TP17 LVD_IB G LVD_VB G AE AD XTAL25_ IN XTAL25_ OUT V s sV s sV s sV s s VccA_LV DS VSSA_L VDS VccIO VccIO VccME VccME Vss Vss AD AC CRT_DD C_DATA DDPD_C TRLCLK VssA_D AC VccADA C CRT_IRT N NC_2 Vss Vss Vss Vss VccME VccME Vss Vss AC AB Vss Vss Vss Vss Vss Vss Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 VccME VccME Vss Vss AB AA DDPD_C TRLDAT A CRT_DD C_CLK CRT_BL UE CRT_GR EEN CRT_RE D NC_3 AA Y SDVO_C TRLCLK SDVO_C TRLDAT A Vss Vss Vss Vss Vcc3_3 Vcc3_3 Vss Vss Vss VccME VccME VccME Y W L_DDC_ DATA L_BKLTE N CRT_HS YNC CRT_VS YNC DAC_IR EF NC_1 W V Vss Vss Vss Vss Vss Vss Vss VccME VccME Vss Vss VccME VccME VccME V U L_VDD_ EN L_BKLTC TL DDPC_C TRLCLK DDPC_C TRLDAT A L_DDC_ CLK NC_4 U T L_CTRL_ DATA L_CTRL_ CLK V s sV s sV s sV s sV s s VccME1 _1 VccME Vss Vss Vss Vss VSS T R CLKOUT _PCI2 CLKOUT _PCI4 REFCLK 14IN CLKOUT _PCI1 CLKOUT FLEX2 / GPIO66 CLKOUT FLEX1 / GPIO65 R P Vss Vss Vss Vss Vss Vss Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vss VccSus3 _3 P N CLKOUT FLEX0 / GPIO64 CLKOUT _PCI3 Vss CLKOUT FLEX3 / GPIO67 CLKOUT _PCI0 NC_5 N M REQ3# / GPIO54 PIRQF# / GPIO3 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss M L AD12 AD13 AD16 AD22 AD24 AD30 REQ0# PIRQB# REQ2# / GPIO52 TP17 TP16 TP14 VccSusH DA L K Vss AD14 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss K J AD15 AD18 C/BE0# GNT3# / GPIO55 PERR# C/BE2# AD9 TRDY# AD6 V5REF TP15 HDA_SD IN1 USBP12 N J H GNT0# GNT1# / GPIO51 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss H G AD21 PIRQC# AD1 AD28 FRAME# AD31 AD3 STOP# AD25 FWH4 / LFRAME# LDRQ1# GPIO23 HDA_SD O USBP12 P G F Vss C/BE3# Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss F E SERR# AD26 PAR AD23 AD27 REQ1# / GPIO50 AD2 GPIO1 GPIO7 HDA_DOC K_EN# / GPIO33 FWH0 / LAD0 HDA_SY NC HDA_BC LK E D PIRQE# / GPIO2 DEVSEL # C/BE1# PIRQG# / GPIO4 Vss PLOCK# Vss AD11 Vss FWH1 / LAD1 Vss HDA_SD IN3 Vss D C Vss_NCT F Vss AD17 AD5 AD29 GNT2# / GPIO53 A D 4A D 1 9A D 7G P I O 1 7 FWH2 / LAD2 HDA_RS USBRBI AS# C B Vss_NCT F Vss_NCT F Vss Vss PIRQD# Vss AD0 Vss PIRQA# Vss FWH3 / LAD3 Vss HDA_SD IN0 Vss B A Vss_NCT F Vss_NCT F Vss_NCT F AD10 PIRQH# / GPIO5 CLKIN_P CILOOP BACK AD8 AD20 IRDY# GPIO6 HDA_DOC K_RST# / GPIO13 LDRQ0# HDA_SD IN2 USBRBI AS A 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
308 Datasheet
Figure 6-6. PCH ballout (top vi ew—right side) (Mobile SFF Only) 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BE PETp1 DMI1TXP DMI0RXP DMI1RXN DMI2RXP DMI3TXN FDI_RXP
4 FDI_INT FDI_LSY
Vss_NCT F Vss_NCT F Vss_NCT F BE BD Vss Vss DMI2TXN Vss VCCFDIP LL Vss FDI_RXP
2 Vss PMSYNC
H Vss Vss Vss_NCT F Vss_NCT F BD BC PETn1 DMI1TXN DMI0RXN DMI1RXP DMI2RXN DMI3TXP FDI_RXN FDI_LSY NC1 FDI_FSY NC1 PECI Reserved Vss Vss_NCT F BC BB Vss Vss DMI2TXP Vss VSS Vss FDI_RXN
2 Vss FDI_FSY
NC0 Vss Reserved Reserved BB BA PERn1 CLKIN_D MI_N DMI_ZCO MP DMI0TXN DMI3RXP FDI_RXP FDI_RXP FDI_RXP
7 Reserved Reserved Reserved Reserved Reserved BA
AY Vss Vss Vss Vss VSS Vss Vss Vss Vss Vss Vss Vss AY AW PERp1 CLKIN_D MI_P DMI_IRC OMP DMI0TXP DMI3RXN FDI_RXN FDI_RXN FDI_RXN
7 Reserved Reserved Reserved Reserved Reserved AW
AV Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Reserved Reserved AV AU PETn2 TP1 TP2 TP3 FDI_RXN FDI_RXP FDI_RXN
5 VSS Reserved Reserved Reserved NV_ALE NV_CLE AU
AT Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Reserved Vss AT AR PETp2 VccVRM VccVRM VccVRM FDI_RXP FDI_RXN FDI_RXP
5 Reserved Reserved Reserved Reserved Reserved Reserved AR
RM Vss Vss Vss Vss Vss CLKIN_B CLK_N CLKIN_B CLK_P AP AN Reserved Reserved SPI_MOS I SPI_MIS O CLKOUT_ DP_N / CLKOUT_ BCLK1_N CLKOUT_ DP_P / CLKOUT_ BCLK1_P AN AM VccIO VccIO VccIO VccIO VccIO VccIO VccIO Vss Vss Vss Vss Vss Vss Vss AM AL Reserved SPI_CS1 SPI_CS0 # SPI_CLK CLKOUT_ DMI_N CLKOUT_ DMI_P AL AK Vss VccIO Vss VccIO V_CPU_I O V_CPU_I O V s sV s sV s sV s sV s sV s s CLKOUT_ BCLK0_P CLKOUT_ PCIE8P CLKOUT_ BCLK0_N CLKOUT_ PCIE8N AK AJ Vcc3_3 TP8 SATA0RX N SATA0RX P Vss VCCSATA PLL AJ AH Vss Vss Vcc_DMI Vss VccPNAN D VccPNAN D VccE3_3 VccE3_3 VSS Vss Vss VSS Vss Vss AH AG SATA0TX N SATA0TX P CLKIN_S ATA_P / CKSSCD CLKIN_S ATA_N / CKSSCD SATA1TX N SATA1TX P AG AF VccCore VccCore VccLAN VccLAN VccPNAN D VccPNAN D VccE3_3 VccME3_ SATAICO MPI SATAICO MPO Vss Vss Vss Vss AF AE SATA2RX N SATA2RX P SATA2TX N SATA2TX P SATA1RX P SATA1RX N AE AD VccCore VccCore Vss Vss VccIO Vss VccIO VccIO Vss VSS Vss Vss Vss Vss AD AC VccCore VccCore Vss Vss VccIO VccIO VccIO VccIO SATA3RX P SATA3RX N SATA3TX P SATA3TX N SATA4RX N SATA4RX P AC AB VccCore VccCore Vss Vss VccIO VccIO VccIO VccIO Vss Vss Vss Vss Vss Vss AB AA SATA5RX N SATA5RX P SATA5TX P SATA5TX N SATA4TX N SATA4TX P AA Y VSS VccCore VccCore Vss Vcc3_3 Vcc3_3 Vss Vss Vss Vss Vss Vss Vss Vss Y W SATA5GP / GPIO49 TMP_ALE RT# SATA4GP / GPIO16 SERIRQ BMBUSY # / GPIO0 SDATAO UT1 / GPIO48 CLKRUN # / GPIO32 W V Vss VccIO VccIO VccIO Vss Vss DcpSusB yp DcpSusB yp Vss A20GATE Vss Vss SATA2GP / GPIO36 SATA1GP / GPIO19 V U CL_CLK1 TP23 SATALED SCLOCK / GPIO22 RCIN# SPKR U T VccSus3_
3 VccIO Vss VccIO VccIO VccIO Vss Vss Vss CL_DATA
1 Vss Vss SATA0GP
/ GPIO21 Vss T R PCIECLK RQ1# / GPIO18 PEG_A_C LKRQ# / GPIO47 PWRBTN # GPIO35 SLOAD / GPIO38 SDATAO UT0 / GPIO39 R P VccSus3_ VccSus3_ VccSus3_
3 Vss VccSus3_
VccSus3_ VccSus3_ VccSus3_
3 Vss CL_RST1
# VSS Vss SYS_RES ET# INIT3_3V # P N DcpSST SYS_PW ROK ACPRES ENT / GPIO31 STP_PCI # / GPIO34 SUS_PW R_DN_A CK / GPIO30 PCIECLK RQ2# / GPIO20 N M Vss Vss Vss Vss Vss Vss Vss MEPWRO K Vss Vss SATA3GP / GPIO37 Vss M L USBP9N USBP6P Vss USBP1P TP10 DcpRTC SUSCLK / GPIO62 SMBCLK SLP_M# PME# JTAG_TDI GPIO27 GPIO28 L K Vss Vss Vss Vss Vss Vss Vss RI# Vss Vss PCIECLK RQ0# / GPIO73 SUS_STA T# / GPIO61 K J USBP9P USBP6N V5REF_S US USBP1N TP9 SRTCRS T# TP17 SMBALE RT# / GPIO11 SML0DAT A PCIECLK RQ6# / GPIO45 JTAG_TC K JTAG_TM S TRST# J H Vss Vss Vss Vss Vss Vss Vss Vss SLP_S5# / GPIO63 Vss PCIECLK RQ7# / GPIO46 Vss H G USBP13P USBP7N USBP4N USBP3N CLKIN_D OT_96N INTRUDE OC2# / GPIO41 TP24 GPIO8 GPIO24 GPIO15 PCIECLK RQ5# / GPIO44 JTAG_TD O G F Vss Vss Vss Vss Vss Vss Vss Vss Vss LAN_PHY _PWR_C TRL / GPIO12 SLP_S3# PCIRST# F E USBP13N USBP7P USBP4P USBP3P CLKIN_D OT_96P OC1# / GPIO40 VccRTC INTVRME N SML0ALE RT# / GPIO60 SML1ALE RT# / GPIO74 SLP_LAN # / GPIO29 Vss Vss_NCT F E D USBP10N Vss USBP2P Vss PWROK RSMRST OC7# / GPIO14 OC6# / GPIO10 PCIECLK RQ3# / GPIO25 DRAMPW ROK PLTRST# SLP_S4# D C USBP11N USBP8N USBP5N USBP0P OC5# / GPIO9 OC3# / GPIO42 RTCX2 LAN_RST OC0# / GPIO59 WAKE# BATLOW # / GPIO72 PCIECLK RQ4# / GPIO26 Vss_NCT F C B USBP10P Vss USBP2N Vss RTCRST# Vss SML1CLK / GPIO58 Vss SML0CLK Vss Vss Vss_NCT F B A USBP11P USBP8P USBP5P USBP0N SML1DAT A / GPIO75 OC4# / GPIO43 RTCX1 SMBDAT A PEG_B_C LKRQ# / GPIO56 GPIO57 Vss_NCT F Vss_NCT F A 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Table 6-3. PCH Ballout by Signal name (Mobile SFF Only) PCH SFF Ball Name Ball # A20GATE V10 ACPRESENT / GPIO31 N7 AD0 B40 AD1 G47 AD2 E39 AD3 G39 AD4 C39 AD5 C45 AD6 J35 AD7 C35 AD8 A41 AD9 J39 AD10 A47 AD11 D36 AD12 L51 AD13 L49 AD14 K48 AD15 J51 AD16 L47 AD17 C47 AD18 J49 AD19 C37 AD20 A39 AD21 G51 AD22 L45 AD23 E45 AD24 L43 AD25 G35 AD26 E49 AD27 E43 AD28 G45 AD29 C43 AD30 L41 AD31 G41 BATLOW# / GPIO72 C5 C/BE0# J47 C/BE1# D46 C/BE2# J41 C/BE3# F48 CL_CLK1 U11 CL_DATA1 T10 CL_RST1# P10 CLKIN_BCLK_N AP4 CLKIN_BCLK_P AP2 CLKIN_DMI_N BA23 CLKIN_DMI_P AW23 CLKIN_DOT_96N G17 CLKIN_DOT_96P E17 CLKIN_PCILOOPBA CK A43 CLKIN_SATA_N / CKSSCD_N AG5 CLKIN_SATA_P / CKSSCD_P AG7 CLKOUT_BCLK0_N / CLKOUT_PCIE8N AK2 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AK4 CLKOUT_DMI_N AL3 CLKOUT_DMI_P AL1 CLKOUT_DP_N / CLKOUT_BCLK1_N AN3 CLKOUT_DP_P / CLKOUT_BCLK1_P AN1 CLKOUT_PCI0 N43 CLKOUT_PCI1 R45 CLKOUT_PCI2 R51 CLKOUT_PCI3 N49 CLKOUT_PCI4 R49 CLKOUT_PCIE0N AM48 CLKOUT_PCIE0P AM50 CLKOUT_PCIE1N AW49 CLKOUT_PCIE1P AW51 CLKOUT_PCIE2N AT48 CLKOUT_PCIE2P AT50 CLKOUT_PCIE3N AU49 CLKOUT_PCIE3P AU51 CLKOUT_PCIE4N AR49 CLKOUT_PCIE4P AR51 CLKOUT_PCIE5N AL49 CLKOUT_PCIE5P AL51 PCH SFF Ball Name Ball # CLKOUT_PCIE6N AN49 CLKOUT_PCIE6P AN51 CLKOUT_PCIE7N AJ49 CLKOUT_PCIE7P AJ51 CLKOUT_PEG_A_N AG49 CLKOUT_PEG_A_P AG51 CLKOUT_PEG_B_N AH48 CLKOUT_PEG_B_P AH50 CLKOUTFLEX0 / GPIO64 N51 CLKOUTFLEX1 / GPIO65 R41 CLKOUTFLEX2 / GPIO66 R43 CLKOUTFLEX3 / GPIO67 N45 CLKRUN# / GPIO32 W1 CRT_BLUE AA47 CRT_DDC_CLK AA49 CRT_DDC_DATA AC51 CRT_GREEN AA45 CRT_HSYNC W47 CRT_IRTN AC43 CRT_RED AA43 CRT_VSYNC W45 DAC_IREF W43 DcpRTC L15 DcpSST N11 DcpSus T18 DcpSus T19 DcpSusByp V14 DcpSusByp V16 DDPB_0N BC47 DDPB_0P BE47 DDPB_1N BB44 DDPB_1P BD44 DDPB_2N BC45 DDPB_2P BE45 DDPB_3N BC43 DDPB_3P BE43 DDPB_AUXN BA41 PCH SFF Ball Name Ball #
310 Datasheet
DDPB_AUXP AW41 DDPB_HPD BD36 DDPC_0N BB40 DDPC_0P BD40 DDPC_1N BC41 DDPC_1P BE41 DDPC_2N AW37 DDPC_2P BA37 DDPC_3N BA35 DDPC_3P AW35 DDPC_AUXN BA43 DDPC_AUXP AW43 DDPC_CTRLCLK U47 DDPC_CTRLDATA U45 DDPC_HPD BB36 DDPD_0N BC37 DDPD_0P BE37 DDPD_1N BE39 DDPD_1P BC39 DDPD_2N BC35 DDPD_2P BE35 DDPD_3N AW33 DDPD_3P BA33 DDPD_AUXN AY44 DDPD_AUXP BA45 DDPD_CTRLCLK AC49 DDPD_CTRLDATA AA51 DDPD_HPD AU37 DEVSEL# D48 DMI_IRCOMP AW21 DMI_ZCOMP BA21 DMI0RXN BC21 DMI0RXP BE21 DMI0TXN BA19 DMI0TXP AW19 DMI1RXN BE19 DMI1RXP BC19 DMI1TXN BC23 DMI1TXP BE23 DMI2RXN BC17 DMI2RXP BE17 PCH SFF Ball Name Ball # DMI2TXN BD20 DMI2TXP BB20 DMI3RXN AW17 DMI3RXP BA17 DMI3TXN BE15 DMI3TXP BC15 DRAMPWROK D6 FDI_FSYNC0 BB8 FDI_FSYNC1 BC9 FDI_INT BE11 FDI_LSYNC0 BE9 FDI_LSYNC1 BC11 FDI_RXN0 AU17 FDI_RXN1 AW15 FDI_RXN2 BB12 FDI_RXN3 AR15 FDI_RXN4 BC13 FDI_RXN5 AU13 FDI_RXN6 AW13 FDI_RXN7 AW11 FDI_RXP0 AR17 FDI_RXP1 BA15 FDI_RXP2 BD12 FDI_RXP3 AU15 FDI_RXP4 BE13 FDI_RXP5 AR13 FDI_RXP6 BA13 FDI_RXP7 BA11 FRAME# G43 FWH0 / LAD0 E31 FWH1 / LAD1 D32 FWH2 / LAD2 C31 FWH3 / LAD3 B32 FWH4 / LFRAME# G33 GNT0# H50 GNT1# / GPIO51 H48 GNT2# / GPIO53 C41 GNT3# / GPIO55 J45 GPIO0 W5 GPIO1 E37 GPIO6 A35 PCH SFF Ball Name Ball # GPIO7 E35 GPIO8 G9 GPIO15 G5 GPIO17 C33 GPIO24 G7 GPIO27 L3 GPIO28 L1 GPIO35 R5 GPIO57 A7 HDA_BCLK E27 HDA_DOCK_EN# / GPIO33 E33 HDA_DOCK_RST# / GPIO13 A33 HDA_RST# C29 HDA_SDIN0 B28 HDA_SDIN1 J29 HDA_SDIN2 A29 HDA_SDIN3 D28 HDA_SDO G29 HDA_SYNC E29 INIT3_3V# P2 INTRUDER# G15 INTVRMEN E11 IRDY# A37 JTAG_TCK J5 JTAG_TDI L5 JTAG_TDO G1 JTAG_TMS J3 L_BKLTCTL U49 L_BKLTEN W49 L_CTRL_CLK T48 L_CTRL_DATA T50 L_DDC_CLK U43 L_DDC_DATA W51 L_VDD_EN U51 LAN_PHY_PWR_CTR L / GPIO12 F6 LAN_RST# C11 LDRQ0# A31 LDRQ1# / GPIO23 G31 LVD_IBG AE43 PCH SFF Ball Name Ball #
LVD_VBG AE41 LVD_VREFH AG43 LVD_VREFL AG41 LVDSA_CLK AP46 LVDSA_CLK# AP44 LVDSA_DATA#0 AR41 LVDSA_DATA#1 AV44 LVDSA_DATA#2 AN43 LVDSA_DATA#3 AT46 LVDSA_DATA0 AR43 LVDSA_DATA1 AV46 LVDSA_DATA2 AN41 LVDSA_DATA3 AT44 LVDSB_CLK AH44 LVDSB_CLK# AH46 LVDSB_DATA#0 AL41 LVDSB_DATA#1 AK44 LVDSB_DATA#2 AM46 LVDSB_DATA#3 AJ43 LVDSB_DATA0 AL43 LVDSB_DATA1 AK46 LVDSB_DATA2 AM44 LVDSB_DATA3 AJ41 MEPWROK M10 NC_1 W41 NC_2 AC41 NC_3 AA41 NC_4 U41 NC_5 N41 NV_ALE AU3 NV_CLE AU1 OC0# / GPIO59 C9 OC1# / GPIO40 E15 OC2# / GPIO41 G13 OC3# / GPIO42 C15 OC4# / GPIO43 A15 OC5# / GPIO9 C17 OC6# / GPIO10 D10 OC7# / GPIO14 D12 PAR E47 PCH SFF Ball Name Ball # PCIECLKRQ0# / GPIO73 K4 PCIECLKRQ1# / GPIO18 R11 PCIECLKRQ2# / GPIO20 N1 PCIECLKRQ3# / GPIO25 D8 PCIECLKRQ4# / GPIO26 C3 PCIECLKRQ5# / GPIO44 G3 PCIECLKRQ6# / GPIO45 J7 PCIECLKRQ7# / GPIO46 H4 PCIRST# F2 PECI BC7 PEG_A_CLKRQ# / GPIO47 R9 PEG_B_CLKRQ# / GPIO56 A9 PERn1 BA25 PERn2 BE27 PERn3 AW27 PERn4 BD28 PERn5 AW29 PERn6 AU33 PERn7 BE31 PERn8 BD32 PERp1 AW25 PERp2 BC27 PERp3 BA27 PERp4 BB28 PERp5 BA29 PERp6 AR33 PERp7 BC31 PERp8 BB32 PERR# J43 PETn1 BC25 PETn2 AU25 PETn3 AU27 PETn4 AU29 PETn5 BE29 PCH SFF Ball Name Ball # PETn6 BA31 PETn7 AR31 PETn8 BE33 PETp1 BE25 PETp2 AR25 PETp3 AR27 PETp4 AR29 PETp5 BC29 PETp6 AW31 PETp7 AU31 PETp8 BC33 PIRQA# B36 PIRQB# L37 PIRQC# G49 PIRQD# B44 PIRQE# / GPIO2 D50 PIRQF# / GPIO3 M48 PIRQG# / GPIO4 D44 PIRQH# / GPIO5 A45 PLOCK# D40 PLTRST# D4 PME# L7 PMSYNCH BD8 PROCPWRGD BE7 PWRBTN# R7 PWROK D16 RCIN# U3 REFCLK14IN R47 REQ0# L39 REQ1# / GPIO50 E41 REQ2# / GPIO52 L35 REQ3# / GPIO54 M50 Reserved AU7 Reserved AW3 Reserved AL11 Reserved BA7 Reserved AT4 Reserved BA3 Reserved AN9 Reserved AN11 Reserved AW7 PCH SFF Ball Name Ball #
312 Datasheet
RI# K10 RSMRST# D14 RTCRST# B16 RTCX1 A13 RTCX2 C13 SATA0GP / GPIO21 T4 SATA0RXN AJ7 SATA0RXP AJ5 SATA0TXN AG11 SATA0TXP AG9 SATA1GP / GPIO19 V2 SATA1RXN AE1 SATA1RXP AE3 SATA1TXN AG3 SATA1TXP AG1 SATA2GP / GPIO36 V4 SATA2RXN AE11 SATA2RXP AE9 SATA2TXN AE7 SATA2TXP AE5 SATA3GP / GPIO37 M4 SATA3RXN AC9 PCH SFF Ball Name Ball # SATA3RXP AC11 SATA3TXN AC5 SATA3TXP AC7 SATA4GP / GPIO16 W9 SATA4RXN AC3 SATA4RXP AC1 SATA4TXN AA3 SATA4TXP AA1 SATA5GP / GPIO49/ TEMP_ALERT# W11 SATA5RXN AA11 SATA5RXP AA9 SATA5TXN AA5 SATA5TXP AA7 SATAICOMPI AF12 SATAICOMPO AF10 SATALED# U7 SCLOCK / GPIO22 U5 SDATAOUT0 / GPIO39 R1 SDATAOUT1 / GPIO48 W3 SDVO_CTRLCLK Y50 SDVO_CTRLDATA Y48 SDVO_INTN BA39 SDVO_INTP AW39 SDVO_STALLN AU35 SDVO_STALLP AR35 SDVO_TVCLKINN AU39 SDVO_TVCLKINP AR39 SERIRQ W7 SERR# E51 SLOAD / GPIO38 R3 SLP_LAN# / GPIO29 E5 SLP_M# L9 SLP_S3# F4 SLP_S4# D2 SLP_S5# / GPIO63 H8 SMBALERT# / GPIO11 J11 SMBCLK L11 PCH SFF Ball Name Ball # SMBDATA A11 SML0ALERT# / GPIO60 E9 SML0CLK B8 SML0DATA J9 SML1ALERT# / GPIO74 E7 SML1CLK / GPIO58 B12 SML1DATA / GPIO75 A17 SPI_CLK AL5 SPI_CS0# AL7 SPI_CS1# AL9 SPI_MISO AN5 SPI_MOSI AN7 SPKR U1 SRTCRST# J15 STOP# G37 STP_PCI# / GPIO34 N5 SUS_PWR_DN_ACK / GPIO30 N3 SUS_STAT# / GPIO61 K2 SUSCLK / GPIO62 L13 SYS_PWROK N9 SYS_RESET# P4 THRMTRIP# BE5 TP1 AU23 TP2 AU21 TP3 AU19 TP4 BA51 TP5 BA49 TP6 AY50 TP7 AY48 TP8 AJ9 TP9 J17 TP10 L17 TP12 AE47 TP13 AE45 TP14 L29 TP15 J31 TP16 L31 PCH SFF Ball Name Ball #
TRDY# J37 TRST# J1 USBP0N A19 USBP0P C19 USBP1N J19 USBP1P L19 USBP2N B20 USBP2P D20 USBP3N G19 USBP3P E19 USBP4N G21 USBP4P E21 USBP5N C21 USBP5P A21 USBP6N J23 USBP6P L23 USBP7N G23 USBP7P E23 USBP8N C23 USBP8P A23 USBP9N L25 USBP9P J25 USBP10N D24 USBP10P B24 USBP11N C25 USBP11P A25 USBP12N J27 USBP12P G27 USBP13N E25 USBP13P G25 USBRBIAS A27 USBRBIAS# C27 V_CPU_IO AK18 V_CPU_IO AK19 V5REF J33 V5REF_Sus J21 Vcc3_3 AB33 PCH SFF Ball Name Ball # Vcc3_3 AB34 Vcc3_3 AB36 Vcc3_3 AB38 Vcc3_3 Y36 Vcc3_3 Y38 Vcc3_3 AM38 Vcc3_3 AJ11 Vcc3_3 Y18 Vcc3_3 Y19 Vcc3_3 P30 Vcc3_3 P31 Vcc3_3 P33 Vcc3_3 P34 Vcc3_3 P36 Vcc3_3 P38 VccAClk AE51 VccADAC AC45 VccADPLLA AM34 VccADPLLB AM33 VccALVDS AD38 VccAPLLEXP AM27 VccCore AB24 VccCore AB25 VccCore AC24 VccCore AC25 VccCore AD24 VccCore AD25 VccCore AF24 VccCore AF25 VccCore AF27 VccCore AF28 VccCore AH27 VccCore AH28 VccCore AH30 VccCore AH31 VccCore Y22 VccCore Y24 VccDMI AH22 VCCFDIPLL BD16 VccIO AK27 VccIO AK28 PCH SFF Ball Name Ball # VccIO AM19 VccIO AM21 VccIO AM22 VccIO AM24 VccIO AM25 VccIO AM16 VccIO AM18 VccIO T21 VccIO AD19 VccIO AF33 VccIO AF34 VccIO AD16 VccIO AK24 VccIO AK21 VccIO AB14 VccIO AB16 VccIO AB18 VccIO AB19 VccIO AC14 VccIO AC16 VccIO AC18 VccIO AC19 VccIO AD14 VccIO AD33 VccIO AD34 VccIO T24 VccIO V21 VccIO V22 VccIO V24 VccLAN AF21 VccLAN AF22 VccME AB30 VccME AB31 VccME AC30 VccME AC31 VccME AD30 VccME AD31 VccME V34 VccME T34 VccME T36 VccME V36 PCH SFF Ball Name Ball #
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VccME3_3 AF14 VccME3_3 AF16 VccME3_3 AH14 VccME3_3 AH16 VccPNAND AF18 VccPNAND AF19 VccPNAND AH18 VccPNAND AH19 VccRTC E13 VCCSATAPLL AJ1 VccSus3_3 T25 VccSus3_3 P14 VccSus3_3 P16 VccSus3_3 P18 VccSus3_3 P19 VccSus3_3 P22 VccSus3_3 P24 VccSus3_3 P25 VccSus3_3 P27 VccSusHDA L27 VccTX_LVDS AF36 VccTX_LVDS AF38 VccTX_LVDS AH36 VccTX_LVDS AH38 VccVRM AR21 VccVRM AP22 VccVRM AR19 VccVRM AR23 Vss AP18 Vss AP16 Vss AB10 Vss AB12 Vss AB2 Vss AB21 Vss AB22 PCH SFF Ball Name Ball # Vss AB27 Vss AB28 Vss AB4 Vss AB40 Vss AB42 Vss AB44 Vss AB46 Vss AB48 Vss AB50 Vss AB6 Vss AB8 Vss AC21 Vss AC22 Vss AC27 Vss AC28 Vss AC33 Vss AC34 Vss AC36 Vss AC38 Vss AD10 Vss AD12 Vss AD18 Vss AD2 Vss AD21 Vss AD22 Vss AD27 Vss AD28 Vss AD4 Vss AD40 Vss AD42 Vss AD44 Vss AD46 Vss AD6 Vss AD8 Vss AF2 Vss AF30 Vss AF31 Vss AF4 Vss AF40 Vss AF42 Vss AF44 PCH SFF Ball Name Ball # Vss AF46 Vss AF48 Vss AF50 Vss AF6 Vss AF8 Vss AG45 Vss AG47 Vss AH10 Vss AH2 Vss AH21 Vss AH24 Vss AH25 Vss AH33 Vss AH34 Vss AH4 Vss AH40 Vss AH42 Vss AH6 Vss AH8 Vss AJ3 Vss AJ45 Vss AJ47 Vss AK10 Vss AK12 Vss AK14 Vss AK16 Vss AK22 Vss AK25 Vss AK30 Vss AK31 Vss AK33 Vss AK34 Vss AK36 Vss AK38 Vss AK40 Vss AK42 Vss AK48 Vss AK50 Vss AK6 Vss AK8 Vss AL45 PCH SFF Ball Name Ball #
Ball Name Ball # Vss AT2 Vss AT20 Vss AT22 Vss AT24 Vss AT26 Vss AT28 Vss AT30 Vss AT32 Vss AT34 Vss AT36 Vss AT38 Vss AT40 Vss AT42 Vss AT6 Vss AT8 Vss AU41 Vss AU43 Vss AU45 Vss AU47 Vss AV10 Vss AV12 Vss AV14 Vss AV16 Vss AV18 Vss AV20 Vss AV22 Vss AV24 Vss AV26 Vss AV28 Vss AV30 Vss AV32 Vss AV34 Vss AV36 Vss AV38 Vss AV40 Vss AV42 Vss AV48 Vss AV50 Vss AV6 Vss AV8 Vss AW45 PCH SFF Ball Name Ball # Vss AW47 Vss AY10 Vss AY12 Vss AY14 Vss AY16 Vss AY18 Vss AY2 Vss AY20 Vss AY22 Vss AY24 Vss AY26 Vss AY28 Vss AY30 Vss AY32 Vss AY34 Vss AY36 Vss AY38 Vss AY4 Vss AY40 Vss AY42 Vss AY46 Vss AY6 Vss AY8 Vss B10 Vss B14 Vss B18 Vss B22 Vss B26 Vss B3 Vss B30 Vss B34 Vss B38 Vss B42 Vss B46 Vss B49 Vss B6 Vss BA47 Vss BB10 Vss BB14 Vss BB16 Vss BB18 PCH SFF Ball Name Ball #
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Ball Name Ball # Vss F20 Vss F22 Vss F24 Vss F26 Vss F28 Vss F30 Vss F32 Vss F34 Vss F36 Vss F38 Vss F40 Vss F42 Vss F44 Vss F46 Vss F50 Vss F8 Vss H10 Vss H12 Vss H14 Vss H16 Vss H18 Vss H2 Vss H20 Vss H22 Vss H24 Vss H26 Vss H28 Vss H30 Vss H32 Vss H34 Vss H36 Vss H38 Vss H40 Vss H42 Vss H44 Vss H46 Vss H6 Vss K12 Vss K14 Vss K16 Vss K18 PCH SFF Ball Name Ball # Vss K20 Vss K22 Vss K24 Vss K26 Vss K28 Vss K30 Vss K32 Vss K34 Vss K36 Vss K38 Vss K40 Vss K42 Vss K44 Vss K46 Vss K50 Vss K6 Vss K8 Vss L21 Vss M12 Vss M14 Vss M16 Vss M18 Vss M2 Vss M20 Vss M22 Vss M24 Vss M26 Vss M28 Vss M30 Vss M32 Vss M34 Vss M36 Vss M38 Vss M40 Vss M42 Vss M44 Vss M46 Vss M6 Vss M8 Vss N47 Vss P12 PCH SFF Ball Name Ball #
§ § Vss P21 Vss P28 Vss P40 Vss P42 Vss P44 Vss P46 Vss P48 Vss P50 Vss P6 Vss P8 Vss T12 Vss T14 Vss T16 Vss T2 Vss T22 Vss T28 Vss T30 Vss T31 Vss T33 Vss T38 Vss T40 Vss T42 Vss T44 Vss T46 Vss T6 Vss T8 Vss V12 Vss V18 Vss V19 Vss V25 Vss V31 Vss V33 Vss V38 Vss V40 Vss V42 Vss V44 Vss V46 Vss V48 Vss V50 Vss V6 Vss V8 PCH SFF Ball Name Ball # Vss Y10 Vss Y12 Vss Y14 Vss Y16 Vss Y2 Vss Y21 Vss Y25 Vss Y31 Vss Y33 Vss Y34 Vss Y4 Vss Y40 Vss Y42 Vss Y44 Vss Y46 Vss Y6 Vss Y8 Vss AU11 Vss AM36 Vss AH12 Vss T27 Vss_NCTF A3 Vss_NCTF A49 Vss_NCTF A5 Vss_NCTF A50 Vss_NCTF A51 Vss_NCTF B2 Vss_NCTF B50 Vss_NCTF B51 Vss_NCTF BC1 Vss_NCTF BC51 Vss_NCTF BD1 Vss_NCTF BD2 Vss_NCTF BD50 Vss_NCTF BD51 Vss_NCTF BE1 Vss_NCTF BE2 Vss_NCTF BE3 Vss_NCTF BE49 Vss_NCTF BE50 Vss_NCTF BE51 PCH SFF Ball Name Ball # Vss_NCTF C1 Vss_NCTF C51 Vss_NCTF E1 VssA_DAC AC47 VssA_LVDS AD36 WAKE# C7 XCLK_RCOMP AE49 XTAL25_IN AD50 XTAL25_OUT AD48 PCH SFF Ball Name Ball #
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Package Information
7 Package Information
7.1 PCH package (Desktop Only)
- FCBGA package
- P a c k a g e s i z e : 2 7 mm x 27 mm
- Ball Count: 951
- Ball pitch: 0.7 mm The Desktop package information is shown in Figure 7-1. Note: All dimensions, unless otherwise specified, are in millimeters.
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Figure 7-1. PCH Desktop Package Drawing
7.2 PCH package (Mobile Only)
- FCBGA package
- P a c k a g e s i z e : 2 7 mm x 25 mm
- Ball Count: 1071
- Ball pitch: 0.6 mm The PCH Mobile package information is shown in Figure 7-2. Note: All dimensions, unless otherwise specified, are in millimeters.
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Figure 7-2. PCH B-Step Mobile Package Drawing
7.3 PCH package (Mobile SFF Only)
- FCBGA package
- P a c k a g e s i z e : 2 2 mm x 20 mm
- Ball Count: 1045 Ball pitch: 0.593 mm The PCH SFF Mobile package information is shown in Figure 7-3. Note: All dimensions, unless otherwise specified, are in millimeters.
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§ § Figure 7-3. PCH Mobile SFF Package Drawing
Electrical Characteristics
8 Electrical Characteristics
This chapter contains the DC and AC characteristics for the PCH. AC timing diagrams are included.
8.1 Thermal Specifications
8.1.1 Desktop Storage Specificat ions and Thermal Design Power
(TDP) For desktop thermal information, see the Intel® 5 Series Express Chipset Platform Controller Hub (PCH) Thermal Mechanical Specifications and Design Guidelines (TMS), Document # 407051.
8.1.2 Mobile Storage Specificatio ns and Thermal Design Power
(TDP) NOTES: 1. Refers to a component device that is not assembled in a board or socket and is not electrically connected to a voltage reference or I/O signal. 2. Specified temperatures are not to exceed valu es based on data collected. Exceptions for surface mount reflow are specified by the applicable JEDEC standard. Non-adherence may affect PCH reliability. 3. Tabsolute storage applies to the unassembled component only and does not apply to the shipping media, moisture barrier bags, or dessicant. 4. Intel branded products are specified and cert ified to meet the following temperature and humidity limits that are given as an example only (Non-Operating Temperature Limit: -40 °C to 70 °C and Humidity: 50% to 90%, non-condensing with a maximum wet bulb of 28 °C.) Post board attach storage temperature limits are not specified for non-Intel branded boards. 5. The JEDEC J-JSTD-020 moisture level rating an d associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag. 6. Nominal temperature and humidity conditions and durations are given and tested within the constraints imposed by TSUSTAINED storage and customer shelf life in applicable Intel boxes and bags. 7. The thermal solution needs to ensure that the temperature does not exceed the maximum junction temperature (Tj,max) limit. See the Embedded Controller Support Provided by Ibex Peak(IBX) - Technical Update - Rev. 1.5 Document number 390730 for details on how measure Tj. Table 8-1. Storage Conditions Parameter Description Min Max Notes TABSOLUTE STORAGE The non-operating device storage temperature. Damage (latent or otherwise) may occur when exceeded for any length of time TSUSTAINED STORAGE The ambient storage temperature (in shipping media) for a sustained period of time. -5 °C 40 °C 4,5 RHSUSTAINED STORAGE The maximum device storage relative humidity for a sustained period of time. 60% @ 24 °C 5,6 TIME SUSTAINED STORAGE A prolonged or extended period of time; typically associated with customer shelf life. Months Months 6 Tj (Mobile only) Mobile Thermal Junction Operating Temperature limits 0 °C 108 °C 7
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NOTES: 1. For usage configurations please see the Mobile Ibex Peak Platform Controller Hub (PCH) Thermal Design Power (TDP) and Scenario Guidance Document # 427704.
8.2 Absolute Maximum and Minimum Ratings
Table 8-3 specifies absolute maximum and minimum ratings. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits (but within the absolute maximum and minimum ratings) the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time, it will either not function or its reliability will be severely degraded when returned to conditions within the functional operating condition limits. Although the PCH/ICHx contains protective circuitry to resist damage from Electro - Static Discharge (ESD), precautions should always be taken to avoid high static voltages or electric fields. Table 8-2. Mobile Thermal Design Power SKU Thermal Design Power (TDP) Notes QM57 3.5 W 1 HM57 3.5 W 1 HM55 3.5 W 1 PM55 3.5 W 1 QS57 3.4 W 1 Table 8-3. PCH Absolute Maximum Ratings Parameter Maximum Limits Voltage on any 5 V Tolerant Pin with respect to Ground (V5REF = 5 V) -0.5 to V5REF + 0.5 V Voltage on any 3.3 V Pin with respect to Ground -0.5 to Vcc3_3 + 0.4 V Voltage on any 1.8 V Tolerant Pin with respect to Ground -0.5 to VccVRM + 0.5 V Voltage on any 1.05 V Tolerant Pin with respect to Ground -0.5 to VccIO + 0.5 V 1.05 V Supply Voltage with respect to VSS -0.5 to 1.3 V 1.8 V Supply Voltage with respect to VSS -0.5 to 3.7 V 3.3 V Supply Voltage with respect to VSS -0.5 to 3.7 V 5.0 V Supply Voltage with respect to VSS -0.5 to 5.5 V V_CPU_IO Supply Voltage with respect to VSS -0.5 to 1.3 V 1.8 V Supply Voltage for the analog PLL with respect to VSS -0.5 to 1.98 V
8.3 Intel ® 5 Series Chipset and Intel® 3400 Series
Chipset Power Supply range
8.4 General DC Characteristics
Note that ICC values in Table 8-5 and Table 8-6 are all pre-silicon estimates. Values will be updated when characterized on real silicon is completed. NOTES: 1. G3 state shown to provide an estimate of battery life. 2. Icc (RTC) data is taken with VccRTC at 3.0 V while the system in a mechanical off (G3) state at room temperature. Table 8-4. PCH Power Supply Range Power Supply Minimum Nominal Maximum 1.05 V 1.00 V 1.05 V 1.10 V 1.5 V 1.43 V 1.50 V 1.58 V 1.8 V 1.71 V 1.80 V 1.89 V 3.3 V 3.14 V 3.30 V 3.47 V 5 V 4.75 V 5.00 V 5.25 V Table 8-5. Measured I CC (Desktop Only) Voltage Rail Voltage (V) S0 Iccmax Current Integrated Graphics (A) S0 Iccmax Current External Graphics (A) S0 Idle Current Integrated Graphics (A) S0 Idle Current External Graphics (A) Sx Iccmax Current (A) Sx Idle Current (A) V_CPU_IO 1.1/ V5REF 5 .001 .001 .001 .001 — — — VccRTC 3.3 N/A N/A N/A N/A N/A N/A 6 uA See notes 1, 2
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NOTES: 1. G3 state shown to provide an estimate of battery life. 2. Icc (RTC) data is taken with VccRTC at 3.0 V while the system in a mechanical off (G3) state at room temperature. Table 8-6. Measured I CC (Mobile Only) Voltage Rail Voltage (V) S0 Iccmax Current Integrated Graphics (A) S0 Iccmax Current External Graphics (A) S0 Idle Current Integrated Graphics (A) S0 Idle Current External Graphics (A) Sx Iccmax Current (A) Sx Idle Current (A) V_CPU_IO 1.1/ V5REF 5 .001 .001 .001 .001 — VccRTC 3.3 N/A N/A N/A N/A N/A N/A 6 uA See notes 1, 2
NOTES: 1. G3 state shown to provide an estimate of battery life. 2. Icc (RTC) data is taken with VccRTC at 3.0 V while the system in a mechanical off (G3) state at room temperature. Table 8-7. Measured ICC (SFF Only) Voltage Rail Voltage (V) S0 Iccmax Current Integrated Graphics (A) S0 Iccmax Current External Graphics (A) S0 Idle Current Integrated Graphics (A) S0 Idle Current External Graphics (A) Sx Iccmax Current (A) Sx Idle Current (A) V_CPU_IO 1.1/ V5REF 5 .001 .001 .001 .001 — VccRTC 3.3 N/A N/A N/A N/A N/A N/A 6 uA See notes 1, 2
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Table 8-8. DC Characteristic Input Signal Association (Sheet 1 of 2) Symbol Associated Signals VIH1/VIL1 (5V Tolerant) PCI Signals: AD[31:0], C/BE[3:0]#, DEVSEL#, FRAME#, IRDY#, PAR, PERR#, PLOCK#, REQ[3:0]#, SERR#, STOP#, TRDY# Interrupt Signals: PIRQ[D:A]#, PIRQ[H:E]#, SERIRQ GPIO Signals: GPIO[54, 52, 50, 5:2] VIH2/VIL2 Digital Display Port Hot Plug Detect: DDPB_HPD, DDPC_HPD, DDPD_HPD VIH3/VIL3 Clock Signals: REFCLK14IN Power Management Signals: PWRBTN#, RI#, SYS_RESET#, WAKE#, CLKRUN# (Mobile Only) Mobile Only: AC_PRESENT GPIO Signals: GPIO[67:61, 57, 48, 39, 38, 34, 32, 31, 30, 29, 24, 22, 17, 7, 6, 1] Intel® Quiet System Technology Signals: TACH[3:0] Strap Signals:, SATALED# (Strap purposes only) VIH4/VIL4 Clock Signals: CLKIN_PCILOOPBACK Processor Signals:A20GATE PCI Signals: PME# Interrupt Signals: SERIRQ Integrated Clock Signals: PEG_A_CLKRQ#, PEG_B_CLKRQ#, PCIECLKRQ[7:0]# Power Management Signals: BATLOW# SATA Signals: SATA[5:0]GP SPI Signals: SPI_MISO Strap Signals: SPKR, SPI_MOSI, GNT[3:0]#, (Strap purposes only) LPC/Firmware Hub Signals: LAD[3:0]/FWH[3:0], LDRQ0#, LDRQ1#, GPIO Signals: GPIO[73, 72, 59, 56, 55, 53, 51, 49, 47:40, 37, 36, 35, Desktop Only: GPIO[72, 12] USB Signals: OC[7:0]# VIH5/VIL5 SMBus Signals: SMBCLK, SMBDATA, SMBALERT# System Management Signals: SML[1:0]CLK(1), SML[1:0]DATA(1) GPIO Signals: GPIO[75, 74, 60, 58, 11] Processor Interface: RCIN# Power Management Signals: SYS_PWROK, LAN_RST#, MEPWROK VIH6/VIL6 JTAG Signals: JTAG_TDI, JTAG_TMS, TRST#, JTAG_TCK VIH7/VIL7 Processor Signals: THRMTRIP# VIMIN8/VIMAX8 PCI Express* Data RX Signals: PER[p,n][8:1] VIH9/VIL9 Real Time Clock Signals: RTCX1 VIMIN10 -Gen1i/ VIMAX10-Gen1i SATA Signals: SATA[5:0]RX[P,N] (1.5 Gb/s internal SATA) VIMIN10 -Gen1m/ VIMAX10-Gen1m SATA Signals: SATA[5:0]RX[P,N] (1.5 Gb/s external SATA) VIMIN10 -Gen2i/ VIMAX10-Gen2i SATA Signals: SATA[5:0]RX[P,N] (3.0 Gb/s internal SATA) VIMIN10 -Gen2m/ VIMAX10-Gen2m SATA Signals: SATA[5:0]RX[P,N] (3.0 Gb/s external SATA)
NOTES: 1. V DI = | USBPx[P] – USBPx[N]. 2. Includes VDI range. 3. Applies to Low-Speed/High-Speed USB. 4. PCI Express mVdiff p-p = 2*|PETp[x] – PETn[x]|. 5. SATA Vdiff, RX (VIMAX10/MIN10) is measured at the SATA connector on the receiver side (generally, the motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]RXP – SATA[x]RXN|. 6. VccRTC is the voltage applied to the VccRTC we ll of the PCH. When the system is in a G3 state, this is generally supplied by the coin cell battery, but for S5 and greater, this is generally VccSus3_3. 7. CL_Vref = 0.27 CL_VREF1 applie s to Mobile configurations. 8. This is an AC characteri stic that represents transient values for these signals. 9. Applies to High-Speed USB 2.0. VIH11/VIL11 Intel High Definition Audio Signals: HDA_SDIN[3:0] (3.3V Mode) Strap Signals: HDA_SDOUT, HDA_SYNC (Strap purposes only) GPIO Signals: GPIO13 NOTE: See VIL_HDA/VIH_HDA for High Definition Audio Low Voltage Mode VIH12 (Absolute Maximum) / VIL12 (Absolute Minimum) / Vclk_in_cross(abs) Clock Signals: CLKIN_BCLK_[P,N], CLKIN_DMI_[P,N], CLKIN_DOT96[P,N], CLKIN_SATA_[P,N] / CKSSCD_[P,N] VIH13/VIL13 Miscellaneous Signals: RTCRST# VIH14/VIL14 Power Management Signals: PWROK, RSMRST# System Management Signals: INTRUDER# Miscellaneous Signals: INTVRMEN, SRTCRST# VIH15/VIL15 Digital Display Control Signals: CRT_DDC_CLK, CRT_DDC_DATA SDVO_CTRLCLK, SDVO_CTRLDATA, DDPC_CTRLCLK, DDPC_CTRLDATA, DDPD_CTRLCLK, DDPD_CTRLDATA Mobile only: L_BKLTEN, L_BKLTCTL, L_DDC_CLK, L_DDC_DATA VIH_CL/VIL_CL Controller Link: CL_CLK1, CL_DATA1 VDI / VCM / VSE (5V Tolerant) USB Signals: USBP[13:0][P,N] (Low-speed and Full-speed) VHSSQ / VHSDSC / VHSCM (5V Tolerant) USB Signals: USBP[13:0][P,N] (in High-speed Mode) VIH_HDA / VIL_HDA Intel ® High Definition Audio Signals: HDA_SDIN[3:0] Strap Signals: HDA_SDOUT, HDA_SYNC (Strap purposes only) NOTE: Only applies when running in Low Voltage Mode (1.5 V) VIH_SST/VIL_SST Intel® Quiet System Technology and Thermal Reporting Signals: SST VIH_PECI/ VIL_PECI Intel® Quiet System Technology and Thermal Reporting Signals: PECI VIH_FDI/VIL_FDI Intel® Flexible Display Interface Signals: FDI_RX[P,N][7:0] VAUX-Diff-P-P Digital Display Port Aux Signal (Receiving Side): DDP[D:B]_AUX[P,N] VIH_XTAL25/ VIL_XTAL25
25 MHz Crystal Input: (Used in Display Clock Integration Mode)
XTAL25_IN Table 8-8. DC Characteri stic Input Signal Association (Sheet 2 of 2) Symbol Associated Signals
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Table 8-9. DC Input Charac teristics (Sheet 1 of 3) Symbol Parameter Min Max Unit Notes VIL1 Input Low Voltage –0.5 0.3(3.3V) V Note 10 VIH1 Input High Voltage 0.5 (3.3V) V5REF + 0.5 V Note 10 VIL2 Input Low Voltage — .8 V VIH2 Input High Voltage 2 — V VIL3 Input Low Voltage –0.5 0.8 V VIH3 Input High Voltage 2.0 3.3 V + 0.5 V Note 10 VIL4 Input Low Voltage –0.5 0.3(3.3 V) V Note 10 VIH4 Input High Voltage 0.5(3.3 V) 3.3 V + 0.5 V Note 10 VIL5 Input Low Voltage –0.5 0.8 V VIH5 Input High Voltage 2.1 3.3 V + 0.5 V Note 10 VIL6 Input Low Voltage -0.5 0.35 V Note 11 VIH6 Input High Voltage 0.75 1.05 V + 0.5 V Note 11 VIL7 Input Low Voltage 0 0.51(V_CPU_IO) V VIH7 Input High Voltage 0 .81(V_CPU_IO) V_CPU_IO V VIMIN8 Minimum Input Voltage 175 — mVdiff p-p Note 4 VIMAX8 Maximum Input Voltage — 1200 mVdiff p-p Note 4 VIL9 Input Low Voltage –0.5 0.10 V VIH9 Input High Voltage 0.50 1.2 V VIMIN10- Gen1i Minimum Input Voltage - 1.5 Gb/s internal SATA 325 — mVdiff p-p Note 5 VIMAX10- Gen1i Maximum Input Voltage - 1.5 Gb/s internal SATA —6 0 0 mVdiff p-p Note 5 VIMIN10- Gen1m Minimum Input Voltage - 1.5 Gb/s eSATA 240 — mVdiff p-p Note 5 VIMAX10- Gen1m Maximum Input Voltage - 1.5 Gb/s eSATA —6 0 0 mVdiff p-p Note 5 VIMIN10- Gen2i Minimum Input Voltage - 3.0 Gb/s internal SATA 275 — mVdiff p-p Note 5 VIMAX10- Gen2i Maximum Input Voltage - 3.0 Gb/s internal SATA —7 5 0 mVdiff p-p Note 5 VIMIN10- Gen2m Minimum Input Voltage - 3.0 Gb/s eSATA 240 — mVdiff p-p Note 5 VIMAX10- Gen2m Maximum Input Voltage - 3.0 Gb/s eSATA —7 5 0 mVdiff p-p Note 5 VIL11 Input Low Voltage –0.5 0.35(3.3 V) V Note 10
VIH11 Input High Voltage 0.65(3.3 V) 3.3 + 0.5V V Note 10 VIL12 (Absolute Minimum) Input Low Voltage -0.3 — V VIH12 (Absolute Maximum) Input High Voltage — 1.150 V VIL13 Input Low Voltage –0.5 0.78 V VIH13 Input High Voltage 2.3 VccRTC + 0.5 V Note 6 VIL14 Input Low Voltage –0.5 0.78 V VIH14 Input High Voltage 2.0 VccRTC + 0.5 V Note 6 VIL15 Input Low Voltage –0.5 0.3*(3.3 V) V Note 10 VIH15 Input High Voltage 0.7*(3.3 V) 3.3 V + 0.5 V Note 10 VIL_CL Input Low Voltage –0.3 (CL_VREF - 0.075) V Note 7 VIH_CL Input High Voltage (CL_VREF + 0.075) 1.2 V Note 7 Vclk_in_cros s(abs) Absolute Crossing Point 0.250 0.550 V VDI Differential Input Sensitivity 0.2 — V Note 1,3 VCM Differential Common Mode Range 0.8 2.5 V Note 2,3 VSE Single-Ended Receiver Threshold 0.8 2.0 V Note 3 VHSSQ HS Squelch Detection Threshold 100 150 mV Note 9 VHSDSC HS Disconnect Detection Threshold 525 625 mV Note 9 VHSCM HS Data Signaling Common Mode Voltage Range –50 500 mV Note 9 VIL_HDA Input Low Vo ltage 0 0.4(Vcc_HDA) V VIH_HDA Input High Voltage 0.6(Vcc_HDA) 1.5 V VIL_SST Input Low Voltage -0.3 0.4 V VIH_SST Input High Voltage 1.1 1.5 V VIL_PECI Input Low Voltage -0.15 0.275(V_CPU_IO) V VIH_PECI Input High Voltage 0.725(V_CPU_IO) V_CPU_IO + 0.15 V VIL_FDI Minimum Input Voltage 175 — mVdiff p-p VIH_FDI Maximum Input Voltage — 1000 mVdiff p-p Table 8-9. DC Input Charac teristics (Sheet 2 of 3) Symbol Parameter Min Max Unit Notes
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NOTES: 1. V DI = | USBPx[P] – USBPx[N]. 2. Includes VDI range. 3. Applies to Low-Speed/Full-Speed USB. 4. PCI Express mVdiff p-p = 2*|PETp[x] - PETn[x]|. 5. SATA Vdiff, RX (VIMAX10/MIN10) is measured at the SATA connector on the receiver side (generally, the motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]RXP – SATA[x]RXN|. 6. VccRTC is the voltage applied to the VccRTC we ll of the PCH. When the system is in a G3 state, this is generally supplied by the coin cell battery, but for S5 and greater, this is generally VccSus3_3. 7. CL_Vref = 0.27 (VccCL1_5). CL_VREF0 applies to Desktop configurations. CL_VREF1 applies to Mobile configurations. 8. This is an AC Characteristic that repr esents transient values for these signals. 9. Applies to High-Speed USB 2.0. 10. 3.3 V refers to VccSus3_3 for signals in the suspend well and to Vcc3_3 for signals in the core well and to VccME3_3 for signals in the ME well. See Table 3-2, or Table 3-3 for signal and power well association. 11. 1.1 V refers to VccIO or VccCore for signals in the core well and to VccME for signals in the ME well. See Table 3-2 or Table 3-3 for signal and power well association. 12. Specification applies when 25 MHz crystal is used on the platform. XTAL25_IN is terminated low when crystal input is not used. VAUX-Diff-P- P Digital Display Port Auxiliary Signal peak-to-peak voltage at receiving device 0.32 1.36 Vdiffp VIL_XTAL25 Minimum Input Voltage -0.15 0.15 V 12 VIH_XTAL25 Maximum Input Voltage 0.7 1.1 V 12 Table 8-9. DC Input Charac teristics (Sheet 3 of 3) Symbol Parameter Min Max Unit Notes Table 8-10. DC Characteristic Output Signal Association (Sheet 1 of 3) Symbol Associated Signals VOH1/VOL1 Processor Signal: PMSYNCH, PROCPWRGD VOH2/VOL2 LPC/Firmware Hub Signals: LAD[3:0]/FWH[3:0], LFRAME#/FWH[4], INIT3_3V# Power Management Signal: (Mobile Only) LAN_PHY_PWR_CTRL Intel® High Definition Audio Signals: HDA_DOCK_EN# (Mobile Only), HDA_DOCK_RST# (Mobile Only) PCI Signals: AD[31:0], C/BE[3:0], DEVSEL#, FRAME#, IRDY#, PAR, PCIRST#, GNT[3:0]#, PME#(1) Interrupt Signals: PIRQ[D:A], PIRQ[H:E]#(1) GPIO Signals: GPIO[73, 72, 59, 56, 55:50, 49, 47:44 43:40, 37, 36, 35, SPI Signals: SPI_CS0#, SPI_CS1#, SPI_MOSI, SPI_CLK Miscellaneous Signals: SPKR VOH3/VOL3 SMBus Signals: SMBCLK(1), SMBDATA(1) System Management Signals: SML[1:0]CLK(1), SML[1:0]DATA(1), SML0ALERT#, SML1ALERT# GPIO Signals: GPIO[75, 74, 60, 58, 11]
Power Management Signals: SLP_S3#, SLP_S4#, SLP_S5#, SLP_M#, SLP_LAN#, SUSCLK, SUS_STAT#, SUS_PWR_DN_ACK, CLKRUN# (Mobile Only) STP_PCI# SATA Signals: SATALED#, SCLOCK, SLOAD, SDATAOUT0, SDATAOUT1 GPIO Signals: GPIO[63:61, 57, 48, 39, 38, 34, 32, 31, 30, 29, 24, 22, 17, 7, 6, 1] Controller Link: CL_RST1# Interrupt Signals: SERIRQ VOH5/VOL5 USB Signals: USBP[13:0][P,N] in Low-speed and Full-speed Modes VOL6/VOL6 (Fast Mode) Digital Display Control Signals: CRT_DDC_CLK, CRT_DDC_DATA SDVO_CTRLCLK, SDVO_CTRLDATA, DDPC_CTRLCLK, DDPC_CTRLDATA, DDPD_CTRLCLK, DDPD_CTRLDATA Mobile only: L_CTRL_CLK, L_CTRL_DATA, L_VDD_EN, L_BKLTEN, L_BKLTCTL, L_DDC_CLK, L_DDC_DATA, NOTE: Fast Mode is not applicable to L_VDD_EN VOH6 L_VDD_EN, L_BKLTEN, L_BKLTCTL VOMIN7 - Gen1i,m/ VOMAX7-Gen1i,m SATA Signals: SATA[5:0]RX[P,N] (1.5 Gb/s Internal and External SATA) VOMIN7 - Gen2i,m/ VOMAX7-Gen2i,m SATA Signals: SATA[5:0]RX[P,N] (3.0 Gb/s Internal and External SATA) VOMIN8/VOMAX8 PCI Express* Data TX Signals: PET[p,n][8:1] Digital Display Ports when configured as HDMI/DVI: DDPB_[3:0][P,N], DDPC_[3:0][P,N], DDPD_[3:0][P,N] SDVO Signals: SDVO_INT[P,N], SDVO_TVCLKIN[P,N], SDVO_STALL[P,N] VOH9/VOL9 Power Management Signal: PLTRST# VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK USB Signals: USBP[13:0][P:N] in High-speed Mode VOH_HDA/ VOL_HDA Intel® High Definition Audio Signals: HDA_RST#, HDA_SDOUT, HDA_SYNC VOL_JTAG JTAG Signals: JTAG_TDO VOH_PCICLK/ VOL_PCICLK Single Ended Clock Interface Output Signals: CLKOUT_PCI[4:0], CLKOUTFLEX[3:0] GPIO Signals: [67:64] VOL_SGPIO SGPIO Signals: SCLOCK, SLOAD, SDATAOUT0, SDATAOUT1 GPIO[48, 39, 38, 22] VOH_PWM/ VOL_PWM Intel® Quiet System Technology Signals: PWM[3:0] Table 8-10. DC Characteri stic Output Signal Association (Sheet 2 of 3) Symbol Associated Signals
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NOTE: 1. These signals are open-drain. VOH_CRT/ VOL_CRT Display Signals: CRT_HSYNC, CRT_VSYNC VOH_CL1/ VOL_CL1 Controller Link Signals: Mobile Only: CL_CLK1, CL_DATA1 VOH_SST/ VOL_SST SST signal: SST VOH_PECI/ VOL_PECI PECI signal: PECI VAUX-Diff-P-P Digital Display Port Aux Signal (Transmit Side): DDP[D:B]_AUX[P,N] VOH_FDI// VOL_FDI Intel® FDI signals:FDI_FSYNC_[1:0],FDI_LSYNC_[1:0],FDI_INT Table 8-10. DC Characteristic Output Signal Association (Sheet 3 of 3) Symbol Associated Signals
Table 8-11. DC Output Charac teristics (Sheet 1 of 2) Symbol Parameter Min Max Unit I OL / IOH Notes VOL1 Output Low Voltage — 0.255 V 3 mA VOH1 Output High Voltage V_CPU_IO - 0.3 V_CPU_IO V -3 mA VOL2 Output Low Voltage — 0.1(3.3 V) V 1.5 mA Note 7 VOH2 Output High Voltage 0.9(3.3 V) 3.3 V -0.5 mA Note 7 VOL3 Output Low Voltage 0 0.4 V 4 mA VOH3 Output High Voltage 3.3 V - 0.5 — V -2 mA Note 1, 7 VOL4 Output Low Voltage — 0.4 V 6 mA VOH4 Output High Voltage 3.3 V- 0.5 3.3 V V -2 mA Note 7 VOL5 Output Low Voltage — 0.4 V 5 mA VOH5 Output High Voltage 3.3 V – 0.5 — V -2 mA Note 7 VOL6 Output Low Voltage 0 400 mV 3 mA Note 2 VOL6 (Fast Mode) Output Low Voltage 0 600 mV 6 mA Note 2 VOH6 Output High Voltage 3.3 V – 0.5 3.3 V -2 mA Note 7, 2 VOMIN7- Gen1i,m Minimum Output Voltage 400 — mVdif fp-p Note 3 VOMAX7- Gen1i,m Maximum Output Voltage —6 0 0 mVdif fp-p Note 3 VOMIN7- Gen2i,m Minimum Output Voltage 400 — mVdif fp-p Note 3 VOMAX7- Gen2i,m Maximum Output Voltage —7 0 0 mVdif fp-p Note 3 VOMIN8 Output Low Voltage 400 — mVdif fp-p Note 2 VOMAX8 Output High Voltage — 600 mVdif fp-p Note 2 VOL9 Output Low Voltage — 0.1(3.3 V) V 1.5 mA Note 7 VOH9 Output High Voltage 0.9(3.3 V) 3.3 V -2.0 mA Note 7 VHSOI HS Idle Level –10.0 10.0 mV VHSOH HS Data Signaling High 360 440 mV VHSOL HS Data Signaling Low –10.0 10.0 mV VCHIRPJ Chirp J Level 700 1100 mV VCHIRPK Chirp K Level –900 –500 mV VOL_HDA Output Low Voltage — 0.1(VccSusHDA V) V 1.5 mA VOH_HDA Output High Voltage 0.9(VccSusHDA V) — V -0.5 mA VOL_PWM Output Low Voltage — 0.4 V 8 mA VOH_PWM Output High Voltage — — Note 1 VOL_SGPIO Output Low Voltage — 0.4 V VOL_CRT Output Low Voltage — 0.5 V 8 mA VOH_CRT Output High Voltage 2.4 — V 8 mA VOL_CL1 Output Low Voltage — 0.15 V 1 mA
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NOTES: 1. The SERR#, PIRQ[H:A], SMBDATA, SM BCLK, SML[1:0]CLK, SML[1:0]DATA, SML[1:0]’ALERT# and PWM[3:0] signal has an open-drain driver and SATALED# has an open-collector driver, and the VOH / IOH specification does not apply. This signal must have external pull up resistor. 2. PCI Express mVdiff p-p = 2*|PETp[x] – PETn[x]|. 3. SATA Vdiff, tx (V OMIN7/VOMAX7) is measured at the SATA connector on the transmit side (generally, the motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]TXP – SATA[x]TXN|. 4. Maximum Iol for PROCPWRGD is 12mA for shor t durations (<500 mS per 1.5 s) and 9 mA for long durations. 5. For INIT3_3V only, for low current devices, the following applies: VOL5 Max is 0.15 V at an IOL5 of 2 mA. 6. 3.3 V refers to VccSus3_3 for signals in the suspend well, to Vcc3_3 for signals in the core well and to VccME3_3 for those signals in the ME well. See Table 3-2 or Table 3-3 for signal and power well association. 7. 3.3 V refers to VccSus3_3 for signals in the suspend well and to Vcc3_3 for signals in the core well and to VccME3_3 for signals in the ME well. See Table 3-2, or Table 3-3 for signal and power well association. VOH_CL1 Output High Voltage .61 .98 V VOL_SST Output Low Voltage 0 0.3 V 0.5 mA VOH_SST Output High Voltage 1.1 1.5 V -6 mA VOL_PECI Output Low Voltage — 0.25(V_CPU_IO) V 0.5 mA VOH_PECI Output High Voltage 0.75(V_CPU_IO) V_CPU_IO -6 mA VOL_HDA Output Low Voltage — 0.1(VccHDA) V 1.5 mA VOL_JTAG Output Low Voltage 0 0.1(1.05 V) V 1.5 mA V_CLKOUT_sw ing Differential Output Swing 300 — mV V_CLKOUT_cr oss Clock Cross-Over point 300 550 mV V_CLKOUTMIN Min output Voltage -0.3 — V V_CLKOUTMA X Max output Voltage 1.15 V V VOL_PCICLK Output Low Voltage — 0.4 V -1 mA VOH_PCICLK Output High Voltage 2.4 — V 1 mA VAUX-Diff-P-P Digital Display Port Auxiliary Signal peak-to-peak voltage at transmitting device 0.39 1.38 Vdiffp VOL_FDI Output Low Voltage -.1 0.2(3.3V) V 4.1 mA Note 7 VOH_FDI Output High Voltage .8(3.3V) 1.2 V 4.1 mA Note 7 Table 8-11. DC Output Charac teristics (Sheet 2 of 2) Symbol Parameter Min Max Unit I OL / IOH Notes
NOTES: 1. The I/O buffer supply voltage is measured at the PCH package pins. The tolerances shown in Table 8-12 are inclusive of all noise from DC up to 20 MHz. In testing, the voltage rails should be measured with a bandwidth limited oscilloscope that has a rolloff of 3 dB/decade above 20 MHz. 2. Includes Single Ended clocks REFC LK14IN, CLKOUTFLEX[3:0] and PCICLKIN. Table 8-12. Other DC Characteristics Symbol Parameter Min Nom Max Unit Notes V_CPU_IO Processor I/F .998 1.05 1.10 V 1 V_CPU_IO Processor I/F 1.05 1.1 1.16 V 1 V5REF PCH Core Well Reference Voltage 4.75 5 5.25 V 1 Vcc3_3 I/O Buffer Voltage 3.14 3.3 3.47 V 1 VccVRM 1.8 V Internal PLL and VRMs (1.8 V for Desktop and Mobile) 1.746 1.8 1.854 V 1,3 V5REF_Sus Suspend Well Reference Voltage 4.75 5 5.25 V 1 VccSus3_3 Suspend Well I/O Buffer Voltage 3.14 3.3 3.47 V 1 VccCore Internal Logic Voltage .998 1.05 1.10 V 1 VccIO Core Well I/O buffers .998 1.05 1.10 V 1 Vcc_DMI DMI Buffer Voltage .998 1.05 1.10 V VccLAN LAN Controller Voltage .998 1.05 1.10 V 1 VccME3_3 3.3V Supply for Intel® Management Engine 3.14 3.3 3.47 V 1 VccME 1.05 V Supply for Intel® Management Engine .998 1.05 1.10 V 1 VccRTC (G3-S0) Battery Voltage 2 — 3.47 V 1 VccSusHDA High Definition Audio Controller Suspend Voltage 3.14 3.3 3.47 V 1 VccSusHDA (low voltage) High Definition Audio Controller Low Voltage Mode Suspend Voltage 1.43 1.5 1.58 V 1 VccADPLLA Display PLL A power .998 1.05 1.10 1 VccADPLLB Display PLL B power .998 1.05 1.10 1 VccADAC Display DAC Analog Power. This power is supplied by the core well. 3.14 3.3 3.47 1 VccALVDS Analog power supply for LVDS (Mobile Only) 3.14 3.3 3.47 1 VccTX_LVDS I/O power supply for LV DS. (Mobile Only) 1.71 1.8 1.89 1 ILI1 PCI_3V Hi-Z State Data Line Leakage –10 — 10 µA (0 V < VIN < Vcc3_3) ILI2 PCI_5V Hi-Z State Data Line Leakage –70 — 70 µA Max VIN =
2.7 V Min
VIN = 0.5 V ILI3 Input Leakage Current – All Other –10 — 10 µA 2 CIN Input Capacitance – All Other — — TBD pF F C = 1 MHz COUT Output Capacitance — — TBD pF F C = 1 MHz CI/O I/O Capacitance — — 10 pF F C = 1 MHz Typical Value CL XTAL1 6 pF CL XTAL2 6 pF
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- Includes only DC tolerance. AC tolerance will be 2% and DC tolerance will be 3% in addition to this range.
8.5 Display DC Characteristics
NOTES: 1. Measured at each R, G, B termination accordin g to the VESA Test Procedure – Evaluation of Analog Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000). 2. Max steady-state amplitude. 3. Min steady-state amplitude. 4. Defined for a double 75- ohm termination. 5. Set by external refe rence resistor value. 6. INL and DNL measured and calculated acco rding to VESA video signal standards. 7. Max full-scale voltage difference among R,G, B outputs (percentage of steady-state full- scale voltage). Table 8-13. Signal Groups Signal Group Associ ated Signals Note LVDS LVDSA_DATA[3:0], LVDSA_DATA#[3:0], LVDSA_CLK, LVDSA_CLK#, LVDSB_DATA[3:0], LVDSB_DATA#[3:0], LVDSB_CLK, LVDSB_CLK# CRT DAC CRT_RED, CRT_GREEN, CRT_BLUE, CRT_IRTN, CRT_TVO_IREF Digital DisplayPort Auxillary DDP[D:B]_AUX[P,N] Table 8-14. CRT DAC Signal Group DC Char acteristics: Functional Operating Range (VccADAC = 3.3 V ±5%) Parameter Min Nom Max Unit Notes DAC Resolution —8— B i t s 1 Max Luminance (full-scale) 0.665 0.7 0.77 V 1, 2, 4 white video level voltage Min Luminance — 0 — V 1, 3, 4 black video level voltage LSB Current —7 3 . 2—u A 4 , 5 Integral Linearity (INL) -1 — 1 LSB 1, 6 Differential Linearity (DNL) -1 — 1 LSB 1, 6 Video channel-channel voltage ampli- tude mismatch ——6 % 7 Monotonicity Yes
Table 8-15. LVDS Interface: Functional Operating Range (VccALVDS = 3.3 V ±5%) Symbol Parameter Min Nom Max Unit VOD Differential Output Voltage 250 350 450 mV ΔVOD Change in VOD be tween Complementary Output States ——5 0 m V VOS Offset Voltage 1.125 1.25 1.375 V ΔVOS Change in VOS between Complementary Output States ——5 0 m V IOs Output Short Circuit Current —- 3 . 5- 1 0 m A IOZ Output TRI-STATE Current —± 1 ± 1 0 u A Table 8-16. Display Port Auxiliary Signal Group DC Characteristics Symbol Parameter Min Nom Max Unit Vaux-diff-p-p Aux peak-to-peak voltage at a transmitting devices 0.39 — 1.38 V Aux peak-to-peak voltage at a receiving devices 0.32 — 1.36 V Vaux-term-R AUX CH termination DC resistance —1 0 0 — Ω V-aux-dc-cm AUX DC common mode voltage 0— 2 V V-aux_turn- CM Aux turn around common mode voltage —0 . 4 V
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8.6 AC Characteristics
NOTES: 1. Specified at the measurement point into a ti ming and voltage compliance test load and measured over any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye diagram). 2. A T TX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTXJITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 3. Specified at the measurement point and measured over any 250 consecutive UIs. The test load documented in the PCI Express* specification 2.0 should be used as the RX device when taking measurements (also refer to the Receiver compliance eye diagram). If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. 4. A T RX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and interconnect collected any 250 consecutive UIs. The TRX- EYE-MEDIAN-to--MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total 0.6 UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. 5. Nominal Unit Interval is 400 ps for 2.5 GT/s and 200 ps for 5 GT/s. Table 8-17. PCI Express* Interface Timings Symbol Parameter Min Ma x Unit Figures Notes Transmitter and Receiver Timings UI Unit Interval – PCI Express* 399.88 400.12 ps 5 TTX-EYE Minimum Transmission Eye Width 0.7 — UI 8-26 1,2 TTX-RISE/ Fall D+/D- TX Out put Rise/Fall time — 0.125 UI 1,2 TRX-EYE Minimum Receiver Eye Width 0.40 — UI 8-27 3,4
NOTES: 1. Specified at the measurement point into a ti ming and voltage compliance test load and measured over any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye diagram). 2. A T TX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTXJITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. NOTES: 1. Specified at the measurement point into a ti ming and voltage compliance test load and measured over any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye diagram). 2. A T TX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTXJITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 3. Specified at the measurement point and measured over any 250 consecutive UIs. The test load documented in the PCI Express* specification 2.0 should be used as the RX device Table 8-18. HDMI Interface Timings (DDP[D:B][3:0]) Symbol Parameter Min Max Unit Figures Notes Transmitter and Receiver Timings UI Unit Interval 600 4000 ps TTX-EYE Minimum Transmission Eye Width 0.8 — UI 1,2 TTX-RISE/Fall D+/D- TX Out put Rise/Fall time — 0.125 UI 1,2 TMDS Clock Jitter —0 . 2 5 U I T-skew- intra-pair Intra pair skew at source connector —0 . 1 5 T BIT T-skew- inter-pair Inter pair skew at source connector —0 . 2 Tchar acter Duty Cycle Clock Duty Cycle 10 60% % Table 8-19. SDVO Interface Timings Symbol Parameter Min Max Unit Figures Notes Transmitter and Receiver Timings UI Unit Interval 369.89 1000 ps 5 TTX-EYE Minimum Transmission Eye Width 0.7 — UI 8-26 1,2 TTX-RISE/ Fall D+/D- TX Out put Rise/Fall time —0 . 1 2 5 U I 1 , 2 TRX-EYE Minimum Receiver Eye Width 0.40 — UI 8-27 3,4
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when taking measurements (also refer to the Receiver compliance eye diagram). If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. 4. A T RX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and interconnect collected any 250 consecutive UIs. The TRX- EYE-MEDIAN-to--MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total 0.6 UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. 5. Nominal Unit Interval for highest SDVO sp eed is 370 ps. However, depending on the resolution on the interface, the UI may be more than 370 ps. Table 8-20. DisplayPort Interf ace Timings (DDP[D:B][3:0]) Symbol Parameter Min Nom Max Unit UI_High_Rate Unit Interval for High Bit Rate (2.7 Gbps/lane) 370 — ps UI_Low_Rate Unit Interval for Reduced Bit Rate (1.62 Gbps/lane) 617 — ps Down_Spread_ Amplitude Link clock down spreading 0 — 0.5 % Down_Spread_ Frequency Link clock down-spreading frequency 30 — 33 kHz Ltx-skew- intrapair Lane Intra-pair output skew at Tx package pins —2 0 p s Ttx-rise/ fall_mismatch_ chipdiff Lane Intra-pair Rise/Fall time mismatch at Tx package pin 5% — VTX-DIFFp-p-level1 Differential Peak-to-peak Output Voltage level 1 0.34 0.4 0.46 V VTX-DIFFp-p-level2 Differential Peak-to-peak Output Voltage level 2 0.51 0.6 0.68 V VTX-DIFFp-p-level3 Differential Peak-to-peak Output Voltage level 3 0.69 0.8 0.92 V VTX-preemp_ratio No Pre-emphasis 0 0 0 dB VTX-preemp_ratio 3.5 dB Pre-emphasis Level 2.8 3.5 4.2 dB VTX-preemp_ratio 6.0 dB Pre-emphasis Level 4.8 6 7.2 dB LTX-SKEW- INTER_PAIR Lane-to-Lane Output Skew at Tx package pins ——2 U I
NOTES: 1. Measurement Point for Rise and Fall time: V IL(min)–VIL(max). 2. Cb = total capacitance of one bus line in pF. If mixed with High-speed mode devices, faster fall times according to High-Speed mode Tr/Tf are allowed. Table 8-21. DisplayPort Aux Interface Symbol Parameter Min Nom Max Unit UI Aux unit interval 0.4 0.5 0.6 us Aux_bus_park AUX CH bus park time 10 — — ns Tcycle-to-cycle jitter maximum allowable UI variation within a single transaction at the connector pins of a transmitting device
0.04 UI —
maximum allowable UI variation within a single transaction at the connector pins of a receiving device
0.05 UI —
Table 8-22. DDC Characteristics DDC Signals: CRT_DDC_CLK, CRT_DDC_DATA, L_DDC_CLK, L_DDC_DATA, SDVO_CTRLCLK, SDVO_CTRLDATA, DDP[D:C]_CTRLCLK, DDP[D:C]_CTRLDATA Symbol Parameter Standard Mode Fast Mode 1 MHz Units Max Min Max Min Max Fscl Operating Frequency 100 — 400 — 1000 kHz Tr Rise Time1 —— — — n s Tf Fall Time1 250 20+0.1Cb 2 250 — 120 ns
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Table 8-23. LVDS Interface AC characterist ics at Various Frequencies (Sheet 1 of 2) Symbol Parameter Min Nom Max Unit Figures Notes LLHT LVDS Low-to-High Transition Time 0.25 0.5 0.75 ns Figure 8-24 1, Across receiver termination LHLT LVDS High-to-Low Transition Time 0.25 0.5 0.75 ns 1, Across receiver termination Frequency = 40-MHz TPPos0 Transmitter Output Pulse for Bit 0 -0.25 0 0.25 ns Figure 8-25 TPPos1 Transmitter Output Pulse for Bit 1 3.32 3.57 3.82 ns TPPos2 Transmitter Output Pulse for Bit 2 6.89 7.14 7.39 ns TPPos3 Transmitter Output Pulse for Bit 3 10.46 10.71 10.96 ns TPPos4 Transmitter Output Pulse for Bit 4 14.04 14.29 14.54 ns TPPos5 Transmitter Output Pulse for Bit 5 17.61 17.86 18.11 ns TPPos6 Transmitter Output Pulse for Bit 6 21.18 21.43 21.68 ns TJCC Transmitter Jitter Cycle-to-Cycle — 350 370 ps Frequency = 65-MHz TPPos0 Transmitter Output Pulse for Bit 0 -0.20 0 0.20 ns Figure 8-25 TPPos1 Transmitter Output Pulse for Bit 1 2.00 2.20 2.40 ns TPPos2 Transmitter Output Pulse for Bit 2 4.20 4.40 4.60 ns TPPos3 Transmitter Output Pulse for Bit 3 6.39 6.59 6.79 ns TPPos4 Transmitter Output Pulse for Bit 4 8.59 8.79 8.99 ns TPPos5 Transmitter Output Pulse for Bit 5 10.79 10.99 11.19 ns TPPos6 Transmitter Output Pulse for Bit 6 12.99 13.19 13.39 ns TJCC Transmitter Jitter Cycle-to-Cycle — — 250 ps
348 Datasheet
NOTES: 1. Measured at each R, G, B terminat ion according to the VESA Test Procedure – Evaluation of Analog Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000). 2. R, G, B Max Video Rise/Fall Time: 50% of minimum pixel clock period. 3. R, G, B Min Video Rise/Fall Time: 10% of minimum pixel clock period. 4. Max settling time: 30% of minimum pixel clock period. 5. Video channel-channel output skew: 25% of minimum pixel clock period. 6. Overshoot/undershoot: ±12% of black-whit e video level (full-scale) step function. 7. Noise injection ratio: 2.5% of maximum lu minance voltage (dc to max. pixel frequency). 8. R, G, B AC parameters are strongly dependent on the board implementation. Table 8-24. CRT DAC AC Characteristics Parameter Min Nom Max Units Notes Pixel Clock Frequency 400 MHz R, G, B Video Rise Time 0.25 — 1.25 ns 1, 2, 8 (10-90% of black-to-white transition, @ 400-MHz pixel clock) R, G, B Video Fall Time 0.25 — 1.25 ns 1, 3, 8 (90-10% of white-to-black transition, @ 400-MHz pixel clock) Settling Time 0.75 ns 1, 4, 8 @ 400-MHz pixel clock Video channel-to-channel output skew 0.625 ns 1, 5, 8 @ 400-MHz pixel clock Overshoot/ Undershoot -0.084 — +0.084 V 1, 6, 8 Full-scale voltage step of 0.7 V Noise Injection Ratio 2.5 % 1, 7, 8 Table 8-25. Clock Timings (Sheet 1 of 3) Sym Parameter Min Max Unit Notes Figure PCI Clock (CLKOUT_PCI[4:0]) t1 Period 29.566 30.584 ns 8-9 t2 High Time 10.826 17.850 ns 8-9 t3 Low Time 10.426 17.651 ns 8-9 Duty Cycle 40 60 % t4 Rising Edge Rate 1.0 4 V/ns 8-9 t5 Falling Edge Rate 1.0 4 V/ns 8-9 Jitter — 500 ps 7,9
14 MHz Flex Clock (CLKOUTFLEX[3:0])
t6 Period 69.820 69.862 ns 8-9 t7 High Time 29.975 38.467 ns 8-9 t8 Low Time 29.575 38.267 ns 8-9 Duty Cycle 40 60 % - Rising Edge Rate 1.0 4 V/ns 5 - Falling Edge Rate 1.0 4 V/ns 5 Jitter — 1000 ps 7,9
48 MHz Flex Clock (CLKOUTFLEX3)
t9 Period 20.831 20.835 ns 18 - 9 t10 High Time 8.217 11.152 ns 8-9
t11 Low Time 7.817 10.952 ns 8-9 Duty Cycle 40 60 % - Rising Edge Rate 1.0 4 V/ns 5 -F a l l i n g E d g e R a t e 1 . 0 4 V / n s 5 Jitter — 350 ps 7,9 CLKOUT_BCLK[1:0]_[P,N] Period Period SSC On 7.349 7.688 ns 8-28 Period Period SSC Off 7.349 7.651 ns 8-28 DtyCyc Duty Cycle 40 60 % 8-28 V_Swing Differential Output Swing 300 mV 8-28 Slew_rise Rising Edge Rate 1.5 4 V/ns 8-28 Slew_fall Falling Edge Rate 1.5 4 V/ns 8-28 Jitter (CLKOUT_BCLK[0]_P:N]) — 150 ps 7,9 Jitter (CLKOUT_BCLK[1]_P:N]) — 350 ps 7,9 BCLK Input (CLKIN_BCLK_[P:N]) Period Period SSC on 7.349 7.688 ns 8-28 Period Period SSC Off 7.349 7.651 ns 8-28 Slew Rate 1 8 V/ns 7 Input Jitter (see Clock Chip Specification) -1 5 0 p s 8 CLKOUT_DP_[P,N] Period Period SSC On 7.983 8.726 ns 8-28 Period Period SSC Off 7.983 8.684 ns 8-28 DtyCyc Duty Cycle 40 60 % 8-28 V_Swing Differential Output Swing 300 — mV 8-28 Slew_rise Rising Edge Rate 1.5 4 V/ns 8-28 Slew_fall Falling Edge Rate 1.5 4 V/ns 8-28 Jitter 350 ps 7,9 CLKOUT_PCIE[7:0], CLKOUT_DMI_[P,N], CLKOUT_PEG_[B:A]_[P,N] Period Period SSC On 9.849 10.201 ns 8-28 Period Period SSC Off 9.849 10.151 ns 8-28 DtyCyc Duty Cycle 40 60 % 8-28 V_Swing Differential Output Swing 300 — mV 8-28 Slew_rise Rising Edge Rate 1.5 4 V/ns 8-28 Slew_fall Falling Edge Rate 1.5 4 V/ns 8-28 Jitter — 150 ps 7,9,10 SMBus/SMLink Clock (SMBCLK, SML[1:0]CLK) fsmb Operating Frequency 10 100 KHz t18 High time 4.0 50 μs 28 - 1 8 t19 Low time 4.7 — μs 8-18 Table 8-25. Clock Timings (Sheet 2 of 3) Sym Parameter Min Max Unit Notes Figure
350 Datasheet
t20 Rise time — 1000 ns 8-18 t21 Fall time — 300 ns 8-18 SMLink0 Clock (SML0CLK) (See note 13) fsmb Operating Frequency 0 400 KHz t18_SML High time 0.6 50 μs2 8-18 t19_SML Low time 1.3 — μs 8-18 t20_SML Rise time — 300 ns 8-18 t21_SML Fall time — 300 ns 8-18 HDA_BCLK (Intel® High Definition Audio) fHDA Operating Frequency 24.0 MHz Frequency Tolerance — 100 ppm t26a Input Jitter (see Clock Chip Specification) — 300 ppm t27a High Time (Measured at 0.75 Vcc) 18.75 22.91 ns 8-9 t28a Low Time (Measured at 0.35 Vcc) 18.75 22.91 ns 8-9 SATA Clock and DMI Clock (CLKIN_SATA_[P:N], CLKIN_DMI_[P:N]) from a clock chip t36 Period 9.997 10.0533 ns Slew rate 1 8 V/ns Input Jitter (see Clock Chip Specification) — 150 ps 7 DOT 96MHz (CLKIN_DOT96[P,N]) from a clock chip t36 Period 10.066 10.768 ns Slew rate 1 8 V/ns Input Jitter (see Clock Chip Specification) — 350 ps 7 Suspend Clock (SUSCLK) fsusclk Operating Frequency 32 kHz 4 t39 High Time 10 — μs 4 t39a Low Time 10 — μs 4 Intel ® Quiet System Technology fpwm PWM Operating Frequency 10 28,000 Hz SPI_CLK Slew_Rise Output Rise Slew Rate (0.2Vcc - 0.6Vcc) 14 V / n s 7 8-29 Slew_Fall Output Fall Slew Rate (0.6Vcc - 0.2Vcc) 14 V / n s 7 8-29 XTAL25_IN/XTAL25_OUT ppm Crystal Tolerance Cut Accuracy Max 35 ppm (@ 25 °C ±3 °C) ppm Temperature Stability Max 30 ppm @ (-10 °C to 70 °C) ppm Aging Max 5 ppm Table 8-25. Clock Timings (Sheet 3 of 3) Sym Parameter Min Max Unit Notes Figure
NOTES: 1. The CLK48 expects a 40/60% duty cycle. 2. The maximum high time (t18 Max) provide a simple ensured method for devices to detect bus idle conditions. 3. BCLK Rise and Fall times are measured from 10%VDD and 90%VDD. 4. SUSCLK duty cycle can range from 30% minimum to 70% maximum. 5. Edge rates in a system as measured from 0.8 V to 2.0 V. 6. The active frequency can be 5 MHz, 50 MH z, or 62.5 MHz depending on the interface speed. Dynamic changes of the normal operating frequency are not allowed. 7. Testing condition: 1 KOhm pull up to Vcc, 1 KOhm pull down and 10 pF pull down and 1/2 inch trace (see Figure 8-29 for more detail). 8. Jitter is specified as cycle to cycle measured in pico seconds. Period min and max includes cycle to cycle jitter. 9. On all jitter measurements care should be taken to set the zero crossing voltage (for rising edge) of the clock to be the point where the edge rate is the fastest. Using a Math function = Average(Derivavitive(Ch1)) and set the averages to 64, place the cursors where the slope is the highest on the rising edge—usual ly this lower half of the rising edge. The reason this is defined is for users trying to measure in a system it is impossible to get the probe exactly at the end of the Transmission line with large Flip Chip components, this results in a reflection induced ledge in the middle of the rising edge and will significantly increase measured jitter. 10. Phase jitter requirement: The designated Gen2 outputs will meet the reference clock jitter requirements from the PCI Express Gen2 Base Specification. The test is to be performed on a component test board under quiet conditions with all clock outputs on. Jitter analysis is performed using a standardized tool provided by the PCI SIG. Measurement methodology is defined in Intel document “PCI Express Reference Clock Jitter Measurements”. Note that this is not for CLKOUT_PCIE[7:0]. 11. Crystal Specifications provided are guidelines and applies when a 25 MHz crystal is used on the platform. Total of crystal cut accuracy, temperature stability, frequency variations due to parasitics and load capacitances and aging is recommended to be less than 90 ppm. 12. When SMLink0 is configured to run in Fast Mode using a soft strap, the operating frequency is in the range of 300 KHz – 400 KHz.
352 Datasheet
NOTE: PCI Local Bus Specification, Revision 2.3 for measurement details. Table 8-26. PCI Interface Timing Sym Parameter Min Max Units Notes Figure t40 AD[31:0] Valid Delay 2 11 ns 1 8-10 t41 AD[31:0] Setup Time to PCICLK Rising 7 — ns 8-11 t42 AD[31:0] Hold Time from PCICLK Rising 0 — ns 8-11 t43 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR, PERR#, PLOCK#, DEVSEL# Valid Delay from PCICLK Rising 21 1n s 1 8-10 t44 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PAR, PERR#, PLOCK#, IDSEL, DEVSEL# Output Enable Delay from PCICLK Rising 2n s 8-14 t45 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, PERR#, PLOCK#, DEVSEL#, GNT[A:B]# Float Delay from PCICLK Rising 22 8n s 8-12 t46 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, PERR#, DEVSEL#, Setup Time to PCICLK Rising 7n s 8-11 t47 C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#, SERR#, PERR#, DEVSEL#, REQ[A:B]# Hold Time from PCLKIN Rising 0—n s 8-11 t48 PCIRST# Low Pulse Width 1 ms 8-13 t49 GNT[3:0]# Valid Delay from PCICLK Rising 21 2n s t50 REQ[3:0]# Setup Time to PCICLK Rising 12 — ns
NOTES: 1. Driver output resistance under steady state drive is specified at 28 ohms at minimum and 43 ohms at maximum. 2. Timing difference between th e differential data signals. 3. Measured at crossover point of differential data signals. 4. Measured at 50% swing point of data signals. 5. Measured from last crossover point to 50% swin g point of data line at leading edge of EOP. 6. Measured from 10% to 90% of the data signal. 7. Full-speed Data Rate has minimum of 11.97 Mb/s and maximum of 12.03 Mb/s. 8. Low-speed Data Rate has a minimum of 1.48 Mb/s and a maximum of 1.52 Mb/s. Table 8-27. Universal Serial Bus Timing Sym Parameter Min Max Units Notes Fig Full-speed Source (Note 7) t100 USBPx+, USBPx- Driver Rise Time 4 20 ns 1, CL = 50 pF 8-15 t101 USBPx+, USBPx- Driver Fall Time 4 20 ns 1, CL = 50 pF 8-15 t102 Source Differential Driver Jitter - To Next Transition - For Paired Transitions –3.5 3.5 ns ns 2, 3 8-16 t103 Source SE0 interval of EOP 160 175 ns 4 8-17 t104 Source Jitter for Differential Transition to SE0 Transition –2 5 ns 5 t105 Receiver Data Jitter Tolerance - T o Next Transition - For Paired Transitions –18.5 18.5 ns ns 3 8-16 t106 EOP Width: Must accept as EOP 82 — ns 4 8-17 t107 Width of SE0 interval during differential transition —1 4 n s Low-speed Source (Note 8) t108 USBPx+, USBPx – Driver Rise Time 75 300 ns 1, 6 CL = 50 pF CL = 350 pF 8-15 t109 USBPx+, USBPx – Driver Fall Time 75 300 ns 1,6 CL = 50 pF CL = 350 pF 8-15 t110 Source Differential Driver Jitter To Next Transition For Paired Transitions –25 –14 ns ns 2, 3 8-16 t111 Source SE0 interval of EOP 1.25 1.50 µs 4 8-17 t112 Source Jitter for Differential Transition to SE0 Transition –40 100 ns 5 t113 Receiver Data Jitter Tolerance - To Next Transition - For Paired Transitions –152 –200 152 200 ns ns 3 8-16 t114 EOP Width: Must accept as EOP 670 — ns 4 8-17 t115 Width of SE0 interval during differential transition — 210 ns
354 Datasheet
NOTES: 1. 20% – 80% at transmitter. 2. 80% – 20% at transmitter. 3. As measured from 100 mV differential cros spoints of last and first edges of burst. 4. Operating data period during Out-Of-Band burst transmissions. Table 8-28. SATA Interface Timings Sym Parameter Min Max Units Notes Figure UI Gen I Operating Data Period 666.43 670.23 ps UI-2 Gen II Operating Data Period (3Gb/ s) 333.21 335.11 ps t120 Rise Time 0.15 0.41 UI 1 t121 Fall Time 0.15 0.41 UI 2 t122 TX differential skew — 20 ps t123 COMRESET 310.4 329.6 ns 3 t124 COMWAKE transmit spacing 103.5 109.9 ns 3 t125 OOB Operating Data period 646.67 686.67 ns 4 Table 8-29. SMBus Timing (Sheet 1 of 2) Sym Parameter Min Max Units Notes Fig t130 Bus Free Time Between Stop and Start Condition 4.7 — µs 8-18 t130SM LFM Bus Free Time Between Stop and Start Condition 1.3 — µs 5 8-18 t131 Hold Time after (repeated) Start Condition. After this period, the first clock is generated. 4.0 — µs 8-18 t131SM LFM Hold Time after (repeated) Start Condition. After this period, the first clock is generated. 0.6 — µs 5 8-18 t132 Repeated Start Condition Setup Time 4.7 — µs 8-18 t132SM LFM Repeated Start Condition Setup Time 0.6 — µs 5 8-18 t133 Stop Condition Setup Time 4.0 — µs 8-18 t133SM LFM Stop Condition Setup Time 0.6 — µs 5 8-18 t134 Data Hold Time 0 — ns 4 8-18 t134SM LFM Data Hold Time 0 — ns 4, 5 8-18 t135 Data Setup Time 250 — ns 8-18 t135SM LFM Data Setup Time 100 — ns 5 8-18 t136 Device Time Out 25 35 ms 1 t137 Cumulative Clock Low Extend Time (slave device) —2 5 m s 2 8-19
NOTES: 1. A device will timeout when an y clock low exceeds this value. 2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to stop. If a slave device exceeds this time, it is expected to release both its clock and data lines and reset itself. 3. t138 is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack or ack-to-stop. 4. t134 has a minimum timing for I 2C of 0 ns, while the minimum timing for SMBus is 300 ns. 5. Timings with the SMLFM designator apply on ly to SMLink0 and only when SMLink0 is operating in Fast Mode. t138 Cumulative Clock Low Extend Time (master device) —1 0 m s 3 8-19 Table 8-29. SMBus Timing (Sheet 2 of 2) Sym Parameter Min Max Units Notes Fig Table 8-30. Intel ® High Definition Audio Timing Sym Parameter Min Max Units Notes Fig t143 Time duration for which HDA_SD is valid before HDA_BCLK edge. 7—n s 8-21 t144 Time duration for which HDA_SDOUT is valid after HDA_BCLK edge. 7—n s 8-21 t145 Setup time for HDA_SDIN[3:0] at rising edge of HDA_BCLK 15 — ns 8-21 t146 Hold time for HDA_SDIN[3:0] at rising edge of HDA_BCLK 0—n s 8-21 Table 8-31. LPC Timing Sym Parameter Min Max Units Notes Fig t150 LAD[3:0] Valid Delay from PCICLK Rising 2 11 ns 8-10 t151 LAD[3:0] Output Enable Delay from PCICLK Rising 2—n s 8-14 t152 LAD[3:0] Float Delay from PCICLK Rising — 28 ns 8-12 t153 LAD[3:0] Setup Time to PCICLK Rising 7 — ns 8-11 t154 LAD[3:0] Hold Time from PCICLK Rising 0 — ns 8-11 t155 LDRQ[1:0]# Setup Time to PCICLK Rising 12 — ns 8-11 t156 LDRQ[1:0]# Hold Time from PCICLK Rising 0 — ns 8-11 t157 eE# Valid Delay from PCICLK Rising 2 12 ns 8-10
356 Datasheet
NOTES: 1. The typical clock frequency driven by the PCH is 17.86 MHz. 2. Measurement point for low time and hi gh time is taken at 0.5(VccME3_3). Table 8-32. Miscellaneous Timings Sym Parameter Min Max Units Notes Fig t160 SERIRQ Setup Time to PCICLK Rising 7 — ns 8-11 t161 SERIRQ Hold Time from PCICLK Rising 0 — ns 8-11 t162 RI#, EXTSMI#, GPIO, USB Resume Pulse Width 2 — RTCCLK 8-13 t163 SPKR Valid Delay from OSC Rising — 200 ns 8-10 t164 SERR# Active to NMI Active — 200 ns t165 IGNNE# Inactive from FERR# Inactive — 230 ns Table 8-33. SPI Timings (20 MHz) Sym Parameter Min Max Units Notes Fig t180a Serial Clock Frequency - 20M Hz Operation 17.06 18.73 MHz 1 t183a Tco of SPI_MOSI with respect to serial clock falling edge at the host -5 13 ns 8-20 t184a Setup of SPI_MISO with respect to serial clock falling edge at the host 16 — ns 8-20 t185a Hold of SPI_MISO with respect to serial clock falling edge at the host 0— n s 8-20 t186a Setup of SPI_CS[1:0]# assertion with respect to serial clock rising at the host 30 — ns 8-20 t187a Hold of SPI_CS[1:0]# de-assertion with respect to serial clock falling at the host 30 — ns 8-20 t188a SPI_CLK high time 26.37 — ns 8-20 t189a SPI_CLK low time 26.82 — ns 8-20
NOTES: 1. The typical clock frequency dr iven by the PCH is 31.25 MHz. 2. Measurement point for low time and high time is taken at 0.5(VccME3_3). NOTES: 1. Typical clock frequency driven by the PCH is 50 MHz. This frequency is not available for ES1 samples. 2. When using 50 MHz mode ensure target flash component can meet t188c and t189c specifications. 3. Measurement point for low time and high time is taken at 0.5(VccME3_3). Table 8-34. SPI Timings (33 MHz) Sym Parameter Min Max Units Notes Fig t180b Serial Clock Frequency - 33 MHz Operation 29.83 32.81 MHz 1 t183b Tco of SPI_MOSI with respect to serial clock falling edge at the host -5 5 ns 8-20 t184b Setup of SPI_MISO with respect to serial clock falling edge at the host 8— n s 8-20 t185b Hold of SPI_MISO with respect to serial clock falling edge at the host 0— n s 8-20 t186b Setup of SPI_CS[1:0]# assertion with respect to serial clock rising at the host 30 — ns 8-20 t187b Hold of SPI_CS[1:0]# de-assertion with respect to serial clock falling at the host 30 — ns 8-20 t188b SPI_CLK High time 14.88 - ns 8-20 t189b SPI_CLK Low time 15.18 - ns 8-20 Table 8-35. SPI Timings (50 MHz) Sym Parameter Min Max Units Notes Fig t180c Serial Clock Frequency - 50MHz Operation 46.99 53.40 MHz 1 t183c Tco of SPI_MOSI with respect to serial clock falling edge at the host -3 3 ns 8-20 t184c Setup of SPI_MISO with respect to serial clock falling edge at the host 8— n s 8-20 t185c Hold of SPI_MISO with respect to serial clock falling edge at the host 0— n s 8-20 t186c Setup of SPI_CS[1:0]# assertion with respect to serial clock rising edge at the host 30 — ns 8-20 t187c Hold of SPI_CS[1:0]# assertion with respect to serial clock rising edge at the host 30 — ns 8-20 t188c SPI_CLK High time 7.1 — ns 2, 3 8-20 t189c SPI_CLK Low time 11.17 — ns 2, 3 8-20
358 Datasheet
NOTES: 1. The originator must drive a mo re restrictive time to allow for quantized sampling errors by a client yet still attain the minimum time less than 500 µs. tBIT limits apply equally to tBIT- A and tBIT-M. PCH is targeted on 1 Mbps which is 1 µs bit time. 2. The minimum and maximum bit times are relative to t BIT defined in the Timing Negotiation pulse. 3. t BIT-A is the negotiated address bit time and tBIT-M is the negotiated message bit time. Table 8-36. SST Timings Sym Parameter Min Max Units Notes Fig tBIT Bit time (overall time evident on SST) Bit time driven by an originator 0.495 0.495 500 250 µs µs 1- tBIT,jitter Bit time jitter between adjacent bits in an SST message header or data bytes after timing has been negotiated ——% t BIT,drift Change in bit time across a SST address or SST message bits as driven by the originator. This limit only applies across tBIT-A bit drift and tBIT-M drift. ——% tH1 High level time for logic '1' 0.6 0.8 x t BIT 2 tH0 High level time for logic '0' 0.2 0.4 x t BIT tSSTR Rise time (measured from VOL = 0.3 V to VIH,min) —2 5 + 5 ns/ node tSSTF Fall time (measured from VOH = 1.1 V to VIL,max) —3 3 ns/ node
NOTES: 1. The originator must drive a mo re restrictive time to allow for quantized sampling errors by a client yet still attain the minimum time less than 500 µs. tBIT limits apply equally to tBIT-A and tBIT-M. PCH is targeted on 2 MHz which is 500 ns bit time. 2. The minimum and maximum bit times are relative to t BIT defined in the Timing Negotiation pulse. 3. Extended trace lengths may appear as additional nodes. 4. t BIT-A is the negotiated address bit time and tBIT-M is the negotiated message bit time. NOTES: 1. Measured from (CL_Vref – 50 mV to CL_Vre f + 50 mV) at the receiving device side. No test load is required for this measurement as the receiving device fulfills this purpose. 2. CL_Vref = 0.12*(VccSus3_3). Table 8-37. PECI Timings Sym Parameter Min Max Units Notes Fig tBIT Bit time (overall time evident on PECI) Bit time driven by an originator 0.495 0.495 500 250 µs µs 1 tBIT,jitter Bit time jitter between adjacent bits in an PECI message header or data bytes after timing has been negotiated —— % tBIT,drift Change in bit time across a PECI address or PECI message bits as driven by the originator. This limit only applies across tBIT-A bit drift and tBIT-M drift. —— % tH1 High level time for logic '1' 0.6 0.8 x t BIT 2 tH0 High level time for logic '0' 0.2 0.4 x t BIT tPECIR Rise time (measured from VOL to VIH,min, Vtt(nom) -5%) — 30 + 5 ns/ node 3 tPECIF Fall time (measured from VOH to VIL,max, Vtt(nom) +5%) —3 0 ns/ node 3 Table 8-38. Controller Link Receive Timings Sym Parameter Min Max Units Notes Fig t190 Single bit time 13 — ns 8-30 t191 Single clock period 15 — ns 8-30 t192 Rise time/Fall time 0.11 3.5 V/ns 1 8-31 t193 Setup time before CL_CLK1 0.9 — ns 8-30 t194 Hold time after CL_CLK1 0.9 — ns 8-30 VIL_AC Input low voltage (AC) — CL_Vref – 0.08 V2 VIH_AC Input high voltage (AC) CL_Vref +0.08 —V 2
360 Datasheet
8.7 Power Sequencing an d Reset Signal Timings
Table 8-39. Power Sequencing and Reset Signal Timings (Sheet 1 of 3) Sym Parameter Min Max Units Notes Fig t200 VccRTC active to RTCRST# inactive 9 — ms 8-1 t201 VccSUS active to RSMRST# inactive 10 — ms 1 8-1 t202 RSMRST# inactive to SUSCLK toggling 97 — ms 2 8-1 t203 SLP_S5# high to SLP_S4# high 30 us 3 8-2 t204 SLP_S4# high to SLP_S3# high 30 us 4 8-2 t205 Vcc active to PWROK high 10 — ms 5 8-2, 8-3 t206 PWROK deglitch time 1 — ms 6 8-2, 8-3 t207 VccLAN & VccME stable to MEPWROK high 1— m s 8-2, 8-4 t208 Clock chip clock ou tputs to PWROK high 1 — ms 8-2, 8-3 t209 PWROK active to PROCPWRGD active See Note 7 —m s 7 8-2, 8-3 t210 PROCPWRGD high to SUS_STAT# high 1 — ms 8-2, 8-3 t211 SUS_STAT# high to PLTRST# high 60 — us 8-2, 8-3 t212 LAN_RST# de-assertion or MEPWROK assertion (whichever comes first) to SPI message 500 — us 18 8-4 t213 MEPWROK asserted to CL_RST1# de- asserted (Mobile Only) 500 — us 8 8-4 t214 DMI message and all PCI Express ports and DMI in L2/L3 state to SUS_STAT# active 60 — us 8-5 t215 SUS_STAT# active to STP_PCI# active 60 — us 8-5 t216 STP_PCI# active to PLTRST# active 150 — us 8-5 t217 PLTRST# active to PROCPWRGD inactive 30 — us 8-5 t218 PROCPWRGD deassetion to clocks invalid 10 — us 8-5 t219 Clocks invalid to SLP_S3# assertion 1 — us 8-5 t220 SLP_S3# low to SLP_S4# low 30 — us 8-5 t221 SLP_S4# low to SLP_S5# low 30 — us 8-5 t222 SLP_S3# active to PWROK de-asserted 0 — 8-5 t223 PWROK rising to DRAMPWRGD rising 0 — us 8-6 t224 DRAMPWRGD falling to SLP_S4# falling -100 — ns 9 8-6 t225 VccRTC supply active to VccSus supplies active 0 — ms 1, 10 8-1
t226 RTCRST# high to RSMRST# high 20 — ns 8-1 t227 VccSUS supplies high to VccME3_3 high 0 — ms 1 t228 LAN Power Rails active to LAN_RST# de-assertion 1— m s 1 1 t229 VccME high to Vcc1_05 high 0 — ms 8-2 t230 MEPWROK high to PWROK high 0 — ms 8-2 t231 PWROK low to Vcc falling 40 — ns 12, 13, t232 MEPWROK falling to VccME or VccME3_3 falling 40 — ns 14 t233 SLP_S3# falling to Vcc falling 5 — us 12, 13 t234 LAN_RST# rising to VccLAN falling 40 — ns 13, 14 t235 RSMRST# falling to VccSUS falling 40 — ns 1, 13, t236 RTCRST# falling to VccRTC falling 0 — ms t237 SLP_LAN# (or LANPHYPC) rising to Intel LAN Phy power high and stable —2 0m s t238 RSMRST# falling to any of VccSUS supplies, VccME, VccME3_3, or Vcc falling 40 — ns 1, 12, 13, 14 t239 V5REF_Sus active to VccSus3_3 active 0 — ms 15 t240 V5REF active to Vcc3_3 active See Note —m s1 5 t241 VccSus supplies active to Vcc supplies active 0— m s 1 , 1 2 t242 HDA_RST# active low pulse width 1 — μs t243 HDA_RST# inactive to HDA_BIT_CLK startup delay 170 — μs t244 VccSus active to SLP_S5#, SLP_S4#, SLP_S3#, SUS_STAT#, PLTRST# and PCIRST#active —5 0n s t245 RSMRST# de-assertion to SLP_S5# de- assertion 97 — ms 16, 2 t246 S4 Wake Event to SLP_S4# inactive (S4 Wake) See Note Below 3 t247 S3 Wake Event to SLP_S3# inactive (S3 Wake) See Note Below 4 t248 SLP_M# inactive to SLP_S3# inactive — ±10 ns t250 LANRST# assertion to PWROK assertion 0— m s t251 RSMRST# de-assertion to MEPWROK assertion 0— m s Table 8-39. Power Sequencing and Re set Signal Timings (Sheet 2 of 3) Sym Parameter Min Max Units Notes Fig
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NOTES: 1. VccSus supplies include VccSus3_3, V5REF_Su s, VccSusHDA, VccLAN (if LAN powered in S3/S4/S5), and VccME3_3 and VccME (if Intel® ME powered in S3/S4/S5). 2. This timing is a nominal value counted using RT C clock. If RTC clock isn’t already stable at the rising edge of RSMRST#, this timing could be shorter or longer than the specified value. 3. Dependency on SLP_S4# and SLP_M# stretching. 4. Dependency on SLP_S3# and SLP_M# stretching. 5. It is required that the power rails associated with PCI/PCIe (typically the 3.3 V, 5 V, and
12 V core well rails) have been valid for 99 ms prior to PWROK assertion to comply with
the 100 ms PCI/PCIe 2.0 specification on PLTRST# de-assertion. System designers must ensure the requirement is met on the platforms. 6. Ensure PWROK is a solid logic '1' befo re proceeding with the boot sequence. NOTE: If PWROK drops after t206 it will be considered a power failure. 7. t209 minimum timing selectable as 1 ms (recommended), 5 ms, 50 ms, or 100 ms using bits 9:8 of PCHSTRP15. 8. Requires SPI messaging to be completed. 9. The negative min timing implies that DRAMP WRGD must either fall before SLP_S4# or within 100 ns after it. 10. The VccSus supplies must never be active while the VccRTC supply is inactive. 11. Measured from VccLAN power wi thin voltage specification to LAN_RST# = (Vih+Vil)/2. The rising edge of LAN_RST# needs to be a clean, monotonic edge for frequency content below 10 MHz. 12. Vcc includes VccIO, VccCORE, Vcc3_3, VccADPLLA, VccADPLLB, VccADAC, V5REF, V_CPU_IO, VccDMI, VccLAN (if LAN only power in S0), VccALVDS (mobile only), VccTX_LVDS (mobile only), and VccME3_3 and VccME (if Intel ® ME only powered in S0). 13. A Power rail is considered to be inactive when the rail is at its nominal voltage minus 5% or less. 14. Board design may meet (t231 AND t232 AND t234 AND t235) OR (t238). 15. V5REF must be powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after Vcc3_3, or before Vcc3_3 within 0.7 V. V5REF_Sus must be powered up before VccSus3_3, or after VccSus3_3 within 0.7 V. Also, V5REF_Sus must power down after VccSus3_3, or before VccSus3_3 within 0.7 V. 16. If RTC clock is not already stable at RSMRST# rising edge, this time may be longer. 17. RSMRST# falling edge must transition to 0. 8 V or less before VccSus3_3 drops to 2.9 V 18. LAN_RST# high to SPI Soft-Start Reads is an internal PCH timing. The timing cannot be measured externally and included here for general power sequencing reference. t252 THRMTRIP# active to SLP_S3#, SLP_S4#, SLP_S5# active —1 7 5n s t253 RSMRST# rising edge transition from 20% to 80% —5 0 μs t254 RSMRST# falling edge transition — — — 17 Table 8-39. Power Sequencing and Reset Signal Timings (Sheet 3 of 3) Sym Parameter Min Max Units Notes Fig
8.8 Power Management Timing Diagrams
Figure 8-1. G3 w/RTC Loss to S4/S5 Timing Diagram Figure 8-2. S5 to S0 Timing Diagram Signal NameDestinationSource SUSCLK RSMRST#Board PCH PCH Board VccRTCBoard PCH RTCRST#Board PCH t200 VccSUSBoard PCH t201 SLP_S5#PCH Board t202 toggling Only for S4 after G3 t226 t225 MEPWROK may come up earlier than PWROK, but no later LAN_RST# may come up earlier than or at the same time as PWROK, or it may be statically grounded for platforms not using Intel LAN SLP_S3# VccME SLP_M# Signal NameDestSource SLP_S4# SLP_S5#PCH Board PCH Board PCH Board PCH Board Board PCH VCC_CPU Board Processor Could come up as early as before SLP_S5# or as late as SLP_S3#, but no later stable STP_PCI# Clock Chip Outputs PROCPWRGD SUS_STAT# PWROK DRAMPWRGD SYS_PWROKProcessor VRM PCH Board PCH PCH Processor MEPWROKBoard PCH VccBoard PCH PCH Clock Chip Ramps to ‘1’ with Vcc power t208 Clock Chip PCH t209 PLTRST# t210 PCH Processor PCH Board PCH Processor/ Board t203 t204 No required ordering w.r.t. PWROK, but SYS_PWROK will typically be first t205 LAN_RST#Board PCH t207 t211 t206 t229 t230
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Figure 8-3. S3/M3 to S0 Timing Diagram Figure 8-4. S5/Moff - S5/M3 Timing Diagram SLP_S3# VccME SLP_M# Signal NameDestSource SLP_S4# SLP_S5#PCH Board PCH Board PCH Board PCH Board Board PCH Vcc_cpu Board Processor stable STP_PCI# Clock Chip Outputs PROCPWRGD SUS_STAT# PWROK DRAMPWRGD SYS_PWROKProcessor VRM PCH Board PCH PCH Processor MEPWROKBoard PCH VccBoard PCH PCH Clock Chip Ramps to ‘1’ with Vcc_main t208 Clock Chip PCH t209 PLTRST# t210 PCH Processor PCH Board PCH Processor/ Board No required ordering w.r.t. PWROK, but SYS_PWROK will typically be first t205 LAN_RST#Board PCH t211 t206 SLP_S3# VccME, VccLAN SLP_M# Signal NameDestSource SLP_S4# SLP_S5#PCH Board PCH Board PCH Board PCH Board Board PCH SPI CL_RST1# MEPWROKBoard PCH PCH SPI Flash PCH Controller Link LAN_RST#Board PCH t212 t207 t213 LAN_RST# will come up at the same time as MEPWROK, or it may be statically grounded for platforms not using Intel LAN
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8.9 AC Timing Diagrams
Figure 8-7. Clock Cycle Time Figure 8-8. Transmitting Position (Data to Strobe) Figure 8-9. Clock Timing CLKA/ CLKB YA/YB Tppos1 Tppos2 Tppos3 Tppos4 Tppos5 Tppos6 Tppos0 2.0V 0.8V Period High Time Low Time Fall Time Rise Time
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Figure 8-14. Output Enable Delay Figure 8-15. USB Rise and Fall Times Figure 8-16. USB Jitter Clock Output Output Enable Delay VT 1.5V Differential Data Lines 90% 10% 10% 90% tR tF Rise Time Fall Time CL CL Low-speed: 75 ns at CL = 50 pF, 300 ns at CL = 350 pF Full-speed: 4 to 20 ns at CL = 50 pF High-speed: 0.8 to 1.2 ns at CL = 10 pF Paired Transitions Consecutive Transitions Crossover Points T period Differential Data Lines Jitter
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Figure 8-20. SPI Timings Figure 8-21. Intel® High Definition Audio Input and Output Timings SPI_CLK SPI_MOSI SPI_MISO SPI_CS# t186 t187 t184 t185 t183 t189t188 HDA_SDOUT HDA_SDIN[3:0] HDA_BIT_CLK t143 t143t144 t144 t145 t146
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Figure 8-25. Transmitting Position (Data to Strobe) CLKA/ CLKB YA/YB Tppos1 Tppos2 Tppos3 Tppos4 Tppos5 Tppos6 Tppos0 Figure 8-26. PCI Express Transmitter Eye
Figure 8-27. PCI Express Receiver Eye VRS-Diffp-p-Min>175mV .4 UI =TRX-EYE min VTS-Diff = 0mV D+/D- Crossing point
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Figure 8-28. Measurement Points for Differential Waveforms. V min = -0.30V V max = 1.15V Vcross max = 550mV Vcross min = 300 mV Vcross delta = 140mV V min = -0.30V V max = 1.15V Vcross max = 550mV Vcross min = 300 mV Vcross delta = 140mV Clock# Clock Clock Clock# Vcross median Clock Clock# Vcross median Clock Clock# Vcross median +75 mV Vcross median -75mV Trise Tfall Clock-Clock# Vih_min = +150 mV Vil_max = -150 mV Positive Duty Cycle (Differential ) 0.0V Clock-Clock# .0V Negative Duty Cycle (Differential) Clock Period (Differential) Fall Edge Rate Rise Edge Rate Differential Clock – Differential Measurements Differential Clock – Single Ended Measurements
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Register and Memory Mapping
9 Register and Memory Mapping
The PCH contains registers that are located in the processor’s I/O space and memory space and sets of PCI configuration registers that are located in PCI configuration space. This chapter describes the PCH I/O and memory maps at the register-set level. Register access is also described. Register-level address maps and Individual register bit descriptions are provided in the following chapters. The following notations and definitions are used in the register/instruction description chapters. RO Read Only. In some cases, if a register is read only, writes to this register location have no effect. However, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. See the I/O and memory map tables for details. WO Write Only. In some cases, if a register is write only, reads to this register location have no effect. However, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. See the I/O and memory map tables for details. R/W Read/Write. A register with this attribute can be read and written. R/WC Read/Write Clear. A register bit with this attribute can be read and written. However, a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect. R/WO Read/Write-Once. A register bit with this attribute can be written only once after power up. After the first write, the bit becomes read only. R/WL Read/Write Lockable. A register bit with the attribute can be read at any time but writes may only occur if the associated lock bit is set to unlock. If the associated lock bit is set to lock, this register bit becomes RO unless otherwise indicated. R/WLO Read/Write, Lock-Once. A register bit with this attribute can be written to the non-locked value multiple times, but to the locked value only once. After the locked value has been written, the bit becomes read only. Reserved The value of reserved bits must never be changed. For details see Section 9.2. Default When the PCH is reset, it sets its registers to predetermined default states. It is the responsibility of the system initialization software to determine configuration, operating parameters, and optional system features that are applicable, and to program the PCH registers accordingly. Bold Register bits that are highlighted in bold text indicate that the bit is implemented in the PCH. Register bits that are not implemented or are hardwired will remain in plain text.
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9.1 PCI Devices and Functions
The PCH incorporates a variety of PCI devices and functions, as shown in Table 9-1. They are divided into seven logical devices for consumer SKUs. The first is the DMI-To- PCI bridge (Device 30). The second device (Device 31) contains most of the standard PCI functions that always existed in the PCI-to-ISA bridges (South Bridges), such as the Intel ® PIIX4. The third and fourth (Device 29 and Device 26) are the USB and USB2 host controller devices. The fifth (Device 28) is PCI Express device. The sixth (Device 27) is HD Audio controller device. The seventh (Device 25) is the Gigabit Ethernet controller device. The eighth device (Device 22) is the Intel ® Management Engine Interface (Intel® MEI). If for some reason, the particular system platform does not want to support any one of the Device Functions, with the exception of D30:F0 and D23:F0 can individually be disabled. The integrated Gigabit Ethernet controller will be disabled if no Platform LAN Connect component is detected (See Chapter 5.3). When a function is disabled, it does not appear at all to the software. A disabled function will not respond to any register reads or writes, insuring that these devices appear hidden to software. b NOTES: 1. The PCI-to-LPC bridge contai ns registers that control LPC, Power Management, System Management, GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA. 2. SATA controller 2 (D31:F5) is only visible when D31:F2 CC.SCC=01h. 3. This table shows the default PCI Express Function Number-to-Root Port mapping. Function numbers for a given root port are assignable through the “Root Port Function Number and Hide for PCI Express Root Ports” register (RCBA+0404h). 4. Prior to BIOS initialization of the PCH USB su bsystem, the EHCI controllers will appear as Function 7. After BIOS initialization, the EHCI controllers will be Function 0. Table 9-1. PCI Devi ces and Functions Bus:Device:Function Fu nction Description Bus 0:Device 30:Function 0 PCI-to-PCI Bridge Bus 0:Device 31:Function 0 LPC Controller 1 Bus 0:Device 31:Function 2 SATA Controller #1 Bus 0:Device 31:Function 3 SMBus Controller Bus 0:Device 31:Function 5 SATA Controller #2 2 Bus 0:Device 31:Function 6 Thermal Subsystem Bus 0:Device 29:Function 0 USB EHCI Controller #1 Bus 0:Device 26:Function 0 USB EHCI Controller #2 Bus 0:Device 28:Function 0 PCI Express* Port 1 Bus 0:Device 28:Function 1 PCI Express Port 2 Bus 0:Device 28:Function 2 PCI Express Port 3 Bus 0:Device 28:Function 3 PCI Express Port 4 Bus 0:Device 28:Function 4 PCI Express Port 5 Bus 0:Device 28:Function 5 PCI Express Port 6 Bus 0:Device 28:Function 6 PCI Express Port 7 Bus 0:Device 28:Function 7 PCI Express Port 8 Bus 0:Device 27:Function 0 Intel ® High Definition Audio Controller Bus 0:Device 25:Function 0 Gigabit Ethernet Controller Bus 0:Device 22:Function 0 Intel ® Management Engine Interface #1 Bus 0:Device 22:Function 1 Intel ® Management Engine Interface #2 Bus 0:Device 22:Function 2 IDE-R Bus 0:Device 22:Function 3 KT
Register and Memory Mapping
9.2 PCI Configuration Map
Each PCI function on the PCH has a set of PCI configuration registers. The register address map tables for these register sets are included at the beginning of the chapter for the particular function. Configuration Space registers are accessed through configuration cycles on the PCI bus by the Host bridge using configuration mechanism #1 detailed in the PCI Local Bus Specification, Revision 2.3. Some of the PCI registers contain reserved bits. Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. Note the software does not need to perform read, merge, write operation for the configuration address register. In addition to reserved bits within a register, the configuration space contains reserved locations. Software should not write to reserved PCI configuration locations in the device-specific region (above address offset 3Fh).
9.3 I/O Map
The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be moved, but in some cases can be disabled. Variable ranges can be moved and can also be disabled.
9.3.1 Fixed I/O Address Ranges
Table 9-2 shows the Fixed I/O decode ranges from the processor perspective. Note that for each I/O range, there may be separate behavior for reads and writes. DMI (Direct Media Interface) cycles that go to target ranges that are marked as “Reserved” will not be decoded by the PCH, and will be passed to PCI unless the Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0). If a PCI master targets one of the fixed I/O target ranges, it will be positively decoded by the PCH in medium speed. Address ranges that are not listed or marked “Reserved” are not decoded by the PCH (unless assigned to one of the variable ranges). Table 9-2. Fixed I/O Ranges Decoded by Intel ® PCH (Sheet 1 of 3) I/O Address Read Target Write Target Internal Unit 00h–08h DMA Controller DMA Controller DMA 09h–0Eh RESERVED DMA Controller DMA 0Fh DMA Controller DMA Controller DMA 10h–18h DMA Controller DMA Controller DMA 19h–1Eh RESERVED DMA Controller DMA 1Fh DMA Controller DMA Controller DMA 20h–21h Interrupt Controller Interrupt Controller Interrupt 24h–25h Interrupt Controller Interrupt Controller Interrupt 28h–29h Interrupt Controller Interrupt Controller Interrupt 2Ch–2Dh Interrupt Controller Interrupt Controller Interrupt 2E–2F LPC SIO LPC SIO Forwarded to LPC
Register and Memory Mapping
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30h–31h Interrupt Controller Interrupt Controller Interrupt 34h–35h Interrupt Controller Interrupt Controller Interrupt 38h–39h Interrupt Controller Interrupt Controller Interrupt 3Ch–3Dh Interrupt Controller Interrupt Controller Interrupt 40h–42h Timer/Counter Timer/Counter PIT (8254) 43h RESERVED Timer/Counter PIT 4E–4F LPC SIO LPC SIO Forwarded to LPC 50h–52h Timer/Counter Timer/Counter PIT 53h RESERVED Timer/Counter PIT 60h Microcontroller Microcontroller Forwarded to LPC 61h NMI Controller NMI Controller Processor I/F 62h Microcontroller Microcontroller Forwarded to LPC 64h Microcontroller Microcontroller Forwarded to LPC 66h Microcontroller Microcontroller Forwarded to LPC 70h RESERVED1 NMI and RTC Controller RTC 71h RTC Controller RTC Controller RTC 72h RTC Controller NMI and RTC Controller RTC 73h RTC Controller RTC Controller RTC 74h RTC Controller NMI and RTC Controller RTC 75h RTC Controller RTC Controller RTC 76h RTC Controller NMI and RTC Controller RTC 77h RTC Controller RTC Controller RTC 80h DMA Controller, or LPC, or PCI DMA Controller and LPC or PCI DMA 81h–83h DMA Controller DMA Controller DMA 84h–86h DMA Controller DMA Controller and LPC or PCI DMA 87h DMA Controller DMA Controller DMA 88h DMA Controller DMA Controller and LPC or PCI DMA 89h–8Bh DMA Controller DMA Controller DMA 8Ch–8Eh DMA Controller DMA Controller and LPC or PCI DMA 08Fh DMA Controller DMA Controller DMA 90h–91h DMA Controller DMA Controller DMA 92h Reset Generator Reset Generator Processor I/F 93h–9Fh DMA Controller DMA Controller DMA A0h–A1h Interrupt Controller Interrupt Controller Interrupt A4h–A5h Interrupt Controller Interrupt Controller Interrupt A8h–A9h Interrupt Controller Interrupt Controller Interrupt ACh–ADh Interrupt Controller Interrupt Controller Interrupt B0h–B1h Interrupt Controller Interrupt Controller Interrupt B2h–B3h Power Management Power Management Power Management B4h–B5h Interrupt Controller Interrupt Controller Interrupt B8h–B9h Interrupt Controller Interrupt Controller Interrupt Table 9-2. Fixed I/O Ranges Decoded by Intel ® PCH (Sheet 2 of 3) I/O Address Read Target Write Target Internal Unit
Register and Memory Mapping NOTE: 1. See Section 13.7.2. BCh–BDh Interrupt Controller Interrupt Controller Interrupt C0h–D1h DMA Controller DMA Controller DMA D2h–DDh RESERVED1 DMA Controller DMA DEh–DFh DMA Controller DMA Controller DMA F0h FERR# / Interrupt Controller FERR# / Interrupt Controller Processor I/F 170h–177h SATA Controller or PCI SATA Controller or PCI Forwarded to SATA 1F0h–1F7h SATA Controller or PCI SATA Controller or PCI Forwarded to SATA 200h-207h Gameport Low Gameport Low Forwarded to LPC 208h-20Fh Gameport High Gameport High Forwarded to LPC 376h SATA Controller or PCI SATA Controller or PCI Forwarded to SATA 3F6h SATA Controller or PCI SATA Controller or PCI Forwarded to SATA 4D0h–4D1h Interrupt Controller Interrupt Controller Interrupt CF9h Reset Generator Reset Generator Processor I/F Table 9-2. Fixed I/O Ranges Decoded by Intel ® PCH (Sheet 3 of 3) I/O Address Read Target Write Target Internal Unit
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9.3.2 Variable I/O Decode Ranges
Table 9-3 shows the Variable I/O Decode Ranges. They are set using Base Address Registers (BARs) or other configuration bits in the various PCI configuration spaces. The PNP software (PCI or ACPI) can use their configuration mechanisms to set and adjust these values. Warning: The Variable I/O Ranges should not be set to conflict with the Fixed I/O Ranges. Unpredictable results if the configuration software allows conflicts to occur. The PCH does not perform any checks for conflicts. NOTE: 1. All ranges are decoded directly from DMI. The I/O cycles will not be seen on PCI, except the range associated with PCI bridge. 2. The LAN range is typically not used, as the registers can also be accessed via a memory space. 3. There is also an alias 400h above the parallel port range that is used for ECP parallel ports. Table 9-3. Variable I/O Decode Ranges Range Name Mappable Size (Bytes) Target ACPI Anywhere in 64 KB I/O Space 64 Power Management IDE Bus Master Anywhere in 64 KB I/O Space 1. 16 or 32 2. 16 1. SATA Host Controller #1, #2 2. IDE-R Native IDE Command Anywhere in 64 KB I/O Space 1 8 1. SATA Host Controller #1, #2 2. IDE-R Native IDE Control Anywhere in 64 KB I/O Space 1 4 1. SATA Host Controller #1, #2 2. IDE-R SATA Index/Data Pair Anywhere in 64 KB I/O Space 16 SATA Host Controller #1, #2 SMBus Anywhere in 64 KB I/O Space 32 SMB Unit TCO 96 Bytes above ACPI Base 32 TCO Unit GPIO Anywhere in 64 KB I/O Space 128 GPIO Unit Parallel Port 3 Ranges in 64 KB I/O Space 8
3 LPC Peripheral
Serial Port 1 8 Ranges in 64 KB I/O Space 8 LPC Peripheral Serial Port 2 8 Ranges in 64 KB I/O Space 8 LPC Peripheral Floppy Disk Controller 2 Ranges in 64 KB I/O Space 8 LPC Peripheral LAN Anywhere in 64 KB I/O Space 32
2 LAN Unit
LPC Generic 1 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral LPC Generic 2 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral LPC Generic 3 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral LPC Generic 4 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral I/O Trapping Ranges Anywhere in 64 KB I/O Space 1 to 256 Trap on Backbone PCI Bridge Anywhere in 64 KB I/O Space I/O Base/ Limit PCI Bridge PCI Express Root Ports Anywhere in 64 KB I/O Space I/O Base/ Limit PCI Express Root Ports 1-8 KT Anywhere in 64 KB I/O Space 8 KT
Register and Memory Mapping
9.4 Memory Map
Table 9-4 shows (from the processor perspective) the memory ranges that the PCH decodes. Cycles that arrive from DMI that are not directed to any of the internal memory targets that decode directly from DMI will be driven out on PCI unless the Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0). PCI cycles generated by external PCI masters will be positively decoded unless they fall in the PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller’s range, it will be forwarded up to DMI. Software must not attempt locks to the PCH memory-mapped I/O ranges for EHCI and HPET. If attempted, the lock is not honored which means potential deadlock conditions may occur. Table 9-4. Memory Decode Ranges from Processor Perspective (Sheet 1 of 3) Memory Range Target Dependency/Comments 0000 0000h–000D FFFFh 0010 0000h–TOM (Top of Memory) Main Memory TOM registers in Host controller 000E 0000h–000E FFFFh LPC or SPI Bit 6 in BIOS Decode Enable register is set 000F 0000h–000F FFFFh LPC or SPI Bit 7 in BIOS Decode Enable register is set FEC_ _000h–FEC_ _040h IO(x) APIC inside PCH _ _is controlled using APIC Range Select (ASEL) field and APIC Enable (AEN) bit FEC1 0000h–FEC1 7FFF PCI Express* Port 1 PCI Express* Root Port 1 I/OxAPIC Enable (PAE) set FEC1 8000h–FEC1 FFFFh PCI Express* Port 2 PCI Express* Root Port 2 I/OxAPIC Enable (PAE) set FEC2 0000h–FEC2 7FFFh PCI Express* Port 3 PCI Express* Root Port 3 I/OxAPIC Enable (PAE) set FEC2 8000h–FEC2 FFFFh PCI Express* Port 4 PCI Express* Root Port 4 I/OxAPIC Enable (PAE) set FEC3 0000h–FEC3 7FFFh PCI Express* Port 5 PCI Express* Root Port 5 I/OxAPIC Enable (PAE) set FEC3 8000h–FEC3 FFFFh PCI Express* Port 6 PCI Express* Root Port 6 I/OxAPIC Enable (PAE) set FEC4 0000 - FEC4 7FFF PCI Express* Port 7 PCI Express* Root Port 7I/OxAPIC Enable (PAE) set FEC4 8000 - FEC4 FFFF PCI Express* Port 8 PCI Express* Root Port 8I/OxAPIC Enable (PAE) set FED4 0000h–FED4 BFFFh TPM on LPC None FFC0 0000h–FFC7 FFFFh FF80 0000h–FF87 FFFFh LPC or SPI (or PCI)2 Bit 8 in BIOS Decode Enable register is set FFC8 0000h–FFCF FFFFh FF88 0000h–FF8F FFFFh LPC or SPI (or PCI)2 Bit 9 in BIOS Decode Enable register is set FFD0 0000h–FFD7 FFFFh FF90 0000h–FF97 FFFFh LPC or SPI (or PCI)2 Bit 10 in BIOS Decode Enable register is set FFD8 0000h–FFDF FFFFh FF98 0000h–FF9F FFFFh LPC or SPI (or PCI)2 Bit 11 in BIOS Decode Enable register is set FFE0 000h–FFE7 FFFFh FFA0 0000h–FFA7 FFFFh LPC or SPI (or PCI)2 Bit 12 in BIOS Decode Enable register is set
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FFE8 0000h–FFEF FFFFh FFA8 0000h–FFAF FFFFh LPC or SPI (or PCI)2 Bit 13 in BIOS Decode Enable register is set FFF0 0000h–FFF7 FFFFh FFB0 0000h–FFB7 FFFFh LPC or SPI (or PCI)2 Bit 14 in BIOS Decode Enable register is set FFF8 0000h–FFFF FFFFh FFB8 0000h–FFBF FFFFh LPC or SPI (or PCI)2 Always enabled. The top two, 64 KB blocks of this range can be swapped, as described in Section 9.4.1. FF70 0000h–FF7F FFFFh FF30 0000h–FF3F FFFFh LPC or SPI (or PCI)
2 Bit 3 in BIOS Decode Enable register is set
FF60 0000h–FF6F FFFFh FF20 0000h–FF2F FFFFh LPC or SPI (or PCI)2 Bit 2 in BIOS Decode Enable register is set FF50 0000h–FF5F FFFFh FF10 0000h–FF1F FFFFh LPC or SPI (or PCI)2 Hub (or PCI)2 Bit 1 in BIOS Decode Enable register is set FF40 0000h–FF4F FFFFh FF00 0000h–FF0F FFFFh LPC or SPI (or PCI)2 Bit 0 in BIOS Decode Enable register is set
128 KB anywhere in 4-GB
Enable using BAR in Device 25:Function 0 (Integrated LAN Controller MBARA)
4 KB anywhere in 4 GB
Enable using BAR in Device 25:Function 0 (Integrated LAN Controller MBARB)
1 KB anywhere in 4-GB
Controller #11 Enable using standard PCI mechanism (Device 29, Function 0) Controller #21 Enable using standard PCI mechanism (Device 26, Function 0)
512 B anywhere in 64-bit
Intel® High Definition Audio Host Controller Enable using standard PCI mechanism (Device 27, Function 0) FED4 0000h–FED4 FFFFh TPM on LPC None Memory Base/Limit anywhere in 4 GB range PCI Bridge Enable via standard PCI mechanism (Device 30: Function 0) Prefetchable Memory Base/Limit anywhere in 64-bit address range PCI Bridge Enable via standard PCI mechanism (Device 30: Function 0)
64 KB anywhere in 4 GB
LPC Generic Memory Range. Enable via setting bit[0] of the LPC Generic Memory Range register (D31:F0:offset 98h).
32 Bytes anywhere in 64-
bit address range SMBus Enable using standard PCI mechanism (Device 31: Function 3)
2 KB anywhere above
64 KB to 4 GB range
Controller #1 AHCI memory-mapped registers. Enable using standard PCI mechanism (Device 31: Function 2) Memory Base/Limit anywhere in 4 GB range PCI Express Root Ports 1-8 Enable via standard PCI mechanism (Device 28: Function 0-7) Prefetchable Memory Base/Limit anywhere in 64-bit address range PCI Express Root Ports 1-8 Enable using standard PCI mechanism (Device 28: Function 0-7)
4 KB anywhere in 64-bit
address range Thermal Reporting Enable using standard PCI mechanism (Device 31: Function 6 TBAR/TBARH) address range Thermal Reporting Enable using standard PCI mechanism (Device 31: Function 6 TBARB/TBARBH) Table 9-4. Memory Decode Ranges from Processor Perspective (Sheet 2 of 3) Memory Range Target Dependency/Comments
Register and Memory Mapping NOTES: 1. Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High Precision Event Timers. If attempted, the lock is not honored, which means potential deadlock conditions may occur. 2. PCI is the target when the Boot BIOS Destination selection bits are set to 10b (Chipset Config Registers:Offset 3401 bits 11:10). When PCI selected, the Firmware Hub Decode Enable bits have no effect.
9.4.1 Boot-Block Update Scheme
The PCH supports a “top-block swap” mode that has the PCH swap the top block in the FWH or SPI flash (the boot block) with another location. This allows for safe update of the Boot Block (even if a power failure occurs). When the “TOP_SWAP” Enable bit is set, the PCH will invert A16 for cycles going to the upper two 64 KB blocks in the FWH or appropriate address lines as selected in Boot Block Size (BOOT_BLOCK_SIZE) soft strap for SPI. Specifically for FHW, in this mode accesses to FFFF_0000h-FFFF_FFFFh are directed to FFFE_0000h-FFFE_FFFFh and vice versa. When the Top Swap Enable bit is 0, the PCH will not invert A16. Specifically for SPI, in this mode the “Top-Block Swap” behavior is as described below. When the Top Swap Enable bit is 0, the PCH will not invert any address bit. This bit is automatically set to 0 by RTCRST#, but not by PLTRST#. The scheme is based on the concept that the top block is reserved as the “boot” block, and the block immediately below the top block is reserved for doing boot-block updates.
16 Bytes anywhere in 64-
bit address range Intel® MEI #1, #2 Enable using standard PCI mechanism (Device 22: Function 1:0) range KT Enable using standard PCI mechanism (Device 22: Function 3)
16 KB anywhere in 4 GB
(RCRB) Enable using setting bit[0] of the Root Complex Base Address register (D31:F0:offset F0h). FED0 X000h–FED0 X3FFh High Precision Event Timers 1 BIOS determines the “fixed” location which is one of four, 1-KB ranges where X (in the first column) is 0h, 1h, 2h, or 3h. All other PCI None Table 9-4. Memory Decode Ranges from Processor Perspective (Sheet 3 of 3) Memory Range Target Dependency/Comments Table 9-5 SPI Mode Address Swapping BOOT_BLOCK_SIZE Value Accesses to Being Directed to 000 (64KB) FFFF_0000h–FFFF_FFFFh FFFE_0000h–FFFE_FFFFh and vice versa 001 (128KB) FFFE_0000h–FFFF_FFFFh FFFC_0000h–FFFD_FFFFh and vice versa 010 (256KB) FFFC_0000h–FFFF_FFFFh FFF8_0000h–FFFB_FFFFh and vice versa 011 (512KB) FFF8_0000h–FFFF_FFFFh FFF0_0000h–FFF7_FFFFh and vice versa 100 (1MB) FFF0_0000h–FFFF_FFFFh FFE0_0 000h–FFEF_FFFFh and vice versa 101 - 111 Reserved Reserved
Register and Memory Mapping
386 Datasheet
The algorithm is: 1. Software copies the top block to the block immediately below the top 2. Software checks that the copied block is correct. This could be done by performing a checksum calculation. 3. Software sets the TOP_SWAP bit. This will invert the appropriate address bits for the cycles going to the FWH or SPI. 4. Software erases the top block 5. Software writes the new top block 6. Software checks the new top block 7. Software clears the TOP_SWAP bit 8. Software sets the Top_Swap Lock-Down bit If a power failure occurs at any point after step 3, the system will be able to boot from the copy of the boot block that is stored in the block below the top. This is because the TOP_SWAP bit is backed in the RTC well. Note: The top-block swap mode may be forced by an external strapping option (See Section 2.28). When top-block swap mode is forced in this manner, the TOP_SWAP bit cannot be cleared by software. A re-boot with the strap removed will be required to exit a forced top-block swap mode. Note: Top-block swap mode only affects accesses to the Firmware Hub space, not feature space for FWH. Note: The top-block swap mode has no effect on accesses below FFFE_0000h for FWH. § §
Chipset Configuration Registers
10 Chipset Configuration Registers
This section describes all registers and base functionality that is related to chipset configuration and not a specific interface (such as LPC, PCI, or PCI Express*). It contains the root complex register block, which describes the behavior of the upstream internal link. This block is mapped into memory space, using the Root Complex Base Address (RCBA) register of the PCI-to-LPC bridge. Accesses in this space must be limited to 32-(DW) bit quantities. Burst accesses are not allowed. All chipset configuration registers are located in the core well unless otherwise indicated.
10.1 Chipset Configuration Registers (Memory Space)
Note: Address locations that are not shown should be treated as Reserved (see Section 9.2 for details). Table 10-1. Chipset Configurat ion Register Memory Map (Memory Space) (Sheet 1 of 3) Offset Mnemonic Register Name Default Type 0014–0017h V0CTL VC 0 Resource Control 800000FFh R/W, RO 001A–001Bh V0STS VC 0 Resource Status 0000h RO 001C–001Fh V1CAP Virtual Channel 1 Resource Capability 00008001h R/WO, RO 0020–0023h V1CTL VC 1 Resource Control 00000000h R/W 0026–0027h V1STS VC 1 Resource Status 0000h RO 0050–0053h CIR0 Chipset Initialization Register 0 00000000h R/W 0088–008Bh CIR1 Chipset Initialization Register 1 00000000h R/WO 00AC–00AFh REC Root Error Command 0000h R/W 01A0–01A3h ILCL Internal Link Capability List 00010006h RO 01A4–01A7h LCAP Link Capabilities 00012841h RO, R/ WO 01A8–01A9h LCTL Link Control 0000h R/W 01AA–01ABh LSTS Link Status 0041h RO 0220–0223h BCR Backbone Configuration 00000000h R/W 0224–0227h RPC Root Port Configuration 0000000yh R/W, RO 0234–0327h DMIC DMI Control 00000000h R/W, RO 0238–023Bh RPFN Root Port Function Number for PCI Express Root Ports 76543210h R/WO, RO 0290–0293h FLRSTAT Function Level Reset Pending Status Summary 00000000h RO 1D40–1D47h CIR5 Chipset Initialization Register 5 000000000000 0000h R/W
Chipset Configuration Registers
388 Datasheet
1E00–1E03h TRSR Trap Status Register 00000000h R/WC, RO 1E10–1E17h TRCR Trapped Cycle Register 000000000000 0000h RO 1E18–1E1Fh TWDR Trapped Write Data Register 000000000000 0000h RO 1E80–1E87h IOTR0 I/O Trap Register 0 000000000000 0000h R/W 1E88–1E8Fh IOTR1 I/O Trap Register 1 000000000000 0000h R/W 1E90–1E97h IOTR2 I/O Trap Register 2 000000000000 0000h R/W 1E98–1E9Fh IOTR3 I/O Trap Register 3 000000000000 0000h R/W 2010–2013h DMC DMI Miscellaneous Control Register 00000002h R/W 2024–2027h CIR6 CIR6—Chipset Initialization Register 6 0B4030C0h R/W 2324–2327h DMC2 DMI Miscellaneous Control Register 2 0FFF0FFFh R/W 3000–3000h TCTL TCO Configuration 00h R/W 3100–3103h D31IP Device 31 Interrupt Pin 03243200h R/W, RO 3104–3107h D30IP Device 30 Interrupt Pin 00000000h RO 3108–310Bh D29IP Device 29 Interrupt Pin 10004321h R/W 310C–310Fh D28IP Device 28 Interrupt Pin 00214321h R/W 3110–3113h D27IP Device 27 Interrupt Pin 00000001h R/W 3114–3117h D26IP Device 26 Interrupt Pin 30000321h R/W 3118–311Bh D25IP Device 25 Interrupt Pin 00000001h R/W 3124–3127h D22IP Device 22 Interrupt Pin 00000001h R/W 3140–3141h D31IR Device 31 Interrupt Route 3210h R/W 3142–3143h D30IR Device 30 Interrupt Route 0000h RO 3144–3145h D29IR Device 29 Interrupt Route 3210h R/W 3146–3147h D28IR Device 28 Interrupt Route 3210h R/W 3148–3149h D27IR Device 27 Interrupt Route 3210h R/W 314C–314Fh D26IR Device 26 Interrupt Route 3210h R/W 3150–3153h D25IR Device 25 Interrupt Route 3210h R/W 3154–3157h D24IR Device 24 Interrupt Route 3210h R/W 315C–316Fh D22IR Device 22 Interrupt Route 3210h R/W 31FE–31FFh OIC Other Interrupt Control 0000h R/W 3310–3313h PRSTS Power and Reset Status 02020000h RO, R/ WC 3314–3317h CIR7 Chipset Initalization Register 7 00000000h R/W Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 2 of 3) Offset Mnemonic Register Name Default Type
Chipset Configuration Registers 3324–3327h CIR8 Chipset Initalization Register 8 00000000h R/W 3330–3333h CIR9 Chipset Initalization Register 9 00000000h R/W 3340–3343h CIR10 Chipset Initalization Register 10 00000000h R/W 3350–3353h CIR13 Chipset Initalization Register 13 00000000h R/W 3368–336Bh CIR14 Chipset Initalization Register 14 00000000h R/W 3378–337Bh CIR15 Chipset Initalization Register 15 00000000h R/W 3388–338Bh CIR16 Chipset Initalization Register 16 00000000h R/W 33A0–33A3h CIR17 Chipset Initalization Register 17 00000000h R/W 33A8–33ABh CIR18 Chipset Initalization Register 18 00000000h R/W 33C0–33C3h CIR19 Chipset Initalization Register 19 00000000h R/W 33CC–33CFh CIR20 Chipset Initalization Register 20 00000000h R/W 33D0–33D3h CIR21 Chipset Initalization Register 21 00000000h R/W 33D4–33D7h CIR22 Chipset Initalization Register 22 00000000h R/W 3400–3403h RC RTC Configuration 00000000h R/W, R/WLO 3404–3407h HPTC High Precision Timer Configuration 00000000h R/W 3410–3413h GCS General Control and Status 000000yy0h R/W, R/WLO 3414–3414h BUC Backed Up Control 00h R/W 3418–341Bh FD Function Disable 00000000h R/W 341C–341Fh CG Clock Gating 00000000h R/W 3420–3420h FDSW Function Disable SUS Well 00h R/W 3428–342Bh FD2 Function Disable 2 00000000h R/W 3590–3594h MISCCTL Miscellaneous Control Register 00000000h R/W 35A0–35A3h USBOCM1 USB Overcurrent MAP Register 1 00000000h R/WO 35A4–35A7h USBOCM2 USB Overcurrent MAP Register 2 00000000h R/WO 35B0–35B3h RMHWKCTL USB Remap Control 00000000h R/WO Table 10-1. Chipset Configurat ion Register Memory Map (Memory Space) (Sheet 3 of 3) Offset Mnemonic Register Name Default Type
Chipset Configuration Registers
390 Datasheet
10.1.1 V0CTL—Virtual Channel 0 Resource Control Register
Offset Address: 0014–0017h Attribute: R/W, RO Default Value: 80000023h Size: 32-bit
10.1.2 V0STS—Virtual Channel 0 Resource Status Register
Offset Address: 001A–001Bh Attribute: RO Default Value: 0000h Size: 16-bit Bit Description 31 Virtual Channel Enable (EN)— RO. Always set to 1. VC0 is always enabled and cannot be disabled. 30:27 Reserved 26:24 Virtual Channel Identifier (ID)—RO. Indicates the ID to use for this virtual channel. 23:16 Reserved 15:8 Extended TC/VC Map (ETVM): Defines the upper 8-bits of the VC0 16-bit TC/VC mapping registers. These registers use the PCI Express reserved TC[3] traffic class bit. 7:1 Transaction Class / Virtual Channel Map (TVM)—R/W. Indicates which transaction classes are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the virtual channel. 15:2 Reserved 1 VC Negotiation Pending (NP)—RO. When set, indicates the virtual channel is still being negotiated with ingress ports.
Chipset Configuration Registers
10.1.3 V1CTL—Virtual Channel 1 Resource Control Register
Offset Address: 0020–0023h Attribute: R/W, RO Default Value: 00000000h Size: 32-bit
10.1.4 V1STS—Virtual Channel 1 Resource Status Register
Offset Address: 0026–0027h Attribute: RO Default Value: 0000h Size: 16-bit
10.1.5 CIR0—Chipset Init ialization Register 0
Offset Address: 0050–0053h Attribute: R/W Default Value: 00000000h Size: 32-bit Bit Description 31 Virtual Channel Enable (EN)—R/W. Enables the VC when set. Disables the VC when cleared. 30:28 Reserved 27:24 Virtual Channel Identifier (ID)—R/W. Indicates the ID to use for this virtual channel. 23:16 Reserved 15:8 Extended TC/VC Map (ETVM): Defines the upper 8-bits of the VC0 16-bit TC/VC mapping registers. These registers use the PCI Express reserved TC[3] traffic class bit. 7:1 Transaction Class / Virtual Channel Map (TVM)—R/W. Indicates which transaction classes are mapped to this virtual channel. When a bit is set, this transaction class is mapped to the virtual channel. 15:2 Reserved 1 VC Negotiation Pending (NP)—RO. When set, indicates the virtual channel is still being negotiated with ingress ports. 31:0 CIR0 Field 0—R/W. BIOS must set this field.
Chipset Configuration Registers
392 Datasheet
10.1.6 CIR1—Chipset Initia lization Register 1
Offset Address: 0088–008Bh Attribute: R/WO Default Value: 00000000h Size: 32-bit
10.1.7 REC—Root Error Command Register
Offset Address: 00AC–00AFh Attribute: R/W Default Value: 0000h Size: 32-bit
10.1.8 ILCL—Internal Link Ca pabilities List Register
Offset Address: 01A0–01A3h Attribute: RO Default Value: 00010006h Size: 32-bit Bit Description 31:21 Reserved 20 CIR1 Field 3—R/WO. BIOS must set this bit. 19:16 Reserved 15 CIR1 Field 2—R/WO. BIOS must set this bit. 14:13 Reserved 12 CIR1 Field 1—R/WO. BIOS must set this bit. 11:0 Reserved Bit Description Drop Poisoned Downstream Packets (DPDP)—R/W. Determines how downstream packets on DMI are handled that are received with the EP field set, indicating poisoned data: 1 = This packet and all subsequent packets with data received on DMI for any VC will have their Unsupported Transaction (UT) field set causing them to master Abort downstream. Packets without data such as memory, IO and config read requests are allowed to proceed. 1 = Packets are forwarded downstream without forcing the UT field set. 30:0 Reserved Bit Description 31:20 Next Capability Offset (NEXT)— RO. Indicates this is the last item in the list. 19:16 Capability Version (CV)—RO. Indicates the version of the capability structure. 15:0 Capability ID (CID)—RO. Indicates this is capability for DMI.
Chipset Configuration Registers
10.1.9 LCAP—Link Capabilities Register
Offset Address: 01A4–01A7h Attribute: R/WO, RO Default Value: 00012841h Size: 32-bit
10.1.10 LCTL—Link Control Register
Offset Address: 01A8–01A9h Attribute: R/W Default Value: 0000h Size: 16-bit Bit Description 31:18 Reserved 17:15 L1 Exit Latency (EL1)—R/WO. 000b = Less than 1 µs 001b = 1 µs to less than 2 µs 010b = 2 µs to less than 4 µs 011b = 4 µs to less than 8 µs 100b = 8 µs to less than 16 µs 101b = 16 µs to less than 32 µs 110b = 32 µs to 64 µs 111b = More than 64 µs 14:12 L0s Exit Latency (EL0)—R/W. This field indicates that exit latency is 128 ns to less than 256 ns. 11:10 Active State Link PM Support (APMS)—R/W. Indicates the level of ASPM support on DMI. 00 = Disabled 01 = L0s entry supported 10 = Reserved 11 = L0s and L1 entry supported 9:4 Maximum Link Width (MLW)—RO. Indicates the maximum link width is 4 ports. 3:0 Maximum Link Speed (MLS)—RO. Indicates the link speed is 2.5 Gb/s. Bit Description 15:8 Reserved Extended Synch (ES)—R/W. When set, forces exte nded transmission of FTS ordered sets when exiting L0s prior to entering L0 and extra TS1 sequences at exit from L1 prior to entering L0. 6:2 Reserved 1:0 Active State Link PM Control (ASPM)—R/W. Indicates whether DMI should enter L0s, L1, or both. 00 = Disabled 01 = L0s entry enabled 10 = L1 entry enabled 11 = L0s and L1 entry enabled
Chipset Configuration Registers
394 Datasheet
10.1.11 LSTS—Link Status Register
Offset Address: 01AA–01ABh Attribute: RO Default Value: 0041h Size: 16-bit
10.1.12 BCR—Backbone Co nfiguration Register
Offset Address: 0220–0223h Attribute: R/W Default Value: 00000000h Size: 32-bit
10.1.13 RPC—Root Port Configuration Register
Offset Address: 0224–0227h Attribute: R/W, RO Default Value: 0000000yh (y = 00xxb) Size: 32-bit Bit Description 15:10 Reserved 9:4 Negotiated Link Width (NLW)— RO. Negotiated link width is x4 (000100b). 3:0 Link Speed (LS)—RO. Link is 2.5 Gb/s. Bit Description 31:7 Reserved 6 BCR Field 2—R/W. BIOS must set this bit. 5:3 Reserved 2:0 BCR Field 1—R/W. BIOS program this field to 101b Bit Description 31:12 Reserved GBE Over PCIe Root Port Enable (GBEPCIERPEN)—RW. 0 = GbE MAC/PHY communication is not enabled over PCI Express. 1 = The PCI Express port selected by the GBEPCIEPORTSEL register will be used for GbE MAC/PHY over PCI Express communication The default value for this register is set by the GBE_PCIE_EN soft strap. NOTE: GbE and PCIE will use the output of this register and not the soft strap.
Chipset Configuration Registers 10:8 GBE Over PCIe Root Port Select (GBEPCIERPSEL)—RW. If the GBEPCIERPEN is a ‘1’, then this register determines which port is used for GbE MAC/PHY communication over PCI Express. This register is set by soft strap and is writable to support separate PHY on motherboard and docking station. 111 = Port 8 (Lane 7) 110 = Port 7 (Lane 6) 101 = Port 6 (Lane 5) 100 = Port 5 (Lane 4) 011 = Port 4 (Lane 3) 010 = Port 3 (Lane 2) 001 = Port 2 (Lane 1) 000 = Port 1 (Lane 0) The default value for this register is set by the GBE_PCIEPORTSEL[2:0] soft strap. NOTE: GbE and PCIE will use the output of this register and not the soft strap. High Priority Port Enable (HPE)—R/W. 0 = The high priority path is not enabled. 1 = The port selected by the HPP field in this register is enabled for high priority. It will be arbitrated above all other VC0 (including integrated VC0) devices. 6:4 High Priority Port (HPP)—R/W. This controls which port is enabled for high priority when the HPE bit in this register is set. 111 = Port 8 110 = Port 7 101 = Port 6 100 = Port 5 101 = Port 4 010 = Port 3 001 = Port 2 000 = Port 1 3:2 Port Configuration2 (PC2)—RO. This controls how the PCI bridges are organized in various modes of operation for Ports 5-8. For the following mappings, if a port is not shown, it is considered a x1 port with no connection. This bit is set by the PCIEPCS2[1:0] soft strap. 11 = 1 x4, Port 5 (x4) 10 = 2 x2, Port 5 (x2), Port 7 (x2) 01 = 1 x2 and 2 x1s, Port 5 (x2), Port 7 (x1) and Port 8 (x1) 00 = 4 x1s, Port 5 (x1), Port 6 (x1), Port 7 (x1) and Port 8 (x1) This bit is in the resume well and is only reset by RSMRST#. 1:0 Port Configuration (PC)—RO. This controls how the PCI bridges are organized in various modes of operation for Ports 1-4. For the following mappings, if a port is not shown, it is considered a x1 port with no connection. These bits are set by the PCIEPCS1[1:0] soft strap. 11 = 1 x4, Port 1 (x4) 10 = 2 x2, Port 1 (x2), Port 3 (x2) 01 = 1x2 and 2x1s, Port 1 (x2), Port 3 (x1) and Port 4 (x1) 00 = 4 x1s, Port 1 (x1), Port 2 (x1), Port 3 (x1) and Port 4 (x1) These bits are in the resume well and are only reset by RSMRST#. Bit Description
Chipset Configuration Registers
396 Datasheet
10.1.14 DMIC—DMI Control Register
Offset Address: 0234–0237h Attribute: R/W Default Value: 00000000h Size: 32-bit Express* Root Ports Register Offset Address: 0238–023Ch Attribute: R/WO, RO Default Value: 76543210h Size: 32-bit For the PCI Express root ports, the assignment of a function number to a root port is not fixed. BIOS may re-assign the function numbers on a port by port basis. This capability will allow BIOS to disable/hide any root port and still have functions 0 thru N- 1 where N is the total number of enabled root ports. Port numbers will remain fixed to a physical root port. The existing root port Function Disable registers operate on physical ports (not functions). Port Configuration (1x4, 4x1, etc.) is not affected by the logical function number assignment and is associated with physical ports. Bit Description 31:2 Reserved 1:0 DMI Clock Gate Enable (DMICGEN)—R/W. BIOS must program this field to 10b. Bit Description Root Port 8 Config Hide (RP8CH)— RW. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to 1, the root port will not claim any downstream configuration transactions. 30:28 Root Port 8 Function Number (RP8FN)—R/WO. These bits set the function number for PCI Express Root Port 8. This root port function number must be a unique value from the other root port function numbers Root Port 7 Config Hide (RP7CH)—RW. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to 1, the root port will not claim any downstream configuration transactions. 26:24 Root Port 7 Function Number (RP7FN)—R/WO. These bits set the function number for PCI Express Root Port 7. This root port function number must be a unique value from the other root port function numbers Root Port 6 Config Hide (RP6CH)— RW. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to 1, the root port will not claim any downstream configuration transactions. 22:20 Root Port 6 Function Number (RP6FN)—R/WO. These bits set the function number for PCI Express Root Port 6. This root port function number must be a unique value from the other root port function numbers Root Port 5 Config Hide (RP5CH)—RW. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to 1, the root port will not claim any downstream configuration transactions.
Chipset Configuration Registers
10.1.16 FLRSTAT—FLR Pend ing Status Register
Offset Address: 0290–0293h Attribute: RO Default Value: 00000000h Size: 32-bit 18:16 Root Port 5 Function Number (RP5FN)—R/WO. These bits set the function number for PCI Express Root Port 5. This root port function number must be a unique value from the other root port function numbers Root Port 4 Config Hide (RP4CH)—RW. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to 1, the root port will not claim any downstream configuration transactions. 14:12 Root Port 4 Function Number (RP4FN)—R/WO. These bits set the function number for PCI Express Root Port 4. This root port function number must be a unique value from the other root port function numbers Root Port 3 Config Hide (RP3CH)—RW. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to 1, the root port will not claim any downstream configuration transactions. 10:8 Root Port 3 Function Number (RP3FN)—R/WO. These bits set the function number for PCI Express Root Port 3. This root port function number must be a unique value from the other root port function numbers Root Port 2 Config Hide (RP2CH)—RW. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to 1, the root port will not claim any downstream configuration transactions. 6:4 Root Port 2 Function Number (RP2FN)—R/WO. These bits set the function number for PCI Express Root Port 2. This root port function number must be a unique value from the other root port function numbers Root Port 1 Config Hide (RP1CH)—RW. This bit is used to hide the root port and any devices behind it from being discovered by the OS. When set to 1, the root port will not claim any downstream configuration transactions. 2:0 Root Port 1 Function Number (RP1FN)—R/WO. These bits set the function number for PCI Express Root Port 1. This root port function number must be a unique value from the other root port function numbers Bit Description Bit Description 31:17 Reserved FLR Pending Status for D29:F0, EHCI #1— R0. 0 = Function Level Reset is not pending. 1 = Function Level Reset is pending. FLR Pending Status for D26:F0, EHCI #2— R0. 0 = Function Level Reset is not pending. 1 = Function Level Reset is pending. 10:9 Reserved FLR Pending Status for D26:F0, EHCI#2— R0. 0 = Function Level Reset is not pending. 1 = Function Level Reset is pending. 7:0 Reserved
Chipset Configuration Registers
398 Datasheet
10.1.17 CIR5—Chipset Init ialization Register 5
Offset Address: 1D40h–1D47h Attribute: R/W Default Value: 0000000000000000h Size: 64-bit
10.1.18 TRSR—Trap Status Register
Offset Address: 1E00–1E03h Attribute: R/WC, RO Default Value: 00000000h Size: 32-bit
10.1.19 TRCR—Trapped Cycle Register
Offset Address: 1E10–1E17h Attribute: RO Default Value: 0000000000000000h Size: 64-bit This register saves information about the I/O Cycle that was trapped and generated the SMI# for software to read. Bit Description 63:1 Reserved 0 CIR5 Field 1—R/W. BIOS must program this field to 1b. Bit Description 31:4 Reserved 3:0 Cycle Trap SMI# Status (CTSS)—R/WC. These bits are set by hardware when the corresponding Cycle Trap register is enabled and a matching cycle is received (and trapped). These bits are OR’ed together to create a single status bit in the Power Management register space. Note that the SMI# and trapping must be enabled to set these bits. These bits are set before the completion is generated for the trapped cycle, thereby ensuring that the processor can enter the SMI# handler when the instruction completes. Each status bit is cleared by writing a 1 to the corresponding bit location in this register. Bit Description 63:25 Reserved Read/Write# (RWI)—RO. 0 = Trapped cycle was a write cycle. 1 = Trapped cycle was a read cycle. 23:20 Reserved 19:16 Active-high Byte Enables (AHBE)—RO. This is the DWord-aligned byte enables associated with the trapped cycle. A 1 in any bit location indicates that the corresponding byte is enabled in the cycle. 15:2 Trapped I/O Address (TIOA)—RO. This is the DWord- aligned address of the trapped cycle. 1:0 Reserved
Chipset Configuration Registers
10.1.20 TWDR—Trapped Write Data Register
Offset Address: 1E18–1E1Fh Attribute: RO Default Value: 0000000000000000h Size: 64-bit This register saves the data from I/O write cycles that are trapped for software to read.
10.1.21 IOTRn—I/O Trap Register (0–3)
Offset Address: 1E80–1E87h Register 0 Attribute: R/W 1E88–1E8Fh Register 1 1E90–1E97h Register 2 1E98–1E9Fh Register 3 Default Value: 0000000000000000h Size: 64-bit These registers are used to specify the set of I/O cycles to be trapped and to enable this functionality. Bit Description 63:32 Reserved 31:0 Trapped I/O Data (TIOD)—RO. DWord of I/O write data. This field is undefined after trapping a read cycle. Bit Description 63:50 Reserved Read/Write Mask (RWM)—R/W. 0 = The cycle must match the type specified in bit 48. 1 = Trapping logic will operate on both read and write cycles. Read/Write# (RWIO)—R/W. 0 = Write 1 = Read NOTE: The value in this field does not matter if bit 49 is set. 47:40 Reserved 39:36 Byte Enable Mask (BEM)—R/W. A 1 in any bit position indicates that any value in the corresponding byte enable bit in a received cycle will be treated as a match. The corresponding bit in the Byte Enables field, below, is ignored. 35:32 Byte Enables (TBE)—R/W. Active-high DWord- aligned byte enables. 31:24 Reserved 23:18 Address[7:2] Mask (ADMA)—R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for traps on address ranges up to 256 bytes in size. 17:16 Reserved 15:2 I/O Address[15:2] (IOAD)—R/W. DWord-aligned address Trap and SMI# Enable (TRSE)—R/W. 0 = Trapping and SMI# logic disabled. 1 = The trapping logic specified in this register is enabled.
Chipset Configuration Registers
400 Datasheet
10.1.22 DMC—DMI Miscella neous Control Register
Offset Address: 2010–2013h Attribute: R/W Default Value: 00000002h Size: 32-bit
10.1.23 CIR6—Chipset Init ialization Register 6
Offset Address: 2024–2027h Attribute: R/W Default Value: 0B4030C0h Size: 32-bit
10.1.24 DMC2—DMI Miscellane ous Control Register 2
Offset Address: 2324–2327h Attribute: R/W Default Value: 0FFF0FFFh Size: 32-bit Bit Description 31:20 Reserved DMI Misc. Control Field 1—R/W. BIOS shall always program this field. 0 = Disable DMI Power Savings. 1 = Enable DMI Power Savings. 18:0 ReservedBit Description 31:24 (Mobile Only) Reserved 23:21 (Mobile Only) CIR6 Field 2—R/W. BIOS must program this field to 011b. 20:8 (Mobile Only) Reserved 31:8 (Desktop Only) Reserved 7 CIR6 Field 1—R/W. BIOS must clear this bit. 6:0 Reserved Bit Description 31:28 Reserved 27:16 DMI Misc. Control Field 2—R/W. BIOS shall always program this field. 15:0 Reserved
Chipset Configuration Registers
10.1.25 TCTL—TCO Confi guration Register
Offset Address: 3000–3000h Attribute: R/W Default Value: 00h Size: 8-bit Bit Description TCO IRQ Enable (IE)—R/W. 0 = TCO IRQ is disabled. 1 = TCO IRQ is enabled, as selected by the TCO_IRQ_SEL field. 6:3 Reserved 2:0 TCO IRQ Select (IS)—R/W. Specifies on which IRQ the TCO will internally appear. If not using the APIC, the TCO interrupt must be routed to IRQ9–11, and that interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the TCO interrupt can also be mapped to IRQ20–23, and can be shared with other interrupt. 000 = IRQ 9 001 = IRQ 10 010 = IRQ 11 011 = Reserved 100 = IRQ 20 (only if APIC enabled) 101 = IRQ 21 (only if APIC enabled) 110 = IRQ 22 (only if APIC enabled) 111 = IRQ 23 (only if APIC enabled) When setting the these bits, the IE bit should be cleared to prevent glitching. When the interrupt is mapped to APIC interrupts 9, 10, or 11, the APIC should be programmed for active-high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC should be programmed for active-low reception.
Chipset Configuration Registers
402 Datasheet
10.1.26 D31IP—Device 31 In terrupt Pin Register
Offset Address: 3100–3103h Attribute: R/W, RO Default Value: 03243200h Size: 32-bit Bit Description 31:28 Reserved 27:24 Thermal Sensor Pin (TSIP)— R/W. Indicates which pin the Thermal Sensor controller drives as its interrupt 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h–Fh = Reserved 23:20 SATA Pin 2 (SIP2)— R/W. Indicates which pin the SATA controller 2 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h–Fh = Reserved 19:16 Reserved 15:12 SMBus Pin (SMIP)—R/W. Indicates which pin the SM Bus controller drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h–Fh = Reserved 11:8 SATA Pin (SIP)—R/W. Indicates which pin the SATA controller drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h–Fh = Reserved 7:4 Reserved 3:0 LPC Bridge Pin (LIP)—RO. Curr ently, the LPC bridge does not generate an interrupt, so this field is read-only and 0.
Chipset Configuration Registers
10.1.27 D30IP—Device 30 In terrupt Pin Register
Offset Address: 3104–3107h Attribute: RO Default Value: 00000000h Size: 32-bit
10.1.28 D29IP—Device 29 In terrupt Pin Register
Offset Address: 3108–310Bh Attribute: R/W Default Value: 10004321h Size: 32-bit Bit Description 31:4 Reserved 3:0 PCI Bridge Pin (PIP)—RO. Currently, the PCI bridge does not generate an interrupt, so this field is read-only and 0. Bit Description 31:4 Reserved 3:0 EHCI #1 Pin (E1P)—R/W. Indicates which pin the EHCI controller #1 drives as its interrupt, if controller exists. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–7h = Reserved NOTE: EHCI Controller #1 is mapped to Device 29 Function 0 when RMH is enabled.
Chipset Configuration Registers
404 Datasheet
10.1.29 D28IP—Device 28 In terrupt Pin Register
Offset Address: 310C–310Fh Attribute: R/W Default Value: 00214321h Size: 32-bit Bit Description 31:28 PCI Express* #8 Pin (P8IP)—R/W. Indicates which pin th e PCI Express* port #8 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h–7h = Reserved 27:24 PCI Express #7 Pin (P7IP)—R/W. Indicates which pin the PCI Express port #7 drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–7h = Reserved 23:20 PCI Express* #6 Pin (P6IP)—R/W. Indicates which pin th e PCI Express* port #6 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h–7h = Reserved 19:16 PCI Express #5 Pin (P5IP)—R/W. Indicates which pin the PCI Express port #5 drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–7h = Reserved 15:12 PCI Express #4 Pin (P4IP)—R/W. Indicates which pin th e PCI Express* port #4 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# (Default) 5h–7h = Reserved 11:8 PCI Express #3 Pin (P3IP)—R/W. Indicates which pin the PCI Express port #3 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# 3h = INTC# (Default) 4h = INTD# 5h–7h = Reserved
Chipset Configuration Registers
10.1.30 D27IP—Device 27 In terrupt Pin Register
Offset Address: 3110–3113h Attribute: R/W Default Value: 00000001h Size: 32-bit 7:4 PCI Express #2 Pin (P2IP)—R/W. Indicates which pin the PCI Express port #2 drives as its interrupt. 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5h–7h = Reserved 3:0 PCI Express #1 Pin (P1IP)—R/W. Indicates which pin the PCI Express port #1 drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–7h = Reserved Bit Description Bit Description 31:4 Reserved 3:0 Intel® High Definition Audio Pin (ZIP)— R/W. Indicates which pin the Intel® High Definition Audio controller drives as its interrupt. 0h = No interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–Fh = Reserved
Chipset Configuration Registers
406 Datasheet
10.1.31 D26IP—Device 26 In terrupt Pin Register
Offset Address: 3114–3117h Attribute: R/W Default Value: 30000321h Size: 32-bit
10.1.32 D25IP—Device 25 In terrupt Pin Register
Offset Address: 3118–311Bh Attribute: R/W Default Value: 00000001h Size: 32-bit Bit Description 31:4 Reserved 3:0 EHCI #2 Pin (E2P)— R/W. Indicates which pin EHCI controller #2 drives as its interrupt, if controller exists. 0h = No Interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–Fh = Reserve NOTE: EHCI Controller #2 is mapped to Device 26 Function 0 when RMH is enabled and Device 26 function 7 when RMH is disabled. Bit Description 31:4 Reserved 3:0 GBE LAN Pin (LIP)— R/W. Indicates which pin the internal GbE LAN controller drives as its interrupt 0h = No Interrupt 1h = INTA# (Default) 2h = INTB# 3h = INTC# 4h = INTD# 5h–Fh = Reserved
Chipset Configuration Registers
10.1.33 D22IP—Device 22 In terrupt Pin Register
Offset Address: 3124–3127h Attribute: R/W Default Value: 00000001h Size: 32-bit
10.1.34 D31IR—Device 31 In terrupt Route Register
Offset Address: 3140–3141h Attribute: R/W Default Value: 3210h Size: 16-bit Bit Description 31:16 Reserved 15:12 KT Pin (KTIP)— R/W. Indicates which pin the Keyboard text PCI functionality drives as its interrupt 0h = No Interrupt 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# 5h–Fh = Reserved 11:8 IDE-R Pin (IDERIP)— R/W. Indicates which pin the IDE Redirect PCI functionality drives as its interrupt 0h = No Interrupt 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# 5h–Fh = Reserved 7:4 Intel® MEI #2 Pin (MEI2IP)— R/W. Indicates which pin the Management Engine Interface #2 drives as its interrupt 0h = No Interrupt 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# 5h–Fh = Reserved 3:0 Intel® MEI #1 Pin (MEI1IP)— R/W. Indicates which pin the Management Engine Interface controller #1 drives as its interrupt 0h = No Interrupt 1h = INTA# 2h = INTB# 3h = INTC# 4h = INTD# 5h–Fh = Reserved Bit Description
15 Reserved
Chipset Configuration Registers
408 Datasheet
10.1.35 D30IR—Device 30 In terrupt Route Register
Offset Address: 3142–3143h Attribute: RO Default Value: 0000h Size: 16-bit 14:12 Interrupt D Pin Route (IDR)—R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 31 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#
11 Reserved
10:8 Interrupt C Pin Route (ICR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTC# pin reported for device 31 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 6:4 Interrupt B Pin Route (IBR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTB# pin reported for device 31 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#
3 Reserved
2:0 Interrupt A Pin Route (IAR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTA# pin reported for device 31 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# Bit Description Bit Description 15:0 Reserved. No interrupt s generated from Device 30.
Chipset Configuration Registers
10.1.36 D29IR—Device 29 In terrupt Route Register
Offset Address: 3144–3145h Attribute: R/W Default Value: 3210h Size: 16-bit Bit Description 14:12 Interrupt D Pin Route (IDR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTD# pin reported for device 29 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 10:8 Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is connected to the INTC# pin reported for device 29 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 6:4 Interrupt B Pin Route (IBR)—R/W. Indicates which physical pin on the PCH is connected to the INTB# pin reported for device 29 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 2:0 Interrupt A Pin Route (IAR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTA# pin reported for device 29 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#
Chipset Configuration Registers
410 Datasheet
10.1.37 D28IR—Device 28 In terrupt Route Register
Offset Address: 3146–3147h Attribute: R/W Default Value: 3210h Size: 16-bit Bit Description 14:12 Interrupt D Pin Route (IDR)—R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 28 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 10:8 Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is connected to the INTC# pin reported for device 28 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 6:4 Interrupt B Pin Route (IBR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTB# pin reported for device 28 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 2:0 Interrupt A Pin Route (IAR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTA# pin reported for device 28 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#
Chipset Configuration Registers
10.1.38 D27IR—Device 27 In terrupt Route Register
Offset Address: 3148–3149h Attribute: R/W Default Value: 3210h Size: 16-bit Bit Description 14:12 Interrupt D Pin Route (IDR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTD# pin reported for device 27 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 10:8 Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is connected to the INTC# pin reported for device 27 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 6:4 Interrupt B Pin Route (IBR)—R/W. Indicates which physical pin on the PCH is connected to the INTB# pin reported for device 27 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 2:0 Interrupt A Pin Route (IAR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTA# pin reported for device 27 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#
Chipset Configuration Registers
412 Datasheet
10.1.39 D26IR—Device 26 In terrupt Route Register
Offset Address: 314C–314Fh Attribute: R/W Default Value: 3210h Size: 16-bit Bit Description 14:12 Interrupt D Pin Route (IDR)— R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 26 functions: 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 10:8 Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is connected to the INTC# pin reported for device 26 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 6:4 Interrupt B Pin Route (IBR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTB# pin reported for device 26 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 2:0 Interrupt A Pin Route (IAR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTA# pin reported for device 26 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#
Chipset Configuration Registers
10.1.40 D25IR—Device 25 In terrupt Route Register
Offset Address: 3150–3151h Attribute: R/W Default Value: 3210h Size: 16-bit Bit Description 14:12 Interrupt D Pin Route (IDR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTD# pin reported for device 25 functions: 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 10:8 Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is connected to the INTC# pin reported for device 25 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 6:4 Interrupt B Pin Route (IBR)—R/W. Indicates which physical pin on the PCH is connected to the INTB# pin reported for device 25 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 2:0 Interrupt A Pin Route (IAR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTA# pin reported for device 25 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#
Chipset Configuration Registers
414 Datasheet
10.1.41 D24IR—Device 24 In terrupt Route Register
Offset Address: 3154–3155h Attribute: R/W Default Value: 3210h Size: 16-bit Bit Description 14:12 Interrupt D Pin Route (IDR)—R/W. Indicates which physical pin on the PCH is connected to the INTD# pin reported for device 24 functions: 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 10:8 Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is connected to the INTC# pin reported for device 24 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 6:4 Interrupt B Pin Route (IBR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTB# pin reported for device 24 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 2:0 Interrupt A Pin Route (IAR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTA# pin reported for device 24 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#
Chipset Configuration Registers
10.1.42 D22IR—Device 22 In terrupt Route Register
Offset Address: 315C–315Fh Attribute: R/W Default Value: 3210h Size: 16-bit Bit Description 14:12 Interrupt D Pin Route (IDR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTD# pin reported for device 22 functions: 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# (Default) 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 10:8 Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is connected to the INTC# pin reported for device 22 functions. 0h = PIRQA# 1h = PIRQB# 2h = PIRQC# (Default) 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 6:4 Interrupt B Pin Route (IBR)—R/W. Indicates which physical pin on the PCH is connected to the INTB# pin reported for device 22 functions. 0h = PIRQA# 1h = PIRQB# (Default) 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH# 2:0 Interrupt A Pin Route (IAR)—R/W. Indicates which phys ical pin on the PCH is connected to the INTA# pin reported for device 22 functions. 0h = PIRQA# (Default) 1h = PIRQB# 2h = PIRQC# 3h = PIRQD# 4h = PIRQE# 5h = PIRQF# 6h = PIRQG# 7h = PIRQH#
Chipset Configuration Registers
416 Datasheet
10.1.43 OIC—Other Interrupt Control Register
Offset Address: 31FE–31FFh Attribute: R/W Default Value: 0000h Size: 16-bit NOTE: FEC10000h–FEC4FFFFh is allocated to PCIe when I/OxApic Enable (PAE) bit is set. Bit Description 15:10 Reserved Coprocessor Error Enable (CEN)—R/W. 0 = FERR# will not generate IRQ13 nor IGNNE#. 1 = If FERR# is low, the PCH generates IRQ13 internally and holds it until an I/O port F0h write. It will also drive IGNNE# active. APIC Enable (AEN)—R/W. 0 = The internal IOxAPIC is disabled. 1 = Enables the internal IOxAPIC and its address decode. NOTE: Software should read this register after modifying APIC enable bit prior to access to the IOxAPIC address range. 7:0 APIC Range Select (ASEL)— R/W.These bits define address bits 19:12 for the IOxAPIC range. The default value of 00h enables compatibility with prior PCH products as an initial value. This value must not be changed unless the IOxAPIC Enable bit is cleared.
Chipset Configuration Registers
10.1.44 PRSTS—Power and Reset Status
Offset Address: 3310–3313h Attribute: RO, R/WC Default Value: 02020000h Size: 32-bit
10.1.45 CIR7—Chipset Init alization Register 7
Offset Address: 3314–3317h Attribute: R/W Default Value: 00000000h Size: 32-bit Bit Description 31:16 Reserved 15 Power Management Watchdog Timer—R/WC. This bit is set when the Power Management watchdog timer causes a global reset. 14:7 Reserved 6 Intel® Management Engine Watchdog Timer Status—R/WC. This bit is set when the Intel Management Engine watchdog timer causes a global reset. Wake On Lan Override Wake Status (WOL_OVR_WK_STS)—R/WC. This bit gets set when all of the following conditions are met:
- Integrated LAN Signals a Power Management Event
- The system is not in S0
- The “WOL Enable Override” bit is set in configuration space. BIOS can read this status bit to determine this wake source. Software clears this bit by writing a 1 to it.
3 ME Host Power Down (ME_HOST_PWRDN)— R/WC.This bit is set when the Intel Management Engine generates a host reset with power down. ME Host Reset Warm Status (ME_HRST_WARM_STS)—R/WC. This bit is set when the Intel ® Management Engine generates a Host reset without power cycling. Software clears this bit by writing a 1 to this bit position. ME Host Reset Cold Status (ME_HRST_COLD_STS)—R/WC. This bit is set when the Intel Management Engine generates a Host reset with power cycling. Software clears this bit by writing a 1 to this bit position. ME WAKE STATUS (ME_WAKE_STS)—R/WC. This bit is set when the Intel Management Engine generates a Non-Maskable wake event, and is not affected by any other enable bit. When this bit is set, the Host Power Management logic wakes to S0. Bit Description 31:4 Reserved 3:0 CIR7 Field 1—R/W. BIOS must program this field to 1111b.
Chipset Configuration Registers
418 Datasheet
10.1.46 CIR8—Chipset Init ialization Register 8
Offset Address: 3324–3327h Attribute: R/W Default Value: 00000000h Size: 32-bit
10.1.47 CIR9—Chipset Init ialization Register 9
Offset Address: 3330–3333h Attribute: R/W Default Value: 00000000h Size: 32-bit
10.1.48 CIR10—Chipset Initialization Register 10
Offset Address: 3340–3343h Attribute: R/W Default Value: 00000000h Size: 32-bit
10.1.49 CIR13—Chipset Initialization Register 13
Offset Address: 3350–3353h Attribute: R/W Default Value: 00000000h Size: 32-bit
10.1.50 CIR14—Chipset Initialization Register 14
Offset Address: 3368–336Bh Attribute: R/W Default Value: 00000000h Size: 32-bit Bit Description 31:0 CIR8 Field 1— R/W. BIOS must program this field to 04000000h. Bit Description 31:0 CIR9 Field 1— R/W. BIOS must program this field to 00000000h. Bit Description 31:0 CIR10 Field 1— R/W. BIOS must program this field to 00000000h for Intel® Core™ i5 processor-based systems. Bit Description 31:0 CIR13 Field 1— R/W. BIOS must program this field to 000FFFFFh for Intel® Core™ i5 processorbased systems. Bit Description 31:0 CIR14 Field 1— R/W. BIOS must program this field to 00061080h for Intel® Core™ i5 processor-based systems.
Chipset Configuration Registers
10.1.51 CIR15—Chipset Init ialization Register 15
Offset Address: 3378–337Bh Attribute: R/W Default Value: 00000000h Size: 32-bit
10.1.52 CIR16—Chipset Init ialization Register 16
Offset Address: 3388–338Bh Attribute: R/W Default Value: 00000000h Size: 32-bit
10.1.53 CIR17—Chipset Init ialization Register 17
Offset Address: 33A0–33A3h Attribute: R/W Default Value: 00000000h Size: 32-bit
10.1.54 CIR18—Chipset Init ialization Register 18
Offset Address: 33A8–33ABh Attribute: R/W Default Value: 00000000h Size: 32-bit
10.1.55 CIR19—Chipset Init ialization Register 19
Offset Address: 33C0–33C3h Attribute: R/W Default Value: 00000000h Size: 32-bit Bit Description 31:0 CIR15 Field 1— R/W. BIOS must program this field to 00000000h for Intel® Core™ i5 processor-based systems. Bit Description 31:0 CIR16 Field 1— R/W. BIOS must program this field to 7F8F9F80h for Intel® Core™ i5 processor-based systems. Bit Description 31:0 CIR17 Field 1— R/W. BIOS must program this field to 00000000h for Intel® Core™ i5 processor-based systems. Bit Description 31:0 CIR18 Field 1— R/W. BIOS must program this field to 00003900 for Intel® Core™ i5 processor-based systems. Bit Description 31:0 CIR19 Field 1— R/W. BIOS must program this field to 00020002h for Intel® Core™ i5 processor-based systems.
Chipset Configuration Registers
420 Datasheet
10.1.56 CIR20—Chipset Initialization Register 20
Offset Address: 33CC–33CFh Attribute: R/W Default Value: 00000000h Size: 32-bit
10.1.57 CIR21—Chipset Initialization Register 21
Offset Address: 33D0–33D3h Attribute: R/W Default Value: 00000000h Size: 32-bit
10.1.58 CIR22—Chipset Initialization Register 22
Offset Address: 33D4–33D7h Attribute: R/W Default Value: 00000000h Size: 32-bit Bit Description 31:0 CIR20 Field 1— R/W. BIOS must program this field to 00044B00h for Intel® Core™ i5 processor-based systems. Bit Description 31:0 CIR21 Field 1— R/W. BIOS must program this field to 00002000h for Intel® Core™ i5 processor-based systems. Bit Description 31:0 CIR22 Field 1— R/W. BIOS must program this field to 00020000h for Intel® Core™ i5 processor-based systems. Program this register after all registers in the 3330-33D3 range and D31:F0:A9h are already programmed.
Chipset Configuration Registers
10.1.59 RC—RTC Conf iguration Register
Offset Address: 3400–3403h Attribute: R/W, R/WLO Default Value: 00000000h Size: 32-bit
10.1.60 HPTC—High Precision Ti mer Configuration Register
Offset Address: 3404–3407h Attribute: R/W Default Value: 00000000h Size: 32-bit Bit Description 31:5 Reserved Upper 128 Byte Lock (UL)—R/WLO. 0 = Bytes not locked. 1 = Bytes 38h–3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be accessed. Writes will be dropped and reads will not return any ensured data. Bit reset on system reset. Lower 128 Byte Lock (LL)—R/WLO. 0 = Bytes not locked. 1 = Bytes 38h–3Fh in the lower 128-byte bank of RTC RAM are locked and cannot be accessed. Writes will be dropped and reads will not return any ensured data. Bit reset on system reset. Upper 128 Byte Enable (UE)—R/W. 0 = Bytes locked. 1 = The upper 128-byte bank of RTC RAM can be accessed. 1:0 Reserved Bit Description 31:8 Reserved Address Enable (AE)—R/W. 0 = Address disabled. 1 = The PCH will decode the High Precision Timer memory address range selected by bits 1:0 below. 6:2 Reserved 1:0 Address Select (AS)—R/W. This 2-bit field selects 1 of 4 possible memory address ranges for the High Precision Timer functionality. The encodings are: 00 = FED0_0000h–FED0_03FFh 01 = FED0_1000h–FED0_13FFh 10 = FED0_2000h–FED0_23FFh 11 = FED0_3000h–FED0_33FFh
Chipset Configuration Registers
422 Datasheet
10.1.61 GCS—General Control and Status Register
Offset Address: 3410–3413h Attribute: R/W, R/WLO Default Value: 00000yy0h (yy = xx0000x0b)Size: 32-bit Bit Description 31:13 Reserved Function Level Reset Capability Structure Select (FLRCSSEL)—R/W. 0 = Function Level Reset (FLR) will use the standard capability structure with unique capability ID assigned by PCISIG. 1 = Vendor Specific Capability Structure is selected for FLR. 11:10 Boot BIOS Straps (BBS)— R/W. This field determines the destination of accesses to the BIOS memory range. The default values for these bits represent the strap values of GNT1# /GPIO51 (bit 11) at the rising edge of PWROK and GNT0# (bit 10) at the rising edge of PWROK. When PCI is selected, the top 16 MB of memory below 4 GB (FF00_0000h to FFFF_FFFFh) is accepted by the primary side of the PCI P2P bridge and forwarded to the PCI bus. This allows systems with corrupted or unprogrammed flash to boot from a PCI device. The PCI-to-PCI bridge Memory Space Enable bit does not need to be set (nor any other bits) for these cycles to go to PCI. Note that BIOS decode range bits and the other BIOS protection bits have no effect when PCI is selected. This functionality is intended for debug/testing only. When SPI or LPC is selected, the range that is decoded is further qualified by other configuration bits described in the respective sections. The value in this field can be overwritten by software as long as the BIOS Interface Lock-Down (bit 0) is not set. NOTE: Booting to PCI is intended for debug/testing only. Boot BIOS Destination Select to LPC/PCI by functional strap or using Boot BIOS Destination Bit will not affect SPI accesses initiated by Intel® Management Engine or Integrated GbE LAN. Server Error Reporting Mode (SERM)—R/W. 0 = The PCH is the final target of all errors. The Processor sends a messages to the PCH for the purpose of generating NMI. 1 = The Processor is the final target of all errors from PCI Express* and DMI. In this mode, if the PCH detects a fatal, non-fatal, or correctable error on DMI or its downstream ports, it sends a message to the Processor. If the PCH receives an ERR_* message from the downstream port, it sends that message to the Processor. 8:7 Reserved FERR# MUX Enable (FME)—R/W. This bit enables FERR # to be a processor break event indication. 0 = Disabled. 1 = The PCH examines FERR# during a C2, C3, or C4 state as a break event. See Chapter 5.13.4 for a functional description. Bits 11:10 Description 00b LPC
01 RESERVED
Chipset Configuration Registers No Reboot (NR)—R/W. This bit is set when the “No Reboot” strap (SPKR pin on the PCH) is sampled high on PWROK. This bit may be set or cleared by software if the strap is sampled low but may not override the strap when it indicates “No Reboot”. 0 = System will reboot upon the second timeout of the TCO timer. 1 = The TCO timer will count down and generate the SMI# on the first timeout, but will not reboot on the second timeout. Alternate Access Mode Enable (AME)—R/W. 0 = Disabled. 1 = Alternate access read only registers can be written, and write only registers can be read. Before entering a low power state, several registers from powered down parts may need to be saved. In the majority of cases, this is not an issue, as registers have read and write paths. However, several of the ISA compatible registers are either read only or write only. To get data out of write-only registers, and to restore data into read-only registers, the PCH implements an alternate access mode. For a list of these registers see Section 5.13.10. Shutdown Policy Select (SPS)—R/W. 0 = PCH will drive INIT# in response to the shutdown Vendor Defined Message (VDM). (default) 1 = PCH will treat the shutdown VDM similar to receiving a CF9h I/O write with data value06h, and will drive PLTRST# active. Reserved Page Route (RPR)—R/W. Determines where to send the reserved page registers. These addresses are sent to PCI or LPC for the purpose of generating POST codes. The I/O addresses modified by this field are: 80h, 84h, 85h, 86h, 88h, 8Ch, 8Dh, and 8Eh. 0 = Writes will be forwarded to LPC, shadowed within the PCH, and reads will be returned from the internal shadow 1 = Writes will be forwarded to PCI, shadowed within the PCH, and reads will be returned from the internal shadow. NOTE: if some writes are done to LPC/PCI to these I/O ranges, and then this bit is flipped, such that writes will now go to the other interface, the reads will not return what was last written. Shadowing is performed on each interface. The aliases for these registers, at 90h, 94h, 95h, 96h, 98h, 9Ch, 9Dh, and 9Eh, are always decoded to LPC. BIOS Interface Lock-Down (BILD)—R/WLO. 0 = Disabled. 1 = Prevents BUC.TS (offset 3414, bit 0) and GCS.BBS (offset 3410h, bits 11:10) from being changed. This bit can only be written from 0 to 1 once. Bit Description
Chipset Configuration Registers
424 Datasheet
10.1.62 BUC—Backed Up Control Register
Offset Address: 3414–3414h Attribute: R/W Default Value: 0000000xb Size: 8-bit All bits in this register are in the RTC well and only cleared by RTCRST# Bit Description 7:6 Reserved LAN Disable— R/W. 0 = LAN is Enabled 1 = LAN is Disabled. Changing the internal GbE controller from disabled to enabled requires a system reset (write of 0Eh to CF9h (RST_CNT Register)) immediately after clearing the LAN disable bit. A reset is not required if changing the bit from enabled to disabled. This bit is locked by the Function Disable SUS Well Lockdown register. Once locked this bit can not be changed by software. Daylight Savings Override (SDO)— R/W. 0 = Daylight Savings is Enabled. 1 = The DSE bit in RTC Register B is set to Read-only with a value of 0 to disable daylight savings. 3:1 Reserved Top Swap (TS)—R/W. 0 = PCH will not invert A16. 1 = PCH will invert A16, A17, or A18 for cycles going to the BIOS space . If booting from LPC (FWH), then the boot-block size is 64 KB and A16 is inverted if Top Swap is enabled. If booting from SPI, then the BIOS Boot-Block size soft strap determines if A16, A17, or A18 should be inverted if Top Swap is enabled. If PCH is strapped for Top-Swap (GNT3#/GPIO55 is low at rising edge of PWROK), then this bit cannot be cleared by software. The strap jumper should be removed and the system rebooted.
Chipset Configuration Registers
10.1.63 FD—Function Disable Register
Offset Address: 3418–341Bh Attribute: R/W Default Value: See bit description Size: 32-bit When disabling a function, only the configuration space is disabled. Software must ensure that all functionality within a controller that is not desired (such as memory spaces, I/O spaces, and DMA engines) is disabled prior to disabling the function. When a function is disabled, software must not attempt to re-enable it. A disabled function can only be re-enabled by a platform reset. Bit Description 31:26 Reserved Serial ATA Disable 2 (SAD2)— R/W. Default is 0. 0 = The SATA controller #2 (D31:F5) is enabled. 1 = The SATA controller #2 (D31:F5) is disabled. Thermal Sensor Registers Disable (TTD)— R/W. Default is 0. 0 = Thermal Sensor Registers (D31:F6) are enabled. 1 = Thermal Sensor Registers (D31:F6) are disabled. PCI Express* 8 Disable (PE8D)—R/W. Default is 0. When disabled, the link for this port is put into the “link down” state. 0 = PCI Express* port #8 is enabled. 1 = PCI Express port #8 is disabled. PCI Express 7 Disable (PE7D)—R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express port #7 is enabled. 1 = PCI Express port #7 is disabled. PCI Express* 6 Disable (PE6D)—R/W. Default is 0. When disabled, the link for this port is put into the “link down” state. 0 = PCI Express* port #6 is enabled. 1 = PCI Express port #6 is disabled. PCI Express 5 Disable (PE5D)—R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express port #5 is enabled. 1 = PCI Express port #5 is disabled. PCI Express 4 Disable (PE4D)—R/W. Default is 0. When disabled, the link for this port is put into the “link down” state. 0 = PCI Express port #4 is enabled. 1 = PCI Express port #4 is disabled. NOTE: This bit must be set when Port 1 is configured as a x4. PCI Express 3 Disable (PE3D)—R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express port #3 is enabled. 1 = PCI Express port #3 is disabled. NOTE: This bit must be set when Port 1 is configured as a x4. PCI Express 2 Disable (PE2D)—R/W. Default is 0. When disabled, the link for this port is put into the link down state. 0 = PCI Express port #2 is enabled. 1 = PCI Express port #2 is disabled. NOTE: This bit must be set when Port 1 is configured as a x4 or a x2.
Chipset Configuration Registers
426 Datasheet
PCI Express 1 Disable (PE1D)—R/W. Default is 0. When di sabled, the link for this port is put into the link down state. 0 = PCI Express port #1 is enabled. 1 = PCI Express port #1 is disabled. EHCI #1 Disable (EHCI1D)—R/W. Default is 0. 0 = The EHCI #1 is enabled. 1 = The EHCI #1 is disabled. LPC Bridge Disable (LBD)—R/W. Default is 0. 0 = The LPC bridge is enabled. 1 = The LPC bridge is disabled. Unlike the other disables in this register, the following additional spaces will no longer be decoded by the LPC bridge:
- · Memory cycles below 16 MB (1000000h)
- · I/O cycles below 64 KB (10000h)
- · The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF Memory cycle in the LPC BIOS range below 4 GB will still be decoded when this bit is set; however, the aliases at the top of 1 MB (the E and F segment) no longer will be decoded. EHCI #2 Disable (EHCI2D)—R/W. Default is 0. 0 = The EHCI #2 is enabled. 1 = The EHCI #2 is disabled. 12:5 Reserved Intel ® High Definition Audio Disable (HDAD)—R/W. Default is 0. 0 = The Intel® High Definition Audio controller is enabled. 1 = The Intel® High Definition Audio controller is disabled and its PCI configuration space is not accessible. SMBus Disable (SD)—R/W. Default is 0. 0 = The SMBus controller is enabled. 1 = The SMBus controller is disabled. Setting this bit only disables the PCI configuration space. Serial ATA Disable 1 (SAD1)—R/W. Default is 0. 0 = The SATA controller #1 (D31:F2) is enabled. 1 = The SATA controller #1 (D31:F2) is disabled.
0 BIOS must set this bit to 1b. Bit Description
Chipset Configuration Registers
10.1.64 CG—Clock Gating Register
Offset Address: 341C–341Fh Attribute: R/W Default Value: 00000000h Size: 32-bit Bit Description Legacy (LPC) Dynamic Clock Gate Enable— R/W. 0 = Legacy Dynamic Clock Gating is Disabled 1 = Legacy Dynamic Clock Gating is Enabled
30 Reserved
29.28 CG Field 1—R/W. BIOS must program this field to 11b. SATA Port 3 Dynamic Clock Gate Enable— R/W. 0 = SATA Port 3 Dynamic Clock Gating is Disabled 1 = SATA Port 3 Dynamic Clock Gating is Enabled SATA Port 2 Dynamic Clock Gate Enable— R/W. 0 = SATA Port 2 Dynamic Clock Gating is Disabled 1 = SATA Port 2 Dynamic Clock Gating is Enabled SATA Port 1 Dynamic Clock Gate Enable— R/W. 0 = SATA Port 1 Dynamic Clock Gating is Disabled 1 = SATA Port 1 Dynamic Clock Gating is Enabled SATA Port 0 Dynamic Clock Gate Enable— R/W. 0 = SATA Port 0 Dynamic Clock Gating is Disabled 1 = SATA Port 0 Dynamic Clock Gating is Enabled LAN Static Clock Gating Enable (LANSCGE)— R/W. 0 = LAN Static Clock Gating is Disabled 1 = LAN Static Clock Gating is Enabled when the LAN Disable bit is set in the Backed Up Control RTC register. High Definition Audio Dynamic Clock Gate Enable— R/W. 0 = High Definition Audio Dynamic Clock Gating is Disabled 1 = High Definition Audio Dynamic Clock Gating is Enabled High Definition Audio Static Clock Gate Enable— R/W. 0 = High Definition Audio Static Clock Gating is Disabled 1 = High Definition Audio Static Clock Gating is Enabled USB EHCI Static Clock Gate Enable— R/W. 0 = USB EHCI Static Clock Gating is Disabled 1 = USB EHCI Static Clock Gating is Enabled USB EHCI Dynamic Clock Gate Enable— R/W. 0 = USB EHCI Dynamic Clock Gating is Disabled 1 = USB EHCI Dynamic Clock Gating is Enabled SATA Port 5 Dynamic Clock Gate Enable— R/W. 0 = SATA Port 5 Dynamic Clock Gating is Disabled 1 = SATA Port 5 Dynamic Clock Gating is Enabled SATA Port 4 Dynamic Clock Gate Enable— R/W. 0 = SATA Port 4 Dynamic Clock Gating is Disabled 1 = SATA Port 4 Dynamic Clock Gating is Enabled PCI Dynamic Gate Enable— R/W. 0 = PCI Dynamic Gating is Disabled 1 = PCI Dynamic Gating is Enabled 15:6 Reserved
Chipset Configuration Registers
428 Datasheet
10.1.65 FDSW—Function Disa ble SUS Well Register
Offset Address: 3420h Attribute: R/W Default Value: 00h Size: 8-bit
10.1.66 FD2—Function Disable 2 Register
Offset Address: 3428–342Bh Attribute: R/W Default Value: 00000000h Size: 32-bit SMBus Clock Gating Enable (SMBCGEN)— R/W. 0 = SMBus Clock Gating is Disabled. 1 = SMBus Clock Gating is Enabled. 4:1 Reserved PCI Express Root Port Static Clock Gate Enable— R/W. 0 = PCI Express root port Static Clock Gating is Disabled 1 = PCI Express root port Static Clock Gating is Enabled Bit Description Bit Description Function Disable SUS Well Lockdown (FDSWL)—R/W 0 = FDSW registers are not locked down 1 = FDSW registers are locked down NOTE: This bit must be set when Intel ® Active Management Technology is enabled. 6:0 Reserved Bit Description 31:5 Reserved KT Disable (KTD)— R/W. Default is 0. 0 = Keyboard Text controller (D22:F3) is enabled. 1 = Keyboard Text controller (D22:F3) is Disabled IDE-R Disable (IRERD)— R/W. Default is 0. 0 = IDE Redirect controller (D22:F2) is Enabled. 1 = IDE Redirect controller (D22:F2) is Disabled. Intel ® MEI #2 Disable (MEI2D)— R/W. Default is 0. 0 = Intel® MEI controller #2 (D22:F1) is enabled. 1 = Intel® MEI controller #2 (D22:F1) is disabled. Intel® MEI #1 Disable (MEI1D)— R/W. Default is 0. 0 = Intel® MEI controller #1 (D22:F0) is enabled. 1 = Intel® MEI controller #1 (D22:F0) is disabled.
Chipset Configuration Registers
10.1.67 MISCCTL—Miscellaneous Control Register
Offset Address: 3590–3593h Attribute: R/W Default Value: 00000000h Size: 32-bit This register is in the suspend well. This register is not reset on D3-to-D0, HCRESET nor core well reset. Bit Description 31:2 Reserved EHCI 2 USBR Enable— R/W. When set, this bit enables support for the USB-r redirect device on the EHCI controller in Device 26. SW must complete programming the following registers before this bit is set: 1. Enable RMH 2. HCSPARAMS (N_CC, N_Ports) EHCI 1 USBR Enable— R/W. When set, this bit enables support for the USB-r redirect device on the EHCI controller in Device 29. SW must complete programming the following registers before this bit is set: 1. Enable RMH 2. HCSPARAMS (N_CC, N_Ports)
Chipset Configuration Registers
430 Datasheet
10.1.68 USBOCM1—Overcurre nt MAP Register 1
Offset Address: 35A0–35A3h Attribute: R/W0 Default Value: C0300C03h Size: 32-bit All bits in this register are in the Resume Well and is only cleared by RSMRST#. Bit Description 31:24 OC3 Mapping Each bit position maps OC3# to a set of ports as follows: The OC3# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given port‘s bit map is set only for one OC pin. 23:16 OC2 Mapping Each bit position maps OC2# to a set of ports as follows: The OC2# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given port‘s bit map is set only for one OC pin. 15:8 OC1 Mapping Each bit position maps OC1# to a set of ports as follows: The OC1# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given port‘s bit map is set only for one OC pin. 7:0 OC0 Mapping Each bit position maps OC0# to a set of ports as follows: The OC0# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given port‘s bit map is set only for one OC pin. Bit 31 30 29 28 27 26 25 24 Port 76543210 Bit 23 22 21 20 19 18 17 16 Port 76543210 Bit 15 14 13 12 11 10 9 8 Port 76543210 Bit 76543210 Port 76543210
Chipset Configuration Registers
10.1.69 USBOCM2—Overcurr ent MAP Register 2
Offset Address: 35A4–35A7h Attribute: R/W0 Default Value: 00h Size: 32-bit All bits in this register are in the Resume Well and is only cleared by RSMRST# Bit Description 31:30 Reserved 29:24 OC7 Mapping Each bit position maps OC7# to a set of ports as follows: The OC7# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given port‘s bit map is set only for one OC pin. 23:22 Reserved 21:16 OC6 Mapping Each bit position maps OC6# to a set of ports as follows: The OC6# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given port‘s bit map is set only for one OC pin. 15:14 Reserved 13:8 OC5 Mapping Each bit position maps OC5# to a set of ports as follows: The OC5# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given port‘s bit map is set only for one OC pin. 7:6 Reserved 5:0 OC4 Mapping Each bit position maps OC4# to a set of ports as follows: The OC4# pin is ganged to the overcurrent signal of each port that has its corresponding bit set. It is software responsibility to ensure that a given port‘s bit map is set only for one OC pin. Bit 29 28 27 26 25 24 Port 13 12 11 10 9 8 Bit 21 20 19 18 17 16 Port 13 12 11 10 9 8 Bit 13 12 11 10 9 8 Port 13 12 11 10 9 8 Bit 543210 Port 13 12 11 10 9 8
Chipset Configuration Registers
432 Datasheet
10.1.70 RMHWKCTL—Rate Matching Hub Wake Control Register
Offset Address: 35B0–35B3h Attribute: R/W Default Value: 00000000h Size: 32-bit All bits in this register are in the Resume Well and is only cleared by RSMRST#. Bit Description 31:10 Reserved RMH 2 Inherit EHCI2 Wake Control Settings: When this bit is set, the RMH behaves as if bits 6:4 of this register reflect the appropriate bits of EHCI PORTSC0 bits 22:20. RMH 1 Inherit EHCI1 Wake Control Settings: When this bit is set, the RMH behaves as if bits 2:0 of this register reflect the appropriate bits of EHCI PORTSC0 bits 22:20. RMH 2 Upstream Wake on Device Resume This bit governs the hub behavior when globally suspended and the system is in Sx. 0 = Enables the port to be sensitive to device initiated resume events as system wake-up events. That is, the hub will initiate a resume on its upstream port and cause a wake from Sx when a device resume occurs on an enabled DS port 1 = Device resume event is seen on a downstream port, the hub does not initiate a wake upstream and does not cause a wake from Sx RMH 2 Upstream Wake on OC Disable This bit governs the hub behavior when globally suspended and the system is in Sx. 0 = Enables the port to be sensitive to over-current conditions as system wake-up events. That is, the hub will initiate a resume on its upstream port and cause a wake from Sx when an OC condition occurs on an enabled DS port 1 = Over-current event does not initiate a wake upstream and does not cause a wake from Sx RMH 2 Upstream Wake on Disconnect Disable This bit governs the hub behavior when globally suspended and the system is in Sx 0 = Enables disconnect events on downstream port to be treated as resume events to be propagated upstream. In this case, it is allowed to initiate a wake on its upstream port and cause a system wake from Sx in response to a disconnect event on a downstream port 1 = Downstream disconnect events do not initiate a resume on its upstream port or cause a resume from Sx. RMH 2 Upstream Wake on Connect Enable This bit governs the hub behavior when globally suspended and the system is in Sx. 0 = Enables connect events on a downstream port to be treated as resume events to be propagated upstream. As well as waking up the system from Sx. 1 = Downstream connect events do not wake the system from Sx nor does it initiate a resume on its upstream port. RMH 1 Upstream Wake on Device Resume This bit governs the hub behavior when globally suspended and the system is in Sx. 0 = Enables the port to be sensitive to device initiated resume events as system wake-up events. That is, the hub will initiate a resume on its upstream port and cause a wake from Sx when a device resume occurs on an enabled DS port 1 = Device resume event is seen on a downstream port, the hub does not initiate a wake upstream and does not cause a wake from Sx
Chipset Configuration Registers § § RMH 1 Upstream Wake on OC Disable This bit governs the hub behavior when globally suspended and the system is in Sx. 0 = Enables the port to be sensitive to over-current conditions as system wake-up events. That is, the hub will initiate a resume on its upstream port and cause a wake from Sx when an OC condition occurs on an enabled DS port 1 = Over-current event does not initiate a wake upstream and does not cause a wake from Sx RMH 1 Upstream Wake on Disconnect Disable This bit governs the hub behavior when globally suspended and the system is in Sx 0 = Enables disconnect events on downstream port to be treated as resume events to be propagated upstream. In this case, it is allowed to initiate a wake on its upstream port and cause a system wake from Sx in response to a disconnect event on a downstream port 1 = Downstream disconnect events do not initiate a resume on its upstream port or cause a resume from Sx. RMH 1 Upstream Wake on Connect Enable This bit governs the hub behavior when globally suspended and the system is in Sx. 0 = Enables connect events on a downstream port to be treated as resume events to be propagated upstream. As well as waking up the system from Sx. 1 = Downstream connect events do not wake the system from Sx nor does it initiate a resume on its upstream port. Bit Description
Chipset Configuration Registers
434 Datasheet
PCI-to-PCI Bridge Registers (D30:F0)
11 PCI-to-PCI Bridge Registers
(D30:F0) The PCH PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements the buffering and control logic between PCI and the backbone. The arbitration for the PCI bus is handled by this PCI device.
11.1 PCI Configuration Registers (D30:F0)
Note: Address locations that are not shown should be treated as Reserved (see Section 9.2 for details). Table 11-1. PCI Bridge Register Address Map (PCI-PCI—D30:F0) Offset Mnemonic Register Name Default Type 00h–01h VID Vendor Identification 8086h RO 02h–03h DID Device Identification See register description RO 04h–05h PCICMD PCI Command 0000h R/W, RO 06h–07h PSTS PCI Status 0010h R/WC, RO 08h RID Revision Identification See register description RO 09h–0Bh CC Class Code 060401h RO 0Dh PMLT Primary Master Latency Timer 00h RO 0Eh HEADTYP Header Type 01h RO 18h–1Ah BNUM Bus Number 000000h RO 1Bh SMLT Secondary Master Latency Timer 00h R/W 1Ch–1Dh IOBASE_LIMIT I/O Ba se and Limit 0000h R/W, RO 1Eh–1Fh SECSTS Secondary Status 0280h R/WC, RO 20h–23h MEMBASE_ LIMIT Memory Base and Limit 00000000h R/W 24h–27h PREF_MEM_ BASE_LIMIT Prefetchable Memory Base and Limit 00010001h R/W, RO 28h–2Bh PMBU32 Prefetchable Memory Upper 32 Bits 00000000h R/W 2Ch–2Fh PMLU32 Prefetchable Memory Limit Upper 32 Bits 00000000h R/W 34h CAPP Capability List Pointer 50h RO 3Ch–3Dh INTR Interrupt Information 0000h R/W, RO 3Eh–3Fh BCTRL Bridge Control 0000h R/WC, RO, R/W 40h–41h SPDH Secondary PCI Device Hiding 0000h R/W, RO 44h–47h DTC Delayed Transaction Control 00000000h R/W 48h–4Bh BPS Bridge Proprietary Status 00000000h R/WC, RO 4Ch–4Fh BPC Bridge Policy Configuration 00001200h R/W RO 50–51h SVCAP Subsystem Vendor Capability Pointer 000Dh RO 54h–57h SVID Subsystem Vendor IDs 00000000 R/WO
PCI-to-PCI Bridge Registers (D30:F0)
436 Datasheet
11.1.1 VID—Vendor Identification Register (PCI-PCI—D30:F0)
Offset Address: 00h–01h Attribute: RO Default Value: 8086h Size: 16 bits
11.1.2 DID—Device Identification Register (PCI-PCI—D30:F0)
Offset Address: 02h–03h Attribute: RO Default Value: See bit description Size: 16 bits
11.1.3 PCICMD—PCI Command Re gister (PCI-PCI—D30:F0)
Offset Address: 04h –05h Attribute: R/W, RO Default Value: 0000h Size: 16 bits Bit Description 15:0 Vendor ID—RO. This is a 16-bit value assi gned to Intel. Intel VID = 8086h. Bit Description 15:0 Device ID— RO. This is a 16-bit value assigned to the PCI bridge. See the Intel® 5 Series Chipset and Intel® 3400 Series Chipset Specification Update for the value of the Device ID Register. Bit Description 15:11 Reserved 10 Interrupt Disable (ID)—RO. Hardwired to 0. The PCI bridge has no interrupts to disable 9 Fast Back to Back Enable (FBE)—RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a. SERR# Enable (SERR_EN)—R/W. 0 = Disable. 1 = Enable the PCH to generate an NMI (or SMI# if NMI routed to SMI#) when the D30:F0 SSE bit (offset 06h, bit 14) is set. 7 Wait Cycle Control (WCC)—RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a. Parity Error Response (PER)— R/W. 0 = The PCH ignores parity errors on the PCI bridge. 1 = The PCH will set the SSE bit (D30:F0, offset 06h, bit 14) when parity errors are detected on the PCI bridge. 5 VGA Palette Snoop (VPS)—RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a. 4 Memory Write and Invalidate Enable (MWE)—RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a 3 Special Cycle Enable (SCE)—RO. Hardwired to 0, per the PCI Express* Base Specification, Revision 1.0a and the PCI- to-PCI Bridge Specification.
PCI-to-PCI Bridge Registers (D30:F0)
11.1.4 PSTS—PCI Status Register (PCI-PCI—D30:F0)
Offset Address: 06h –07h Attribute: R/WC, RO Default Value: 0010h Size: 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bus Master Enable (BME)— R/W. 0 = Disable 1 = Enable. Allows the PCI-to-PCI bridge to accept cycles from PCI. Memory Space Enable (MSE)—R/W. Controls the response as a target for memory cycles targeting PCI. 0 = Disable 1 = Enable I/O Space Enable (IOSE)— R/W. Controls the response as a target for I/O cycles targeting PCI. 0 = Disable 1 = Enable Bit Description Bit Description Detected Parity Error (DPE)— R/WC. 0 = Parity error Not detected. 1 = Indicates that the PCH detected a parity error on the internal backbone. This bit gets set even if the Parity Error Response bit (D30:F0:04 bit 6) is not set.
PCI-to-PCI Bridge Registers (D30:F0)
438 Datasheet
Signaled System Error (SSE)—R/WC. Several internal an d external sources of the bridge can cause SERR#. The first class of errors is parity errors related to the backbone. The PCI bridge captures generic data parity errors (errors it finds on the backbone) as well as errors returned on backbone cycles where the bridge was the master. If either of these two conditions is met, and the primary side of the bridge is enabled for parity error response, SERR# will be captured as shown below. As with the backbone, the PCI bus captures the same sets of errors. The PCI bridge captures generic data parity errors (errors it finds on PCI) as well as errors returned on PCI cycles where the bridge was the master. If either of these two conditions is met, and the secondary side of the bridge is enabled for parity error response, SERR# will be captured as shown below. The final class of errors is system bus errors. There are three status bits associated with system bus errors, each with a corresponding enable. The diagram capturing this is shown below. After checking for the three above classes of errors, an SERR# is generated, and PSTS.SSE logs the generation of SERR#, if CMD.SEE (D30:F0:04, bit 8) is set, as shown below. Received Master Abort (RMA)— R/WC. 0 = No master abort received. 1 = Set when the bridge receives a master abort status from the backbone. Received Target Abort (RTA)—R/WC. 0 = No target abort received. 1 = Set when the bridge receives a target abort status from the backbone. Bit Description
PCI-to-PCI Bridge Registers (D30:F0)
11.1.5 RID—Revision Identificati on Register (PCI-PCI—D30:F0)
Offset Address: 08h Attribute: RO Default Value: See bit description Size: 8 bits
11.1.6 CC—Class Code Register (PCI-PCI—D30:F0)
Offset Address: 09h–0Bh Attribute: RO Default Value: 060401h Size: 24 bits Signaled Target Abort (STA)—R/WC. 0 = No signaled target abort 1 = Set when the bridge generates a completion packet with target abort status on the backbone. 10:9 Reserved Data Parity Error Detected (DPD)— R/WC. 0 = Data parity error Not detected. 1 = Set when the bridge receives a completion packet from the backbone from a previous request, and detects a parity error, and CMD.PERE is set (D30:F0:04 bit 6). 7:5 Reserved 4 Capabilities List (CLIST)—RO. Hardwired to 1. Capability list exist on the PCI bridge. 3 Interrupt Status (IS)—RO. Hardwired to 0. The PCI bridge does not generate interrupts. 2:0 Reserved Bit Description Bit Description 7:0 Revision ID—RO. See the Intel® 5 Series Chipset and Intel® 3400 Series Chipset Specification Update for the value of the Revision ID Register Bit Description 23:16 Base Class Code (BCC)—RO. Hardwired to 06h. Indicates this is a bridge device. 15:8 Sub Class Code (SCC)—RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI bridge. 7:0 Programming Interface (PI)—RO. Hardwired to 01h. Indicates the bridge is subtractive decode
PCI-to-PCI Bridge Registers (D30:F0)
440 Datasheet
(PCI-PCI—D30:F0) Offset Address: 0Dh Attribute: RO Default Value: 00h Size: 8 bits
11.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0)
Offset Address: 0Eh Attribute: RO Default Value: 01h Size: 8 bits
11.1.9 BNUM—Bus Number Re gister (PCI-PCI—D30:F0)
Offset Address: 18h–1Ah Attribute: R/W Default Value: 000000h Size: 24 bits Bit Description 7:3 Master Latency Timer Count (MLTC)—RO. Reserved per the PCI Express* Base Specification, Revision 1.0a. 2:0 Reserved Bit Description 7 Multi-Function Device (MFD)—RO. A 0 indicates a single function device 6:0 Header Type (HTYPE)— RO. This 7-bit field identifies the header layout of the configuration space, which is a PCI-to-PCI bridge in this case. Bit Description 23:16 Subordinate Bus Number (SBBN)—R/W. Indicates the highest PCI bus number below the bridge. 15:8 Secondary Bus Number (SCBN)—R/W. Indicates the bus number of PCI. 7:0 Primary Bus Number (PBN)—R/W. This field is default to 00h. In a multiple-PCH system, programmable PBN allows an PCH to be located on any bus. System configuration software is responsible for initializing these registers to appropriate values. PBN is not used by hardware in determining its bus number.
PCI-to-PCI Bridge Registers (D30:F0) (PCI-PCI—D30:F0) Offset Address: 1Bh Attribute: R/W Default Value: 00h Size: 8 bits This timer controls the amount of time the PCH PCI-to-PCI bridge will burst data on its secondary interface. The counter starts counting down from the assertion of FRAME#. If the grant is removed, then the expiration of this counter will result in the de- assertion of FRAME#. If the grant has not been removed, then the PCH PCI-to-PCI bridge may continue ownership of the bus.
11.1.11 IOBASE_LIMIT—I/O Ba se and Limit Register
(PCI-PCI—D30:F0) Offset Address: 1Ch–1Dh Attribute: R/W, RO Default Value: 0000h Size: 16 bits Bit Description 7:3 Master Latency Timer Count (MLTC)— R/W. This 5-bit field indicates the number of PCI clocks, in 8-clock increments, that the PCH remains as master of the bus. 2:0 Reserved Bit Description 15:12 I/O Limit Address Limit bits[15:12]—R/W. I/O Base bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh. 11:8 I/O Limit Address Capability (IOLC)— RO. Indicates that the bridge does not support 32-bit I/O addressing. 7:4 I/O Base Address (IOBA)—R/W. I/O Base bits corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h. 3:0 I/O Base Address Capability (IOBC)—RO. Indicates that the bridge does not support 32-bit I/O addressing.
PCI-to-PCI Bridge Registers (D30:F0)
442 Datasheet
11.1.12 SECSTS—Secondary Status Register (PCI-PCI—D30:F0)
Offset Address: 1Eh –1Fh Attribute: R/WC, RO Default Value: 0280h Size: 16 bits Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description Detected Parity Error (DPE)—R/WC. 0 = Parity error not detected. 1 = PCH PCI bridge detected an address or data parity error on the PCI bus Received System Error (RSE)— R/WC. 0 = SERR# assertion not received 1 = SERR# assertion is received on PCI. Received Master Abort (RMA)— R/WC. 0 = No master abort. 1 = This bit is set whenever the bridge is acting as an initiator on the PCI bus and the cycle is master-aborted. For Processor/PCH interface packets that have completion required, this must also cause a target abort to be returned and sets PSTS.STA. (D30:F0:06 bit 11) Received Target Abort (RTA)—R/WC. 0 = No target abort. 1 = This bit is set whenever the bridge is acting as an initiator on PCI and a cycle is target-aborted on PCI. For Processor/PCH interface packets that have completion required, this event must also cause a target abort to be returned, and sets PSTS.STA. (D30:F0:06 bit 11). Signaled Target Abort (STA)— R/WC. 0 = No target abort. 1 = This bit is set when the bridge is acting as a target on the PCI Bus and signals a target abort. 10:9 DEVSEL# Timing (DEVT)— RO. 01h = Medium decode timing. Data Parity Error Detected (DPD)—R/WC. 0 = Conditions described below not met. 1 = The PCH sets this bit when all of the following three conditions are met:
- The bridge is the initiator on PCI.
- PERR# is detected asserted or a parity error is detected internally
- BCTRL.PERE (D30:F0:3E bit 0) is set. 7 Fast Back to Back Capable (FBC)—RO. Hardwi red to 1 to indicate that the PCI to PCI target logic is capable of receiving fast back-to-back cycles.
6 Reserved
5 66 MHz Capable (66MHZ_CAP)—RO. Hardwired to 0. This bridge is 33 MHz capable only. 4:0 Reserved
PCI-to-PCI Bridge Registers (D30:F0) (PCI-PCI—D30:F0) Offset Address: 20h–23h Attribute: R/W Default Value: 00000000h Size: 32 bits This register defines the base and limit, aligned to a 1-MB boundary, of the non- prefetchable memory area of the bridge. Accesses that are within the ranges specified in this register will be sent to PCI if CMD.MSE is set. Accesses from PCI that are outside the ranges specified will be accepted by the bridge if CMD.BME is set. and Limit Register (PCI-PCI—D30:F0) Offset Address: 24h–27h Attribute: R/W, RO Default Value: 00010001h Size: 32-bit Defines the base and limit, aligned to a 1-MB boundary, of the prefetchable memory area of the bridge. Accesses that are within the ranges specified in this register will be sent to PCI if CMD.MSE is set. Accesses from PCI that are outside the ranges specified will be accepted by the bridge if CMD.BME is set. Bit Description 31:20 Memory Limit (ML)—R/W. These bits are compared with bits 31:20 of the incoming address to determine the upper 1-MB aligned value (exclusive) of the range. The incoming address must be less than this value. 19:16 Reserved 15:4 Memory Base (MB)—R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value (inclusive) of the range. The incoming address must be greater than or equal to this value. 3:0 Reserved Bit Description 31:20 Prefetchable Memory Limit (PML)— R/W. These bits are compared with bits 31:20 of the incoming address to determine the upper 1-MB aligned value (exclusive) of the range. The incoming address must be less than this value. 19:16 64-bit Indicator (I64L) — RO. Indicates support for 64-bit addressing. 15:4 Prefetchable Memory Base (PMB)— R/W. These bits are compared with bits 31:20 of the incoming address to determine the lower 1-MB aligned value (inclusive) of the range. The incoming address must be greater than or equal to this value. 3:0 64-bit Indicator (I64B) — RO. Indicates support for 64-bit addressing.
PCI-to-PCI Bridge Registers (D30:F0)
444 Datasheet
Register (PCI-PCI—D30:F0) Offset Address: 28h–2Bh Attribute: R/W Default Value: 00000000h Size: 32 bits Register (PCI-PCI—D30:F0) Offset Address: 2C–2Fh Attribute: R/W Default Value: 00000000h Size: 32 bits
11.1.17 CAPP—Capability List Poin ter Register (PCI-PCI—D30:F0)
Offset Address: 34h Attribute: RO Default Value: 50h Size: 8 bits
11.1.18 INTR—Interrupt Informat ion Register (PCI-PCI—D30:F0)
Offset Address: 3Ch –3Dh Attribute: R/W, RO Default Value: 0000h Size: 16 bits Bit Description 31:0 Prefetchable Memory Base Upper Portion (PMBU)—R/W. Upper 32-bits of the prefetchable address base. Bit Description 31:0 Prefetchable Memory Limit Upper Portion (PMLU)—R/W. Upper 32-bits of the prefetchable address limit. Bit Description 7:0 Capabilities Pointer (PTR)— RO. Indicates that the pointer for the first entry in the capabilities list is at 50h in configuration space. Bit Description 15:8 Interrupt Pin (IPIN)— RO. The PCI bridge does not assert an interrupt. 7:0 Interrupt Line (ILINE)—R/W. Software written value to indicate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. Since the bridge does not generate an interrupt, BIOS should program this value to FFh as per the PCI bridge specification.
PCI-to-PCI Bridge Registers (D30:F0)
11.1.19 BCTRL—Bridge Control Register (PCI-PCI—D30:F0)
Offset Address: 3Eh –3Fh Attribute: R/WC, RO, R/W Default Value: 0000h Size: 16 bits Bit Description 15:12 Reserved Discard Timer SERR# Enable (DTE)—R/W. Controls the generation of SERR# on the primary interface in response to the DTS bit being set: 0 = Do not generate SERR# on a secondary timer discard 1 = Generate SERR# in response to a secondary timer discard 10 Discard Timer Status (DTS)— R/WC. This bit is set to 1 when the secondary discard timer (see the SDT bit below) expires for a delayed transaction in the hard state. Secondary Discard Timer (SDT)—R/W. This bit sets the maximum number of PCI clock cycles that the PCH waits for an initiator on PCI to repeat a delayed transaction request. The counter starts once the delayed transaction data is has been returned by the system and is in a buffer in the PCH PCI bridge. If the master has not repeated the transaction at least once before the counter expires, the PCH PCI bridge discards the transaction from its queue. 0 = The PCI master timeout value is between 215 and 216 PCI clocks 1 = The PCI master timeout value is between 210 and 211 PCI clocks 8 Primary Discard Timer (PDT)—R/W. This bit is R/W for software compatibility only. 7 Fast Back to Back Enable (FBE)—RO. Hardwi red to 0. The PCI logic will not generate fast back-to-back cycles on the PCI bus. Secondary Bus Reset (SBR)— R/W. Controls PCIRST# assertion on PCI. 0 = Bridge de-asserts PCIRST# 1 = Bridge asserts PCIRST#. When PCIRST# is asserted, the delayed transaction buffers, posting buffers, and the PCI bus are initialized back to reset conditions. The rest of the part and the configuration registers are not affected. Master Abort Mode (MAM)—R/W. Controls the PCH PCI bridge’s behavior when a master abort occurs: Master Abort on Processor /PCH Interconnect (DMI): 0 = Bridge asserts TRDY# on PCI. It drives all 1s for reads, and discards data on writes. 1 = Bridge returns a target abort on PCI. Master Abort PCI (non-locked cycles): 0 = Normal completion status will be returned on the Processor/PCH interconnect. 1 = Target abort completion status will be returned on the Processor/PCH interconnect. NOTE: All locked reads will return a completer abort completion status on the Processor/PCH interconnect. VGA 16-Bit Decode (V16D)— R/W. Enables the PCH PCI bridge to provide 16-bits decoding of VGA I/O address precluding the decode of VGA alias addresses every 1 KB. This bit requires the VGAE bit in this register be set.
PCI-to-PCI Bridge Registers (D30:F0)
446 Datasheet
VGA Enable (VGAE)—R/W. When set to a 1, the PCH PCI bridge forwards the following transactions to PCI regardless of the value of the I/O base and limit registers. The transactions are qualified by CMD.MSE (D30:F0:04 bit 1) and CMD.IOSE (D30:F0:04 bit 0) being set.
- Memory addresses: 000A0000h–000BFFFFh
- I/O addresses: 3B0h–3BBh an d 3C0h–3DFh. For the I/O addresses, bits [63:16] of the address must be 0, and bits [15:10] of the address are ignored (that is, aliased). The same holds true from secondary accesses to the primary interface in reverse. That is, when the bit is 0, memory and I/O addresses on the secondary interface between the above ranges will be claimed. ISA Enable (IE)—R/W. This bit only applies to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space. If this bit is set, the PCH PCI bridge will block any forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to 3FFh). SERR# Enable (SEE)— R/W. Controls the forwarding of secondary interface SERR# assertions on the primary interface. When set, the PCI bridge will forward SERR# pin.
- SERR# is asserted on the secondary interface.
- This bit is set.
- CMD.SEE (D30:F0:04 bit 8) is set. Parity Error Response Enable (PERE)—R/W. 0 = Disable 1 = The PCH PCI bridge is enabled for parity error reporting based on parity errors on the PCI bus. Bit Description
PCI-to-PCI Bridge Registers (D30:F0) (PCI-PCI—D30:F0) Offset Address: 40h–41h Attribute: R/W, RO Default Value: 0000h Size: 16 bits This register allows software to hide the PCI devices, either plugged into slots or on the motherboard.
11.1.21 DTC—Delayed Transa ction Control Register
(PCI-PCI—D30:F0) Offset Address: 44h –47h Attribute: R/W Default Value: 00000000h Size: 32 bits Bit Description 15:4 Reserved 3 Hide Device 3 (HD3)—R/W, RO. Same as bit 0 of this register, except for device 3 (AD[19]) 2 Hide Device 2 (HD2)— R/W, RO. Same as bit 0 of this register, except for device 2 (AD[18]) 1 Hide Device 1 (HD1)—R/W, RO. Same as bit 0 of this register, except for device 1 (AD[17]) Hide Device 0 (HD0)— R/W, RO. 0 = The PCI configuration cycles for this slot are not affected. 1 = The PCH hides device 0 on the PCI bus. This is done by masking the IDSEL (keeping it low) for configuration cycles to that device. Since the device will not see its IDSEL go active, it will not respond to PCI configuration cycles and the processor will think the device is not present. AD[16] is used as IDSEL for device 0. Bit Description Discard Delayed Transactions (DDT)— R/W. 0 = Logged delayed transactions are kept. 1 = The PCH PCI bridge will discard any delayed transactions it has logged. This includes transactions in the pending queue, and any transactions in the active queue, whether in the hard or soft DT state. The prefetchers will be disabled and return to an idle state. NOTES:If a transaction is running on PCI at the time this bit is set, that transaction will continue until either the PCI master disconnects (by de-asserting FRAME#) or the PCI bridge disconnects (by asserting STOP#). This bit is cleared by the PCI bridge when the delayed transaction queues are empty and have returned to an idle state. Software sets this bit and polls for its completion Block Delayed Transactions (BDT)—R/W. 0 = Delayed transactions accepted 1 = The PCH PCI bridge will not accept incoming transactions which will result in delayed transactions. It will blindly retry these cycles by asserting STOP#. All postable cycles (memory writes) will still be accepted. 29:8 Reserved
PCI-to-PCI Bridge Registers (D30:F0)
448 Datasheet
7:6 Maximum Delayed Transactions (MDT)—R/W. Controls the maximum number of delayed transactions that the PCH PCI bridge will run. Encodings are: 00 =) 2 Active, 5 pending 01 =) 2 active, no pending 10 =) 1 active, no pending 11 =) Reserved
5 Reserved
Auto Flush After Disconnect Enable (AFADE)—R/W. 0 = The PCI bridge will retain any fetched data until required to discard by producer/ consumer rules. 1 = The PCI bridge will flush any prefetched data after either the PCI master (by de- asserting FRAME#) or the PCI bridge (by asserting STOP#) disconnects the PCI transfer. Never Prefetch (NP)—R/W. 0 = Prefetch enabled 1 = The PCH will only fetch a single DW and will not enable prefetching, regardless of the command being an Memory read (MR), Memory read line (MRL), or Memory read multiple (MRM). Memory Read Multiple Prefetch Disable (MRMPD)— R/W. 0 = MRM commands will fetch multiple cache lines as defined by the prefetch algorithm. 1 = Memory read multiple (MRM) commands will fetch only up to a single, 64-byte aligned cache line. Memory Read Line Prefetch Disable (MRLPD)— R/W. 0 = MRL commands will fetch multiple cache lines as defined by the prefetch algorithm. 1 = Memory read line (MRL) commands will fetch only up to a single, 64-byte aligned cache line. Memory Read Prefetch Disable (MRPD)— R/W. 0 = MR commands will fetch up to a 64-byte aligned cache line. 1 = Memory read (MR) commands will fetch only a single DW. Bit Description
PCI-to-PCI Bridge Registers (D30:F0) (PCI-PCI—D30:F0) Offset Address: 48h –4Bh Attribute: R/WC, RO Default Value: 00000000h Size: 32 bits Bit Description 31:17 Reserved PERR# Assertion Detected (PAD)—R/WC. This bit is set by hardware whenever the PERR# pin is asserted on the rising edge of PCI clock. This includes cases in which the chipset is the agent driving PERR#. It remains asserted until cleared by software writing a 1 to this location. When enabled by the PERR#-to-SERR# Enable bit (in the Bridge Policy Configuration register), a 1 in this bit can generate an internal SERR# and be a source for the NMI logic. This bit can be used by software to determine the source of a system problem. 15:7 Reserved 6:4 Number of Pending Transactions (NPT)— RO. This read-only indicator tells debug software how many transactions are in the pending queue. Possible values are: 000 = No pending transaction 001 = 1 pending transaction 010 = 2 pending transactions 011 = 3 pending transactions 100 = 4 pending transactions 101 = 5 pending transactions 110–111 = Reserved NOTE: This field is not valid if DTC.MDT (offset 44h:bits 7:6) is any value other than ‘00’. 3:2 Reserved 1:0 Number of Active Transactions (NAT)— RO. This read-only indicator tells debug software how many transactions are in the active queue. Possible values are: 00 = No active transactions 01 = 1 active transaction 10 = 2 active transactions 11 = Reserved
PCI-to-PCI Bridge Registers (D30:F0)
450 Datasheet
(PCI-PCI—D30:F0) Offset Address: 4Ch –4Fh Attribute: R/W Default Value: 00001200h Size: 32 bits Bit Description 31:14 Reserved 13:8 Upstream Read Latency Threshold (URLT)—R/W: This field specifies the number of PCI clocks after internally enqueuing an upstream memory read request at which point the PCI target logic should insert wait states to optimize lead-off latency. When the master returns after this threshold has been reached and data has not arrived in the Delayed Transaction completion queue, then the PCI target logic will insert wait states instead of immediately retrying the cycle. The PCI target logic will insert up to 16 clocks of target initial latency (from FRAME# assertion to TRDY# or STOP# assertion) before retrying the PCI read cycle (if the read data has not arrived yet). Note that the starting event for this Read Latency Timer is not explicitly visible externally. A value of 0h disables this policy completely such that wait states will never be inserted on the read lead-off data phase. The default value (12h) specifies 18 PCI clocks (540 ns) and is approximately 4 clocks less than the typical idle lead-off latency expected for desktop PCH systems. This value may need to be changed by BIOS, depending on the platform. Subtractive Decode Policy (SDP)—R/W. 0 = The PCI bridge always forwards memory and I/O cycles that are not claimed by any other device on the backbone (primary interface) to the PCI bus (secondary interface). 1 = The PCI bridge will not claim and forward memory or I/O cycles at all unless the corresponding Space Enable bit is set in the Command register. NOTE: The Boot BIOS Destination Selection strap can force the BIOS accesses to PCI. PERR#-to-SERR# Enable (PSE)—R/W. When this bit is set, a 1 in the PERR# Assertion status bit (in the Bridge Proprietary Status register) will result in an internal SERR# assertion on the primary side of the bridge (if also enabled by the SERR# Enable bit in the primary Command register). SERR# is a source of NMI. Secondary Discard Timer Testmode (SDTT)— R/W. 0 = The secondary discard timer expiration will be defined in BCTRL.SDT (D30:F0:3E, bit 9) 1 = The secondary discard timer will expire after 128 PCI clocks. 4:3 Reserved CMD.MSE BPC.SDP Range Forwarding Policy
00 D o n ’ t C a r e Forward unclaimed
0 1 Don’t Care Forwarding Prohibited 1X W i t h i n r a n g e Positive decode and forward 1X O u t s i d e Subtractive decode & forward
PCI-to-PCI Bridge Registers (D30:F0) (PCI-PCI—D30:F0) Offset Address: 50h –51h Attribute: RO Default Value: 000Dh Size: 16 bits
11.1.25 SVID—Subsystem Vendor IDs Register (PCI-PCI—D30:F0)
Offset Address: 54h –57h Attribute: R/WO Default Value: 00000000h Size: 32 bits § § Peer Decode Enable (PDE)— R/W. 0 = The PCI bridge assumes that all memory cycles target main memory, and all I/O cycles are not claimed. 1 = The PCI bridge will perform peer decode on any memory or I/O cycle from PCI that falls outside of the memory and I/O window registers Received Target Abort SERR# Enable (RTAE)—R/W. When set, th e PCI bridge will report SERR# when PSTS.RTA (D30:F0:06 bit 12) or SSTS.RTA (D30:F0:1E bit 12) are set, and CMD.SEE (D30:F0:04 bit 8) is set. Bit Description Bit Description 15:8 Next Capability (NEXT)— RO. Value of 00h indicates this is the last item in the list. 7:0 Capability Identifier (CID)— RO. Value of 0Dh indicates this is a PCI bridge subsystem vendor capability. Bit Description 31:16 Subsystem Identifier (SID)— R/WO. Indicates the subsystem as identified by the vendor. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset). 15:0 Subsystem Vendor Identifier (SVID)— R/WO. Indicates the manufacturer of the subsystem. This field is write once and is locked down until a bridge reset occurs (not the PCI bus reset).
PCI-to-PCI Bridge Registers (D30:F0)
452 Datasheet
Gigabit LAN Configuration Registers
12 Gigabit LAN Configuration
(Gigabit LAN—D25:F0) Note: Register address locations that are not shown in Table 12-1 should be treated as Reserved. Table 12-1. Gigabit LAN Configuration Registers Address Map (Gigabit LAN—D25:F0) (Sheet 1 of 2) Offset Mnemonic Register Name Default Type 00h–01h VID Vendor Identification 8086h RO 02h–03h DID Device Identification See register description RO 04h–05h PCICMD PCI Command 0000h R/W, RO 06h–07h PCISTS PCI Status 0010h R/WC, RO 08h RID Revision Identification See register description RO 09h–0Bh CC Class Code 020000h RO 0Ch CLS Cache Line Size 00h R/W 0Dh PLT Primary Latency Timer 00h RO 0Eh HEADTYP Header Type 00h RO 10h–13h MBARA Memory Base Address A 00000000h R/W, RO 14h–17h MBARB Memory Base Address B 00000000h R/W, RO 18h–1Bh MBARC Memory Base Address C 00000001h R/W, RO 2Ch–2Dh SID Subsystem ID See register description RO 2Eh–2Fh SVID Subsystem Vendor ID See register description RO 30h–33h ERBA Expansion ROM Base Address See register description RO 34h CAPP Capabilities List Pointer C8h RO 3Ch–3Dh INTR Interrupt Information See register description R/W, RO 3Eh MLMG Maximum Latency/Minimum Grant 00h RO C8h–C9h CLIST1 Capabilities List 1 D001h RO CAh–CBh PMC PCI Power Ma nagement Capability See register description RO CCh–CDh PMCS PCI Power Management Control and Status See register R/WC, R/W, RO
Gigabit LAN Configuration Registers
454 Datasheet
12.1.1 VID—Vendor Identi fication Register
(Gigabit LAN—D25:F0) Address Offset: 00h –01h Attribute: RO Default Value: 8086h Size: 16 bits
12.1.2 DID—Device Identi fication Register
(Gigabit LAN—D25:F0) Address Offset: 02h–03h Attribute: RO Default Value: See bit description Size: 16 bits CFh DR Data Register See register description RO D0h–D1h CLIST2 Capabilities List 2 E005h R/WO, RO D2h–D3h MCTL Message Control 0080h R/W, RO D4h–D7h MADDL Message Address Low See register description R/W D8h–DBh MADDH Message Address High See register description R/W DCh–DDh MDAT Message Data See register description R/W E0h–E1h FLRCAP Function Level Reset Capability 0009h RO E2h–E3h FLRCLV Function Level Reset Capability Length and Value See register description R/WO, RO E4h–E5h DEVCTRL Device Control 0000h R/W, RO Table 12-1. Gigabit LAN Config uration Registers Address Map (Gigabit LAN—D25:F0) (Sheet 2 of 2) Offset Mnemonic Register Name Default Type Bit Description 15:0 Vendor ID— RO. This is a 16-bit value assigned to Intel. The field may be auto-loaded from the NVM at address 0Eh during init time depending on the "Load Vendor/Device ID" bit field in NVM word 0Ah with a default value of 8086h. Bit Description 15:0 Device ID—RO. This is a 16-bit value assigned to the PCH Gigabit LAN controller. The field may be auto-loaded from the NVM word 0Dh during initialization time depending on the "Load Vendor/Device ID" bit field in NVM word 0Ah.
Gigabit LAN Configuration Registers (Gigabit LAN—D25:F0) Address Offset: 04h–05h Attribute: R/W, RO Default Value: 0000h Size: 16 bits Bit Description 15:11 Reserved Interrupt Disable—R/W. This disables pin-based INTx# interrupts on enabled Hot- Plug and power management events. This bit has no effect on MSI operation. 0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or power management and MSI is not enabled. 1 = Internal INTx# messages will not be generated. This bit does not affect interrupt forwarding from devices connected to the root port. Assert_INTx and Deassert_INTx messages will still be forwarded to the internal interrupt controllers if this bit is set. 9 Fast Back to Back Enable (FBE)—RO. Hardwired to 0. SERR# Enable (SEE)—R/W. 0 = Disable 1 = Enables the Gb LAN controller to generate an SERR# message when PSTS.SSE is set. 7 Wait Cycle Control (WCC) — RO. Hardwired to 0. Parity Error Response (PER)—R/W. 0 = Disable. 1 = Indicates that the device is capable of reporting parity errors as a master on the backbone. 5 Palette Snoop Enable (PSE)—RO. Hardwired to 0. 4 Postable Memory Write Enable (PMWE)—RO. Hardwired to 0. 3 Special Cycle Enable (SCE) — RO. Hardwired to 0. Bus Master Enable (BME)—R/W. 0 = Disable. All cycles from the device are master aborted 1 = Enable. Allows the root port to forward cycles onto the backbone from a Gigabit LAN* device. Memory Space Enable (MSE)—R/W. 0 = Disable. Memory cycles within the range specified by the memory base and limit registers are master aborted on the backbone. 1 = Enable. Allows memory cycles within the range specified by the memory base and limit registers can be forwarded to the Gigabit LAN device. I/O Space Enable (IOSE)—R/W. This bit controls access to the I/O space registers. 0 = Disable. I/O cycles within the range specified by the I/O base and limit registers are master aborted on the backbone. 1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit registers can be forwarded to the Gigabit LAN device.
Gigabit LAN Configuration Registers
456 Datasheet
(Gigabit LAN—D25:F0) Address Offset: 06h –07h Attribute: R/WC, RO Default Value: 0010h Size: 16 bits Bit Description Detected Parity Error (DPE)— R/WC. 0 = No parity error detected. 1 = Set when the Gb LAN controller receives a command or data from the backbone with a parity error. This is set even if PCIMD.PER (D25:F0, bit 6) is not set. Signaled System Error (SSE)— R/WC. 0 = No system error signaled. 1 = Set when the Gb LAN controller signals a system error to the internal SERR# logic. Received Master Abort (RMA)— R/WC. 0 = Root port has not received a completion with unsupported request status from the backbone. 1 = Set when the GbE LAN controller receives a completion with unsupported request status from the backbone. Received Target Abort (RTA)— R/WC. 0 = Root port has not received a completion with completer abort from the backbone. 1 = Set when the Gb LAN controller receives a completion with completer abort from the backbone. Signaled Target Abort (STA)— R/WC. 0 = No target abort received. 1 = Set whenever the Gb LAN controller forwards a target abort received from the downstream device onto the backbone. 10:9 DEVSEL# Timing Status (DEV_STS) — RO. Hardwired to ‘0’. Master Data Parity Error Detected (DPED)—R/WC. 0 = No data parity error received. 1 = Set when the Gb LAN Controller receives a completion with a data parity error on the backbone and PCIMD.PER (D25:F0, bit 6) is set. 7 Fast Back to Back Capable (FB2BC)—RO. Hardwired to ‘0’. 6R e s e r v e d 5 66 MHz Capable—RO. Hardwired to 0. 4 Capabilities List—RO. Hardwired to 1. Indi cates the presence of a capabilities list. Interrupt Status — RO. Indicates status of Hot-Plug and power management interrupts on the root port that result in INTx# message generation. 0 = Interrupt is de-asserted. 1 = Interrupt is asserted. This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the state of PCICMD.Interrupt Disable bit (D25:F0:04h:bit 10). 2:0 Reserved
Gigabit LAN Configuration Registers (Gigabit LAN—D25:F0) Offset Address: 08h Attribute: RO Default Value: See bit description Size: 8 bits (Gigabit LAN—D25:F0) Address Offset: 09h –0Bh Attribute: RO Default Value: 020000h Size: 24 bits (Gigabit LAN—D25:F0) Address Offset: 0Ch Attribute: R/W Default Value: 00h Size: 8 bits
12.1.8 PLT—Primary Late ncy Timer Register
(Gigabit LAN—D25:F0) Address Offset: 0Dh Attribute: RO Default Value: 00h Size: 8 bits (Gigabit LAN—D25:F0) Address Offset: 0Eh Attribute: RO Default Value: 00h Size: 8 bits Bit Description 7:0 Revision ID—RO. See the Intel® 5 Series Chipset and Intel® 3400 Series Chipset Specification Update for the value of the Revision ID Register Bit Description 23:0 Class Code—RO. Identifies the device as an Ethernet Adapter. 020000h = Ethernet Adapter. Bit Description 7:0 Cache Line Size—R/W. This field is impl emented by PCI devices as a read write field for legacy compatibility purposes but has no impact on any device functionality. Bit Description 7:0 Latency Timer (LT) —RO. Hardwired to 0. Bit Description 7:0 Header Type (HT)—RO. 00h = Indicates this is a single function device.
Gigabit LAN Configuration Registers
458 Datasheet
(Gigabit LAN—D25:F0) Address Offset: 10h –13h Attribute: R/W, RO Default Value: 00000000h Size: 32 bits The internal CSR registers and memories are accessed as direct memory mapped offsets from the base address register. SW may only access whole DWord at a time. (Gigabit LAN—D25:F0) Address Offset: 14h –17h Attribute: R/W, RO Default Value: 00000000h Size: 32 bits The internal registers that are used to access the LAN Space in the External FLASH device. Access to these registers are direct memory mapped offsets from the base address register. Software may only access a DWord at a time. Bit Description 31:17 Base Address (BA)—R/W. Software programs this field with the base address of this region. 16:4 Memory Size (MSIZE)—R/W . Memory size is 128 KB. 3 Prefetchable Memory (PM)— RO. The GbE LAN controller does not implement prefetchable memory. 2:1 Memory Type (MT)—RO. Set to 00b indicating a 32 bit BAR. 0 Memory / IO Space (MIOS)—RO. Set to 0 indicating a Memory Space BAR. Bit Description 31:12 Base Address (BA)—R/W. Software programs this field with the base address of this region. 11:4 Memory Size (MSIZE)—R/W . Memory size is 4 KB. 3 Prefetchable Memory (PM)—RO. The Gb LAN controller does not implement prefetchable memory. 2:1 Memory Type (MT)—RO. Set to 00b indicating a 32 bit BAR. 0 Memory / IO Space (MIOS)—RO. Set to 0 indicating a Memory Space BAR.
Gigabit LAN Configuration Registers (Gigabit LAN—D25:F0) Address Offset: 18h –1Bh Attribute: R/W, RO Default Value: 00000001h Size: 32 bits Internal registers, and memories, can be accessed using I/O operations. There are two 4B registers in the I/O mapping window: Addr Reg and Data Reg. Software may only access a DWord at a time. (Gigabit LAN—D25:F0) Address Offset: 2Ch –2Dh Attribute: RO Default Value: See bit description Size: 16 bits
12.1.14 SID—Subsys tem ID Register
(Gigabit LAN—D25:F0) Address Offset: 2Eh –2Fh Attribute: RO Default Value: See bit description Size: 16 bits
12.1.15 ERBA—Expansion RO M Base Address Register
(Gigabit LAN—D25:F0) Address Offset: 30h –33h Attribute: RO Default Value: See bit description Size: 32 bits Bit Description 31:5 Base Address (BA)—R/W. Software programs this field with the base address of this region. 4:1 I/O Size (IOSIZE)— RO. I/O space size is 32 Bytes. 0 Memory / I/O Space (MIOS)— RO. Set to 1 indicating an I/O Space BAR. Bit Description 15:0 Subsystem Vendor ID (SVID)— RO. This value may be loaded automatically from the NVM Word 0Ch upon power up depending on the "Load Subsystem ID" bit field in NVM word 0Ah. A value of 8086h is default for this field upon power up if the NVM does not respond or is not programmed. All functions are initialized to the same value. Bit Description 15:0 Subsystem ID (SID)—RO. This value may be loaded automatically from the NVM Word 0Bh upon power up or reset depending on the “Load Subsystem ID” bit field in NVM word 0Ah with a default value of 0000h. This value is loadable from NVM word location 0Ah. Bit Description 31:0 Expansion ROM Base Address (ERBA)— RO. This register is used to define the address and size information for boot-time access to the optional FLASH memory. If no Flash memory exists, this register reports 00000000h.
Gigabit LAN Configuration Registers
460 Datasheet
(Gigabit LAN—D25:F0) Address Offset: 34h Attribute: R0 Default Value: C8h Size: 8 bits (Gigabit LAN—D25:F0) Address Offset: 3Ch–3Dh Attribute: R/W, RO Default Value: 0100h Size: 16 bits Function Level Reset: No
12.1.18 MLMG—Maximum Latenc y/Minimum Grant Register
(Gigabit LAN—D25:F0) Address Offset: 3Eh Attribute: RO Default Value: 00h Size: 8 bits (Gigabit LAN—D25:F0) Address Offset: C8h–C9h Attribute: RO Default Value: D001h Size: 16 bits Bit Description 7:0 Capabilities Pointer (PTR)— RO. Indicates that the pointer for the first entry in the capabilities list is at C8h in configuration space. Bit Description 15:8 Interrupt Pin (IPIN)— RO. Indicates the interrupt pin driven by the GbE LAN controller. 01h = The GbE LAN controller implements legacy interrupts on INTA. 7:0 Interrupt Line (ILINE)— R/W. Default = 00h. Software written value to indicate which interrupt line (vector) the interrupt is connected to. No hardware action is taken on this register. Bit Description 7:0 Maximum Latency/Minimum Grant (MLMG)—RO. Not used. Hardwired to 00h. Bit Description 15:8 Next Capability (NEXT)— RO. Value of D0h indicates the location of the next pointer. 7:0 Capability ID (CID)— RO. Indicates the linked list item is a PCI Power Management Register.
Gigabit LAN Configuration Registers
12.1.20 PMC—PCI Power Manageme nt Capabilities Register
(Gigabit LAN—D25:F0) Address Offset: CAh –CBh Attribute: RO Default Value: See bit descriptions Size: 16 bits Function Level Reset: No (Bits 15:11 only) Bit Description 15:11 PME_Support (PMES)—RO. This five-bit field indicate s the power states in which the function may assert PME#. It depend on PM Ena and AUX-PWR bits in word 0Ah in the NVM: These bits are not reset by Function Level Reset. 10 D2_Support (D2S)—RO. The D2 state is not supported. 9 D1_Support (D1S)— RO. The D1 state is not supported. 8:6 Aux_Current (AC)—RO. Required current defi ned in the Data Register. 5 Device Specific Initialization (DSI)—RO. Set to 1. The GbE LAN Controller requires its device driver to be executed following transition to the D0 un-initialized state. 3 PME Clock (PMEC)—RO. Hardwired to 0. 2:0 Version (VS)—RO. Hardwired to 010b to indicate support for Revision 1.1 of the PCI Power Management Specification. Condition Function Value PM Ena=0 No PME at all states 0000b PM Ena & AUX-PWR=0 PME at D0 and D3hot 01001b PM Ena & AUX-PWR=1 PME at D0, D3hot and D3cold 11001b
Gigabit LAN Configuration Registers
462 Datasheet
12.1.21 PMCS—PCI Power Mana gement Control and Status
Register (Gigabit LAN—D25:F0) Address Offset: CCh –CDh Attribute: R/WC, R/W, RO Default Value: See bit description Size: 16 bits Function Level Reset: No (Bit 8 only) Bit Description 15 PME Status (PMES)— R/WC. This bit is set to 1 when the function detects a wake-up event independent of the state of the PMEE bit. Writing a 1 will clear this bit. 14:13 Data Scale (DSC)— R/W. This field indicates the scaling factor to be used when interpreting the value of the Data register. For the GbE LAN and common functions this field equals 01b (indicating 0.1 watt units) if the PM is enabled in the NVM, and the Data_Select field is set to 0, 3, 4, 7, (or 8 for Function 0). Else it equals 00b. For the manageability functions this field equals 10b (indicating 0.01 watt units) if the PM is enabled in the NVM, and the Data_Select field is set to 0, 3, 4, 7. Else it equals 00b. 12:9 Data Select (DSL)— R/W. This four-bit field is used to select which data is to be reported through the Data register (offset CFh) and Data_Scale field. These bits are writeable only when the Power Management is enabled using NVM. 0h = D0 Power Consumption 3h = D3 Power Consumption 4h = D0 Power Dissipation 7h = D3 Power Dissipation 8h = Common Power All other values are reserved. PME Enable (PMEE)— R/W. If Power Management is enabled in the NVM, writing a 1 to this register will enable Wakeup. If Power Management is disabled in the NVM, writing a 1 to this bit has no affect, and will not set the bit to 1. This bit is not reset by Function Level Reset. 7:4 Reserved - Returns a value of 0000. 3 No Soft Reset (NSR)— RO. Defines if the device executed internal reset on the transition to D0. the LAN controller always reports 0 in this field. 2 Reserved - Returns a value of 0b. 1:0 Power State (PS)— R/W. This field is used both to determine the current power state of the GbE LAN Controller and to set a new power state. The values are: 00 = D0 state (default) 01 = Ignored 10 = Ignored 11 = D3 state (Power Management must be enables in the NVM or this cycle will be ignored).
Gigabit LAN Configuration Registers (Gigabit LAN—D25:F0) Address Offset: CFh Attribute: RO Default Value: See bit description Size: 8 bits
12.1.23 CLIST 2—Capabiliti es List Register 2
(Gigabit LAN—D25:F0) Address Offset: D0h–D1h Attribute: R/WO, RO Default Value: E005h Size: 16 bits Function Level Reset: No (Bits 15:8 only) (Gigabit LAN—D25:F0) Address Offset: D2h–D3h Attribute: R/W, RO Default Value: 0080h Size: 16 bits Bit Description 7:0 Reported Data (RD)—RO. This register is used to report power consumption and heat dissipation. This register is controlled by the Data_Select field in the PMCS (Offset CCh, bits 12:9), and the power scale is reported in the Data_Scale field in the PMCS (Offset CCh, bits 14:13). The data of this field is loaded from the NVM if PM is enabled in the NVM or with a default value of 00h otherwise. Bit Description 15:8 Next Capability (NEXT)— R/WO. Value of E0h points to the Function Level Reset capability structure. These bits are not reset by Function Level Reset. 7:0 Capability ID (CID)— RO. Indicates the linked list item is a Message Signaled Interrupt Register. Bit Description 15:8 Reserved 7 64-bit Capable (CID)— RO. Set to 1 to indicate that the GbE LAN Controller is capable of generating 64-bit message addresses. 6:4 Multiple Message Enable (MME)— RO. Returns 000b to indicate that the GbE LAN controller only supports a single message. 3:1 Multiple Message Capable (MMC)— RO. The GbE LAN controller does not support multiple messages. MSI Enable (MSIE)— R/W. 0 = MSI generation is disabled. 1 = The Gb LAN controller will generate MSI for interrupt assertion instead of INTx signaling.
Gigabit LAN Configuration Registers
464 Datasheet
(Gigabit LAN—D25:F0) Address Offset: D4h–D7h Attribute: R/W Default Value: See bit description Size: 32 bits (Gigabit LAN—D25:F0) Address Offset: D8h–DBh Attribute: R/W Default Value: See bit description Size: 32 bits (Gigabit LAN—D25:F0) Address Offset: DCh–DDh Attribute: R/W Default Value: See bit description Size: 16 bits (Gigabit LAN—D25:F0) Address Offset: E0h–E1h Attribute: RO Default Value: 0009h Size: 16 bits Bit Description 31:0 Message Address Low (MADDL)— R/W. Written by the system to indicate the lower 32 bits of the address to use for the MSI memory write transaction. The lower two bits will always return 0 regardless of the write operation. Bit Description 31:0 Message Address High (MADDH)— R/W. Written by the system to indicate the upper 32 bits of the address to use for the MSI memory write transaction. Bit Description 31:0 Message Data (MDAT)— R/W. Written by the system to indicate the lower 16 bits of the data written in the MSI memory write DWORD transaction. The upper 16 bits of the transaction are written as 0000h. Bit Description 15:8 Next Pointer— RO. This field provides an offset to the next capability item in the capability list. The value of 00h indicates the last item in the list. 7:0 Capability ID— RO. The value of this field depends on the FLRCSSEL bit. 13h = If FLRCSSEL = 0 09h = If FLRCSSEL = 1, indicating vendor specific capability.
Gigabit LAN Configuration Registers
12.1.29 FLRCLV—Function Level Re set Capability Length and
(Gigabit LAN—D25:F0) Address Offset: E2h–E3h Attribute: R/WO, RO Default Value: See Description. Size: 16 bits Function Level Reset: No (Bit s 9:8 Only When FLRCSSEL = 0) When FLRCSSEL = 0, this register is defined as follows: When FLRCSSEL = 1, this register is defined as follows:
12.1.30 DEVCTRL—Device Control (Gigabit LAN—D25:F0)
Address Offset: E4–E5h Attribute: R/W, RO Default Value: 0000h Size: 16 bits Bit Description 15:10 Reserved Function Level Reset Capability— R/WO. 1 = Support for Function Level Reset. This bit is not reset by Function Level Reset. TXP Capability— R/WO. 1 = Indicates support for the Transactions Pending (TXP) bit. TXP must be supported if FLR is supported. 7:0 Capability Length— RO. The value of this field indicates the number of bytes of the vendor specific capability as require by the PCI spec. It has the value of 06h for the Function Level Reset capability. Bit Description 15:12 Vendor Specific Capability ID— RO. A value of 2h in this field identifies this capability as Function Level Reset. 11:8 Capability Version—RO. The value of this field indicates the version of the Function Level Reset Capability. Default is 0h. 7:0 Capability Length— RO. The value of this field indicates the number of bytes of the vendor specific capability as require by the PCI spec. It has the value of 06h for the Function Level Reset capability. Bit Description 15:9 Reserved Transactions Pending (TXP)— R/W. 1 = Indicates the controller has issued Non-Posted requests which have not been completed. 0 = Indicates that completions for all Non-Posted requests have been received. 7:1 Reserved Initiate Function Level Reset— RO. This bit is used to initiate an FLT transition. A write of 1 initiates the transition. Since hardware must not respond to any cycles until Function Level Reset completion, the value read by software from this bit is 0.
Gigabit LAN Configuration Registers
466 Datasheet
§ §
LPC Interface Bridge Registers (D31:F0)
13 LPC Interface Bridge Registers
(D31:F0) The LPC bridge function of the PCH resides in PCI Device 31:Function 0. This function contains many other functional units, such as DMA and Interrupt controllers, Timers, Power Management, System Management, GPIO, RTC, and LPC Configuration Registers. Registers and functions associated with other functional units are described in their respective sections.
13.1 PCI Configuration Registers (LPC I/F—D31:F0)
Note: Address locations that are not shown should be treated as Reserved. Table 13-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 1 of 2) Offset Mnemonic Register Name Default Type 00h–01h VID Vendor Identification 8086h RO 02h–03h DID Device Identification See register description RO 04h–05h PCICMD PCI Command 0007h R/W, RO 06h–07h PCISTS PCI Status 0210h R/WC, RO 08h RID Revision Identification See register description RO 09h PI Programming Interface 00h RO 0Ah SCC Sub Class Code 01h RO 0Bh BCC Base Class Code 06h RO 0Dh PLT Primary Latency Timer 00h RO 0Eh HEADTYP Header Type 80h RO 2Ch–2Fh SS Sub System Identifiers 00000000h R/WO 34h CAPP Capability List Pointer E0h RO 40h–43h PMBASE ACPI Base Address 00000001h R/W, RO 44h ACPI_CNTL ACPI Control 00h R/W 48h–4Bh GPIOBASE GPIO Base Address 00000001h R/W, RO 4C GC GPIO Control 00h R/W 60h–63h PIRQ[ n]_ROUT PIRQ[A–D] Routing Control 80808080h R/W 64h SIRQ_CNTL Serial IRQ Control 10h R/W, RO 68h–6Bh PIRQ[ n]_ROUT PIRQ[E–H] Routing Control 80808080h R/W 6Ch–6Dh LPC_IBDF IOxAPIC Bus:Device:Function 00F8h R/W 70h–7F HPET Configuration 80h LPC_I/O_DEC I/O Decode Ranges 0000h R/W
LPC Interface Bridge Registers (D31:F0)
468 Datasheet
13.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0)
Offset Address: 00h –01h Attribute: RO Default Value: 8086h Size: 16-bit Lockable: No Power Well: Core
13.1.2 DID—Device Identification Register (LPC I/F—D31:F0)
Offset Address: 02h –03h Attribute: RO Default Value: See bit description Size: 16-bit Lockable: No Power Well: Core 82h–83h LPC_EN LPC I/F Enables 0000h R/W 84h–87h GEN1_DEC LPC I/F Generic Decode Range 1 00000000h R/W 88h–8Bh GEN2_DEC LPC I/F Generic Decode Range 2 00000000h R/W 8Ch–8Eh GEN3_DEC LPC I/F Generic Decode Range 3 00000000h R/W 90h–93h GEN4_DEC LPC I/F Generic Decode Range 4 00000000h R/W 94h–97h ULKMC USB Legacy Keyboard / Mouse Control 98h–9Bh LGMR LPC Generic Memory Range 00000000h R/W A0h–CFh Power Management (See Section 13.8.1) D0h–D3h FWH_SEL1 Firmware Hub Select 1 00112233h R/W, RO D4h–D5h FWH_SEL2 Firmware Hub Select 2 4567h R/W D8h–D9h FWH_DEC_EN1 Firmware Hub Decode Enable 1 FFCFh R/W, RO DCh BIOS_CNTL BIOS Control 00h R/WLO, R/W, RO E0h–E1h FDCAP Feature Detect ion Capability ID 0009h RO E2h FDLEN Feature Detection Capability Length 0Ch RO E3h FDVER Feature Detection Version 10h RO E4h–EBh FDVCT Feature Vector See Description RO F0h–F3h RCBA Root Complex Base Address 00000000h R/W Table 13-1. LPC Interface PCI Register Addr ess Map (LPC I/F—D31:F0) (Sheet 2 of 2) Offset Mnemonic Register Name Default Type Bit Description 15:0 Vendor ID—RO. This is a 16-bit value assi gned to Intel. Intel VID = 8086h Bit Description 15:0 Device ID— RO. This is a 16-bit value assigned to the PCH LPC bridge. See the Intel®
5 Series Chipset and Intel® 3400 Series Chipset Specification Update for the value of
the Device ID Register.
LPC Interface Bridge Registers (D31:F0)
13.1.3 PCICMD—PCI COMMAND Re gister (LPC I/F—D31:F0)
Offset Address: 04h –05h Attribute: R/W, RO Default Value: 0007h Size: 16-bit Lockable: No Power Well: Core Bit Description 15:10 Reserved 9 Fast Back to Back Enable (FBE)—RO. Hardwired to 0. 8 SERR# Enable (SERR_EN)— R/W. The LPC bridge generates SERR# if this bit is set. 7 Wait Cycle Control (WCC)—RO. Hardwired to 0. Parity Error Response Enable (PERE)— R/W. 0 = No action is taken when detecting a parity error. 1 = Enables the PCH LPC bridge to respond to parity errors detected on backbone interface. 5 VGA Palette Snoop (VPS)—RO. Hardwired to 0. 4 Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0. 3 Special Cycle En able (SCE)—RO. Hardwired to 0. 2 Bus Master Enable (BME)—RO. Bus Masters cannot be disabled. 1 Memory Space Enable (MSE)—RO. Memory space cannot be disabled on LPC. 0 I/O Space Enable (IOS E)—RO. I/O space cannot be disabled on LPC.
LPC Interface Bridge Registers (D31:F0)
470 Datasheet
13.1.4 PCISTS—PCI Status Re gister (LPC I/F—D31:F0)
Offset Address: 06h –07h Attribute: RO, R/WC Default Value: 0210h Size: 16-bit Lockable: No Power Well: Core Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no effect. Bit Description Detected Parity Error (DPE)— R/WC. Set when the LPC bridge detects a parity error on the internal backbone. Set even if the PCICMD.PERE bit (D31:F0:04, bit 6) is 0 = Parity Error Not detected. 1 = Parity Error detected. 14 Signaled System Error (SSE)—R/WC. Set when the LPC bridge signals a system error to the internal SERR# logic. Master Abort Status (RMA)— R/WC. 0 = Unsupported request status not received. 1 = The bridge received a completion with unsupported request status from the backbone. Received Target Abort (RTA)— R/WC. 0 = Completion abort not received. 1 = Completion with completion abort received from the backbone. Signaled Target Abort (STA)— R/WC. 0 = Target abort Not generated on the backbone. 1 = LPC bridge generated a completion packet with target abort status on the backbone. 10:9 DEVSEL# Timing Status (DEV_STS)— RO. 01 = Medium Timing. Data Parity Error Detected (DPED)— R/WC. 0 = All conditions listed below Not met. 1 = Set when all three of the following conditions are met:
- LPC bridge receives a co mpletion packet from the backbone from a previous request,
- Parity error has been detected (D31:F0:06, bit 15)
- PCICMD.PERE bit (D31:F0 :04, bit 6) is set.
7 Fast Back to Back Capable (FBC): Reserved – bit has no meaning on the internal
backbone. 5 66 MHz Capable (66MHZ_CAP)—Reserved – bit has no meaning on the internal backbone. 4 Capabilities List (CLIST)— RO. Capability list exists on the LPC bridge. 3 Interrupt Status (IS)—RO. The LPC bridge does not generate interrupts. 2:0 Reserved
LPC Interface Bridge Registers (D31:F0)
13.1.5 RID—Revision Identification Register (LPC I/F—D31:F0)
Offset Address: 08h Attribute: RO Default Value: See bit description Size: 8 bits
13.1.6 PI—Programming Interface Register (LPC I/F—D31:F0)
Offset Address: 09h Attribute: RO Default Value: 00h Size: 8 bits
13.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Ah Attribute: RO Default Value: 01h Size: 8 bits
13.1.8 BCC—Base Clas s Code Register (LPC I/F—D31:F0)
Offset Address: 0Bh Attribute: RO Default Value: 06h Size: 8 bits
13.1.9 PLT—Primary La tency Timer Register (LPC I/F—D31:F0)
Offset Address: 0Dh Attribute: RO Default Value: 00h Size: 8 bits Bit Description 7:0 Revision ID (RID)— RO. See the Intel® 5 Series Chipset and Intel® 3400 Series Chipset Specification Update for the value of the Revision ID Register Bit Description 7:0 Programming Interface—RO. Bit Description 7:0 Sub Class Code—RO. 8-bit value that indicates th e category of bridge for the LPC bridge. 01h = PCI-to-ISA bridge. Bit Description 7:0 Base Class Code—RO. 8-bit value that indicates the type of device for the LPC bridge. 06h = Bridge device. Bit Description 7:3 Master Latency Count (MLC)—Reserved. 2:0 Reserved
LPC Interface Bridge Registers (D31:F0)
472 Datasheet
13.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0)
Offset Address: 0Eh Attribute: RO Default Value: 80h Size: 8 bits
13.1.11 SS—Sub System Identifier s Register (LPC I/F—D31:F0)
Offset Address: 2Ch –2Fh Attribute: R/WO Default Value: 00000000h Size: 32 bits This register is initialized to logic 0 by the assertion of PLTRST#. This register can be written only once after PLTRST# de-assertion.
13.1.12 CAPP—Capability List Poin ter Register (LPC I/F—D31:F0)
Offset Address: 34h Attribute: RO Default Value: E0h Size: 8 bits
13.1.13 PMBASE—ACPI Base Addres s Register (LPC I/F—D31:F0)
Offset Address: 40h –43h Attribute: R/W, RO Default Value: 00000001h Size: 32 bit Lockable: No Usage: ACPI, Legacy Power Well: Core Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These registers can be mapped anywhere in the 64-K I/O space on 128-byte boundaries. Bit Description 7 Multi-Function Device— RO. This bit is 1 to indicate a multi-function device. 6:0 Header Type— RO. This 7-bit field identifies the header layout of the configuration space. Bit Description 31:16 Subsystem ID (SSID)— R/WO. This is written by BIOS. No hardware action taken on this value. 15:0 Subsystem Vendor ID (SSVID)— R/WO. This is written by BIOS. No hardware action taken on this value. Bit Description 7:0 Capability Pointer (CP)— RO. Indicates the offset of the first Capability Item. Bit Description 31:16 Reserved 15:7 Base Address—R/W. This field provides 128 byte s of I/O space for ACPI, GPIO, and TCO logic. This is placed on a 128-byte boundary. 6:1 Reserved 0 Resource Type Indicator (RTE)—RO. Ha rdwired to 1 to indicate I/O space.
LPC Interface Bridge Registers (D31:F0)
13.1.14 ACPI_CNTL—ACPI Control Register (LPC I/F—D31:F0)
Offset Address: 44h Attribute: R/W Default Value: 00h Size: 8 bit Lockable: No Usage: ACPI, Legacy Power Well: Core
13.1.15 GPIOBASE—GPIO Ba se Address Register
(LPC I/F—D31:F0) Offset Address: 48h–4Bh Attribute: R/W, RO Default Value: 00000001h Size: 32 bit Bit Description ACPI Enable (ACPI_EN)— R/W. 0 = Disable. 1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the ACPI power management function is enabled. Note that the APM power management ranges (B2/B3h) are always enabled and are not affected by this bit. 6:3 Reserved 2:0 SCI IRQ Select (SCI_IRQ_SEL)— R/W. Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI must be routed to IRQ9–11, and that interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the SCI can also be mapped to IRQ20–23, and can be shared with other interrupts. When the interrupt is mapped to APIC interrupts 9, 10, or 11, the APIC should be programmed for active-high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC should be programmed for active-low reception. 000b IRQ9 001b IRQ10 010b IRQ11 011b Reserved 100b IRQ20 (Only available if APIC enabled) 101b IRQ21 (Only available if APIC enabled) 110b IRQ22 (Only available if APIC enabled) 111b IRQ23 (Only available if APIC enabled) Bit Description 31:16 Reserved. Always 0. 15:7 Base Address (BA)— R/W. Provides the 128 bytes of I/O space for GPIO. 6:1 Reserved. Always 0. 0 RO. Hardwired to 1 to indicate I/O space.
LPC Interface Bridge Registers (D31:F0)
474 Datasheet
13.1.16 GC—GPIO Control Regi ster (LPC I/F—D31:F0)
Offset Address: 4Ch Attribute: R/W Default Value: 00h Size: 8 bit Bit Description 7:5 Reserved GPIO Enable (EN)— R/W. This bit enables/disables decode of the I/O range pointed to by the GPIO Base Address register (D31:F0:48h) and enables the GPIO function. 0 = Disable. 1 = Enable. 3:1 Reserved GPIO Lockdown Enable (GLE)—R/W. This bit enables lockdown of the following GPIO registers:
- Offset 00h: GPIO_USE_SEL
- Offset 04h: GP_IO_SEL
- Offset 0Ch: GP_LVL
- Offset 30h: GPIO_USE_SEL2
- Offset 34h: GP_IO_SEL2
- Offset 38h: GP_LVL2
- Offset 40h: GPIO_USE_SEL3
- Offset 44h: GP_IO_SEL3
- Offset 48h: GP_LVL3
- Offset 60h: GP_RST_SEL 0 = Disable. 1 = Enable. When this bit is written from 1-to-0, an SMI# is generated, if enabled. This ensures that only SMM code can change the above GPIO registers after they are locked down.
LPC Interface Bridge Registers (D31:F0)
13.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C, D] Routing Control Register
(LPC I/F—D31:F0) Offset Address: PIRQA – 60h, PIRQB – 61h, Attribute: R/W PIRQC – 62h, PIRQD – 63h Default Value: 80h Size: 8 bit Lockable: No Power Well: Core Bit Description Interrupt Routing Enable (IRQEN)— R/W. 0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0]. 1 = The PIRQ is not routed to the 8259. NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The value of this bit may subsequently be changed by the OS when setting up for I/O APIC interrupt delivery mode. 6:4 Reserved 3:0 IRQ Routing—R/W. (ISA compatible.) Value IRQ Value IRQ 0000b Reserved 1000b Reserved 0001b Reserved 1001b IRQ9 0010b Reserved 1010b IRQ10 0011b IRQ3 1011b IRQ11 0100b IRQ4 1100b IRQ12 0101b IRQ5 1101b Reserved 0110b IRQ6 1110b IRQ14 0111b IRQ7 1111b IRQ15
LPC Interface Bridge Registers (D31:F0)
476 Datasheet
(LPC I/F—D31:F0) Offset Address: 64h Attribute: R/W, RO Default Value: 10h Size: 8 bit Lockable: No Power Well: Core Bit Description Serial IRQ Enable (SIRQEN)— R/W. 0 = The buffer is input only and internally SERIRQ will be a 1. 1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ. Serial IRQ Mode Select (SIRQMD)— R/W. 0 = The serial IRQ machine will be in quiet mode. 1 = The serial IRQ machine will be in continuous mode. NOTE: For systems using Quiet Mode, this bit should be set to 1 (Continuous Mode) for at least one frame after coming out of reset before switching back to Quiet Mode. Failure to do so will result in the PCH not recognizing SERIRQ interrupts. 5:2 Serial IRQ Frame Size (SIRQSZ)— RO. Fixed field that indicates the size of the SERIRQ frame as 21 frames. 1:0 Start Frame Pulse Width (SFPW)— R/W. This is the number of PCI clocks that the SERIRQ pin will be driven low by the serial IRQ machine to signal a start frame. In continuous mode, the PCH will drive the start frame for the number of clocks specified. In quiet mode, the PCH will drive the start frame for the number of clocks specified minus one, as the first clock was driven by the peripheral. 00 = 4 clocks 01 = 6 clocks 10 = 8 clocks 11 = Reserved
LPC Interface Bridge Registers (D31:F0) (LPC I/F—D31:F0) Offset Address: PIRQE – 68h, PIRQF – 69h, Attribute: R/W PIRQG – 6Ah, PIRQH – 6Bh Default Value: 80h Size: 8 bit Lockable: No Power Well: Core
13.1.20 LPC_IBDF—IOxAPIC Bu s:Device:Function Register
(LPC I/F—D31:F0) Offset Address: 6Ch–6Dh Attribute: R/W Default Value: 00F8h Size: 16 bit Bit Description Interrupt Routing Enable (IRQEN)— R/W. 0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified in bits[3:0]. 1 = The PIRQ is not routed to the 8259. NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are being used. The value of this bit may subsequently be changed by the OS when setting up for I/O APIC interrupt delivery mode. 6:4 Reserved 3:0 IRQ Routing—R/W. (ISA compatible.) QQ 0000b Reserved 1000b Reserved 0001b Reserved 1001b IRQ9 0010b Reserved 1010b IRQ10 0011b IRQ3 1011b IRQ11 0100b IRQ4 1100b IRQ12 0101b IRQ5 1101b Reserved 0110b IRQ6 1110b IRQ14 0111b IRQ7 1111b IRQ15 Bit Description 15:0 IOxAPIC Bus:Device:Function (IBDF)—R/W. this field specifies the bus:device:function that PCH’s IOxAPIC will be using for the following:
- As the Requester ID when initiating Interrupt Messages to the processor.
- As the Completer ID when responding to the reads targeting the IOxAPIC’s Memory-Mapped I/O registers. The 16-bit field comprises the following: This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can program this field to provide a unique bus:device:function number for the internal IOxAPIC. p 15:8 Bus Number 7:3 Device Number 2:0 Function Number
LPC Interface Bridge Registers (D31:F0)
478 Datasheet
13.1.21 LPC_HnBDF—HPET n Bu s:Device:Function Register
(LPC I/F—D31:F0) Address Offset H 0BDF 70h–71h H1BDF 72h–73h H2BDF 74h–75h H3BDF 76h–77h H4BDF 78h–79h H5BDF 7Ah–7Bh H6BDF 7Ch–7Dh H7BDF 7Eh–7Fh Attribute: R/W Default Value: 00F8h Size: 16 bit Bit Description 15:0 HPET n Bus:Device:Function (HnBDF)— R/W. This field specifies the bus:device:function that the PCH’s HPET n will be using in the following:
- As the Requester ID when initiating Interrupt Messages to the processor
- As the Completer ID when responding to the reads targeting the corresponding HPET’s Memory-Mapped I/O registers The 16-bit field comprises the following: This field is default to Bus 0: Device 31: Function 0 after reset. BIOS shall program this field accordingly if unique bus:device:function number is required for the corresponding HPET. Bits Description 15:8 Bus Number 7:3 Device Number 2:0 Function Number
LPC Interface Bridge Registers (D31:F0)
13.1.22 LPC_I/O_DEC—I/O De code Ranges Register
(LPC I/F—D31:F0) Offset Address: 80h Attribute: R/W Default Value: 0000h Size: 16 bit Bit Description 15:13 Reserved FDD Decode Range—R/W. Determines which range to decode for the FDD Port 0 = 3F0h–3F5h, 3F7h (Primary) 1 = 370h–375h, 377h (Secondary) 11:10 Reserved 9:8 LPT Decode Range—R/W. This field determines which range to decode for the LPT Port. 00 = 378h–37Fh and 778h–77Fh 01 = 278h–27Fh (port 279h is read only) and 678h–67Fh 10 = 3BCh –3BEh and 7BCh–7BEh 11 = Reserved 7R e s e r v e d 6:4 COMB Decode Range—R/W. This field determines wh ich range to decode for the COMB Port. 000 = 3F8h–3FFh (COM1) 001 = 2F8h–2FFh (COM2) 010 = 220h–227h 011 = 228h–22Fh 100 = 238h–23Fh 101 = 2E8h–2EFh (COM4) 110 = 338h–33Fh 111 = 3E8h–3EFh (COM3) 3R e s e r v e d 2:0 COMA Decode Range—R/W. This field determines wh ich range to decode for the COMA Port. 000 = 3F8h–3FFh (COM1) 001 = 2F8h–2FFh (COM2) 010 = 220h–227h 011 = 228h–22Fh 100 = 238h–23Fh 101 = 2E8h–2EFh (COM4) 110 = 338h–33Fh 111 = 3E8h–3EFh (COM3)
LPC Interface Bridge Registers (D31:F0)
480 Datasheet
13.1.23 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)
Offset Address: 82h –83h Attribute: R/W Default Value: 0000h Size: 16 bit Power Well: Core Bit Description 15:14 Reserved CNF2_LPC_EN—R/W. Microcontroller Enable # 2. 0 = Disable. 1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This range is used for a microcontroller. CNF1_LPC_EN—R/W. Super I/O Enable. 0 = Disable. 1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This range is used for Super I/O devices. MC_LPC_EN—R/W. Microcontroller Enable # 1. 0 = Disable. 1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This range is used for a microcontroller. KBC_LPC_EN—R/W. Keyboard Enable. 0 = Disable. 1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This range is used for a microcontroller. GAMEH_LPC_EN—R/W. High Gameport Enable 0 = Disable. 1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This range is used for a gameport. GAMEL_LPC_EN—R/W. Low Gameport Enable 0 = Disable. 1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This range is used for a gameport. 7:4 Reserved FDD_LPC_EN—R/W. Floppy Drive Enable 0 = Disable. 1 = Enables the decoding of the FDD range to the LPC interface. This range is selected in the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 12). LPT_LPC_EN—R/W. Parallel Port Enable 0 = Disable. 1 = Enables the decoding of the LPTrange to the LPC interface. This range is selected in the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 9:8). COMB_LPC_EN—R/W. Com Port B Enable 0 = Disable. 1 = Enables the decoding of the COMB range to the LPC interface. This range is selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 6:4). COMA_LPC_EN—R/W. Com Port A Enable 0 = Disable. 1 = Enables the decoding of the COMA range to the LPC interface. This range is selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 3:2).
LPC Interface Bridge Registers (D31:F0)
13.1.24 GEN1_DEC—LPC I/F Generi c Decode Range 1 Register
(LPC I/F—D31:F0) Offset Address: 84h –87h Attribute: R/W Default Value: 00000000h Size: 32 bit Power Well: Core
13.1.25 GEN2_DEC—LPC I/F Generi c Decode Range 2 Register
(LPC I/F—D31:F0) Offset Address: 88h –8Bh Attribute: R/W Default Value: 00000000h Size: 32 bit Power Well: Core Bit Description 31:24 Reserved 23:18 Generic I/O Decode Range Address[7:2] Mask— R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in size. 17:16 Reserved 15:2 Generic I/O Decode Range 1 Base Address (GEN1_BASE)— R/W. NOTE: The PCH Does not provide decode down to the word or byte level 1R e s e r v e d Generic Decode Range 1 Enable (GEN1_EN)— R/W. 0 = Disable. 1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F Bit Description 31:24 Reserved 23:18 Generic I/O Decode Range Address[7:2] Mask— R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in size. 17:16 Reserved 15:2 Generic I/O Decode Range 2 Base Address (GEN1_BASE)— R/W. NOTE: The PCH does not provide decode down to the word or byte level. 1R e s e r v e d Generic Decode Range 2 Enable (GEN2_EN)— R/W. 0 = Disable. 1 = Enable the GEN2 I/O range to be forwarded to the LPC I/F
LPC Interface Bridge Registers (D31:F0)
482 Datasheet
13.1.26 GEN3_DEC—LPC I/F Generi c Decode Range 3 Register
(LPC I/F—D31:F0) Offset Address: 8Ch–8Eh Attribute: R/W Default Value: 00000000h Size: 32 bit Power Well: Core
13.1.27 GEN4_DEC—LPC I/F Generi c Decode Range 4 Register
(LPC I/F—D31:F0) Offset Address: 90h–93h Attribute: R/W Default Value: 00000000h Size: 32 bit Power Well: Core Bit Description 31:24 Reserved 23:18 Generic I/O Decode Range Address[7:2] Mask— R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in size. 17:16 Reserved 15:2 Generic I/O Decode Range 3 Base Address (GEN3_BASE)— R/W. NOTE: The PCH Does not provide decode down to the word or byte level Generic Decode Range 3 Enable (GEN3_EN)— R/W. 0 = Disable. 1 = Enable the GEN3 I/O range to be forwarded to the LPC I/F Bit Description 31:24 Reserved 23:18 Generic I/O Decode Range Address[7:2] Mask— R/W. A 1 in any bit position indicates that any value in the corresponding address bit in a received cycle will be treated as a match. The corresponding bit in the Address field, below, is ignored. The mask is only provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to 256 bytes in size. 17:16 Reserved 15:2 Generic I/O Decode Range 4 Base Address (GEN4_BASE)— R/W. NOTE: The PCH Does not provide decode down to the word or byte level Generic Decode Range 4 Enable (GEN4_EN)— R/W. 0 = Disable. 1 = Enable the GEN4 I/O range to be forwarded to the LPC I/F
LPC Interface Bridge Registers (D31:F0)
13.1.28 ULKMC—USB Legacy Ke yboard / Mouse Control
Register (LPC I/F—D31:F0) Offset Address: 94h–97h Attribute: RO, RWC, R/W Default Value: 00002000h Size: 32 bit Power Well: Core Bit Description 31:16 Reserved SMI Caused by End of Pass-Through (SMIBYENDPS)— R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 7, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred 14:12 Reserved SMI Caused by Port 64 Write (TRAPBY64W)— R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 3, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. SMI Caused by Port 64 Read (TRAPBY64R)— R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 2, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. SMI Caused by Port 60 Write (TRAPBY60W)— R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in bit 1, this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. SMI Caused by Port 60 Read (TRAPBY60R)— R/WC. This bit indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 = Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 = Event Occurred. SMI at End of Pass-Through Enable (SMIATENDPS)—R/W. This bit enables SMI at the end of a pass-through. This can occur if an SMI is generated in the middle of a pass-through, and needs to be serviced later. 0 = Disable 1 = Enable Pass Through State (PSTATE)—RO. 0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to 1 = Indicates that the state machine is in the middle of an A20GATE pass-through sequence.
LPC Interface Bridge Registers (D31:F0)
484 Datasheet
(LPC I/F—D31:F0) Offset Address: 98h–9Bh Attribute: R/W Default Value: 00000000h Size: 32 bit Power Well: Core A20Gate Pass-Through Enable (A20PASSEN)— R/W. 0 = Disable. 1 = Enable. Allows A20GATE sequence Pass-Through function. A specific cycle sequence involving writes to port 60h and 64h does not result in the setting of the SMI status bits. SMI on USB IRQ Enable (USBSMIEN)— R/W. 0 = Disable 1 = Enable. USB interrupt will cause an SMI event. SMI on Port 64 Writes Enable (64WEN)— R/W. 0 = Disable 1 = Enable. A 1 in bit 11 will cause an SMI event. SMI on Port 64 Reads Enable (64REN)— R/W. 0 = Disable 1 = Enable. A 1 in bit 10 will cause an SMI event. SMI on Port 60 Writes Enable (60WEN)— R/W. 0 = Disable 1 = Enable. A 1 in bit 9 will cause an SMI event. SMI on Port 60 Reads Enable (60REN)— R/W. 0 = Disable 1 = Enable. A 1 in bit 8 will cause an SMI event. Bit Description Bit Description 31:16 Memory Address[31:16]— R/W. This field specifies a 64 KB memory block anywhere in the 4 GB memory space that will be decoded to LPC as standard LPC memory cycle if enabled. 15:1 Reserved 0 LPC Memory Range Decode Enable—R/W. When this bit is set to 1, then the range specified in bits 31:16 of this register is enabled for decoding to LPC.
LPC Interface Bridge Registers (D31:F0) (LPC I/F—D31:F0) Offset Address: D0h –D3h Attribute: R/W, RO Default Value: 00112233h Size: 32 bits Bit Description 31:28 FWH_F8_IDSEL—RO. IDSEL for two 512-KB Firmwa re Hub memory ranges and one 128-KB memory range. This field is fixed at 0000. The IDSEL programmed in this field addresses the following memory ranges: FFF8 0000h–FFFF FFFFh FFB8 0000h–FFBF FFFFh 000E 0000h–000F FFFFh 27:24 FWH_F0_IDSEL—R/W. IDSEL for two 512-KB Firm ware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFF0 0000h–FFF7 FFFFh FFB0 0000h–FFB7 FFFFh 23:20 FWH_E8_IDSEL—R/W. IDSEL for two 512-KB Firm ware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFE8 0000h–FFEF FFFFh FFA8 0000h–FFAF FFFFh 19:16 FWH_E0_IDSEL—R/W. IDSEL for two 512-KB Firm ware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFE0 0000h–FFE7 FFFFh FFA0 0000h–FFA7 FFFFh 15:12 FWH_D8_IDSEL—R/W. IDSEL for two 512-KB Firm ware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFD8 0000h–FFDF FFFFh FF98 0000h–FF9F FFFFh 11:8 FWH_D0_IDSEL—R/W. IDSEL for two 512-KB Firm ware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFD0 0000h–FFD7 FFFFh FF90 0000h–FF97 FFFFh 7:4 FWH_C8_IDSEL—R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFC8 0000h–FFCF FFFFh FF88 0000h–FF8F FFFFh 3:0 FWH_C0_IDSEL—R/W. IDSEL for two 512-KB Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FFC0 0000h–FFC7 FFFFh FF80 0000h–FF87 FFFFh
LPC Interface Bridge Registers (D31:F0)
486 Datasheet
(LPC I/F—D31:F0) Offset Address: D4h –D5h Attribute: R/W Default Value: 4567h Size: 16 bits Bit Description 15:12 FWH_70_IDSEL—R/W. IDSEL for two, 1-M Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF70 0000h–FF7F FFFFh FF30 0000h–FF3F FFFFh 11:8 FWH_60_IDSEL—R/W. IDSEL for two, 1-M Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF60 0000h–FF6F FFFFh FF20 0000h–FF2F FFFFh 7:4 FWH_50_IDSEL—R/W. IDSEL for two, 1-M Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF50 0000h–FF5F FFFFh FF10 0000h–FF1F FFFFh 3:0 FWH_40_IDSEL—R/W. IDSEL for two, 1-M Firmware Hub memory ranges. The IDSEL programmed in this field addresses the following memory ranges: FF40 0000h–FF4F FFFFh FF00 0000h–FF0F FFFFh
LPC Interface Bridge Registers (D31:F0)
13.1.32 FWH_DEC_EN 1—Firmware Hub Decode Enable
Register (LPC I/F—D31:F0) Offset Address: D8h –D9h Attribute: R/W, RO Default Value: FFCFh Size: 16 bits Bit Description FWH_F8_EN—RO. This bit enables decoding two 512-KB Firmware Hub memory ranges, and one 128-KB memory range. 0 = Disable 1 = Enable the following ranges for the Firmware Hub FFF80000h–FFFFFFFFh FFB80000h–FFBFFFFFh FWH_F0_EN—R/W. This bit enables decoding two 512-KB Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub: FFF00000h–FFF7FFFFh FFB00000h–FFB7FFFFh FWH_E8_EN—R/W. This bit enables decoding two 512-KB Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub: FFE80000h–FFEFFFFh FFA80000h–FFAFFFFFh FWH_E0_EN—R/W. This bit enables decoding two 512-KB Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub: FFE00000h–FFE7FFFFh FFA00000h–FFA7FFFFh FWH_D8_EN—R/W. This bit enables decoding two 512-KB Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FFD80000h–FFDFFFFFh FF980000h–FF9FFFFFh FWH_D0_EN—R/W. This bit enables decoding two 512-KB Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FFD00000h–FFD7FFFFh FF900000h–FF97FFFFh FWH_C8_EN—R/W. This bit enables decoding two 512-KB Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FFC80000h–FFCFFFFFh FF880000h–FF8FFFFFh FWH_C0_EN—R/W. This bit enables decoding two 512-KB Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FFC00000h–FFC7FFFFh FF800000h–FF87FFFFh
LPC Interface Bridge Registers (D31:F0)
488 Datasheet
NOTE: This register effects the BIOS decode regardless of whether the BIOS is resident on LPC or SPI. The concept of Feature Space does not apply to SPI-based flash. The PCH simply decodes these ranges as memory accesses when enabled for the SPI flash interface. FWH_Legacy_F_EN—R/W. This enables the decoding of the legacy 64KB range at F0000h–FFFFFh. 0 = Disable. 1 = Enable the following legacy ranges for the Firmware Hub F0000h–FFFFFh NOTE: The decode for the BIOS legacy F segment is enabled only by this bit and is not affected by the GEN_PMCON_1.iA64_EN bit. FWH_Legacy_E_EN—R/W. This enables the decoding of the legacy 64KB range at E0000h–EFFFFh. 0 = Disable. 1 = Enable the following legacy ranges for the Firmware Hub E0000h–EFFFFh NOTE: The decode for the BIOS legacy E segment is enabled only by this bit and is not affected by the GEN_PMCON_1.iA64_EN bit. 5:4 Reserved FWH_70_EN—R/W. Enables decoding two 1-M Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FF70 0000h–FF7F FFFFh FF30 0000h–FF3F FFFFh FWH_60_EN—R/W. Enables decoding two 1-M Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FF60 0000h–FF6F FFFFh FF20 0000h–FF2F FFFFh FWH_50_EN— R/W. Enables decoding two 1-M Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FF50 0000h–FF5F FFFFh FF10 0000h–FF1F FFFFh FWH_40_EN—R/W. Enables decoding two 1-M Firmware Hub memory ranges. 0 = Disable. 1 = Enable the following ranges for the Firmware Hub FF40 0000h–FF4F FFFFh FF00 0000h–FF0F FFFFh Bit Description
LPC Interface Bridge Registers (D31:F0) (LPC I/F—D31:F0) Offset Address: DCh Attribute: R/WLO, R/W, RO Default Value: 20h Size: 8 bit Lockable: No Power Well: Core Bit Description 7:6 Reserved SMM BIOS Write Protect Disable (SMM_BWP)—R/WLO. This bit set defines when the BIOS region can be written by the host. 0 = BIOS region SMM protection is disabled. The BIOS Region is writable regardless if Processors are in SMM or not. (Set this field to 0 for legacy behavior) 1 = BIOS region SMM protection is enabled. The BIOS Region is not writable unless all Processors are in SMM. 4 Top Swap Status (TSS)— RO. This bit provides a read-only path to view the state of the Top Swap bit that is at offset 3414h, bit 0. 3:2 SPI Read Configuration (SRC)— R/W. This 2-bit field controls two policies related to BIOS reads on the SPI interface: Bit 3- Prefetch Enable Bit 2- Cache Disable Settings are summarized below: BIOS Lock Enable (BLE)— R/WLO. 0 = Setting the BIOSWE will not cause SMIs. 1 = Enables setting the BIOSWE bit to cause SMIs. Once set, this bit can only be cleared by a PLTRST# BIOS Write Enable (BIOSWE)— R/W. 0 = Only read cycles result in Firmware Hub I/F cycles. 1 = Access to the BIOS space is enabled for both read and write cycles. When this bit is written from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI# is generated. This ensures that only SMI code can update BIOS. p 00b No prefetching, but caching enabled. 64B demand reads load the read buffer cache with “valid” data, allowing repeated code fetches to the same line to complete quickly 01b No prefetching and no caching. One-to-one correspondence of host BIOS reads to SPI cycles. This value can be used to invalidate the cache. 10b Prefetching and Caching enabled. This mode is used for long sequences of short reads to consecutive addresses (i.e, shadowing). 11b Reserved. This is an invalid configuration, caching must be enabled when prefetching is enabled.
LPC Interface Bridge Registers (D31:F0)
490 Datasheet
Register (LPC I/F—D31:F0) Offset Address: E0h–E1h Attribute: RO Default Value: 0009h Size: 16 bit Power Well: Core Register (LPC I/F—D31:F0) Offset Address: E2h Attribute: RO Default Value: 0Ch Size: 8 bit Power Well: Core Register (LPC I/F—D31:F0) Offset Address: E3h Attribute: RO Default Value: 10h Size: 8 bit Power Well: Core Bit Description 15:8 Next Item Pointer (NEXT)—RO. Configuration offset of the next Capability Item. 00h indicates the last item in the Capability List. 7:0 Capability ID— RO. Indicates a Vendor Specific Capability Bit Description 7:0 Capability Length— RO. Indicates the length of this Vendor Specific capability, as required by PCI Specification. Bit Description 7:4 Vendor-Specific Capability ID— RO. A value of 1h in this 4-bit field identifies this Capability as Feature Detection Type. This field allows software to differentiate the Feature Detection Capability from other Vendor-Specific capabilities 3:0 Capability Version— RO. This field indicates the version of the Feature Detection capability
LPC Interface Bridge Registers (D31:F0) (LPC I/F—D31:F0) Offset Address: E4h–EBh Attribute: RO Default Value: See Description Size: 64 bit Power Well: Core (LPC I/F—D31:F0) Offset Address: F0–F3h Attribute: R/W Default Value: 00000000h Size: 32 bit Bit Description 63:45 Reserved Intel® Identity Protection Technology—RO 0 = Capable 1 = Disabled 43:14 Reserved USB* 2.0 Ports 6 and 7—RO 0 = Capable 1 = Disabled
12 Reserved
PCI Express* Ports 7and 8—RO 0 = Capable 1 = Disabled 10:7 Reserved SATA Ports 2 and 3—RO 0 = Capable 1 = Disabled SATA RAID 0/1/5/10 Capability—RO 0 = Capable 1 = Disabled 4:0 Reserved Bit Description 31:14 Base Address (BA)— R/W. Base Address for the root complex register block decode range. This address is aligned on a 16-KB boundary. 13:1 Reserved 0 Enable (EN)— R/W. When set, this bit enables the range specified in BA to be claimed as the Root Complex Register Block.
LPC Interface Bridge Registers (D31:F0)
492 Datasheet
13.2 DMA I/O Registers
Table 13-2. DMA Registers (Sheet 1 of 2) Port Alias Register Name Default Type 00h 10h Channel 0 DMA Base & Current Address Undefined R/W 01h 11h Channel 0 DMA Base & Current Count Undefined R/W 02h 12h Channel 1 DMA Base & Current Address Undefined R/W 03h 13h Channel 1 DMA Base & Current Count Undefined R/W 04h 14h Channel 2 DMA Base & Current Address Undefined R/W 05h 15h Channel 2 DMA Base & Current Count Undefined R/W 06h 16h Channel 3 DMA Base & Current Address Undefined R/W 07h 17h Channel 3 DMA Base & Current Count Undefined R/W 08h 18h Channel 0–3 DMA Command Undefined WO Channel 0–3 DMA Status Undefined RO 0Ah 1Ah Channel 0–3 DMA Write Single Mask 000001XXb WO 0Bh 1Bh Channel 0–3 DMA Channel Mode 000000XXb WO 0Ch 1Ch Channel 0–3 DMA Clear Byte Pointer Undefined WO 0Dh 1Dh Channel 0–3 DMA Master Clear Undefined WO 0Eh 1Eh Channel 0–3 DMA Clear Mask Undefined WO 0Fh 1Fh Channel 0–3 DMA Write All Mask 0Fh R/W 80h 90h Reserved Page Undefined R/W 81h 91h Channel 2 DMA Memory Low Page Undefined R/W 82h — Channel 3 DMA Memory Low Page Undefined R/W 83h 93h Channel 1 DMA Memory Low Page Undefined R/W 84h–86h 94h–96h Reserved Pages Undefined R/W 87h 97h Channel 0 DMA Memory Low Page Undefined R/W 88h 98h Reserved Page Undefined R/W 89h 99h Channel 6 DMA Memory Low Page Undefined R/W 8Ah 9Ah Channel 7 DMA Memory Low Page Undefined R/W 8Bh 9Bh Channel 5 DMA Memory Low Page Undefined R/W 8Ch–8Eh 9Ch–9Eh Reserved Page Undefined R/W 8Fh 9Fh Refresh Low Page Undefined R/W C0h C1h Channel 4 DMA Base & Current Address Undefined R/W C2h C3h Channel 4 DMA Base & Current Count Undefined R/W C4h C5h Channel 5 DMA Base & Current Address Undefined R/W C6h C7h Channel 5 DMA Base & Current Count Undefined R/W C8h C9h Channel 6 DMA Base & Current Address Undefined R/W CAh CBh Channel 6 DMA Base & Current Count Undefined R/W CCh CDh Channel 7 DMA Base & Cu rrent Address Undefined R/W CEh CFh Channel 7 DMA Base & Current Count Undefined R/W
LPC Interface Bridge Registers (D31:F0)
13.2.1 DMABASE_CA—DMA Base an d Current Address Registers
I/O Address: Ch. #0 = 00h; Ch. #1 = 02h Attribute: R/W Ch. #2 = 04h; Ch. #3 = 06h Size: 16 bit (per channel), Ch. #5 = C4h Ch. #6 = C8h but accessed in two 8-bit Ch. #7 = CCh; quantities Default Value: Undefined Lockable: No Power Well:Core D0h D1h Channel 4–7 DMA Command Undefined WO Channel 4–7 DMA Status Undefined RO D4h D5h Channel 4–7 DMA Write Single Mask 000001XXb WO D6h D7h Channel 4–7 DMA Channel Mode 000000XXb WO D8h D9h Channel 4–7 DMA Clear Byte Pointer Undefined WO DAh DBh Channel 4–7 DMA Master Clear Undefined WO DCh DDh Channel 4–7 DMA Clear Mask Undefined WO DEh DFh Channel 4–7 DMA Write All Mask 0Fh R/W Table 13-2. DMA Registers (Sheet 2 of 2) Port Alias Register Name Default Type Bit Description 15:0 Base and Current Address—R/W. This register determines the address for the transfers to be performed. The address specified points to two separate registers. On writes, the value is stored in the Base Address register and copied to the Current Address register. On reads, the value is returned from the Current Address register. The address increments/decrements in the Current Address register after each transfer, depending on the mode of the transfer. If the channel is in auto-initialize mode, the Current Address register will be reloaded from the Base Address register after a terminal count is generated. For transfers to/from a 16-bit slave (channels 5–7), the address is shifted left one bit location. Bit 15 will be shifted into Bit 16. The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop. Before accessing an address register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first
LPC Interface Bridge Registers (D31:F0)
494 Datasheet
13.2.2 DMABASE_CC—DMA Base an d Current Count Registers
I/O Address: Ch. #0 = 01h; Ch. #1 = 03h Attribute: R/W Ch. #2 = 05h; Ch. #3 = 07h Size: 16-bit (per channel), Ch. #5 = C6h; Ch. #6 = CAh but accessed in two 8-bit Ch. #7 = CEh; quantities Default Value: Undefined Lockable: No Power Well:Core
13.2.3 DMAMEM_LP—DMA Memory Low Page Registers
I/O Address: Ch. #0 = 87h; Ch. #1 = 83h Ch. #5 = 8Bh; Ch. #6 = 89h Ch. #7 = 8Ah; Attribute: R/W Default Value: Undefined Size: 8-bit Lockable: No Power Well: Core Bit Description 15:0 Base and Current Count—R/W. This register determines the number of transfers to be performed. The address specified points to two separate registers. On writes, the value is stored in the Base Count register and copied to the Current Count register. On reads, the value is returned from the Current Count register. The actual number of transfers is one more than the number programmed in the Base Count Register (that is, programming a count of 4h results in 5 transfers). The count is decrements in the Current Count register after each transfer. When the value in the register rolls from 0 to FFFFh, a terminal count is generated. If the channel is in auto- initialize mode, the Current Count register will be reloaded from the Base Count register after a terminal count is generated. For transfers to/from an 8-bit slave (channels 0–3), the count register indicates the number of bytes to be transferred. For transfers to/from a 16-bit slave (channels 5–7), the count register indicates the number of words to be transferred. The register is accessed in 8 bit quantities. The byte is pointed to by the current byte pointer flip/flop. Before accessing a count register, the byte pointer flip/flop should be cleared to ensure that the low byte is accessed first. Bit Description 7:0 DMA Low Page (ISA Address bits [23:16])—R/W. This register works in conjunction with the DMA controller's Current Address Register to define the complete 24-bit address for the DMA channel. This register remains static throughout the DMA transfer. Bit 16 of this register is ignored when in 16 bit I/O count by words mode as it is replaced by the bit 15 shifted out from the current address register.
LPC Interface Bridge Registers (D31:F0)
13.2.4 DMACMD—DMA Command Register
I/O Address: Ch. #0 –3 = 08h; Ch. #4–7 = D0h Attribute: WO Default Value: Undefined Size: 8-bit Lockable: No Power Well: Core
13.2.5 DMASTA—DMA Status Register
I/O Address: Ch. #0 –3 = 08h; Ch. #4–7 = D0h Attribute: RO Default Value: Undefined Size: 8-bit Lockable: No Power Well: Core Bit Description 7:5 Reserved. Must be 0. DMA Group Arbitration Priority—WO. Each channel group is individually assigned either fixed or rotating arbitration priority. At part reset, each group is initialized in fixed priority. 0 = Fixed priority to the channel group 1 = Rotating priority to the group. 3 Reserved. Must be 0. DMA Channel Group Enable—WO. Both channel groups are enabled following part reset. 0 = Enable the DMA channel group. 1 = Disable. Disabling channel group 4–7 also disables channel group 0–3, which is cascaded through channel 4. 1:0 Reserved. Must be 0. Bit Description 7:4 Channel Request Status—RO. When a valid DMA reques t is pending for a channel, the corresponding bit is set to 1. When a DMA request is not pending for a particular channel, the corresponding bit is set to 0. The source of the DREQ may be hardware or a software request. Note that channel 4 is the cascade channel, so the request status of channel 4 is a logical OR of the request status for channels 0 through 3. 4 = Channel 0 5 = Channel 1 (5) 6 = Channel 2 (6) 7 = Channel 3 (7) 3:0 Channel Terminal Count Status—RO. When a channel reaches terminal count (TC), its status bit is set to 1. If TC has not been reached, the status bit is set to 0. Channel 4 is programmed for cascade, so the TC bit response for channel 4 is irrelevant: 0 = Channel 0 1 = Channel 1 (5) 2 = Channel 2 (6) 3 = Channel 3 (7)
LPC Interface Bridge Registers (D31:F0)
496 Datasheet
13.2.6 DMA_WRSMSK—DMA Write Single Mask Register
I/O Address: Ch. #0 –3 = 0Ah; Ch. #4–7 = D4h Attribute: WO Default Value: 0000 01xx Size: 8-bit Lockable: No Power Well: Core Bit Description 7:3 Reserved. Must be 0. Channel Mask Select—WO. 0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0]. Therefore, only one channel can be masked / unmasked at a time. 1 = Disable DREQ for the selected channel. 1:0 DMA Channel Select—WO. These bits select the DMA Channel Mode Register to program. 00 = Channel 0 (4) 01 = Channel 1 (5) 10 = Channel 2 (6) 11 = Channel 3 (7)
LPC Interface Bridge Registers (D31:F0)
13.2.7 DMACH_MODE—DMA Channel Mode Register
I/O Address: Ch. #0 –3 = 0Bh; Ch. #4–7 = D6h Attribute: WO Default Value: 0000 00xx Size: 8-bit Lockable: No Power Well: Core Bit Description 7:6 DMA Transfer Mode—WO. Each DMA channel can be programmed in one of four different modes: 00 = Demand mode 01 = Single mode 10 = Reserved 11 = Cascade mode Address Increment/Decrement Select—WO. This bit controls address increment/ decrement during DMA transfers. 0 = Address increment. (default after part reset or Master Clear) 1 = Address decrement. Autoinitialize Enable—WO. 0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count. A part reset or Master Clear disables autoinitialization. 1 = DMA restores the Base Address and Count registers to the current registers following a terminal count (TC). 3:2 DMA Transfer Type—WO. These bits represent the direction of the DMA transfer. When the channel is programmed for cascade mode, (bits[7:6] = 11) the transfer type is irrelevant. 00 = Verify – No I/O or memory strobes generated 01 = Write – Data transferred from the I/O devices to memory 10 = Read – Data transferred from memory to the I/O device 11 = Invalid 1:0 DMA Channel Select—WO. These bits select the DMA Channel Mode Register that will be written by bits [7:2]. 00 = Channel 0 (4) 01 = Channel 1 (5) 10 = Channel 2 (6) 11 = Channel 3 (7)
LPC Interface Bridge Registers (D31:F0)
498 Datasheet
13.2.8 DMA Clear Byte Pointer Register
I/O Address: Ch. #0 –3 = 0Ch; Ch. #4–7 = D8h Attribute: WO Default Value: xxxx xxxx Size: 8-bit Lockable: No Power Well: Core
13.2.9 DMA Master Clear Register
I/O Address: Ch. #0 –3 = 0Dh; Ch. #4–7 = DAh Attribute: WO Default Value: xxxx xxxx Size: 8-bit
13.2.10 DMA_CLMSK—DMA Clear Mask Register
I/O Address: Ch. #0 –3 = 0Eh; Ch. #4–7 = DCh Attribute: WO Default Value: xxxx xxxx Size: 8-bit Lockable: No Power Well: Core Bit Description 7:0 Clear Byte Pointer—WO. No specific pattern. Command enabled with a write to the I/ O port address. Writing to this register initializes the byte pointer flip/flop to a known state. It clears the internal latch used to address the upper or lower byte of the 16-bit Address and Word Count Registers. The latch is also cleared by part reset and by the Master Clear command. This command precedes the first access to a 16-bit DMA controller register. The first access to a 16-bit register will then access the significant byte, and the second access automatically accesses the most significant byte. Bit Description 7:0 Master Clear—WO. No specific pattern. Enabled wi th a write to the port. This has the same effect as the hardware Reset. The Command, Status, Request, and Byte Pointer flip/flop registers are cleared and the Mask Register is set. Bit Description 7:0 Clear Mask Register—WO. No specific pattern. Comm and enabled with a write to the port.
LPC Interface Bridge Registers (D31:F0)
13.2.11 DMA_WRMSK—DMA Write All Mask Register
I/O Address: Ch. #0 –3 = 0Fh; Ch. #4–7 = DEh Attribute: R/W Default Value: 0000 1111 Size: 8-bit Lockable: No Power Well: Core
13.3 Timer I/O Registers
7:4 Reserved. Must be 0. 3:0 Channel Mask Bits—R/W. This register permits all four channels to be simultaneously enabled/disabled instead of enabling/disabling each channel individually, as is the case with the Mask Register – Write Single Mask Bit. In addition, this register has a read path to allow the status of the channel mask bits to be read. A channel's mask bit is automatically set to 1 when the Current Byte/Word Count Register reaches terminal count (unless the channel is in auto-initialization mode). Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0 enables the corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master Clear. When read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask status. Bit 0 = Channel 0 (4)1 = Masked, 0 = Not Masked Bit 1 = Channel 1 (5)1 = Masked, 0 = Not Masked Bit 2 = Channel 2 (6)1 = Masked, 0 = Not Masked Bit 3 = Channel 3 (7)1 = Masked, 0 = Not Masked NOTE: Disabling channel 4 also disables channels 0–3 due to the cascade of channels 0–3 through channel 4. Port Aliases Register Name Default Value Type 40h 50h Counter 0 Interval Time Status Byte Format 0XXXXXXXb RO Counter 0 Counter Access Port Undefined R/W 41h 51h Counter 1 Interval Time Status Byte Format 0XXXXXXXb RO Counter 1 Counter Access Port Undefined R/W 42h 52h Counter 2 Interval Time Status Byte Format 0XXXXXXXb RO Counter 2 Counter Access Port Undefined R/W 43h 53h Timer Control Word Undefined WO Timer Control Word Register XXXXXXX0b WO Counter Latch Command X0h WO
LPC Interface Bridge Registers (D31:F0)
500 Datasheet
13.3.1 TCW—Timer Control Word Register
I/O Address: 43h Attribute: WO Default Value: All bits undefined Size: 8 bits This register is programmed prior to any counter being accessed to specify counter modes. Following part reset, the control words for each register are undefined and each counter output is 0. Each timer must be programmed to bring it into a known state. There are two special commands that can be issued to the counters through this register, the Read Back Command and the Counter Latch Command. When these commands are chosen, several bits within this register are redefined. These register formats are described below: Bit Description 7:6 Counter Select—WO. The Counter Selection bits select the counter the control word acts upon as shown below. The Read Back Command is selected when bits[7:6] are both 1. 00 = Counter 0 select 01 = Counter 1 select 10 = Counter 2 select 11 = Read Back Command 5:4 Read/Write Select—WO. These bits are the read/w rite control bits. The actual counter programming is done through the counter port (40h for counter 0, 41h for counter 1, and 42h for counter 2). 00 = Counter Latch Command 01 = Read/Write Least Significant Byte (LSB) 10 = Read/Write Most Significant Byte (MSB) 11 = Read/Write LSB then MSB 3:1 Counter Mode Selection—WO. These bits select one of six possible modes of operation for the selected counter. Binary/BCD Countdown Select—WO. 0 = Binary countdown is used. The largest possible binary count is 216 1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 104 000b Mode 0 Out signal on end of count (=0) 001b Mode 1 Hardware retriggerable one- shot x10b Mode 2 Rate generator (divide by n counter) x11b Mode 3 Square wave output 100b Mode 4 Software triggered strobe 101b Mode 5 Hardware triggered strobe
LPC Interface Bridge Registers (D31:F0) RDBK_CMD—Read Back Command The Read Back Command is used to determine the count value, programmed mode, and current states of the OUT pin and Null count flag of the selected counter or counters. Status and/or count may be latched in any or all of the counters by selecting the counter during the register write. The count and status remain latched until read, and further latch commands are ignored until the count is read. Both count and status of the selected counters may be latched simultaneously by setting both bit 5 and bit 4 to 0. If both are latched, the first read operation from that counter returns the latched status. The next one or two reads, depending on whether the counter is programmed for one or two byte counts, returns the latched count. Subsequent reads return an unlatched count. LTCH_CMD—Counter Latch Command The Counter Latch Command latches the current count value. This command is used to insure that the count read from the counter is accurate. The count value is then read from each counter's count register through the Counter Ports Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter 2). The count must be read according to the programmed format; that is, if the counter is programmed for two byte counts, two bytes must be read. The two bytes do not have to be read one right after the other (read, write, or programming operations for other counters may be inserted between the reads). If a counter is latched once and then latched again before the count is read, the second Counter Latch Command is ignored. Bit Description 7:6 Read Back Command. Must be 11 to select the Read Back Command Latch Count of Selected Counters. 0 = Current count value of the selected counters will be latched 1 = Current count will not be latched Latch Status of Selected Counters. 0 = Status of the selected counters will be latched 1 = Status will not be latched 3 Counter 2 Select. 1 = Counter 2 count and/or status will be latched 2 Counter 1 Select. 1 = Counter 1 count and/or status will be latched 1 Counter 0 Select. 1 = Counter 0 count and/or status will be latched. 0 Reserved. Must be 0. Bit Description 7:6 Counter Selection. These bits select the counter for latching. If “11” is written, then the write is interpreted as a read back command. 00 = Counter 0 01 = Counter 1 10 = Counter 2 5:4 Counter Latch Command. 00 = Selects the Counter Latch Command. 3:0 Reserved. Must be 0.
LPC Interface Bridge Registers (D31:F0)
502 Datasheet
13.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register
I/O Address: Counter 0 = 40h, Counter 1 = 41h, Attribute: RO Counter 2 = 42h Size: 8 bits per counter Default Value: Bits[6:0] undefined, Bit 7=0 Each counter's status byte can be read following a Read Back Command. If latch status is chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the next read from the counter's Counter Access Ports Register (40h for counter 0, 41h for counter 1, and 42h for counter 2) returns the status byte. The status byte returns the following: Bit Description Counter OUT Pin State—RO. 0 = OUT pin of the counter is also a 0 1 = OUT pin of the counter is also a 1 Count Register Status—RO. This bit indicates when the last count written to the Count Register (CR) has been loaded into the counting element (CE). The exact time this happens depends on the counter mode, but until the count is loaded into the counting element (CE), the count value will be incorrect. 0 = Count has been transferred from CR to CE and is available for reading. 1 = Null Count. Count has not been transferred from CR to CE and is not yet available for reading. 5:4 Read/Write Selection Status—RO. These reflect the re ad/write selection made through bits[5:4] of the control register. The binary codes returned during the status read match the codes used to program the counter read/write selection. 00 = Counter Latch Command 01 = Read/Write Least Significant Byte (LSB) 10 = Read/Write Most Significant Byte (MSB) 11 = Read/Write LSB then MSB 3:1 Mode Selection Status—RO. These bits return the counter mode programming. The binary code returned matches the code used to program the counter mode, as listed under the bit function above. 000 = Mode 0—Out signal on end of count (=0) 001 = Mode 1—Hardware retriggerable one-shot x10 = Mode 2—Rate generator (divide by n counter) x11 = Mode 3—Square wave output 100 = Mode 4—Software triggered strobe 101 = Mode 5—Hardware triggered strobe Countdown Type Status—RO. This bit reflects th e current countdown type. 0 = Binary countdown 1 = Binary Coded Decimal (BCD) countdown.
LPC Interface Bridge Registers (D31:F0)
13.3.3 Counter Access Ports Register
I/O Address: Counter 0 – 40h, Counter 1 – 41h, Attribute: R/W Counter 2 – 42h Default Value: All bits undefined Size: 8 bit 13.4 8259 Interrupt Controller (PIC) Registers
13.4.1 Interrupt Controller I/O MAP
The interrupt controller registers are located at 20h and 21h for the master controller (IRQ 0–7), and at A0h and A1h for the slave controller (IRQ 8–13). These registers have multiple functions, depending upon the data written to them. Table 13-3 shows the different register possibilities for each address. Note: See note addressing active-low interrupt sources in 8259 Interrupt Controllers section (Chapter 5.8). Bit Description 7:0 Counter Port—R/W. Each counter port address is used to program the 16-bit Count Register. The order of programming, either LSB only, MSB only, or LSB then MSB, is defined with the Interval Counter Control Register at port 43h. The counter port is also used to read the current count from the Count Register, and return the status of the counter programming following a Read Back Command. Table 13-3. PIC Registers Port Aliases Register Name Default Value Type 20h 24h, 28h, 2Ch, 30h, 34h, 38h, 3Ch Master PIC ICW1 Init. Cmd Word 1 Undefined WO Master PIC OCW2 Op Ctrl Word 2 001XXXXXb WO Master PIC OCW3 Op Ctrl Word 3 X01XXX10b WO 21h 25h, 29h, 2Dh, 31h, 35h, 39h, 3Dh Master PIC ICW2 Init. Cmd Word 2 Undefined WO Master PIC ICW3 Init. Cmd Word 3 Undefined WO Master PIC ICW4 Init. Cmd Word 4 01h WO Master PIC OCW1 Op Ctrl Word 1 00h R/W A0h A4h, A8h, ACh, B0h, B4h, B8h, BCh Slave PIC ICW1 Init. Cmd Word 1 Undefined WO Slave PIC OCW2 Op Ctrl Word 2 001XXXXXb WO Slave PIC OCW3 Op Ctrl Word 3 X01XXX10b WO A1h A5h, A9h, ADh, B1h, B5h, B9h, BDh Slave PIC ICW2 Init. Cmd Word 2 Undefined WO Slave PIC ICW3 Init. Cmd Word 3 Undefined WO Slave PIC ICW4 Init. Cmd Word 4 01h WO Slave PIC OCW1 Op Ctrl Word 1 00h R/W 4D0h – Master PIC Edge/L evel Triggered 00h R/W 4D1h – Slave PIC Edge/Level Triggered 00h R/W
LPC Interface Bridge Registers (D31:F0)
504 Datasheet
13.4.2 ICW1—Initialization Command Word 1 Register
Offset Address: Master Controller – 20h Attribute: WO Slave Controller – A0h Size: 8 bit /controller Default Value: All bits undefined A write to Initialization Command Word 1 starts the interrupt controller initialization sequence, during which the following occurs: 1. The Interrupt Mask register is cleared. 2. IRQ7 input is assigned priority 7. 3. The slave mode address is set to 7. 4. Special mask mode is cleared and Status Read is set to IRR. Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to complete the initialization sequence. Bit Description 7:5 ICW/OCW Select—WO. These bits are MCS-85 specific, and not needed. 000 = Should be programmed to “000” ICW/OCW Select—WO. 1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4 sequence. 3 Edge/Level Bank Select (LTIM)—WO. Disabled. Replaced by the edge/level triggered control registers (ELCR, D31:F0:4D0h, D31:F0:4D1h). 2 ADI—WO. 0 = Ignored for the PCH. Should be programmed to 0. 1 Single or Cascade (SNGL)—WO. 0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode. ICW4 Write Required (IC4)—WO. 1 = This bit must be programmed to a 1 to indicate that ICW4 needs to be programmed.
LPC Interface Bridge Registers (D31:F0)
13.4.3 ICW2—Initialization Command Word 2 Register
Offset Address: Master Controller – 21h Attribute: WO Slave Controller – A1h Size: 8 bit /controller Default Value: All bits undefined ICW2 is used to initialize the interrupt controller with the five most significant bits of the interrupt vector address. The value programmed for bits[7:3] is used by the processor to define the base address in the interrupt vector table for the interrupt routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h for the master controller and 70h for the slave controller. Offset Address: 21h Attribute: WO Default Value: All bits undefined Size: 8 bits Bit Description 7:3 Interrupt Vector Base Address—WO. Bits [7:3] define the base address in the interrupt vector table for the interrupt routines associated with each interrupt request level input. 2:0 Interrupt Request Level—WO. When writing ICW2, these bi ts should all be 0. During an interrupt acknowledge cycle, these bits are programmed by the interrupt controller with the interrupt to be serviced. This is combined with bits [7:3] to form the interrupt vector driven onto the data bus during the second INTA# cycle. The code is a three bit binary code: 000b IRQ0 IRQ8 001b IRQ1 IRQ9 010b IRQ2 IRQ10 011b IRQ3 IRQ11 100b IRQ4 IRQ12 101b IRQ5 IRQ13 110b IRQ6 IRQ14 111b IRQ7 IRQ15 Bit Description 7:3 0 = These bits must be programmed to 0. Cascaded Interrupt Controller IRQ Connection—WO. This bit indicates that the slave controller is cascaded on IRQ2. When IRQ8#–IRQ15 is asserted, it goes through the slave controller’s priority resolver. The slave controller’s INTR output onto IRQ2. IRQ2 then goes through the master controller’s priority solver. If it wins, the INTR signal is asserted to the processor, and the returning interrupt acknowledge returns the interrupt vector for the slave controller. 1 = This bit must always be programmed to a 1. 1:0 0 = These bits must be programmed to 0.
LPC Interface Bridge Registers (D31:F0)
506 Datasheet
Offset Address: A1h Attribute: WO Default Value: All bits undefined Size: 8 bits
13.4.6 ICW4—Initialization Command Word 4 Register
Offset Address: Master Controller – 021h Attribute: WO Slave Controller – 0A1h Size: 8 bits Default Value: 01h Bit Description 7:3 0 = These bits must be programmed to 0. 2:0 Slave Identification Code—WO. These bits are compared against the slave identification code broadcast by the master controller from the trailing edge of the first internal INTA# pulse to the trailing edge of the second internal INTA# pulse. These bits must be programmed to 02h to match the code broadcast by the master controller. When 02h is broadcast by the master controller during the INTA# sequence, the slave controller assumes responsibility for broadcasting the interrupt vector. Bit Description 7:5 0 = These bits must be programmed to 0. Special Fully Nested Mode (SFNM)—WO. 0 = Should normally be disabled by writing a 0 to this bit. 1 = Special fully nested mode is programmed. 3 Buffered Mode (BUF)—WO. 0 = Must be programmed to 0 for the PCH. This is non-buffered mode. 2 Master/Slave in Buffered Mode—WO. Not used. 0 = Should always be programmed to 0. Automatic End of Interrupt (AEOI)—WO. 0 = This bit should normally be programmed to 0. This is the normal end of interrupt. 1 = Automatic End of Interrupt (AEOI) mode is programmed. Microprocessor Mode—WO. 1 = Must be programmed to 1 to indicate that the controller is operating in an Intel Architecture-based system.
LPC Interface Bridge Registers (D31:F0)
13.4.7 OCW1—Operational Contro l Word 1 (Interrupt Mask)
Offset Address: Master Controller – 021h Attribute: R/W Slave Controller – 0A1h Size: 8 bits Default Value: 00h
13.4.8 OCW2—Operational Co ntrol Word 2 Register
Offset Address: Master Controller – 020h Attribute: WO Slave Controller – 0A0h Size: 8 bits Default Value: Bit[4:0]=undefined, Bit[7:5]=001 Following a part reset or ICW initialization, the controller enters the fully nested mode of operation. Non-specific EOI without rotation is the default. Both rotation mode and specific EOI mode are disabled following initialization. Bit Description 7:0 Interrupt Request Mask—R/W. When a 1 is written to any bit in this register, the corresponding IRQ line is masked. When a 0 is written to any bit in this register, the corresponding IRQ mask bit is cleared, and interrupt requests will again be accepted by the controller. Masking IRQ2 on the master controller will also mask the interrupt requests from the slave controller. Bit Description 7:5 Rotate and EOI Codes (R, SL, EOI)—WO. These three bits control the Rotate and End of Interrupt modes and combinations of the two. 000 = Rotate in Auto EOI Mode (Clear) 001 = Non-specific EOI command 010 = No Operation 011 = *Specific EOI Command 100 = Rotate in Auto EOI Mode (Set) 101 = Rotate on Non-Specific EOI Command 110 = *Set Priority Command 111 = *Rotate on Specific EOI Command *L0 – L2 Are Used 4:3 OCW2 Select—WO. When selecting OCW2, bits 4:3 = 00 2:0 Interrupt Level Select (L2, L1, L0)—WO. L2, L1, and L0 determine the interrupt level acted upon when the SL bit is active. A simple binary code, outlined below, selects the channel for the command to act upon. When the SL bit is inactive, these bits do not have a defined function; programming L2, L1 and L0 to 0 is sufficient in this case. 000b IRQ0/8 000b IRQ4/12 001b IRQ1/9 001b IRQ5/13 010b IRQ2/10 010b IRQ6/14 011b IRQ3/11 011b IRQ7/15
LPC Interface Bridge Registers (D31:F0)
508 Datasheet
13.4.9 OCW3—Operational Control Word 3 Register
Offset Address: Master Controller – 020h Attribute:WO Slave Controller – 0A0h Size: 8 bits Default Value: Bit[6,0]=0, Bit[7,4:2]=undefined, Bit[5,1]=1 Bit Description 7 Reserved. Must be 0. Special Mask Mode (SMM)—WO. 1 = The Special Mask Mode can be used by an interrupt service routine to dynamically alter the system priority structure while the routine is executing, through selective enabling/disabling of the other channel's mask bits. Bit 5, the ESMM bit, must be set for this bit to have any meaning. Enable Special Mask Mode (ESMM)—WO. 0 = Disable. The SMM bit becomes a “don't care”. 1 = Enable the SMM bit to set or reset the Special Mask Mode. 4:3 OCW3 Select—WO. When selecting OCW3, bits 4:3 = 01 Poll Mode Command—WO. 0 = Disable. Poll Command is not issued. 1 = Enable. The next I/O read to the interrupt controller is treated as an interrupt acknowledge cycle. An encoded byte is driven onto the data bus, representing the highest priority level requesting service. 1:0 Register Read Command—WO. These bits provide control for reading the In-Service Register (ISR) and the Interrupt Request Register (IRR). When bit 1=0, bit 0 will not affect the register read selection. When bit 1=1, bit 0 selects the register status returned following an OCW3 read. If bit 0=0, the IRR will be read. If bit 0=1, the ISR will be read. Following ICW initialization, the default OCW3 port address read will be “read IRR”. To retain the current selection (read ISR or read IRR), always write a 0 to bit 1 when programming this register. The selected register can be read repeatedly without reprogramming OCW3. To select a new status register, OCW3 must be reprogrammed prior to attempting the read. 00 = No Action 01 = No Action 10 = Read IRQ Register 11 = Read IS Register
LPC Interface Bridge Registers (D31:F0)
13.4.10 ELCR1—Master Controller Edge/Level Triggered Register
Offset Address: 4D0h Attribute: R/W Default Value: 00h Size: 8 bits In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1), cannot be put into level mode. Bit Description IRQ7 ECL—R/W. 0 = Edge. 1 = Level. IRQ6 ECL—R/W. 0 = Edge. 1 = Level. IRQ5 ECL—R/W. 0 = Edge. 1 = Level. IRQ4 ECL—R/W. 0 = Edge. 1 = Level. IRQ3 ECL—R/W. 0 = Edge. 1 = Level. 2:0 Reserved. Must be 0.
LPC Interface Bridge Registers (D31:F0)
510 Datasheet
13.4.11 ELCR2—Slave Controller Edge/Level Triggered Register
Offset Address: 4D1h Attribute: R/W Default Value: 00h Size: 8 bits In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock, IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level mode. Bit Description IRQ15 ECL—R/W. 0 = Edge 1 = Level IRQ14 ECL—R/W. 0 = Edge 1 = Level 5 Reserved. Must be 0. IRQ12 ECL—R/W. 0 = Edge 1 = Level IRQ11 ECL—R/W. 0 = Edge 1 = Level IRQ10 ECL—R/W. 0 = Edge 1 = Level IRQ9 ECL—R/W. 0 = Edge 1 = Level 0 Reserved. Must be 0.
LPC Interface Bridge Registers (D31:F0)
13.5 Advanced Programmable Interrupt Controller
(APIC)
13.5.1 APIC Register Map
The APIC is accessed using an indirect addressing scheme. Two registers are visible by software for manipulation of most of the APIC registers. These registers are mapped into memory space. The address bits 19:12 of the address range are programmable through bits 7:0 of OIC register (Chipset Config Registers:Offset 31FEh) The registers are shown in Table 13-4. Table 13-5 lists the registers which can be accessed within the APIC using the Index Register. When accessing these registers, accesses must be done one DWord at a time. For example, software should never access byte 2 from the Data register before accessing bytes 0 and 1. The hardware will not attempt to recover from a bad programming model in this case.
13.5.2 IND—Index Register
Memory Address FEC_ _0000h Attribute: R/W Default Value: 00h Size: 8 bits The Index Register will select which APIC indirect register to be manipulated by software. The selector values for the indirect registers are listed in Table 13-5. Software will program this register to select the desired APIC internal register Table 13-4. APIC Direct Registers Address Mnemonic Register Name Size Type FEC_ _0000h IND Index 8 bits R/W FEC_ _0010h DAT Data 32 bits R/W FEC_ _0040h EOIR EOI 32 bits WO Table 13-5. APIC Indirect Registers Index Mnemonic Register Name Size Type
00 ID Identification 32 bits R/W
01 VER Version 32 bits RO
02–0F — Reserved — RO 10–11 REDIR_TBL0 Redirection Table 0 64 bits R/W, RO 12–13 REDIR_TBL1 Redirection Table 1 64 bits R/W, RO 3E–3F REDIR_TBL23 Redirection Table 23 64 bits R/W, RO 40–FF — Reserved — RO Bit Description 7:0 APIC Index—R/W. This is an 8-bit pointer into the I/O APIC register table.
LPC Interface Bridge Registers (D31:F0)
512 Datasheet
13.5.3 DAT—Data Register
Memory Address FEC_ _0000h Attribute: R/W Default Value: 00000000h Size: 32 bits This is a 32-bit register specifying the data to be read or written to the register pointed to by the Index register. This register can only be accessed in DWord quantities.
13.5.4 EOIR—EOI Register
Memory Address FEC_ _0000h Attribute: R/W Default Value: N/A Size: 32 bits The EOI register is present to provide a mechanism to maintain the level triggered semantics for level-triggered interrupts issued on the parallel bus. When a write is issued to this register, the I/O APIC will check the lower 8 bits written to this register, and compare it with the vector field for each entry in the I/O Redirection Table. When a match is found, the Remote_IRR bit (Index Offset 10h, bit 14) for that I/O Redirection Entry will be cleared. Note: If multiple I/O Redirection entries, for any reason, assign the same vector for more than one interrupt input, each of those entries will have the Remote_IRR bit reset to 0. The interrupt, which was prematurely reset, will not be lost because if its input remained active when the Remote_IRR bit was cleared, the interrupt will be reissued and serviced at a later time. Note that only bits 7:0 are actually used. Bits 31:8 are ignored by the PCH. Note: To provide for future expansion, the processor should always write a value of 0 to Bits 31:8. Bit Description 7:0 APIC Data—R/W. This is a 32-bit register for the data to be read or written to the APIC indirect register (Figure 13-5) pointed to by the Index register (Memory Address FEC0_0000h). Bit Description 31:8 Reserved. To provide for future expansion, the processor should always write a value of 0 to Bits 31:8. 7:0 Redirection Entry Clear—WO. When a write is issued to this register, the I/O APIC will check this field, and compare it with the vector field for each entry in the I/O Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection Entry will be cleared.
LPC Interface Bridge Registers (D31:F0)
13.5.5 ID—Identification Register
Index Offset: 00h Attribute: R/W Default Value: 00000000h Size: 32 bits The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset.
13.5.6 VER—Version Register
Index Offset: 01h Attribute: RO, RWO Default Value: 00170020h Size: 32 bits Each I/O APIC contains a hardwired Version Register that identifies different implementation of APIC and their versions. The maximum redirection entry information also is in this register, to let software know how many interrupt are supported by this APIC. Bit Description 31:28 Reserved 27:24 APIC ID—R/W. Software must program this value before using the APIC. 23:16 Reserved 15 Scratchpad Bit. 14:0 Reserved Bit Description 31:24 Reserved 23:16 Maximum Redirection Entries (MRE)— RWO. This is the entry number (0 being the lowest entry) of the highest entry in the redirection table. It is equal to the number of interrupt input pins minus one and is in the range 0 through 239. In the PCH this field is hardwired to 17h to indicate 24 interrupts. BIOS must write to this field after PLTRST# to lockdown the value. this allows BIOS to use some of the entries for its own purpose and thus advertising fewer IOxAPIC Redirection Entries to the OS. 15 Pin Assertion Register Supported (PRQ)—RO. Indicate that the IOxAPIC does not implement the Pin Assertion Register. 14:8 Reserved 7:0 Version (VS)—RO. This is a version number that identifies the implementation version.
LPC Interface Bridge Registers (D31:F0)
514 Datasheet
13.5.7 REDIR_TBL—Redirection Table
Index Offset: 10h –11h (vector 0) through Attribute:R/W, RO 3E–3Fh (vector 23) Default Value: Bit 16 = 1. All other bits undefined Size: 64 bits each, (accessed as two 32 bit quantities) The Redirection Table has a dedicated entry for each interrupt input pin. The information in the Redirection Table is used to translate the interrupt manifestation on the corresponding interrupt pin into an APIC message. The APIC will respond to an edge triggered interrupt as long as the interrupt is held until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery status bit internally to the I/O APIC is set. The state machine will step ahead and wait for an acknowledgment from the APIC unit that the interrupt message was sent. Only then will the I/O APIC be able to recognize a new edge on that interrupt pin. That new edge will only result in a new invocation of the handler if its acceptance by the destination APIC causes the Interrupt Request Register bit to go from 0 to 1. (In other words, if the interrupt was not already pending at the destination.) Bit Description 63:56 Destination—R/W. If bit 11 of this entry is 0 (Physical), then bits 59:56 specifies an APIC ID. In this case, bits 63:59 should be programmed by software to 0. If bit 11 of this entry is 1 (Logical), then bits 63:56 specify the logical destination address of a set of processors. 55:48 Extended Destination ID (EDID)—RO. These bits are sent to a local APIC only when in Processor System Bus mode. They become bits 11:4 of the address. 47:17 Reserved Mask—R/W. 0 = Not masked: An edge or level on this interrupt pin results in the delivery of the interrupt to the destination. 1 = Masked: Interrupts are not delivered nor held pending. Setting this bit after the interrupt is accepted by a local APIC has no effect on that interrupt. This behavior is identical to the device withdrawing the interrupt before it is posted to the processor. It is software's responsibility to deal with the case where the mask bit is set after the interrupt message has been accepted by a local APIC unit but before the interrupt is dispensed to the processor. Trigger Mode—R/W. This field indicates the type of signal on the interrupt pin that triggers an interrupt. 0 = Edge triggered. 1 = Level triggered. Remote IRR—R/W. This bit is used for level tr iggered interrupts; its meaning is undefined for edge triggered interrupts. 0 = Reset when an EOI message is received from a local APIC. 1 = Set when Local APIC/s accept the level interrupt sent by the I/O APIC. Interrupt Input Pin Polarity—R/W. This bit specifies the polarity of each interrupt signal connected to the interrupt pins. 0 = Active high. 1 = Active low. Delivery Status—RO. This field contains the current status of the delivery of this interrupt. Writes to this bit have no effect. 0 = Idle. No activity for this interrupt. 1 = Pending. Interrupt has been injected, but delivery is not complete.
LPC Interface Bridge Registers (D31:F0) NOTE: Delivery Mode encoding: 000 = Fixed. Deliver the signal on the INTR signal of all processor cores listed in the destination. Trigger Mode can be edge or level. 001 = Lowest Priority. Deliver the signal on th e INTR signal of the processor core that is executing at the lowest priority among all the processors listed in the specified destination. Trigger Mode can be edge or level. 010 = SMI (System Management In terrupt). Requires the interrupt to be programmed as edge triggered. The vector information is ignored but must be programmed to all 0s for future compatibility: not supported 011 = Reserved 100 = NMI. Deliver the signal on the NMI signal of all processor cores listed in the destination. Vector information is ignored. NMI is treated as an edge triggered interrupt even if it is programmed as level triggered. For proper operation this redirection table entry must be programmed to edge triggered. The NMI delivery mode does not set the RIRR bit. If the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. Once the count for the NMI pin is reached again, the interrupt will be sent again: not supported 101 = INIT. Deliver the signal to all processor co res listed in the destination by asserting the INIT signal. All addressed local APICs will assume their INIT state. INIT is always treated as an edge triggered interrupt even if programmed as level triggered. For proper operation this redirection table entry must be programmed to edge triggered. The INIT delivery mode does not set the RIRR bit. If the redirection table is incorrectly set to level, the loop count will continue counting through the redirection table addresses. Once the count for the INIT pin is reached again, the interrupt will be sent again: not supported 110 = Reserved 111 = ExtINT. Deliver the signal to the INTR signal of all processor cores listed in the destination as an interrupt that originated in an externally connected 8259A compatible interrupt controller. The INTA cycle that corresponds to this ExtINT delivery will be routed to the external controller that is expected to supply the vector. Requires the interrupt to be programmed as edge triggered. Destination Mode—R/W. This field determines the in terpretation of the Destination field. 0 = Physical. Destination APIC ID is identified by bits 59:56. 1 = Logical. Destinations are identified by matching bit 63:56 with the Logical Destination in the Destination Format Register and Logical Destination Register in each Local APIC. 10:8 Delivery Mode—R/W. This field specifies how the APICs listed in the destination field should act upon reception of this signal. Certain Delivery Modes will only operate as intended when used in conjunction with a specific trigger mode. These encodings are listed in the note below: 7:0 Vector—R/W. This field contains the interrupt vector for this interrupt. Values range between 10h and FEh. Bit Description
LPC Interface Bridge Registers (D31:F0)
516 Datasheet
13.6 Real Time Clock Registers
13.6.1 I/O Register Address Map
The RTC internal registers and RAM are organized as two banks of 128 bytes each, called the standard and extended banks. The first 14 bytes of the standard bank contain the RTC time and date information along with four registers, A–D, that are used for configuration of the RTC. The extended bank contains a full 128 bytes of battery backed SRAM, and will be accessible even when the RTC module is disabled (using the RTC configuration register). Registers A–D do not physically exist in the RAM. All data movement between the host processor and the real-time clock is done through registers mapped to the standard I/O space. The register map appears in Table 13-6. NOTES: 1. I/O locations 70h and 71h are the standard legacy location for the real-time clock. The map for this bank is shown in Table 13-7. Locations 72h and 73h are for accessing the extended RAM. The extended RAM bank is also accessed using an indexed scheme. I/O address 72h is used as the address pointer and I/O address 73h is used as the data register. Index addresses above 127h are not valid. If the extended RAM is not needed, it may be disabled. 2. Software must preserve the value of bit 7 at I/O addresses 70h and 74h. When writing to this address, software must first read the value, and then write the same value for bit 7 during the sequential address write. Note that port 70h is not directly readable. The only way to read this register is through Alt Access mode. Although RTC Index bits 6:0 are readable from port 74h, bit 7 will always return 0. If the NMI# enable is not changed during normal operation, software can alternatively read this bit once and then retain the value for all subsequent writes to port 70h. Table 13-6. RTC I/O Registers I/O Locations If U128E bit = 0 Function 70h and 74h Also alias to 72h and 76h Real-T ime Clock (Standard RAM) Index Register 71h and 75h Also alias to 73h and 77h Real-T ime Clock (Standard RAM) Target Register 72h and 76h Extended RAM In dex Register (if enabled) 73h and 77h Extended RAM Target Register (if enabled)
LPC Interface Bridge Registers (D31:F0)
13.6.2 Indexed Registers
The RTC contains two sets of indexed registers that are accessed using the two separate Index and Target registers (70/71h or 72/73h), as shown in Table 13-7. Table 13-7. RTC (Standard) RAM Bank Index Name 00h Seconds 01h Seconds Alarm 02h Minutes 03h Minutes Alarm 04h Hours 05h Hours Alarm 06h Day of Week 07h Day of Month 08h Month 09h Year 0Ah Register A 0Bh Register B 0Ch Register C 0Dh Register D 0Eh–7Fh 114 Bytes of User RAM
LPC Interface Bridge Registers (D31:F0)
518 Datasheet
13.6.2.1 RTC_REGA—Register A
RTC Index: 0A Attribute: R/W Default Value: Undefined Size: 8-bit Lockable: No Power Well: RTC This register is used for general configuration of the RTC functions. None of the bits are affected by RSMRST# or any other PCH reset signal. Bit Description Update In Progress (UIP)— R/W. This bit may be monitored as a status flag. 0 = The update cycle will not start for at least 488 µs. The time, calendar, and alarm information in RAM is always available when the UIP bit is 0. 1 = The update is soon to occur or is in progress. 6:4 Division Chain Select (DV[2:0])— R/W. These three bits control the divider chain for the oscillator, and are not affected by RSMRST# or any other reset signal. 010 = Normal Operation 11X = Divider Reset 101 = Bypass 15 stages (test mode only) 100 = Bypass 10 stages (test mode only) 011 = Bypass 5 stages (test mode only) 001 = Invalid 000 = Invalid 3:0 Rate Select (RS[3:0])— R/W. Selects one of 13 taps of the 15 stage divider chain. The selected tap can generate a periodic interrupt if the PIE bit is set in Register B. Otherwise this tap will set the PF flag of Register C. If the periodic interrupt is not to be used, these bits should all be set to 0. RS3 corresponds to bit 3. 0000 = Interrupt never toggles 0001 = 3.90625 ms 0010 = 7.8125 ms 0011 = 122.070 µs 0100 = 244.141 µs 0101 = 488.281 µs 0110 = 976.5625 µs 0111 = 1.953125 ms 1000 = 3.90625 ms 1001 = 7.8125 ms 1010 = 15.625 ms 1011 = 31.25 ms 1100 = 62.5 ms 1101 = 125 ms 1110 = 250 ms 1111= 500 ms
LPC Interface Bridge Registers (D31:F0)
13.6.2.2 RTC_REGB—Register B (General Configuration)
RTC Index: 0Bh Attribute: R/W Default Value: U0U00UUU (U: Undefined) Size: 8-bit Lockable: No Power Well: RTC Bit Description Update Cycle Inhibit (SET)— R/W. Enables/Inhibits the update cycles. This bit is not affected by RSMRST# nor any other reset signal. 0 = Update cycle occurs normally once each second. 1 = A current update cycle will abort and subsequent update cycles will not occur until SET is returned to 0. When set is one, the BIOS may initialize time and calendar bytes safely. NOTE: This bit should be set then cleared early in BIOS POST after each powerup directly after coin-cell battery insertion. Periodic Interrupt Enable (PIE)—R/W. This bit is cleared by RSMRST#, but not on any other reset. 0 = Disable. 1 = Enable. Allows an interrupt to occur with a time base set with the RS bits of register Alarm Interrupt Enable (AIE)—R/W. This bit is cleared by RTCRST#, but not on any other reset. 0 = Disable. 1 = Enable. Allows an interrupt to occur when the AF is set by an alarm match from the update cycle. An alarm can occur once a second, one an hour, once a day, or one a month. Update-Ended Interrupt Enable (UIE)—R/W. This bit is cleared by RSMRST#, but not on any other reset. 0 = Disable. 1 = Enable. Allows an interrupt to occur when the update cycle ends. Square Wave Enable (SQWE)— R/W. This bit serves no function in the PCH. It is left in this register bank to provide compatibility with the Motorola 146818B. The PCH has no SQW pin. This bit is cleared by RSMRST#, but not on any other reset. Data Mode (DM)— R/W. This bit specifies either binary or BCD data representation. This bit is not affected by RSMRST# nor any other reset signal. 0 = BCD 1 = Binary Hour Format (HOURFORM)— R/W. This bit indicates the hour byte format. This bit is not affected by RSMRST# nor any other reset signal. 0 = Twelve-hour mode. In twelve-hour mode, the seventh bit represents AM as 0 and PM as one. 1 = Twenty-four hour mode. Daylight Savings Legacy Software Support (DSLSWS)— R/W. Daylight savings functionality is no longer supported. This bit is used to maintain legacy software support and has no associated functionality. If BUC.DSO bit is set, the DSLSWS bit continues to be R/W.
LPC Interface Bridge Registers (D31:F0)
520 Datasheet
13.6.2.3 RTC_REGC—Register C (Flag Register)
RTC Index: 0Ch Attribute: RO Default Value: 00U00000 (U: Undefined) Size: 8-bit Lockable: No Power Well: RTC Writes to Register C have no effect.
13.6.2.4 RTC_REGD—Register D (Flag Register)
RTC Index: 0Dh Attribute: R/W Default Value: 10UUUUUU (U: Undefined) Size: 8-bit Lockable: No Power Well: RTC Bit Description Interrupt Request Flag (IRQF)— RO. IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE). This bit also causes the RTC Interrupt to be asserted. This bit is cleared upon RSMRST# or a read of Register C. Periodic Interrupt Flag (PF)— RO. This bit is cleared upon RSMRST# or a read of Register C. 0 = If no taps are specified using the RS bits in Register A, this flag will not be set. 1 = Periodic interrupt Flag will be 1 when the tap specified by the RS bits of register A is Alarm Flag (AF)— RO. 0 = This bit is cleared upon RTCRST# or a read of Register C. 1 = Alarm Flag will be set after all Alarm values match the current time. Update-Ended Flag (UF)— RO. 0 = The bit is cleared upon RSMRST# or a read of Register C. 1 = Set immediately following an update cycle for each second. 3:0 Reserved. Will always report 0. Bit Description Valid RAM and Time Bit (VRT)—R/W. 0 = This bit should always be written as a 0 for write cycle, however it will return a 1 for read cycles. 1 = This bit is hardwired to 1 in the RTC power well. 6 Reserved. This bit always returns a 0 an d should be set to 0 for write cycles. 5:0 Date Alarm—R/W. These bits store the date of month alarm value. If set to 000000b, then a don’t care state is assumed. The host must configure the date alarm for these bits to do anything, yet they can be written at any time. If the date alarm is not enabled, these bits will return 0s to mimic the functionality of the Motorola 146818B. These bits are not affected by any reset assertion.
LPC Interface Bridge Registers (D31:F0)
13.7 Processor Interface Registers
Table 13-8 is the register address map for the processor interface registers.
13.7.1 NMI_SC—NMI Status and Control Register
I/O Address: 61h Attribute: R/W, RO Default Value: 00h Size: 8-bit Lockable: No Power Well: Core Table 13-8. Processor Interfac e PCI Register Address Map Offset Mnemonic Register Name Default Type 61h NMI_SC NMI Status and Control 00h R/W, RO 70h NMI_EN NMI Enable 80h R/W (special) 92h PORT92 Fast A20 and Init 00h R/W F0h COPROC_ERR Coprocessor Error 00h WO CF9h RST_CNT Reset Control 00h R/WBit Description SERR# NMI Source Status (SERR#_NMI_STS)— RO. 1 = Bit is set if a PCI agent detected a system error and pulses the PCI SERR# line and if bit 2 (PCI_SERR_EN) is cleared. This interrupt source is enabled by setting bit 2 to 0. To reset the interrupt, set bit 2 to 1 and then set it to 0. When writing to port 61h, this bit must be 0. NOTE: This bit is set by any of the PCH internal sources of SERR; this includes SERR assertions forwarded from the secondary PCI bus, errors on a PCI Express* port, or other internal functions that generate SERR#. IOCHK# NMI Source Status (IOCHK_NMI_STS)— RO. 1 = Bit is set if an LPC agent (using SERIRQ) asserted IOCHK# and if bit 3 (IOCHK_NMI_EN) is cleared. This interrupt source is enabled by setting bit 3 to 0. To reset the interrupt, set bit 3 to 1 and then set it to 0. When writing to port 61h, this bit must be a 0. Timer Counter 2 OUT Status (TMR2_OUT_STS)— RO. This bit reflects the current state of the 8254 counter 2 output. Counter 2 must be programmed following any PCI reset for this bit to have a determinate value. When writing to port 61h, this bit must be a 0. Refresh Cycle Toggle (REF_TOGGLE)— RO. This signal toggles from either 0 to 1 or 1 to 0 at a rate that is equivalent to when refresh cycles would occur. When writing to port 61h, this bit must be a 0. IOCHK# NMI Enable (IOCHK_NMI_EN)— R/W. 0 = Enabled. 1 = Disabled and cleared. PCI SERR# Enable (PCI_SERR_EN)— R/W. 0 = SERR# NMIs are enabled. 1 = SERR# NMIs are disabled and cleared. Speaker Data Enable (SPKR_DAT_EN)— R/W. 0 = SPKR output is a 0. 1 = SPKR output is equivalent to the Counter 2 OUT signal value. Timer Counter 2 Enable (TIM_CNT2_EN)— R/W. 0 = Disable 1 = Enable
LPC Interface Bridge Registers (D31:F0)
522 Datasheet
I/O Address: 70h Attribute: R/W (special) Default Value: 80h Size: 8-bit Lockable: No Power Well: Core Note: The RTC Index field is write-only for normal operation. This field can only be read in Alt- Access Mode. Note, however, that this register is aliased to Port 74h (documented in Table 13-6), and all bits are readable at that address.
13.7.3 PORT92—Fast A20 and Init Register
I/O Address: 92h Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Power Well: Core
13.7.4 COPROC_ERR—Coproc essor Error Register
I/O Address: F0h Attribute: WO Default Value: 00h Size: 8-bits Lockable: No Power Well: Core Bits Description NMI Enable (NMI_EN)— R/W (special). 0 = Enable NMI sources. 1 = Disable All NMI sources. 6:0 Real Time Clock Index Address (RTC_INDX)— R/W (special). This data goes to the RTC to select which register or CMOS RAM address is being accessed. Bit Description 7:2 Reserved Alternate A20 Gate (ALT_A20_GATE)— R/W. This bit is Or’d with the A20GATE input signal to generate A20M# to the processor. 0 = A20M# signal can potentially go active. 1 = This bit is set when INIT# goes active. 0 INIT_NOW—R/W. When this bit transitions from a 0 to a 1, the PCH will force INIT# active for 16 PCI clocks. Bits Description 7:0 Coprocessor Error (COPROC_ERR)—WO. Any value written to this register will cause IGNNE# to go active, if FERR# had generated an internal IRQ13. For FERR# to generate an internal IRQ13, the CEN bit must be 1.
LPC Interface Bridge Registers (D31:F0)
13.7.5 RST_CNT—Reset Control Register
I/O Address: CF9h Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Power Well: Core Bit Description 7:4 Reserved Full Reset (FULL_RST)— R/W. This bit is used to determine the states of SLP_S3#, SLP_S4#, and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1), after PWROK going low (with RSMRST# high), or after two TCO timeouts. 0 = PCH will keep SLP_S3#, SLP_S4# and SLP_S5# high. 1 = PCH will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3–5 seconds. NOTE: When this bit is set, it also causes the full power cycle (SLP_S3/4/5# assertion) in response to SYS_RESET#, PWROK#, and Watchdog timer reset sources. 2 Reset CPU (RST_CPU)— R/W. When this bit transitions from a 0 to a 1, it initiates a hard or soft reset, as determined by the SYS_RST bit (bit 1 of this register). System Reset (SYS_RST)— R/W. This bit is used to determine a hard or soft reset to the processor. 0 = When RST_CPU bit goes from 0 to 1, the PCH performs a soft reset by activating INIT# for 16 PCI clocks. 1 = When RST_CPU bit goes from 0 to 1, the PCH performs a hard reset by activating PLTRST# and SUS_STAT# active for a minimum of about 1 milliseconds. In this case, SLP_S3#, SLP_S4# and SLP_S5# state (assertion or de-assertion) depends on FULL_RST bit setting. The PCH main power well is reset when this bit is 1. It also resets the resume well bits (except for those noted throughout the EDS).
LPC Interface Bridge Registers (D31:F0)
524 Datasheet
13.8 Power Management Registers (PM—D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0 space, as well as a separate I/O range. Each register is described below. Unless otherwise indicate, bits are in the main (core) power well. Bits not explicitly defined in each register are assumed to be reserved. When writing to a reserved bit, the value should always be 0. Software should not attempt to use the value read from a reserved bit, as it may not be consistently 1 or 0. (PM—D31:F0) Table 13-9 shows a small part of the configuration space for PCI Device 31: Function 0. It includes only those registers dedicated for power management. Some of the registers are only used for Legacy Power management schemes. (PM—D31:F0) Offset Address: A0h Attribute: R/W, RO, R/WO Default Value: 0000h Size: 16-bit Lockable: No Usage: ACPI, Legacy Power Well: Core Table 13-9. Power Management PCI Register Address Map (PM—D31:F0) Offset Mnemonic Register Name Default Type A0h GEN_PMCON_1 General Power Management Configuration 1 0000h R/W, R/WO, RO A2h GEN_PMCON_2 General Power Management Configuration 2 00h R/W, R/WC, RO A4h GEN_PMCON_3 General Power Management Configuration 3 00h R/W, R/WC A6h GEN_PMCON_LO CK General Power Management Configuration Lock 00h RO, R/WLO A9h CIR4 Chipset Initialization Register 4 01h R/W ABh BM_BREAK_EN BM_BREAK_EN 00h R/W ACh PMIR Power Management Initialization 00000000h R/W, R/WL B8–BBh GPI_ROUT GPI Route Control 00000000h R/W Bit Description 15:11 Reserved BIOS_PCI_EXP_EN—R/W. This bit acts as a global enable for the SCI associated with the PCI Express* ports. 0 = The various PCI Express ports and Processor cannot cause the PCI_EXP_STS bit to go active. 1 = The various PCI Express ports and Processor can cause the PCI_EXP_STS bit to go active. PWRBTN_LVL—RO. This bit indicates the current state of the PWRBTN# signal. 0 = Low. 1 = High.
LPC Interface Bridge Registers (D31:F0) (PM—D31:F0) Offset Address: A2h Attribute: R/W, RO, R/WC Default Value: 00h Size: 8-bit Lockable: No Usage: ACPI, Legacy Power Well: Resume 8:5 Reserved SMI_LOCK— R/WO. When this bit is set, writes to the GLB_SMI_EN bit (PMBASE + 30h, bit 0) will have no effect. Once the SMI_LOCK bit is set, writes of 0 to SMI_LOCK bit will have no effect (that is, once set, this bit can only be cleared by PLTRST#). 3 (Mobile Only) Reserved 3 (Desktop Only) Pseudo CLKRUN_EN(PSEUDO_CLKRUN_EN)— R/W. 0 = Disable. 1 = Enable internal CLKRUN# logic to allow DMI PLL shutdown. This bit has no impact on state of external CLKRUN# pin. NOTES: 1. PSEUDO_CLKRUN_EN bit does not result in STP_PCI# assertion to actually stop the external PCICLK. 2. This bit should be set mutually excl usive with the CLKRUN_EN bit. Setting PSEUDO_CLKRUN_EN in a mobile sku could result in unspecified behavior. 2 (Mobile Only) PCI CLKRUN# Enable (CLKRUN_EN)— R/W. 0 = Disable. PCH drives the CLKRUN# signal low. 1 = Enable CLKRUN# logic to control the system PCI clock using the CLKRUN# and STP_PCI# signals. NOTES: 1. When the SLP_EN# bit is set, the PCH drives the CLKRUN# signal low regardless of the state of the CLKRUN_EN bit. This ensures that the PCI and LPC clocks continue running during a transition to a sleep state. 2. This bit should be set mutually exclusive with the PSEUDO_CLKRUN_EN bit. Setting CLKRUN_EN in a non-mobile sku could result in unspecified behavior. 2 (Desktop Only) Reserved 1:0 Periodic SMI# Rate Select (PER_SMI_SEL)—R/W. Set by software to control the rate at which periodic SMI# is generated. 00 = 64 seconds 01 = 32 seconds 10 = 16 seconds 11 = 8 seconds Bit Description Bit Description DRAM Initialization Bit—R/W. This bit does not effect hardware functionality in any way. BIOS is expected to set this bit prior to starting the DRAM initialization sequence and to clear this bit after completing the DRAM initialization sequence. BIOS can detect that a DRAM initialization sequence was interrupted by a reset by reading this bit during the boot sequence.
- If the bit is 1, then the DRAM initialization was interrupted.
- This bit is reset by the as sertion of the RSMRST# pin.
LPC Interface Bridge Registers (D31:F0)
526 Datasheet
Memory Placed in Self-Refresh (MEM_SR)—RO.
- If the bit is 1, DRAM should have rema ined powered and held in Self-Refresh through the last power state transition (that is, the last time the system left S0).
- This bit is reset by the assertion of the RSMRST# pin. System Reset Status (SRS)— R/WC. Software clears this bit by writing a 1 to it. 0 = SYS_RESET# button Not pressed. 1 = PCH sets this bit when the SYS_RESET# button is pressed. BIOS is expected to read this bit and clear it, if it is set. NOTES: 1. This bit is also reset by RSMRST# and CF9h resets. 2. The SYS_RESET# is implemented in th e Main power well. This pin must be properly isolated and masked to prevent incorrectly setting this Suspend well status bit. CPU Thermal Trip Status (CTS)— R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set when PLTRST# is inactive and THRMTRIP# goes active while the system is in an S0 or S1 state. NOTES: 1. This bit is also reset by RSMRST#, an d CF9h resets. It is not reset by the shutdown and reboot associated with the CPUTHRMTRIP# event. 2. The CF9h reset in the desc ription refers to CF9h type core well reset which includes SYS_RST#, PWROK/SYS_PWROK low, SMBus hard reset, TCO Timeout. This type of reset will clear CTS bit. Minimum SLP_S4# Assertion Width Violation Status—R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time programmed in the SLP_S4# Minimum Assertion Width field (D31:F0:Offset A4h:bits 5:4). The PCH begins the timer when SLP_S4# is asserted during S4/S5 entry, or when the RSMRST# input is de-asserted during G3 exit. Note that this bit is functional regardless of the value in the SLP_S4# Assertion Stretch Enable (D31:F0:Offset A4h:bit 3). NOTE: This bit is reset by the assertion of the RSMRST# pin, but can be set in some cases before the default value is readable.
PWROK Failure (PWROK_FLR)— R/WC. 0 = Software clears this bit by writing a 1 to it, or when the system goes into a G3 state. 1 = This bit will be set any time PWROK goes low, when the system was in S0, or S1 state. NOTE: See Chapter 5.13.10.3 for more details about the PWROK pin functionality. Bit Description
LPC Interface Bridge Registers (D31:F0) (PM—D31:F0) Offset Address: A4h Attribute: R/W, R/WC Default Value: 00h Size: 16-bit Lockable: No Usage: ACPI, Legacy Power Well: RTC, SUS Bit Description PME B0 S5 Disable (PME_B0_S5_DIS)—R/W. When set to 1, this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN. When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. Wakes from power states other than S5 are not affected by this policy bit. The net effect of setting PME_B0_S5_DIS = '1' is described by the truth table below: Y = Wake; N = Don't wake; B0 = PME_B0_EN; OV = WOL Enable Override This bit is cleared by the RTCRST# pin.
14 Reserved
WOL Enable Override— R/W. 0 = WOL policies are determined by PMEB0 enable bit and appropriate LAN status bits 1 = Enable integrated LAN to wake the system in S5 only regardless of the value in the PME_B0_EN bit in the GPE0_EN register. This bit is cleared by the RTCRST# pin. Disable SLP_S4# Stretching after G3: R/W 0 = Enables stretching on SLP_S4# in conjunction with SLP_S4# Assertion Stretch Enable (bit 3) and the Minimum Assertion Width (bits 5:4) 1 = Disables stretching on SLP_S4# regardless of the state of the SLP_S4# Assertion Stretch Enable (bit 3). This bit is cleared by the RTCRST# pin. NOTE: This field is RO when the SLP_Sx# Stretching Policy Lock- Down bit is set. 11:10 SLP_S3# Minimum Assertion Width: R/W This 2-bit value indicates the minimum assertion width of the SLP_S3# signal to ensure that the Main power supplies have been fully power-cycled. Valid Settings are: 00 = 60–100 us 01 = 1–1.2 ms 10 = 50–50.2 ms 11 = 2–2.0002 s This bit is cleared by the RSMRST# pin. NOTE: This field is RO when the SLP_Sx# Stretching Policy Lock-Down bit is set. B0/OV S1/S3/S4 S5
00 N N
01 N Y (LAN only)
11 Y (all PME B0 sources) Y (LAN only)
10 Y (all PME B0 sources) N
LPC Interface Bridge Registers (D31:F0)
528 Datasheet
General Reset Status (GEN_RST_STS)—R/WC. This bit is set by hardware whenever PLTRST# asserts for any reason other than going into a software- entered sleep state (using PM1CNT.SLP_EN write) or a suspend well power failure (RSMRST# pin assertion). BIOS is expected to consult and then write a 1 to clear this bit during the boot flow before determining what action to take based on PM1_STS.WAK_STS = 1. If GEN_RST_STS = 1, the cold reset boot path should be followed rather than the resume path, regardless of the setting of WAK_STS. This bit is cleared by the RSMRST# pin. SLP_LAN# Default Value (SLP_LAN_DEFAULT)— R/W. This bit specifies the value to drive on the SLP_LAN# pin when in Sx/Moff and ME FW nor host BIOS has configured SLP_LAN#/GPIO29 as an output. When this bit is set to 1 SLP_LAN# will default to be driven high, when set to 0 SLP_LAN# will default to be driven low. This bit will always determine SLP_LAN# behavior when in S4/S5/Moff after a G3, in S5/Moff after a host partition reset with power down and when in S5/Moff due to an unconditional power down. This bit is cleared by RTCRST#. 7:6 SWSMI_RATE_SEL—R/W. This field indicates when the SWSMI timer will time out. Valid values are: 00 = 1.5 ms ± 0.6 ms 01 = 16 ms ± 4 ms 10 = 32 ms ± 4 ms 11 = 64 ms ± 4 ms These bits are not cleared by any type of reset except RTCRST#. 5:4 SLP_S4# Minimum Assertion Width—R/W. This field indicates the minimum assertion width of the SLP_S4# signal to ensure that the DRAMs have been safely power-cycled. Valid values are: 11 = 1 second 10 = 2 seconds 01 = 3 seconds 00 = 4 seconds This value is used in two ways: 1. If the SLP_S4# assertion width is ever shorter than this time, a status bit is set for BIOS to read when S0 is entered. 2. If enabled by bit 3 in this register , the hardware will prevent the SLP_S4# signal from de-asserting within this minimum time period after asserting. RTCRST# forces this field to the conservative default state (00b). NOTE: This field is RO when the SLP_S4# Stretching Policy Lock-Down bit is set. SLP_S4# Assertion Stretch Enable—R/W. 0 = The SLP_S4# minimum assertion time is 1 to 2 RTCCLK. 1 = The SLP_S4# signal minimally assert for the time specified in bits 5:4 of this register. This bit is cleared by RTCRST#. NOTE: This bit is RO when the SLP_S4# Stretching Policy Lock-Down bit is set. RTC Power Status (RTC_PWR_STS)—R/W. This bit is set when RTCRST# indicates a weak or missing battery. The bit is not cleared by any type of reset. The bit will remain set until the software clears it by writing a 0 back to this bit position. Bit Description
LPC Interface Bridge Registers (D31:F0) NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC clock period may not be detected by the PCH. Offset Address: A6h Attribute: RO, R/WLO Default Value: 00h Size: 8-bit Lockable: No Usage: ACPI Power Well: Core C Power Failure (PWR_FLR)— R/WC. This bit is in the RTC well, and is not cleared by any type of reset except RTCRST#. 0 = Indicates that the trickle current has not failed since the last time the bit was cleared. Software clears this bit by writing a 1 to it. 1 = Indicates that the trickle current (from the main battery or trickle supply) was removed or failed. NOTE: Clearing CMOS in a PCH-based platform can be done by using a jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low. AFTERG3_EN—R/W. This bit determines what st ate to go to when power is re- applied after a power failure (G3 state). This bit is in the RTC well and is only cleared by RTCRST# assertion. 0 = System will return to S0 state (boot) after power is re-applied. 1 = System will return to the S5 state (except if it was in S4, in which case it will return to S4). In the S5 state, the only enabled wake event is the Power Button or any enabled wake event that was preserved through the power failure. Bit Description Bit Description 7:3 Reserved SLP_S4# Stretching Policy Lock-Down— R/WLO. When set to 1, this bit locks down the SLP_S4# Minimum Assertion Width, the SLP_S4# Assertion Stretch Enable, the Disable SLP_S4# Stretching after G3 and SLP_S4# Assertion Stretch Enable bits in the GEN_PMCON_3 register, making them read-only. This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are always ignored. This bit is cleared by platform reset. ACPI_BASE_LOCK— R/WLO. When set to 1, this bit locks down the ACPI Base Address Register (ABASE) at offset 40h. The Base Address Field becomes read- only. This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are always ignored. Once locked by writing 1, the only way to clear this bit is to perform a platform reset. 0R e s e r v e d
LPC Interface Bridge Registers (D31:F0)
530 Datasheet
13.8.1.5 Chipset Initialization Register 4 (PM—D31:F0)
Offset Address: A9h Attribute: R/W Default Value: 01h Size: 8-bit Lockable: No Usage: ACPI, Legacy Power Well: Core
13.8.1.6 BM_BREAK_EN Register (PM—D31:F0)
Offset Address: ABh Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Usage: ACPI, Legacy Power Well: Core Bit Description 7:0 CIR4 Field 1—R/W. BIOS must program this field to 45h. Bit Description STORAGE_BREAK_EN— R/W. 0 = Serial ATA traffic will not act as a break event. 1 = Serial ATA traffic acts as a break event, Serial ATA master activity will cause BM_STS to be set and will cause a break from C3/C4. PCIE_BREAK_EN— R/W. 0 = PCI Express* traffic will not act as a break event. 1 = PCI Express traffic acts as a break event, PCI Express master activity will cause BM_STS to be set and will cause a break from C3/C4. PCI_BREAK_EN— R/W. 0 = PCI traffic will not act as a break event. 1 = PCI traffic acts as a break event, PCI master activity will cause BM_STS to be set and will cause a break from C3/C4. 4:3 Reserved EHCI_BREAK_EN— R/W. 0 = EHCI traffic will not act as a break event. 1 = EHCI traffic acts as a break event, EHCI master activity will cause BM_STS to be set and will cause a break from C3/C4. HDA_BREAK_EN— R/W. 0 = Intel® High Definition Audio traffic will not act as a break event. 1 = Intel® High Definition Audio traffic acts as a break event, Intel® High Definition Audio master activity will cause BM_STS to be set and will cause a break from C3/ C4.
LPC Interface Bridge Registers (D31:F0)
13.8.1.7 PMIR—Power Management In itialization Register (PM—D31:F0)
Offset Address: ACh Attribute: R/W Default Value: 00000000h Size: 32-bit (PM—D31:F0) Offset Address: B8h–BBh Attribute: R/W Default Value: 00000000h Size: 32-bit Lockable: No Power Well: Resume Note: GPIOs that are not implemented will not have the corresponding bits implemented in this register.
13.8.2 APM I/O Decode
Table 13-10 shows the I/O registers associated with APM support. This register space is enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved (fixed I/O location). Bit Description 31:30 PMIR Field 1— R/W. BIOS must program these bits to 11b. Note: In the manufacturing/debug environments these bits will need to be left as default “00h”. 29:21 Reserved CF9h Global Reset (CF9GR)—R/W. When set, a CF9h write of 6h or Eh will cause a Global reset of both the Host and Intel® ME partitions. If this bit is cleared, a CF9h write of 6h or Eh will only reset the host partition. This bit field is not reset by a CF9h reset. NOTE: Bit 20 is read only when bit 31 set to 1. 19:0 PMIR Field 0—R/W. BIOS must program these bits to 00300h. Bit Description 31:30 GPIO15 Route—R/W. See bits 1:0 for description. Same pattern for GPIO14 through GPIO3 5:4 GPIO2 Route—R/W. See bits 1: 0 for description. 3:2 GPIO1 Route—R/W. See bits 1: 0 for description. 1:0 GPIO0 Route—R/W. GPIO can be routed to caus e an NMI, SMI# or SCI when the GPIO[n]_STS bit is set. If the GPIO0 is not set to an input, this field has no effect. If the system is in an S1–S5 state and if the GPE0_EN bit is also set, then the GPIO can cause a Wake event, even if the GPIO is NOT routed to cause an NMI, SMI# or SCI. 00 = No effect. 01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) 10 = SCI (if corresponding GPE0_EN bit is also set) 11 = NMI (If corresponding GPI_NMI_EN is also set) Table 13-10. APM Register Map Address Mnemonic Regis ter Name Default Type B2h APM_CNT Advanced Power Management Control Port 00h R/W B3h APM_STS Advanced Power Management Status Port 00h R/W
LPC Interface Bridge Registers (D31:F0)
532 Datasheet
13.8.2.1 APM_CNT—Advanced Power Ma nagement Control Port Register
I/O Address: B2h Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Usage: Legacy Only Power Well: Core
13.8.2.2 APM_STS—Advanced Power Management Status Port Register
I/O Address: B3h Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Usage: Legacy Only Power Well: Core
13.8.3 Power Manageme nt I/O Registers
Table 13-11 shows the registers associated with ACPI and Legacy power management support. These registers are enabled in the PCI Device 31: Function 0 space (PM_IO_EN), and can be moved to any I/O location (128-byte aligned). The registers are defined to support the ACPI 3.0a specification, and use the same bit names. Note: All reserved bits and registers will always return 0 when read, and will have no effect when written. Bit Description 7:0 Used to pass an APM command between the OS and the SMI handler. Writes to this port not only store data in the APMC register, but also generates an SMI# when the APMC_EN bit is set. Bit Description 7:0 Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad register and is not affected by any other register or function (other than a PCI reset). Table 13-11. ACPI and Legacy I/O Register Map (Sheet 1 of 2) PMBASE + Offset Mnemonic Register Name ACPI Pointer Default Type 00h–01h PM1_STS PM1 Status PM1a_EVT_BLK 0000h R/WC 02h–03h PM1_EN PM1 Enable PM1a_EVT_BLK+ 2 0000h R/W 04h–07h PM1_CNT PM1 Control PM1a_CNT_BLK 00000000h R/W, WO 08h–0Bh PM1_TMR PM1 Ti mer PMTMR_BLK xx000000h RO 20–27h GPE0_STS General Purpose Event 0 Status GPE0_BLK 00000000h R/WC 28–2Fh GPE0_EN General Purpose Event 0 Enables GPE0_BLK+8 00000000 00000000h R/W 30h–33h SMI_EN SMI# Control and Enable 00000002h R/W, WO, R/WO 34h–37h SMI_STS SMI Status 00000000h R/WC, RO 38h–39h ALT_GP_SMI_EN Altern ate GPI SMI Enable 0000h R/W 3Ah–3Bh ALT_GP_SMI_STS Alternate GPI SMI Status 0000h R/WC
LPC Interface Bridge Registers (D31:F0)
13.8.3.1 PM1_STS—Power Management 1 Status Register
I/O Address: PMBASE + 00h (ACPI PM1a_EVT_BLK) Attribute: R/WC Default Value: 0000h Size: 16-bit Lockable: No Usage: ACPI or Legacy Power Well: Bits 0 –7: Core, Bits 8–15: Resume, except Bit 11 in RTC If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN register, then the PCH will generate a Wake Event. Once back in an S0 state (or if already in an S0 state when the event occurs), the PCH will also generate an SCI if the SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set. Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but can cause an SMI# or SCI. 3Ch–3Dh UPRWC USB Per-Port Registers Write Control 0000h R/WC, RO, R/WO 42h GPE_CNTL General Purpose Event Control 00h RO, R/W 43h — Reserved — — — 44h–45h DEVACT_STS Device Activity Status 0000h R/WC 46h–4Fh — Reserved 50h PM2_CNT PM2 Control PM2a_CNT_BLK 00h R/W 51h–5Fh — Reserved 60h–7Fh — Reserved for TCO — — — Table 13-11. ACPI and Legacy I/O Register Map (Sheet 2 of 2) PMBASE + Offset Mnemonic Register Name ACPI Pointer Default Type Bit Description Wake Status (WAK_STS)— R/WC. This bit is not affected by hard resets caused by a CF9 write, but is reset by RSMRST#. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the system is in one of the sleep states (using the SLP_EN bit) and an enabled wake event occurs. Upon setting this bit, the PCH will transition the system to the ON state. If the AFTERG3_EN bit is not set and a power failure (such as removed batteries) occurs without the SLP_EN bit set, the system will return to an S0 state when power returns, and the WAK_STS bit will not be set. If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit having been set, the system will go into an S5 state when power returns, and a subsequent wake event will cause the WAK_STS bit to be set. Note that any subsequent wake event would have to be caused by either a Power Button press, or an enabled wake event that was preserved through the power failure (enable bit in the RTC well).
LPC Interface Bridge Registers (D31:F0)
534 Datasheet
PCI Express Wake Status (PCIEXPWAK_STS)— R/WC. 0 = Software clears this bit by writing a 1 to it. If the WAKE# pin is still active during the write or the PME message received indication has not been cleared in the root port, then the bit will remain active (that is, all inputs to this bit are level- sensitive). 1 = This bit is set by hardware to indicate that the system woke due to a PCI Express wakeup event. This wakeup event can be caused by the PCI Express WAKE# pin being active or receipt of a PCI Express PME message at a root port. This bit is set only when one of these events causes the system to transition from a non-S0 system power state to the S0 system power state. This bit is set independent of the state of the PCIEXP_WAKE_DIS bit. NOTE: This bit does not itself cause a wake event or prevent entry to a sleeping state. Thus, if the bit is 1 and the system is put into a sleeping state, the system will not automatically wake. 13:12 Reserved Power Button Override Status (PWRBTNOR_STS)— R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set any time a Power Button Override occurs (that is, the power button is pressed for at least 4 consecutive seconds), due to the corresponding bit in the SMBus slave message, Intel ® ME Initiated Power Button Override, Intel® ME Initiated Host Reset with Power down or due to an internal thermal sensor catastrophic condition. The power button override causes an unconditional transition to the S5 state. The BIOS or SCI handler clears this bit by writing a 1 to it. This bit is not affected by hard resets using CF9h writes, and is not reset by RSMRST#. Thus, this bit is preserved through power failures. Note that if this bit is still asserted when the global SCI_EN is set then an SCI will be generated. RTC Status (RTC_STS)— R/WC. This bit is not affected by hard resets caused by a CF9 write, but is reset by RSMRST#. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8# signal). Additionally if the RTC_EN bit (PMBASE + 02h, bit 10) is set, the setting of the RTC_STS bit will generate a wake event. ME_STS— R/WC. This bit is set when the Intel® Management Engine generates a Non- Maskable wake event, and is not affected by any other enable bit. When this bit is set, the Host Power Management logic wakes to S0. This bit is only set by hardware and can only be reset by writing a one to this bit position. This bit is not affected by hard resets caused by a CF9 write, but is reset by RSMRST#. Power Button Status (PWRBTN__STS)— R/WC. This bit is not affected by hard resets caused by a CF9 write. 0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to the S5 state with only PWRBTN# enabled as a wake event. This bit can be cleared by software by writing a one to the bit position. 1 = This bit is set by hardware when the PWRBTN# signal is asserted Low, independent of any other enable bit. In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or SMI# if SCI_EN is not set) will be generated. In any sleeping state S1–S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and PWRBTN_STS are both set, a wake event is generated. NOTE: If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is sell asserted, this will not cause the PWRBN_STS bit to be set. The PWRBTN# signal must go inactive and active again to set the PWRBTN_STS bit. Bit Description
LPC Interface Bridge Registers (D31:F0) 7:6 Reserved Global Status (GBL _STS)— R/WC. 0 = The SCI handler should then clear this bit by writing a 1 to the bit location. 1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI handler. BIOS has a corresponding bit, BIOS_RLS, which will cause an SCI and set this bit. Bus Master Status (BM_STS)—R/WC. This bit will not cause a wake event, SCI or SMI#. 0 = Software clears this bit by writing a 1 to it. 1 = Set by the PCH when a PCH-visible bus master requests access to memory or the BM_BUSY# signal is active. 3:1 Reserved Timer Overflow Status (TMROF_STS)— R/WC. 0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location. 1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23). This will occur every 2.3435 seconds. When the TMROF_EN bit (PMBASE + 02h, bit 0) is set, then the setting of the TMROF_STS bit will additionally generate an SCI or SMI# (depending on the SCI_EN). Bit Description
LPC Interface Bridge Registers (D31:F0)
536 Datasheet
13.8.3.2 PM1_EN—Power Mana gement 1 Enable Register
I/O Address: PMBASE + 02h (ACPI PM1a_EVT_BLK + 2) Attribute: R/W Default Value: 0000h Size: 16-bit Lockable: No Usage: ACPI or Legacy Power Well: Bits 0 –7: Core, Bits 8–9, 11–15: Resume, Bit 10: RTC Bit Description PCI Express* Wake Disable(PCIEXPWAK_DIS)— R/W. Modification of this bit has no impact on the value of the PCIEXP_WAKE_STS bit. 0 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register enabled to wake the system. 1 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register disabled from waking the system. 13:11 Reserved RTC Event Enable (RTC_EN)— R/W. This bit is in the RTC well to allow an RTC event to wake after a power failure. This bit is not cleared by any reset other than RTCRST# or a Power Button Override event. 0 = No SCI (or SMI#) or wake event is generated then RTC_STS (PMBASE + 00h, bit 10) goes active. 1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit goes active.
9 Reserved
Power Button Enable (PWRBTN_EN)— R/W. This bit is used to enable the setting of the PWRBTN_STS bit to generate a power management event (SMI#, SCI). PWRBTN_EN has no effect on the PWRBTN_STS bit (PMBASE + 00h, bit 8) being set by the assertion of the power button. The Power Button is always enabled as a Wake event. 0 = Disable. 1 = Enable. 7:6 Reserved Global Enable (GBL_EN)— R/W. When both the GBL_EN and the GBL_STS bit (PMBASE + 00h, bit 5) are set, an SCI is raised. 0 = Disable. 1 = Enable SCI on GBL_STS going active. 4:1 Reserved Timer Overflow Interrupt Enable (TMROF_EN)— R/W. Works in conjunction with the SCI_EN bit (PMBASE + 04h, bit 0) as described below:
0 X No SMI# or SCI
10 S M I #
11 S C I
LPC Interface Bridge Registers (D31:F0)
13.8.3.3 PM1_CNT—Power Management 1 Control Register
I/O Address: PMBASE + 04h (ACPI PM1a_CNT_BLK) Attribute: R/W, WO Default Value: 00000000h Size: 32-bit Lockable: No Usage: ACPI or Legacy Power Well: Bits 0 –7: Core, Bits 8–12: RTC, Bits 13–15: Resume Bit Description 31:14 Reserved 13 Sleep Enable (SLP_EN)— WO. Setting this bit causes the system to sequence into the Sleep state defined by the SLP_TYP field. 12:10 Sleep Type (SLP_TYP)— R/W. This 3-bit field defines the type of Sleep the system should enter when the SLP_EN bit is set to 1. These bits are only reset by RTCRST#. 9:3 Reserved Global Release (GBL_RLS)— WO. 0 = This bit always reads as 0. 1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software has a corresponding enable and status bits to control its ability to receive ACPI events. Bus Master Reload (BM_RLD)— R/W. This bit is treated as a scratchpad bit. This bit is reset to 0 by PLTRST# 0 = Bus master requests will not cause a break from the C3 state. 1 = Enables Bus Master requests (internal or external) to cause a break from the C3 state. If software fails to set this bit before going to C3 state, the PCH will still return to a snoopable state from C3 or C4 states due to bus master activity. SCI Enable (SCI_EN)— R/W. Selects the SCI interrupt or the SMI# interrupt for various events including the bits in the PM1_STS register (bit 10, 8, 0), and bits in GPE0_STS. 0 = These events will generate an SMI#. 1 = These events will generate an SCI. 000b ON: Typically maps to S0 state. 001b Puts CPU in S1 state. 010b Reserved 011b Reserved 100b Reserved 101b Suspend-To-RAM. Assert SLP_S3 #: Typically maps to S3 state. 110b Suspend-To-Disk. Assert SLP_S3#, and SLP_S4#: Typically maps to S4 state. 111b Soft Off. Assert SLP_S3#, SLP_S4#, and SLP_S5#: Typically maps to S5 state.
LPC Interface Bridge Registers (D31:F0)
538 Datasheet
13.8.3.4 PM1_TMR—Power Management 1 Timer Register
I/O Address: PMBASE + 08h (ACPI PMTMR_BLK) Attribute: RO Default Value: xx000000h Size: 32-bit Lockable: No Usage: ACPI Power Well: Core
13.8.3.5 PM1_TMR—Power Management 1 Timer Register
I/O Address: PMBASE + 08h (ACPI PMTMR_BLK) Attribute: RO Default Value: xx000000h Size: 32-bit Lockable: No Usage: ACPI Power Well: Core Bit Description 31:24 Reserved 23:0 Timer Value (TMR_VAL)— RO. Returns the running count of the PM timer. This counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0 during a PCI reset, and then continues counting as long as the system is in the S0 state. After an S1 state, the counter will not be reset (it will continue counting from the last value in S0 state. Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the TMROF_STS bit (PMBASE + 00h, bit 0) is set. The High-to-Low transition will occur every 2.3435 seconds. If the TMROF_EN bit (PMBASE + 02h, bit 0) is set, an SCI interrupt is also generated. Bit Description 31:24 Reserved 23:0 Timer Value (TMR_VAL)— RO. Returns the running count of the PM timer. This counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0 during a PCI reset, and then continues counting as long as the system is in the S0 state. After an S1 state, the counter will not be reset (it will continue counting from the last value in S0 state. Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the TMROF_STS bit (PMBASE + 00h, bit 0) is set. The High-to-Low transition will occur every 2.3435 seconds. If the TMROF_EN bit (PMBASE + 02h, bit 0) is set, an SCI interrupt is also generated.
LPC Interface Bridge Registers (D31:F0)
13.8.3.6 GPE0_STS—General Purpose Event 0 Status Register
I/O Address: PMBASE + 20h (ACPI GPE0_BLK) Attribute: Bits 0:32 R/WC Bits 33:63 RO Default Value: 0000000000000000h Size: 64-bit Lockable: No Usage: ACPI Power Well: Resume This register is symmetrical to the General Purpose Event 0 Enable Register. Unless indicated otherwise below, if the corresponding _EN bit is set, then when the _STS bit get set, the PCH will generate a Wake Event. Once back in an S0 state (or if already in an S0 state when the event occurs), the PCH will also generate an SCI if the SCI_EN bit is set, or an SMI# if the SCI_EN bit (PMBASE + 04h, bit 0) is not set. Bits 31:16 are reset by a CF9h write; bits 63:32 and 15:0 are not. All are reset by RSMRST#. Bit Description 63:36 Reserved GPIO27_STS—R/WC. 0 = Disable. 1 = Set by hardware and can be reset by writing a one to this bit position or a resume well reset. This bit is set at the level specified in GP27IO_POL. Note that GPIO27 is always monitored as an input for the purpose of setting this bit, regardless of the actual GPIO configuration., 34:32 Reserved 31:16 GPIOn_STS— R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = These bits are set any time the corresponding GPIO is set up as an input and the corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set). If the corresponding enable bit is set in the GPE0_EN register, then when the GPIO[n]_STS bit is set:
- If the system is in an S1–S5 state, the event will also wake the system.
- If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused depending on the GPIO_ROUT bits (D31:F0:B8h, bits 31:30) for the corresponding GPI. NOTE: Mapping is as follows: bit 31 corresponds to GPIO[15]... and bit 16 corresponds to GPIO[0]. 15:14 Reserved PME_B0_STS—R/WC. This bit will be set to 1 by the PCH when any internal device with PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal. Additionally, if the PME_B0_EN bit is set, and the system is in an S0 state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not set). If the PME_B0_STS bit is set, and the system is in an S1–S4 state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the PME_B0_STS bit will generate a wake event, and an SCI (or SMI# if SCI_EN is not set) will be generated. If the system is in an S5 state due to power button override, then the PME_B0_STS bit will not cause a wake event or SCI. The default for this bit is 0. Writing a 1 to this bit position clears this bit. NOTE: HD audio wake events are reported in this bit. Intel ® Management Engine “maskable” wake events are also reported in this bit.
LPC Interface Bridge Registers (D31:F0)
540 Datasheet
PME_STS—R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN bit is set, and the system is in an S0 state, then the setting of the PME_STS bit will generate an SCI or SMI# (if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1–S4 state (or S5 state due to setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will generate a wake event, and an SCI will be generated. If the system is in an S5 state due to power button override or a power failure, then PME_STS will not cause a wake event or SCI. (Desktop Only) Reserved (Mobile Only) BATLOW_STS—R/WC. (Mobile Only) Software clears this bit by writing a 1 to it. 0 = BATLOW# Not asserted 1 = Set by hardware when the BATLOW# signal is asserted. PCI_EXP_STS— R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware to indicate that:
- The PME event message was received on one or more of the PCI Express* ports
- An Assert PMEGPE message receiv ed from the Processor using DMI NOTES: 1. The PCI WAKE# pin has no impact on this bit. 2. If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a Deassert PMEGPE message must be received prior to the software write for the bit to be cleared. 3. If the bit is not cleare d and the corresponding PCI_EXP_EN bit is set, the level-triggered SCI will remain active. 4. A race condition exists where the PCI Express device sends another PME message because the PCI Express device was not serviced within the time when it must resend the message. This may result in a spurious interrupt, and this is comprehended and approved by the PCI Express* Specification, Revision 1.0a. The window for this race condition is approximately 95-105 milliseconds. RI_STS—R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = Set by hardware when the RI# input signal goes active. SMBus Wake Status (SMB_WAK_STS)— R/WC. Software clears this bit by writing a 1 to it. 0 = Wake event Not caused by the PCH’s SMBus logic. 1 = Set by hardware to indicate that the wake event was caused by the PCH’s SMBus logic.This bit will be set by the WAKE/SMI# command type, even if the system is already awake. The SMI handler should then clear this bit. NOTES: 1. The SMBus controller will independently cause an SMI# so this bit does not need to do so (unlike the other bits in this register). 2. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the system is in the S0 state. Therefore, to avoid an instant wake on subsequent transitions to sleep states, software must clear this bit after each reception of the Wake/SMI# command or just prior to entering the sleep state. 3. The SMBALERT_STS bit (D31:F3:I/O Offs et 00h:Bit 5) should be cleared by software before the SMB_WAK_STS bit is cleared. Bit Description
LPC Interface Bridge Registers (D31:F0)
13.8.3.7 GPE0_EN—General Purp ose Event 0 Enables Register
I/O Address: PMBASE + 28h (ACPI GPE0_BLK + 8) Attribute: R/W Default Value: 0000000000000000h Size: 64-bit Lockable: No Usage: ACPI Power Well: Bits 0–7, 9, 12, 14–63 Resume, Bits 8, 10–11, 13 RTC This register is symmetrical to the General Purpose Event 0 Status Register. All the bits in this register should be cleared to 0 based on a Power Button Override or processor Thermal Trip event. The resume well bits are all cleared by RSMRST#. The RTC well bits are cleared by RTCRST#. TCOSCI_STS—R/WC. Software clears this bit by writing a 1 to it. 0 = TOC logic or thermal sensor logic did Not cause SCI. 1 = Set by hardware when the TCO logic or thermal sensor logic causes an SCI. 5:3 Reserved 2 SWGPE_STS—R/WC. The SWGPE_CTRL bit (bit 1 of GPE_CTRL reg) acts as a level input to this bit. HOT_PLUG_STS— R/WC. 0 = This bit is cleared by writing a 1 to this bit position. 1 = When a PCI Express* Hot-Plug event occurs. This will cause an SCI if the HOT_PLUG_EN bit is set in the GEP0_EN register. 63:36 Reserved GPIO27_EN—R/W. 0 = Disable. 1 = Enable the setting of the GPIO27_STS bit to generate a wake event/SCI/SMI#. 34:32 Reserved 31:16 GPIn_EN—R/W. These bits enable the correspon ding GPI[n]_STS bits being set to cause a SCI, and/or wake event. These bits are cleared by RSMRST#. NOTE: Mapping is as follows: bit 31 corresponds to GPIO15... and bit 16 corresponds to GPIO0. PME_B0_EN— R/W. 0 = Disable 1 = Enables the setting of the PME_B0_STS bit to generate a wake event and/or an SCI or SMI#. PME_B0_STS can be a wake event from the S1–S4 states, or from S5 (if entered using SLP_TYP and SLP_EN) or power failure, but not Power Button Override. This bit defaults to 0. NOTE: It is only cleared by Software or RTCRST#. It is not cleared by CF9h writes. PME_EN—R/W. 0 = Disable. 1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI. PME# can be a wake event from the S1–S4 state or from S5 (if entered using SLP_EN, but not power button override).
LPC Interface Bridge Registers (D31:F0)
542 Datasheet
(Desktop Only) Reserved (Mobile Only) BATLOW_EN—R/W. (Mobile Only) 0 = Disable. 1 = Enables the BATLOW# signal to cause an SMI# or SCI (depending on the SCI_EN bit) when it goes low. This bit does not prevent the BATLOW# signal from inhibiting the wake event. PCI_EXP_EN—R/W. 0 = Disable SCI generation upon PCI_EXP_STS bit being set. 1 = Enables PCH to cause an SCI when PCI_EXP_STS bit is set. This is used to allow the PCI Express* ports, including the link to the Processor, to cause an SCI due to wake/PME events. RI_EN—R/W. The value of this bit will be maintained through a G3 state and is not affected by a hard reset caused by a CF9h write. 0 = Disable. 1 = Enables the setting of the RI_STS to generate a wake event. TCOSCI_EN—R/W. 0 = Disable. 1 = Enables the setting of the TCOSCI_STS to generate an SCI. 5:3 Reserved SWGPE_EN—R/W. This bit allows software to control the assertion of SWGPE_STS bit. This bit This bit, when set to 1, enables the SW GPE function. If SWGPE_CTRL is written to a 1, hardware will set SWGPE_STS (acts as a level input) If SWGPE_STS, SWGPE_EN, and SCI_EN are all 1's, an SCI will be generated If SWGPE_STS = 1, SWGPE_EN = 1, SCI_EN = 0, and GBL_SMI_EN = 1 then an SMI# will be generated HOT_PLUG_EN— R/W. 0 = Disables SCI generation upon the HOT_PLUG_STS bit being set. 1 = Enables the PCH to cause an SCI when the HOT_PLUG_STS bit is set. This is used to allow the PCI Express ports to cause an SCI due to hot-plug events.
LPC Interface Bridge Registers (D31:F0)
13.8.3.8 SMI_EN—SMI Control and Enable Register
I/O Address: PMBASE + 30h Attribute: R/W, R/WO, WO Default Value: 00000002h Size: 32 bit Lockable: No Usage: ACPI or Legacy Power Well: Core Note: This register is symmetrical to the SMI status register. Bit Description 31:28 Reserved GPIO_UNLOCK_SMI_EN—R/WO. Setting this bit will cause the Intel® PCH to generate an SMI# when the GPIO_UNLOCK_SMI_STS bit is set in the SMI_STS register. Once written to 1, this bit can only be cleared by PLTRST#. 26:19 Reserved INTEL_USB2_EN—R/W. 0 = Disable 1 = Enables Intel-Specific USB2 SMI logic to cause SMI#. LEGACY_USB2_EN—R/W. 0 = Disable 1 = Enables legacy USB2 logic to cause SMI#. 16:15 Reserved PERIODIC_EN—R/W. 0 = Disable. 1 = Enables the PCH to generate an SMI# when the PERIODIC_STS bit (PMBASE + 34h, bit 14) is set in the SMI_STS register (PMBASE + 34h). TCO_EN—R/W. 0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is set, SMIs that are caused by re-routed NMIs will not be gated by the TCO_EN bit. Even if the TCO_EN bit is 0, NMIs will still be routed to cause SMIs. 1 = Enables the TCO logic to generate SMI#. NOTE: This bit cannot be written once the TCO_LOCK bit is set. MCSMI_ENMicrocontroller SMI Enable (MCSMI_EN)— R/W. 0 = Disable. 1 = Enables PCH to trap accesses to the microcontroller range (62h or 66h) and generate an SMI#. Note that “trapped’ cycles will be claimed by the PCH on PCI, but not forwarded to LPC. 10:8 Reserved BIOS Release (BIOS_RLS)— WO. 0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect. 1 = Enables the generation of an SCI interrupt for ACPI software when a one is written to this bit position by BIOS software. NOTE: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set. Software must take great care not to set the BIOS_RLS bit (which causes GBL_STS to be set) if the SCI handler is not in place.
LPC Interface Bridge Registers (D31:F0)
544 Datasheet
Software SMI# Timer Enable (SWSMI_TMR_EN)—R/W. 0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset the timer and the SMI# will not be generated. 1 = Starts Software SMI# Timer. When the SWSMI timer expires (the timeout period depends upon the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set and an SMI# is generated. SWSMI_TMR_EN stays set until cleared by software. APMC_EN—R/W. 0 = Disable. Writes to the APM_CNT register will not cause an SMI#. 1 = Enables writes to the APM_CNT register to cause an SMI#. SLP_SMI_EN—R/W. 0 = Disables the generation of SMI# on SLP_EN. Note that this bit must be 0 before the software attempts to transition the system into a sleep state by writing a 1 to the SLP_EN bit. 1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an SMI#, and the system will not transition to the sleep state based on that write to the SLP_EN bit. LEGACY_USB_EN—R/W. 0 = Disable. 1 = Enables legacy USB circuit to cause SMI#. BIOS_EN—R/W. 0 = Disable. 1 = Enables the generation of SMI# when ACPI software writes a 1 to the GBL_RLS bit (D31:F0:PMBase + 04h:bit 2). Note that if the BIOS_STS bit (D31:F0:PMBase + 34h:bit 2), which gets set when software writes 1 to GBL_RLS bit, is already a 1 at the time that BIOS_EN becomes 1, an SMI# will be generated when BIOS_EN gets set. End of SMI (EOS)— R/W (special). This bit controls the arbitration of the SMI signal to the processor. This bit must be set for the PCH to assert SMI# low to the processor after SMI# has been asserted previously. 0 = Once the PCH asserts SMI# low, the EOS bit is automatically cleared. 1 = When this bit is set to 1, SMI# signal will be de-asserted for 4 PCI clocks before its assertion. In the SMI handler, the processor should clear all pending SMIs (by servicing them and then clearing their respective status bits), set the EOS bit, and exit SMM. This will allow the SMI arbiter to re-assert SMI upon detection of an SMI event and the setting of a SMI status bit. NOTE: The PCH is able to generate 1st SMI after reset even though EOS bit is not set. Subsequent SMI require EOS bit is set. GBL_SMI_EN— R/W. 0 = No SMI# will be generated by PCH. This bit is reset by a PCI reset event. 1 = Enables the generation of SMI# in the system upon any enabled SMI event. NOTE: When the SMI_LOCK bit is set, this bit cannot be changed. Bit Description
LPC Interface Bridge Registers (D31:F0)
13.8.3.9 SMI_STS—SMI Status Register
I/O Address: PMBASE + 34h Attribute: RO, R/WC Default Value: 00000000h Size: 32-bit Lockable: No Usage: ACPI or Legacy Power Well: Core Note: If the corresponding _EN bit is set when the _STS bit is set, the PCH will cause an SMI# (except bits 8–10 and 12, which do not need enable bits since they are logic ORs of other registers that have enable bits). The PCH uses the same GPE0_EN register (I/O address: PMBase+2Ch) to enable/disable both SMI and ACPI SCI general purpose input events. ACPI OS assumes that it owns the entire GPE0_EN register per the ACPI specification. Problems arise when some of the general-purpose inputs are enabled as SMI by BIOS, and some of the general purpose inputs are enabled for SCI. In this case ACPI OS turns off the enabled bit for any GPIx input signals that are not indicated as SCI general-purpose events at boot, and exit from sleeping states. BIOS should define a dummy control method which prevents the ACPI OS from clearing the SMI GPE0_EN bits. Bit Description 31:28 Reserved 27 GPIO_UNLOCK_SMI_STS— R/WC. This bit will be set if the GPIO registers lockdown logic is requesting an SMI#. Writing a 1 to this bit position clears this bit to 0. SPI_STS— RO. This bit will be set if the SPI logic is generating an SMI#. This bit is read only because the sticky status and enable bits associated with this function are located in the SPI registers. 25:22 Reserved MONITOR_STS— RO. This bit will be set if the Trap/SMI logic has caused the SMI. This will occur when the processor or a bus master accesses an assigned register (or a specific cause of the SMI. 20 PCI_EXP_SMI_STS— RO. PCI Express* SMI event occurred. This could be due to a PCI Express PME event or Hot-Plug event.
19 Reserved
INTEL_USB2_STS— RO. This non-sticky read-only bit is a logical OR of each of the SMI status bits in the Intel-Specific USB2 SMI Status Register ANDed with the corresponding enable bits. Additionally, the Port Disable Write Enable SMI is reported in this bit; the specific status bit for this event is contained in the USB Per-Port Registers Write Control Register in this I/O space. This bit will not be active if the enable bits are not set. Writes to this bit will have no effect. All integrated USB2 Host Controllers are represented with this bit. LEGACY_USB2_STS— RO. This non-sticky read-only bit is a logical OR of each of the SMI status bits in the USB2 Legacy Support Register ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. Writes to this bit will have no effect. All integrated USB2 Host Controllers are represented with this bit.
LPC Interface Bridge Registers (D31:F0)
546 Datasheet
SMBus SMI Status (SMBUS_SMI_STS)— R/WC. Software clears this bit by writing a 1 to it. 0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software must wait at least 15.63 μs after the initial assertion of this bit before clearing it. 1 = Indicates that the SMI# was caused by: 1. The SMBus Slave receiving a message that an SMI# should be caused, or 2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the SMBALERT_DIS bit is cleared, or 3. The SMBus Slave receiving a Host Notify message and the HOST_NOTIFY_INTREN and the SMB_SMI_EN bits are set, or 4. The PCH detecting the SMLINK_SLAVE_SMI command while in the S0 state. SERIRQ_SMI_STS—RO. 0 = SMI# was not caused by the SERIRQ decoder. 1 = Indicates that the SMI# was caused by the SERIRQ decoder. NOTE: This is not a sticky bit PERIODIC_STS—R/WC. Software clears this bit by writing a 1 to it. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the PERIODIC_EN bit (PMBASE + 30h, bit 14) is also set, the PCH generates an SMI#. TCO_STS—R/WC. Software clears this bit by writing a 1 to it. 0 = SMI# not caused by TCO logic. 1 = Indicates the SMI# was caused by the TCO logic. Note that this is not a wake event. Device Monitor Status (DEVMON_STS)— RO. 0 = SMI# not caused by Device Monitor. 1 = Set if bit 0 of the DEVACT_STS register (PMBASE + 44h) is set. The bit is not sticky, so writes to this bit will have no effect. Microcontroller SMI# Status (MCSMI_STS)— R/WC. Software clears this bit by writing a 1 to it. 0 = Indicates that there has been no access to the power management microcontroller range (62h or 66h). 1 = Set if there has been an access to the power management microcontroller range (62h or 66h) and the Microcontroller Decode Enable #1 bit in the LPC Bridge I/O Enables configuration register is 1 (D31:F0:Offset 82h:bit 11). Note that this implementation assumes that the Microcontroller is on LPC. If this bit is set, and the MCSMI_EN bit is also set, the PCH will generate an SMI#. GPE0_STS—RO. This bit is a logical OR of the bits in the ALT_GP_SMI_STS register that are also set up to cause an SMI# (as indicated by the GPI_ROUT registers) and have the corresponding bit set in the ALT_GP_SMI_EN register. Bits that are not routed to cause an SMI# will have no effect on this bit. 0 = SMI# was not generated by a GPI assertion. 1 = SMI# was generated by a GPI assertion. GPE0_STS—RO. This bit is a logical OR of the bits 47:32, 14:10, 8, 6:2, and 0 in the GPE0_STS register (PMBASE + 28h) that also have the corresponding bit set in the GPE0_EN register (PMBASE + 2Ch). 0 = SMI# was not generated by a GPE0 event. 1 = SMI# was generated by a GPE0 event. PM1_STS_REG—RO. This is an ORs of the bits in the ACPI PM1 Status Register (offset PMBASE+00h) that can cause an SMI#. 0 = SMI# was not generated by a PM1_STS event. 1 = SMI# was generated by a PM1_STS event.
LPC Interface Bridge Registers (D31:F0)
13.8.3.10 ALT_GP_SMI_EN—Alterna te GPI SMI Enable Register
I/O Address: PMBASE +38h Attribute: R/W Default Value: 0000h Size: 16-bit Lockable: No Usage: ACPI or Legacy Power Well: Resume SWSMI_TMR_STS—R/WC. Software clears this bit by writing a 1 to it. 0 = Software SMI# Timer has Not expired. 1 = Set by the hardware when the Software SMI# Timer expires. APM_STS—R/WC. Software clears this bit by writing a 1 to it. 0 = No SMI# generated by write access to APM Control register with APMCH_EN bit set. 1 = SMI# was generated by a write access to the APM Control register with the APMC_EN bit set. SLP_SMI_STS—R/WC. Software clears this bit by writing a 1 to the bit location. 0 = No SMI# caused by write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set. 1 = Indicates an SMI# was caused by a write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set. LEGACY_USB_STS—RO. This bit is a logical OR of ea ch of the SMI status bits in the USB Legacy Keyboard/Mouse Control Registers ANDed with the corresponding enable bits. This bit will not be active if the enable bits are not set. 0 = SMI# was not generated by USB Legacy event. 1 = SMI# was generated by USB Legacy event. BIOS_STS—R/WC. 0 = No SMI# generated due to ACPI software requesting attention. 1 = This bit gets set by hardware when a 1 is written by software to the GBL_RLS bit (D31:F0:PMBase + 04h:bit 2). When both the BIOS_EN bit (D31:F0:PMBase + 30h:bit 2) and the BIOS_STS bit are set, an SMI# will be generated. The BIOS_STS bit is cleared when software writes a 1 to its bit position. 1:0 Reserved Bit Description Bit Description 15:0 Alternate GPI SMI Enable— R/W. These bits are used to enable the corresponding GPIO to cause an SMI#. For these bits to have any effect, the following must be true.
- The corresponding bit in the ALT_GP_SMI_EN register is set.
- The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI.
- The corresponding GPIO must be implemented. NOTE: Mapping is as follows: bit 15 corresponds to GPIO15... bit 0 corresponds to GPIO0.
LPC Interface Bridge Registers (D31:F0)
548 Datasheet
13.8.3.11 ALT_GP_SMI_STS—Altern ate GPI SMI Status Register
I/O Address: PMBASE +3Ah Attribute: R/WC Default Value: 0000h Size: 16-bit Lockable: No Usage: ACPI or Legacy Power Well: Resume
13.8.3.12 UPRWC—USB Per-Port Registers Write Control
I/O Address: PMBASE +3Ch Attribute: R/WC, R/W, R/WO Default Value: 0000h Size: 16-bit Lockable: No Usage: ACPI or Legacy Power Well: Resume Bit Description 15:0 Alternate GPI SMI Status—R/WC. These bits re port the status of the corresponding GPIOs. 0 = Inactive. Software clears this bit by writing a 1 to it. 1 = Active These bits are sticky. If the following conditions are true, then an SMI# will be generated and the GPE0_STS bit set:
- The corresponding bit in the ALT_GPI_SM I_EN register (PMBASE + 38h) is set
- The corresponding GPIO must be routed in the GPI_ROUT register to cause an SMI.
- The corresponding GPIO must be implemented. All bits are in the resume well. Default for these bits is dependent on the state of the GPIO pins. Bit Description 15:9 Reserved Write Enable Status—R/WC 0 = This bit gets set by hardware when the “Per-Port Registers Write Enable” bit is written from 0 to 1 1 = This bit is cleared by software writing a 1b to this bit location The setting condition takes precedence over the clearing condition in the event that both occur at once. When this bit is 1b and bit 0 is 1b, the INTEL_USB2_STS bit is set in the SMI_STS register. 7:1 Reserved Write Enable SMI Enable—R/WO 0 = Disable 1 = Enables the generation of SMI when the Per-Port Registers Write Enable (bit 1) is written from 0 to 1. Once written to 1b, this bit can not be cleared by software.
LPC Interface Bridge Registers (D31:F0)
13.8.3.13 GPE_CNTL—General Purpose Control Register
I/O Address: PMBASE +42h Attribute: R/W Default Value: 00h Size: 8-bit Lockable: No Usage: ACPI or Legacy Power Well: Resume Bit Description 8:2 Reserved GPIO27_POL—R/W. This bit controls the polarity of the GPIO27 pin needed to set the GPIO27_STS bit. 0 = GPIO27 = 0 will set the GPIO27_STS bit. 1 = GPIO27 = 1 will set the GPIO27_STS bit. SWGPE_CTRL—R/W. This bit allows software to control the assertion of SWGPE_STS bit. This bit is used by hardware as the level input signal for the SWGPE_STS bit in the GPE0_STS register. When SWGPE_CTRL is 1, SWGPE_STS will be set to 1, and writes to SWGPE_STS with a value of 1 to clear SWGPE_STS will result in SWGPE_STS being set back to 1 by hardware. When SWGPE_CTRL is 0, writes to SWGPE_STS with a value of 1 will clear SWGPE_STS to 0. This bit is cleared to 0 based on a Power Button Override, CPU Thermal Event as well as by the RSMRST# pin assertion.
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