87C196LA INTEL | Alldatasheet
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COPYRIGHT © INTEL CORPORATION, 1996 October 1996 Order Number: 272806-001 87C196LA CHMOS 16-BIT MICROCONTROLLER Automotive NOTE This datasheet contains information on products in the design phase of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. The 87C196LA is a high-performance 16-bit microcontroller. The 87C196LA is composed of a high-speed core with the following peripherals: an asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port with full duplex master/slave transceivers; a six-channel A/D converter with sample and hold; a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophis- ticated, prioritized interrupt structure with programmable peripheral transaction server (PTS). The clock doubler circuitry and oscillator output signal enable a 4 MHz resonator to achieve the same internal clock speed as a more costly 8 MHz resonator in previous applications. This same circuitry can drive other devices where a separate resonator was required in the past. Another cost-savings feature is the fact that the I/O ports are driven low at reset, avoiding the need for pull-up resistors. ■ 20 MHz operation† ■ 24 Kbytes of on-chip OTPROM ■ 768 bytes of on-chip register RAM ■ Register-to-register architecture ■ Peripheral transaction server (PTS) with high-speed, microcoded interrupt service routines ■ Six-channel/10-bit A/D with sample and hold ■ High-speed event processor array — Six capture/compare channels — Two compare-only channels — Two 16-bit software timers † 16 MHz standard; 20 MHz is speed premium ■ Full-duplex serial I/O port with dedicated baud-rate generator ■ Enhanced full-duplex, synchronous serial I/O port (SSIO) ■ Programmable 8- or 16-bit external bus ■ Optional clock doubler with programmable clock output signal ■ SFR register that indicates the source of the last reset ■ Design enhancements for EMI reduction ■ Oscillator failure detection circuitry ■ Watchdog timer (WDT) ■ –40° C to +125° C ambient temperature ■ 52-pin PLCC package
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel dis- claims any express or implied warranty, relating to sale and/or use of Intel products including liability or war- ranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel liter- ature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-548-4725
Figure 1. 87C196LA Block Diagram
6 Capture/
24 Kbytes
768 BytesALU
† Two additional capture/compare channels (EPA6 and EPA7) are available as software timers. They are not connected to package pins.
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1.0 NOMENCLATURE OVERVIEW
Figure 2. Product Nomenclature Table 1. Description of Product Nomenclature 125° C ambient) with Intel standard burn-in.
16 MHz
20 MHz
2.0 PINOUT
Figure 3. 87C196LA 52-pin Package
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Table 2. 87C196LA 52-pin Package Pin Assignments
Table 3. Pin Assignment Arranged by Functional Categories
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3.0 SIGNALS
Table 4. Signal Descriptions These signals are analog inputs to the A/D converter. produce unreliable conversion results. pins with P4.7:0 and PBUS.15:8. progress and is returned high as soon as the bus cycle completes. ADV# shares a package pin with P5.0 and ALE. word is programmed or dumped. AINC# shares a package pin with P2.4.
This active-high output signal is asserted only during external memory cycles. information is available on the system address/data bus. ALE shares a package pin with P5.0 and ADV#. SS should be nominally at the same potential. f, f/2, or f/4. CLKOUT has a 50% duty cycle. CLKOUT shares a package pin with P2.7 and PACT#. These signals are the outputs of the EPA compare-only channels. indicates that an error occurred during the program operation. CPVER shares a package pin with P2.6 and ONCE#. the value of EA# is irrelevant. level of EA# after reset has no effect. High-speed input/output signals for the EPA capture/compare channels. as software timers. EPA5:4 are not implemented. Table 4. Signal Descriptions (Continued)
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device to resume normal operation. The interrupt does not need to be enabled. the command that invoked the power-saving mode. EXTINT shares a package pin with P2.2 and PROG#. This is a high-impedance, input-only port. Port 0 pins should not be left floating. can produce unreliable conversion results. REF must be connected for port 0 to function. selectable special-function signals. selectable special-function signals. address/data bus, which has complementary drivers. P3.7:0 share package pins with AD7:0 and PBUS.7:0. address/data bus, which has complementary drivers. P4.7:0 share package pins with AD15:8 and PBUS.15:8.
This is a memory-mapped, bidirectional port. This is a standardbidirectional port. PACT# shares a package pin with P2.7 and OSCOUT. command and address from the programming bus. PALE# is multiplexed with P2.1 and RXD. device. Slave programming requires external pull-up resistors. P1.1 and P1.2 serve as the upper address lines. PBUS.7:0 share package pins with AD7:0 and P3.7:0. PBUS.15:8 share package pins with AD15:8 and P4.7:0. package pins with AD7:0 and P3.7:0. This active-high input pin enables the on-chip clock multiplier. device reset and must be static while the microcontroller is operating. PMODE:0 share package pins with P0.7:4 and ACH7:4.
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location to be output on the PBUS, while a rising edge ends the data transfer. PROG# shares a package pin with P2.2 and EXTINT. while a low signal indicates a detected error. PVER shares a package pin with P2.0 and TXD. RD# shares a package pin with P5.3. functions as either an input or an open-drain output for data. RXD shares a package pin with P2.1 and PALE#. For handshaking transfers, configure SC1:0 as open-drain outputs. SC0 shares a package pin with P6.4, and SC1 shares a package pin with P6.6. high-impedance input signal. SD0 shares a package pin with P6.5, and SD1 shares a package pin with P6.7.
T2CLK shares a package pin with P1.0 and EPA0. T2DIR shares a package pin with P1.2 and EPA2. 0, it is the serial clock output. TXD shares a package pin with P2.0 and PVER. Connect each VCC pin to the digital supply voltage. This pin supplies operating voltage to the A/D converter. Separating the ground regions provides noise isolation. asserted only during external memory writes. operate at one-half the frequency of the frequency on XTAL1. WR# shares a package pin with P5.2, WRL#, and PLLEN. or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
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asserted for all write operations. WRL# shares a package pin with P5.2, WR#, and PLLEN. or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. clock generators provide the peripheral clocks, CPU clock, and CLKOUT signal. uses an external clock source instead of the on-chip oscillator.
4.0 ADDRESS MAP
5.0 ELECTRICAL CHARACTERISTICS
Table 5. Address Map
8000 External device (memory or I/O) connected to address/data bus Indirect or indexed
2000 Special-purpose memory (internal nonvolatile or external memory) Indirect or indexed
0100 Upper register file (general-purpose register RAM) Indirect, indexed, or win-
0000 Lower register file (register RAM, stack pointer, and CPU SFRs)Direct, indirect, or
- After a reset, the microcontroller fetches its first instruction from 2080H.
- The content or function of these locations may change in future microcontroller revisions, in which
case a program that relies on a location in this range might not function properly. SS should be nominally at the same potential.
- VREF should not exceed VCC by more than 0.5V.
datasheet before finalizing a design.
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5.1 DC Characteristics
Table 6. DC Characteristics at VCC = 4.5V to 5.5V
50 TBD mA
- Device is static and should operate below 1 Hz, but is tested only down to 4 MHz with the PLL
enabled. With the PLL bypassed, the device is tested only down to 8MHz.
- Typicals are based on a limited number of samples and are not guaranteed. The values listed are at
room temperature and VREF = VCC = 5.5V.
- V IH max for port 0 is VREF + 0.5V.
- All bidirectional pins when configured as complementary outputs.
- Standard input pins include XTAL1, EA#, RESET#, and ports 1–6 when configured as inputs.
- All bidirectional pins except P5.1/INST and P2.7/CLKOUT, which are excluded because they are not
weakly pulled low in reset. Bidirectional pins include ports 1–6.
- This specification is not tested in production and is based upon theoretical estimates and/or product
Table 6. DC Characteristics at VCC = 4.5V to 5.5V (Continued)
- Device is static and should operate below 1 Hz, but is tested only down to 4 MHz with the PLL
enabled. With the PLL bypassed, the device is tested only down to 8MHz.
- Typicals are based on a limited number of samples and are not guaranteed. The values listed are at
room temperature and VREF = VCC = 5.5V.
- V IH max for port 0 is VREF + 0.5V.
- All bidirectional pins when configured as complementary outputs.
- Standard input pins include XTAL1, EA#, RESET#, and ports 1–6 when configured as inputs.
- All bidirectional pins except P5.1/INST and P2.7/CLKOUT, which are excluded because they are not
weakly pulled low in reset. Bidirectional pins include ports 1–6.
- This specification is not tested in production and is based upon theoretical estimates and/or product
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5.2 AC Characteristics (Over Specified Operating Conditions)
enabled in clock-doubler mode. Table 7. AC Characteristics
- Testing performed at 4.0 MHz with PLL enabled. With the PLL bypassed, the device is tested only
down to 8 MHz. However, the device is static by design and will typically operate below 1 Hz.
- Typical specifications, not guaranteed.
- Assuming back-to-back bus cycles.
Table 8. AC Characteristics Table 9. AC Timing Symbol Definitions Table 7. AC Characteristics (Continued)
- Testing performed at 4.0 MHz with PLL enabled. With the PLL bypassed, the device is tested only
down to 8 MHz. However, the device is static by design and will typically operate below 1 Hz.
- Typical specifications, not guaranteed.
- Assuming back-to-back bus cycles.
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Figure 4. System Bus Timing
6.0 THERMAL CHARACTERISTICS
210997) provides quality and reliability information.
7.0 DESIGN CONSIDERATIONS
8.0 DEVICE ERRATA
There are no known device errata at this time.
9.0 DATASHEET REVISION HISTORY
Table 10. Thermal Characteristics
- θJA = Thermal resistance between junction
and the surrounding environment (ambient). case in static air flow environment.
- All values of θJA and θJC may fluctuate
- Values listed are at a maximum power dissi-