83C196LC INTEL | Alldatasheet
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COPYRIGHT © INTEL CORPORATION, 1996 December 1996 Order Number: 272805-001 83C196LC, 83C196LD CHMOS 16-BIT MICROCONTROLLER Automotive NOTE This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. The 83C196LC, 83C196LD are low-cost, pin-compatible replacements for the existing 87C196JT and 87C196JR, respectively. These products feature an enhanced synchronous serial I/O (SSIO) port for more flexible communication to other devices. The enhanced SSIO is compatible with Motorola’s Serial Peripheral Interface (SPI) protocol and National’s Microwire protocol. To optimize die size, the A/D converter was removed for use in those applications that use an off-chip A/D converter. The MCS ® 96 microcontroller family members are all high-performance microcontrollers with 16-bit CPUs. The 83C196LC, 83C196LD are composed of a high-speed core with the following peripherals: an asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud-rate generator; an additional synchronous serial I/O port with full duplex master/slave transceivers; a flexible timer/counter structure with prescaler, cascading, and quadrature capabilities; six modularized, multiplexed high-speed I/O for capture and compare (called event processor array) with 200 ns resolution and double buffered inputs; and a sophisticated, prioritized interrupt structure with programmable peripheral transaction server (PTS). The 83C196LC has the highest memory density of the 52-pin MCS 96 microcontroller family, with 32 Kbytes of on-chip ROM, 1 Kbyte of on-chip register RAM, and 512 bytes of code RAM. The high memory integration of the 83C196LC supports high functionality in a low pin-count package and the use of the C programming language. ■ 22 MHz operation† ■ 32 Kbytes of on-chip ROM (LC)
16 Kbytes of on-chip ROM (LD)
■ 1 Kbyte of on-chip register RAM (LC) 384 bytes of on-chip register RAM (LD) ■ 512 bytes of on-chip code RAM (LC only) ■ Register-to-register architecture ■ Peripheral transaction server (PTS) with high-speed, microcoded interrupt service routines ■ Full-duplex serial I/O port with dedicated baud-rate generator ■ Enhanced full-duplex, synchronous serial I/O port (SSIO) † 12 MHz standard; 18 MHz and 22 MHz are speed premium ■ High-speed event processor array — Six capture/compare channels — Two compare-only channels — Two 16-bit software timers ■ Programmable 8- or 16-bit external bus ■ Design enhancements for EMI reduction ■ Oscillator failure detection circuitry ■ SFR register that indicates the source of the last reset ■ Watchdog timer (WDT) ■ Cost reduced replacements for the 87C196JT and 87C196JR. ■ –40° C to +125° C ambient temperature ■ 52-pin PLCC package
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Figure 1. 83C196LC, 83C196LD Block Diagram
512 Bytes
6 Capture/
32 Kbytes (LC)
16 Kbytes (LD)
1 Kbyte (LC)
384 Bytes (LD)ALU
† A seventh capture/compare channel (EPA7) is available as a software timer. It is not connected to a package pin.
1.0 NOMENCLATURE OVERVIEW
Figure 2. Product Nomenclature Table 1. Description of Product Nomenclature 125° C ambient) with Intel standard burn-in.
12 MHz
18 MHz
22 MHz
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2.0 PINOUT
Figure 3. 83C196LC, 83C196LD 52-pin PLCC Package Table 2. 83C196LC, 83C196LD 52-pin PLCC Package Pin Assignments
Table 3. Pin Assignment Arranged by Functional Categories
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3.0 SIGNALS
Table 4. Signal Descriptions AD7:0 share package pins with P3.7:0. AD15:8 share package pins with P4.7:0. progress and is returned high as soon as the bus cycle completes. ADV# shares a package pin with P5.0 and ALE. This active-high output signal is asserted only during external memory cycles. information is available on the system address/data bus. XTAL 1). CLKOUT has a 50% duty cycle. the value of EA# is irrelevant. level of EA# after reset has no effect. High-speed input/output signals for the EPA capture/compare channels. software timer. EPA6:4 are not implemented.
high time is one state time. device to resume normal operation. The interrupt does not need to be enabled. EXTINT shares a package pin with P2.2. the system using a clip-on emulator. ONCE# shares a package pin with P2.6. This is a high-impedance, input-only port. Port 0 pins should not be left floating. selectable special-function signals. selectable special-function signals. inadvertent entry into ONCE mode. P2.2/EXTINT, P2.6/ONCE#, P2.7/CLKOUT. multiplexed address/data bus, which has complementary drivers. P3.7:0 share package pins with AD7:0. Table 4. Signal Descriptions (Continued)
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address/data bus, which has complementary drivers. P4.7:0 share package pins with AD15:8. This is a memory-mapped, bidirectional port. This is a standardbidirectional port. RD# shares a package pin with P5.3. pull-down transistor connected to the RESET# pin for 16 state times. first instruction fetch is from 2080H. functions as either an input or an open-drain output for data. RXD shares a package pin with P2.1. SC0 shares a package pin with P6.4, and SC1 shares a package pin with P6.6. high-impedance input signal. SD0 shares a package pin with P6.5, and SD1 shares a package pin with P6.7. T2CLK shares a package pin with P1.0 and EPA0.
for quadrature counting mode. T2DIR shares a package pin with P1.2 and EPA2. 0, it is the serial clock output. TXD shares a package pin with P2.0. Connect each VCC pin to the digital supply voltage. ground through the lowest possible impedance path. asserted only during external memory writes. WR# shares a package pin with P5.2 and WRL#. or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. asserted for all write operations. WRL# shares a package pin with P5.2 and WR#. or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
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uses an external clock source instead of the on-chip oscillator.
4.0 ADDRESS MAP
5.0 ELECTRICAL CHARACTERISTICS
Table 5. Address Map
0100 Upper register file (general-purpose register RAM)Indirect, indexed, or
- After a reset, the microcontroller fetches its first instruction from 2080H.
- The content or function of these locations may change in future microcontroller revisions, in which
case a program that relies on a location in this range might not function properly. datasheet before finalizing a design.
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5.1 DC Characteristics
Table 6. DC Characteristics at VCC = 4.5V – 5.5V
- All bidirectional pins except CLKOUT. CLKOUT is not pulled weakly high in reset. Bidirectional pins
- Standard input pins include XTAL1, EA#, RESET#, P0.7:2, and ports 1–6 when configured as inputs.
- All bidirectional pins when configured as complementary outputs.
- Device is static and should operate below 1 Hz, but is only tested down to 4 MHz.
- Typicals are based on a limited number of samples and are not guaranteed. The values listed are at
room temperature and VCC = 5.0V.
Table 6. DC Characteristics at VCC = 4.5V – 5.5V (Continued)
- All bidirectional pins except CLKOUT. CLKOUT is not pulled weakly high in reset. Bidirectional pins
- Standard input pins include XTAL1, EA#, RESET#, P0.7:2, and ports 1–6 when configured as inputs.
- All bidirectional pins when configured as complementary outputs.
- Device is static and should operate below 1 Hz, but is only tested down to 4 MHz.
- Typicals are based on a limited number of samples and are not guaranteed. The values listed are at
room temperature and VCC = 5.0V.
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5.2 AC Characteristics
Test Conditions: capacitive load on all pins = 100 pF, rise and fall times = 10 ns, FXTAL 1 = 22 MHz. Table 7. AC Characteristics
- Testing is performed at 4 MHz, however, the device is static by design and will typically operate below
- Typical specifications, not guaranteed.
- Assuming back-to-back bus cycles.
RLAZ (max) = 5 ns by design.
Table 8. AC Timing Symbol Definitions Table 7. AC Characteristics (Continued)
- Testing is performed at 4 MHz, however, the device is static by design and will typically operate below
- Typical specifications, not guaranteed.
- Assuming back-to-back bus cycles.
RLAZ (max) = 5 ns by design.
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Figure 4. System Bus Timing
5.3 AC Characteristics — Serial Port, Shift Register Mode
Figure 5. Serial Port Waveform — Shift Register Mode Table 9. Serial Port Timing — Shift Register Mode
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5.4 AC Characteristics — Synchronous Serial Port
Figure 6. Synchronous Serial Port Table 10. Synchronous Serial Port Timing
5.5 External Clock Drive
Figure 7. External Clock Drive Waveforms Table 11. External Clock Drive
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5.6 Test Output Waveforms
Figure 8. AC Testing Input, Output Waveforms Figure 9. Float Waveforms level occurs with IOL /IOH ≤15 mA.
6.0 THERMAL CHARACTERISTICS
Handbook (order number 210997) provides quality and reliability information.
7.0 DESIGN CONSIDERATIONS
trollers with the following exceptions.
- The synchronous serial I/O port was enhanced to provide more flexible communication to other devices; however, it remains compatible with the 87C196JT and JR non-enhanced SSIO.
- The A/D converter was removed to optimize die size. Follow these recommendations to help maintain hardware and software compatibility between 52-pin, 68-pin, and future microcontrollers.
- Bus width. Since the 83C196LC and LD have neither a WRH# nor a BUSWIDTH pin, the microcontrollers cannot dynamically switch between 8- and 16-bit bus widths. Program the CCBs to select 8-bit bus mode.
- Wait states. Since the 83C196LC and LD have no READY pin, the microcontrollers cannot rely on a READY signal to control wait states. Program the CCBs to limit the number of wait states (0, 1, 2, or 3).
- Write cycle during reset. If the microcontroller is reset during a write cycle, the contents of the external memory device may be corrupted.
- EPA7 . This function exists in the83C196LC and LD, but the associated pin is omitted. You can use this channel either as a software timer or to reset the timers.
- EPA timer reset/write conflict. If an EPA channel resets the timer at the same time your code writes to the timer, it is indeterminate which action takes precedence. If your code uses an EPA channel to reset a timer, do not write to the timer.
- Valid time matches. The timer must increment or decrement to the compare value for a valid match to occur. Writing the compare value to the timer will not cause a match. Resetting the timer also will not cause a match when the compare value is zero.
- NMI . Since the 83C196LC and LD have no NMI pin, the nonmaskable interrupt is not supported. Initialize the NMI vector (at location 203EH) to point to a RET instruction. This method provides glitch protection only.
Table 12. Thermal Characteristics
- θJA = Thermal resistance between junction and the surrounding environment (ambient). Measure-
ments are taken 1 ft. away from case in static air flow environment. JC = Thermal resistance between juction and package surface (case).
- All values of θJA and θJC may fluctuate depending on the environment (with or without airflow, and
- Values listed are at a maximum power dissipation of 0.50 W.
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83C196LC, 83C196LD — AUTOMOTIVE Px_MODE, and Px_DIR registers. Configure the registers for the removed pins as follows: — Clear the corresponding Px_DIR bits. (Configures pins as complementary outputs.) — Clear the corresponding Px_MODE bits. (Selects I/O port function.) — Write either “0” or “1” to the corresponding Px_REG bits. (Effectively ties signals low or high.) — Do not use the bits associated with the removed port pins for conditional branch instructions. Treat these bits as reserved.
- P6.7:4. A value written to any of the upper four bits of P6_REG (bits 4–7) is held in a buffer until the corre- sponding P6_MODE bit is cleared, at which time the value is loaded into the P6_REG bit. A value read from a P6_REG bit is the value currently in the register, not the value in the buffer. Therefore, any change to a P6_REG bit can be read only after the corresponding P6_MODE bit is cleared.
- Reading reserved memory locations. The 87C196JT and JQ implement a precharged peripheral bus within the microcontroller that returns a logic one when reserved bits are read. The 83C196LC and LD use a driven bus within the microcontroller that returns the last value driven on the peripheral data bus when reserved bits are read. 8.0 83C196LC, 83C196LD ERRATA There is no known device errata at this time.
9.0 DATASHEET REVISION HISTORY
This datasheet is valid for devices with an “A” at the end of the topside field process order (FPO) number. Datasheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices.